Scheduling method, device and system and computing equipment

Abstract

The invention provides a scheduling method, the method is executed by a computing device, the computing device comprises a plurality of processors, and the type of at least one instruction set in an instruction set supported by at least one processor in the plurality of processors is different from the type of an instruction set in an instruction set supported by other processors. The scheduling method comprises the steps of obtaining an instruction set type of an application; the type of the instruction set of the application is a subset of the types of a plurality of instruction sets in an instruction set set supported by the target processor; and then distributing the application to the target processor for execution. The method can effectively support data processing of high-performance calculation under an isomorphic multi-instruction-set system structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application. The application number of the original application is 202110770860.3, and the original application date is July 8, 2021. The entire contents of the original application are incorporated into this application by reference.

[0003] This application claims the priority of the Chinese patent application filed with the Intellectual Property Office of the People's Republic of China on May 21, 2021, with application number 202110558600.X and invention name "A method, device and computer equipment for data processing", the entire contents of which are incorporated by reference in this application. Technical Field

[0004] The present application relates to the field of computers, and in particular to a scheduling method, apparatus, system and computing device. Background Art

[0005] The processors of traditional servers are symmetric multi-processing (SMP) or non-uniform memory architecture (NUMA), that is, the instruction set architecture and micro-architecture of multiple processors on the server are exactly the same. The operating system determines the appropriate computing power required for the task by sampling the performance of a specific task, and then schedules the task to the appropriate processor core for execution. Integrating floating-point accelerators in general-purpose computing processors and driving them through specific acceleration instructions is the development trend of general-purpose processor architecture in the era of diverse computing. Compared with general-purpose processors, this type of processor has slightly different micro-architecture and instruction set architecture due to its support for high-performance floating-point acceleration. When a general-purpose processor and a processor with floating-point acceleration form a computing system with a homogeneous multi-instruction set architecture through an interconnected bus in a server, the traditional scheduler will generate an unrecognizable instruction exception when scheduling a task with floating-point acceleration instructions to a general-purpose processor core, resulting in an abnormal exit of the task. The existing processing method is to use a programming framework, and the user calls the interface provided by the programming framework to send the application to the processor specified by the user for execution. This requires the user to have a certain degree of understanding of the instruction set types supported by the processor, and the programming is complex. Therefore, how to provide a task scheduling method that supports high performance under a homogeneous multi-instruction set architecture has become an urgent problem to be solved. Summary of the invention

[0006] The present application provides a scheduling method, apparatus, system and computing device that can support data processing for high-performance computing under a homogeneous multi-instruction set architecture.

[0007] In a first aspect, a scheduling method is provided, the method being executed by a computing device, the computing device comprising a plurality of processors, at least one of the plurality of processors supporting an instruction set set having at least one instruction set of a type different from the instruction set types in the instruction set sets supported by the other processors. The scheduling method comprises: first obtaining the instruction set type of the application, and selecting a target processor from the plurality of processors, wherein the instruction set type of the application is a subset of the types of the plurality of instruction sets in the instruction set set supported by the target processor. The application is then assigned to the target processor for execution. Through the above method, the new scheduling method identifies the instruction set type of the application and the instruction set set supported by the processor before scheduling, so that the operating system has the ability to schedule a mixed system of processors with different instruction set sets.

[0008] In a possible implementation, the method for selecting a target processor from multiple processors can specifically select the target processor from multiple processors according to the type of the instruction set of the application, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set set supported by the target processor. Through the above method, it can be ensured that the application is scheduled to the processor that supports the type of the instruction set of the application, thereby avoiding application execution exceptions.

[0009] In another possible implementation, the target processor belongs to a target scheduling domain, wherein the instruction set set supported by the target scheduling domain is the same as the instruction set set supported by the target processor, and before selecting the target processor, the target scheduling domain is selected from multiple scheduling domains, wherein the type of the instruction set applied is a subset of the types of multiple instruction sets in the instruction set set supported by the target scheduling domain. Through the above method, the scheduling domain can be used to select the target processor, thereby improving the efficiency of scheduling.

[0010] In another possible implementation, the target scheduling domain includes only the target processor, or includes the target processor and other processors, wherein the instruction set set supported by the other processors is the same as the instruction set set supported by the target processor. The above method can be used to manage processors that support the same instruction set set as a scheduling domain, thereby improving scheduling efficiency.

[0011] In another possible implementation, the application includes at least one task, and the scheduling method further includes writing the type of the task's instruction set into the task control block of the task, wherein the type of the task's instruction set is the same as the type of the application's instruction set. Obtaining the type of the application's instruction set specifically includes obtaining the type of the task's instruction set from the task control block. Through the above method, the application can be divided into multiple tasks, and each task can be assigned to a different processor for execution, thereby improving the execution efficiency of the application.

[0012] In another possible implementation, the application is allocated to the target processor for execution, and specifically, the task may be allocated to the target processor for execution.

[0013] In another possible implementation, the target processor includes at least one processing unit, and the task is assigned to the target processor for execution, specifically including: when the target processor supports multi-threaded parallel processing, the task is assigned to a processing unit of the target processor for execution. Through the above method, the multi-threaded parallel processing technology of the processor can be used to execute multiple tasks on one processor at the same time, thereby improving the execution efficiency of the application.

[0014] In another possible implementation, the target processor includes at least one processing core, and the task is assigned to the target processor for execution, specifically including: when the target processor does not support multi-threaded parallel processing, the task is assigned to a processing core of the target processor for execution. Through the above method, the multi-core technology of the processor can be used to execute multiple tasks on one processor at the same time, thereby improving the execution efficiency of the application.

[0015] In another possible implementation, when the processor fails to execute the task, the identifier of the target scheduling domain is stored in the first storage unit of the task control block of the task, wherein the identifier stored in the first storage unit is used to indicate that the processor included in the target scheduling domain cannot be allocated to execute the application. Through the above method, it is possible to avoid the task of the same application being scheduled again to a processor that does not support execution, thereby increasing the probability of successful execution of the application.

[0016] In another possible implementation, when the processor successfully executes the task, the identifier of the target scheduling domain is stored in the second storage unit of the task control block of the task, wherein the identifier stored in the second storage unit is used to indicate that the processor included in the target scheduling domain can be allocated to execute the application. Through the above method, the time for the scheduler to determine whether the scheduling domain supports the execution of the task can be reduced, and the efficiency of application execution can be improved.

[0017] In another possible implementation, obtaining the instruction set type of the application to be executed specifically includes: when the application is compilable, obtaining the instruction set type of the application through a compilation option; or, when the application is not compilable, obtaining the instruction set type of the application through an abnormal instruction. The type of the instruction set of the application can be obtained in two ways. The scheduling method proposed in this application can not only schedule new applications to be executed but also schedule old applications that already have executable files.

[0018] In another possible implementation, the instruction set type of the application is obtained through compilation options, specifically including: directly obtaining the type of instruction set for executing the application specified by the user through compilation options; or first obtaining the type of processor for executing the application specified by the user through compilation options, and then determining the type of instruction set of the application based on the relationship between the processor type and the instruction set type.

[0019] In another possible implementation, after obtaining the instruction set type of the application through the compilation option, the application may be compiled into a binary file, wherein the binary file includes the instruction set type of the application.

[0020] In another possible implementation, after obtaining the instruction set type of the application through the abnormal instruction, the binary code of the abnormal instruction can be parsed to obtain the instruction set type to which the abnormal instruction belongs, and then the instruction set type of the application is set to the type of the abnormal instruction set.

[0021] In another possible implementation, the task is a process generated by a device executing an application.

[0022] In another possible implementation, the task is a thread generated by a device executing an application.

[0023] In a second aspect, the present application provides a computing device, comprising a plurality of processors, wherein at least one instruction set in an instruction set set supported by at least one of the plurality of processors is of a type different from the instruction set types in the instruction set sets supported by the other processors. A main processor among the plurality of processors is used to implement the functions of the operation steps of the scheduling method in the first aspect or any possible implementation of the first aspect.

[0024] In a third aspect, a scheduling device is provided, the scheduling device comprising modules for executing the scheduling method in the first aspect or any possible implementation of the first aspect. The scheduling device is deployed in a computing device, wherein the computing device comprises a plurality of processors, and at least one of the instruction sets supported by at least one of the plurality of processors has a type of at least one instruction set that is different from the type of instruction sets in the instruction sets supported by the other processors.

[0025] In a fourth aspect, the present application provides a scheduling system, comprising a scheduling device for executing the scheduling method in the first aspect or any possible implementation of the first aspect and multiple processors, wherein at least one instruction set in the instruction set set supported by at least one of the multiple processors is of a type different from the instruction set types in the instruction set set supported by other processors. The scheduling device can be located on a different computing device from the multiple processors; at least one of the multiple processors can also be located on a different computing device from the other processors.

[0026] In a fifth aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0027] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0028] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of the structure of a device 100 provided in an embodiment of the present application;

[0030] Figure 2 is a schematic diagram of an operating system 13 provided by the present application;

[0031] Figure 3 This is a schematic diagram of a scheduling domain provided by the present application;

[0032] Figure 4 It is a schematic diagram of a structure of a two-level scheduling domain stored in a memory provided by the present application;

[0033] Figure 5 It is a flowchart of a scheduling method provided in an embodiment of the present application;

[0034] Figure 6 is a schematic diagram of a task control block provided in an embodiment of the present application;

[0035] Figure 7 It is a flowchart of another scheduling method provided in an embodiment of the present application;

[0036] Figure 8 This is a method for setting a "blacklist" provided by this application;

[0037] Fig. 9 This is a method for setting a "white list" provided by this application;

[0038] Fig.10 is a schematic diagram of another task control block provided by the present application;

[0039] Fig.11 It is a schematic diagram of a scheduling device 1100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application are described below in conjunction with the accompanying drawings. Figure 1 1 is a schematic diagram of the structure of a device 100 provided in an embodiment of the present application. The device 100 may be any computing device (e.g., a server) having at least two processors. A device having multiple processors may adopt a symmetric multi-processing architecture (SMP) or a non-uniform memory access architecture (NUMA). For ease of description, the following embodiments of the present application are described by taking the device 100 adopting a NUMA structure as an example. It should be noted that a method for task scheduling provided in the present application is also applicable to devices adopting an SMP structure, as well as devices having other multi-processor structures.

[0041] Device 100 includes processing nodes 14 and 15, wherein multiple processing nodes and memory 16 are connected via a bus, which may be a data bus, a power bus, a control bus, a status signal bus, etc. The bus may also be other types of buses for connecting devices within a computing device, such as Intel Quick Path Interconnect (QPI). It should be noted that the number of processing nodes in device 100 does not constitute a limitation on the present application. Figure 1 The description is made by taking the example that the device 100 includes two processing nodes.

[0042] Each processing node in the device 100 has Figure 1 The structure of a single processing node is shown in FIG. 1 , and the components and connection methods inside each processing node are described below using a processing node (processing node 14) as an example. Processing node 14 includes a processor 140, a memory 144, and a memory manager 143. The processor 140, the memory 144, and the memory manager 143 are interconnected via an on-chip bus.

[0043] Processor 140 is a physical central processing unit (CPU) chip. A processor on a processing node can quickly access the local memory of the node through an on-chip bus, and can also access the memory of other nodes through a high-speed interconnection network. For example, processor 141 of processing node 14 can access memory 144 of processing node 14, and can also access memory 154 of processing node 15. Compared with the processor accessing the memory of the processing node, it will take more time for the processor to access the memory of other processing nodes. Therefore, for a NUMA system, the memory in the same processing node as the processor should ideally contain the information most relevant to the processor. In some embodiments, processor 140 may include multiple cores, such as processor core 141 and processor core 142, which are all integrated on the chip of processor 140. Each processor core may have an independent L1 cache, and different processor cores in the same processor may share an L2 cache. In some embodiments, each processor core may be able to execute multiple threads or processes in parallel through technologies such as simultaneous multithreading. The hardware unit that processes each thread or process is logically a CPU, which can also be called a processing unit, such as processing unit 1411 and processing unit 1412. The processing units of the same processor share the resources of all processors, including L1 cache and logic operation unit.

[0044] Memory 144 or memory 154 refers to an internal memory that directly exchanges data with the processing unit. It can read and write data at any time and at a very fast speed, and serves as a temporary data storage for the operating system or other running programs. Memory 144 or memory 154 includes at least two types of memories, such as random access memory and read-only memory (ROM). For example, the random access memory is dynamic random access memory (DRAM) or storage class memory (SCM). DRAM is a semiconductor memory, and like most random access memories (RAM), it is a volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard disks, but slower access speeds than DRAM, and cheaper costs than DRAM. However, DRAM and SCM are only exemplary descriptions in this embodiment, and memory can also include other random access memories, such as static random access memories (SRAM). As for the read-only memory, for example, it can be a programmable read-only memory (Programmable Read Only Memory, PROM), an erasable programmable read-only memory (Erasable Programmable Read Only Memory, EPROM), etc. In addition, the memory 144 or the memory 154 can also be a dual in-line memory module or a dual-line memory module (Dual In-line Memory Module, referred to as DIMM), that is, a module composed of a dynamic random access memory (DRAM), and can also be a solid state disk (Solid State Disk, SSD). In actual applications, multiple memories and different types of memories can be configured in a NUMA system. This embodiment does not limit the number and type of memory. In addition, the memory can be configured to have a power-saving function. The power-saving function means that when the system loses power and then powers on again, the data stored in the memory will not be lost. The memory with a power-saving function is called a non-volatile memory.

[0045] The memory manager is used to manage and plan the data transfer from the memory to the processing unit and can be a separate chip or integrated into the processor chip.

[0046] Device 100 supports mixing processors of different instruction set versions to form a homogeneous multi-instruction set architecture, which may include the following two scenarios.

[0047] Scenario 1: Mixing general-purpose processors and general-purpose instruction heterogeneous processors.

[0048] A general-purpose instruction heterogeneous processor refers to an accelerator, including a floating-point accelerator, integrated into a general-purpose processor, and specific acceleration instructions are added to drive the accelerator, so that the accelerator can reuse various resources on the processor and support the needs of floating-point calculations of different precisions. For example, Figure 1 The processor 140 may be a general-purpose processor, and the processor 150 may be a general-purpose processor with an integrated floating-point accelerator.

[0049] Scenario 2: A mix of processors produced at different times.

[0050] As chip manufacturing technology advances, the complexity of the hardware circuits of processors produced at different times varies, so the supported instruction set versions are also slightly different. Figure 1 The processor 140 may be a general purpose processor version 9, and the processor 150 may be a general purpose processor version 8.6.

[0051] In the device 100, the operating system 13 is used to run the application, and convert the task generated by the application into instructions and assign it to the processor that can execute the task successfully. In one embodiment, the operating system 13 can run on the main processor of the device 100. After the other processors receive the request to run the application, they send the request to the main processor, and the operating system 13 converts the task generated by the application into instructions and assigns it to the processor that can execute the task successfully. Among them, the main processor can be pre-specified by the user from multiple processors of the device 100, and the present application does not limit the specified method. For example, the main processor can be processor 140 or processor 150. In another embodiment, the operating system 13 can also run on multiple processors of the device 100, for example, the operating system 13 runs on processor 140 and processor 150 at the same time. When a processor receives a request to run the application, the operating system 13 on the processor converts the task generated by the application into instructions and assigns it to the processor that can execute the task successfully. At this time, the processor that executes the operating system 13 can be called the main processor.

[0052] Figure 2 is a schematic diagram of an operating system 13 provided by the present application, taking the operating system stored in the memory 144 as an example. Figure 2As shown, the operating system 13 includes a compiler 131, a loader 132 and a scheduler 133. Among them, the compiler 131 is used to compile the application code into a binary file that can be executed by the processor. When the binary file is executed, the loader 132 creates a corresponding process or thread for loading the instructions of the binary file. On the one hand, each binary file can create a new process when it is loaded once. When a process is created, the loader 132 will also allocate a memory space for the process to save the context related to the process, including: process identifier, process scheduling information, process control information, and the address of the next instruction to be executed, etc. This memory space can also be called a process control block. On the other hand, the loader 132 can also create multiple threads for a process to execute multiple subtasks in the process, and multiple threads can share the software and hardware resources of the process. When a thread is created, the loader 132 will allocate a memory space for the thread in the space occupied by the process control block to save the context related to the thread, including: thread identifier, thread scheduling information, thread control information, and the address of the next instruction to be executed, etc. The memory space allocated to the thread can also be called a thread control block. Finally, the scheduler 133 schedules the application process or thread to different processing units for execution. For ease of description, in the following embodiments, processes or threads are collectively referred to as tasks, and process control blocks or thread control blocks are collectively referred to as task control blocks.

[0053] The operating system 13 may further include a parser 134, which may be used to parse the binary code of the instruction to obtain the instruction set type of the instruction.

[0054] When the scheduler 133 schedules tasks, it may adopt a multi-level scheduling domain management method, where each scheduling domain includes one or more hardware. Figure 3 The hardware can be a processor, and the scheduling domain including one or more processors can be called a physical domain (PHY_domain); the hardware can also be a processor core, and the scheduling domain including one or more processor cores can be called a core domain (MC_domain); the hardware can also be a processor unit, and the scheduling domain including one or more processing units can be called a hyperthreading domain (SMT_domain). The scheduling domain represents the scope of the scheduler 133 to execute the scheduling policy, and the scheduler 133 can execute different scheduling policies in each scheduling domain. The hardware in each scheduling domain can be divided into one or more scheduling groups (CPU group), each scheduling group can be regarded as an independent execution unit, and the scheduler executes scheduling policies between different scheduling groups in the scheduling domain. For example, see Figure 3When the scheduling domain is a physical domain, each processor can be used as a scheduling group; when the scheduling domain is a core domain, each processor core can be used as a scheduling group; when the scheduling domain is a hyperthreading domain, each processing unit can be used as a group. When the operating system 13 is started, the scheduler 133 can establish scheduling domains of different levels and establish corresponding scheduling groups on each level of scheduling domain.

[0055] For example, Figure 1 Taking the processor structure of device 100 as an example, Figure 3 This application provides a schematic diagram of a scheduling domain, such as Figure 3 As shown, the scheduling domain can be divided into a hyperthreading domain, a core domain, and a physical domain. Specifically, the hyperthreading domain is the lowest level scheduling domain, and each processor core can be regarded as a hyperthreading domain, for example, processor core 141 is a hyperthreading domain 1. Each hyperthreading domain is associated with two processing units, for example, hyperthreading domain 1 is associated with processing unit 1411 and processing unit 1412. Each processing unit is a scheduling group in the hyperthreading domain, for example, scheduling group 0 is processing unit 1411. The higher level scheduling domain is the core domain, and each processor can be regarded as a core domain, for example, processor 140 is core domain 1. Each core domain is associated with two processor cores, for example, core domain 1 is associated with processor core 141 and processor core 142. Each processor core is a scheduling group in the core domain, for example, scheduling group 00 is processor core 141. The higher level physical domain consists of multiple processors in the system, and each physical domain is associated with multiple processors, for example, physical domain 1 is associated with processor 140 and processor 1250. In the physical domain, each processor is a scheduling group, for example, scheduling group 000 is processor 140.

[0056] Optionally, when the multi-core processor does not support multi-threaded parallel processing, the scheduling domain can be divided into two levels: a physical domain and a core domain.

[0057] Optionally, when the processor has only one core and supports multi-threaded parallel processing, the scheduling domain can be divided into two levels: a physical domain and a hyperthreading domain.

[0058] Optionally, when the processor has only one core and does not support multi-threaded parallel processing, the scheduling domain is the physical domain.

[0059] The caller 133 can store the topological relationship diagram of the scheduling domain in the form of a structure in the memory. Figure 4 This is a schematic diagram of a structure of a two-level scheduling domain stored in memory provided by the present application, such as Figure 4As shown, the scheduling domain presents a tree-like topological structure. Different levels of scheduling domains are connected together by pointers. The low-level scheduling domain can be regarded as a scheduling group in the high-level scheduling domain. For example, scheduling domain 2 and scheduling domain 3 are scheduling group 1 and scheduling group 2 of scheduling domain 1 respectively. The scheduler can first execute the scheduling policy of scheduling domain 1 between scheduling group 1 and scheduling group 2 in scheduling domain 1. After selecting a scheduling group, such as scheduling group 1, the scheduler assigns the task to scheduling domain 2, and then executes the scheduling policy of scheduling domain 2 between scheduling groups 3-5 of scheduling domain 2. After selecting a scheduling group, such as scheduling group 3, the scheduler assigns the task to scheduling group 3. The structure of the scheduling domain includes the number of the scheduling domain (also called the scheduling domain identifier, when the structure is only a scheduling group, it is NULL), the number of the scheduling group (also called the scheduling group identifier, when the structure is not a scheduling group of other scheduling domains, it is NULL), the scheduling policy, the number of the hardware included in the scheduling domain, and the pointer of the scheduling group (when the structure is only a scheduling group, it is NULL). The scheduling strategy can be set by the user. The user can set different scheduling strategies for scheduling domains of different levels. The setting method is not limited in this application.

[0060] When multiple schedules in a device form a computing system with a homogeneous multi-instruction set architecture, through the task scheduling method provided in the present application, the scheduler 133 can identify the differences in the instruction sets in the application's tasks and schedule the tasks to the processing units that can execute the instruction sets, thereby avoiding the processing units generating unrecognizable instruction exceptions and causing abnormal task exit.

[0061] The following will be combined Figures 5 to 10 The data processing method provided in the embodiment of the present application is described. Figure 5 is a flowchart of a scheduling method provided in an embodiment of the present application. The method can be used Figure 2 Specifically, the method may be executed using a main processor running the operating system 13, which may be a processor specified by a user or a processor running the operating system 13, for example, Figure 1 The processor 140 or the processor 150 in FIG. Figure 5 As shown, the specific methods include:

[0062] S501 . The compiler 131 obtains the type of instruction set of the application.

[0063] Before the application is executed, the code needs to be compiled into a binary executable file, and then scheduled to the processor for execution by the scheduler. When compiling the application code, the compiler 131 can obtain the type of the application instruction set through the compilation options in the following two ways.

[0064] Method 1: The user specifies the processor model that executes the application in the compilation options.

[0065] Users can specify the processor model to execute the application through compilation options, for example:

[0066] -march=cpu-type;

[0067] The right side of the equal sign indicates the processor model that executes the application, and the application can be compiled into a binary file that is executed on the processor of this type.

[0068] After the compiler 131 obtains the processor model, it can determine the instruction set set supported by the processor according to the processor model, and the instruction set set includes the types of all instruction sets supported by the processor. The relationship between the processor model and the instruction set set supported by the processor can be preset and stored in the device in the form of a table. For example, Table 1 is a list of the relationship between processor models and instruction set sets provided in an embodiment of the present application. The table records the model (also called identification) of each processor and the instruction set set supported by the processor of this model.

[0069] Table 1. Processor models and instruction set

[0070]

[0071] Method 2: The user directly specifies the type of instruction set to execute the application in the compilation options.

[0072] The user can directly specify the type of instruction set to execute the application through the compilation option "-m-xxx", which means that the application can be compiled into a binary file that can be executed on a processor of this instruction set type, for example:

[0073] -mmmx –msse;

[0074] Indicates that the instruction set type of the application compilation is MMX and SSE.

[0075] S502 : The compiler 131 writes the type of the instruction set into the executable binary file of the application.

[0076] During the compilation process, the compiler 131 writes the type of the instruction set into the executable binary file generated by the compilation. Exemplarily, the compiler 131 may write the type of the instruction set into the .comment field of the executable binary file.

[0077] S503: Run the executable binary file, and the loader 132 puts the type of instruction set into the task control block.

[0078] When the binary file is executed, the loader 132 creates the corresponding task according to the instructions of the binary file, and creates the corresponding task control block in the memory for saving the context related to the process. The loader 132 also stores the type of the instruction set in the task control blocks of all tasks corresponding to the binary file. Figure 6 is a schematic diagram of a task control block provided by this application. Figure 6 As shown, the application runs to generate multiple tasks, each task corresponds to a task control block, and a space is allocated in each task control block to store the type of the instruction set.

[0079] S504: The scheduler 133 obtains the instruction set of the processor.

[0080] When the operating system is started, the scheduler 133 can obtain the instruction set set supported by the processor deployed on the device. For example, the scheduler 133 can obtain the model of each processor by calling the cpuinfo instruction and reading the modelnade field, and then obtain the type of instruction set supported by each processor according to the list of the relationship between the processor model and the instruction set set. For another example, the scheduler 133 can also directly obtain the type of instruction set supported by each processor by calling the cpuinfo instruction and reading the flag field.

[0081] S505 . The scheduler 133 sets a scheduling domain according to the instruction set of the processor.

[0082] The scheduler 133 sets the processors with the same instruction set as a physical domain according to the instruction set of the processors, and writes the types of all instruction sets in the instruction set into the structure of the physical domain in the form of the instruction set.

[0083] S506 : The scheduler 133 schedules the task to a processing unit that can execute the task.

[0084] When the clock interrupt triggers a task scheduling of a physical domain, the scheduler 133 determines whether the instruction set set of the physical domain includes the types of all instruction sets in the task control block of the task to be scheduled. In the physical domain that can execute the task, a scheduling group, i.e., a processor, is selected according to the scheduling policy of the physical domain. Afterwards, the scheduler 133 can select a scheduling group, i.e., a processor core, from the core domain according to the scheduling policy of the core domain, and then select a scheduling group, i.e., a processing unit, from the hyperthreading domain according to the scheduling policy of the hyperthreading domain to execute the task.

[0085] Optionally, when the multi-core processor does not support multi-threaded parallel processing, the scheduler 133 may select a scheduling group from the core domain, ie, a processing core, to execute the task according to the scheduling policy of the core domain.

[0086] Optionally, when the processor has only one core and supports multi-threaded parallel processing, the scheduler 133 may directly select a scheduling group from the hyper-threading domain according to the scheduling policy of the hyper-threading domain, that is, a processing unit to execute the task.

[0087] Optionally, when the processor has only one core and does not support multi-threaded parallel processing, the scheduler 133 directly selects the scheduling group, that is, the processor executes the task.

[0088] Optionally, when all physical domains cannot execute the task, the scheduler 133 directly reports an error and stops executing the application.

[0089] The task scheduling method proposed in this application can be applied to a homogeneous multi-instruction set structure, and through the cooperation of a compiler and a scheduler, it supports flexible scheduling of a multi-processor system composed of scheduling components of different instruction set versions in a unified operating system.

[0090] For a large number of existing binary executable files and dynamic link libraries, since they cannot be recompiled by the compiler, the instruction set type cannot be written into the executable binary file of the application. The following methods can be used for task scheduling: Figure 7 Another scheduling method provided by this application is Figure 5 Similarly, you can use Figure 2 The operating system 13 shown is executed, specifically, it can be executed using a main processor running the operating system 13, and the main processor can be a processor specified by the user or a processor running the operating system 13, for example, Figure 1 The processor 140 or the processor 150 in FIG. Figure 7 As shown, the specific methods include:

[0091] S701: Run the executable binary file of the application to determine whether an exception occurs in the execution of instructions in the task.

[0092] S702: When an instruction is abnormal, the parser 134 reads the binary code of the abnormal instruction and parses the type of the instruction set of the instruction.

[0093] S703 , similar to S403 , the loader 132 puts the type of instruction set into the task control block.

[0094] S704. The scheduler 133 puts the task corresponding to the abnormal instruction into a waiting queue.

[0095] S705 , the scheduler 133 schedules the task to a processing unit that can execute the task.

[0096] Specifically, similar to S504 to S506 , the scheduler 133 sets the instruction set of the scheduling domain and schedules the task to the processing unit that can execute it.

[0097] Through the above method, the instruction set type of the application can be identified by dynamically identifying abnormal instructions, thereby solving the problem of repeated errors caused by tasks of old applications or dynamic link libraries being scheduled to inappropriate processors.

[0098] In order to reduce the time taken by the scheduler to determine whether the instruction set types are the same and to improve the accuracy of the scheduler's scheduling, a "blacklist" or "whitelist" can also be added to the task control block of the task, where the "blacklist" is used to store the scheduling domains associated with the processors that have abnormalities when executing the task. The "whitelist" is used to store the scheduling domains associated with the processors that successfully execute the task. Figure 8 This application provides a method for setting a "blacklist", which can be used Figure 2 The operating system 13 shown is executed, specifically, it can be executed using a main processor running the operating system 13, and the main processor can be a processor specified by the user or a processor running the operating system 13, for example, Figure 1 The processor 140 or the processor 150 in FIG. Figure 8 As shown, this method can be used in Figure 5 The method shown in the figure is performed after step S506, or it can be performed after step S506. Figure 7 The method shown is executed after step S702, and the method is specifically as follows:

[0099] S801: Run the executable binary file of the application to determine whether an exception occurs in the execution of instructions in the task.

[0100] S802: When an instruction is abnormal, the scheduler 133 obtains the number of the physical domain where the processor where the abnormal instruction occurs is located.

[0101] S803. The loader 132 sets a "blacklist" in the task control block.

[0102] A storage area is allocated in the task control block for storing the "blacklist" of the scheduling domain. For the sake of convenience, the storage area can also be called the first storage unit. The loader 132 stores the physical domain number in the first storage unit of the task control block of all tasks of the application.

[0103] After adding the "blacklist", the scheduler 133 will not schedule the task to the scheduling domain corresponding to the number stored in the "blacklist" during the next scheduling. Optionally, when the "blacklist" of the task includes all physical domains on the device 100, it means that all processors cannot support the instructions for executing the task, and the scheduler 133 can directly report an error and stop executing the application.

[0104] Through the above method, it is possible to avoid the task of the same application being scheduled again to a processor that does not support execution, thereby increasing the probability of successful execution of the application.

[0105] Fig. 9 This is a "whitelist" method provided by this application, which can be used Figure 2 The operating system 13 shown is executed, specifically, it can be executed using a main processor running the operating system 13, and the main processor can be a processor specified by the user or a processor running the operating system 13, for example, Figure 1 The processor 140 or the processor 150 in FIG. Figure 8 As shown, this method can be used in Figure 5 The method shown is executed after step S506, and the method is specifically as follows:

[0106] S901: Run the executable binary file of the application to determine whether an exception occurs in the execution of instructions in the task.

[0107] S902: When no exception occurs in the instruction, the scheduler 133 obtains the number of the physical domain where the processor appears.

[0108] S903. The loader 132 sets a "white list" in the task control block.

[0109] A storage area is allocated in the task control block for storing the "white list" of the scheduling domain. For the sake of convenience, the storage area can also be called a second storage unit. The loader 132 stores the physical domain number in the second storage unit of the task control block of all tasks of the application.

[0110] After adding the "white list", the scheduler 133 can directly schedule tasks to the scheduling domain corresponding to the number stored in the "white list" during the next scheduling.

[0111] Through the above method, the time for the scheduler to determine whether the scheduling domain supports the instruction set required for executing the task can be reduced, thereby improving the efficiency of application execution.

[0112] It should be noted that either a “blacklist” or a “whitelist” can be added to the task control block of the task, or both a “blacklist” and a “whitelist” can be added to the task control block of the task. Fig.10 This is a schematic diagram of a task control block provided by the present application with a “blacklist” and a “whitelist” added.

[0113] It is worth noting that, for the above method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the described order of actions. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required for the present application.

[0114] Other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be familiar with the fact that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0115] Combined with the above Figures 5 to 10 , describes in detail the task scheduling method provided by the embodiment of the present application, and will be combined with Fig.11 , describing a task scheduling device provided according to an embodiment of the present application.

[0116] Fig.11 A schematic diagram of a scheduling device 1100 provided in an embodiment of the present application includes an acquisition unit 1101 and a scheduling unit 1102. The scheduling device 1100 is used to Figure 2 The functions of the operating system 13 are shown.

[0117] The acquisition unit 1101 is used to acquire the type of the instruction set of the application. For specific implementation, please refer to Figure 5 The step S501 in the above embodiment is not described in detail here. In the implementation process of the product, the acquisition unit 1101 may be Figure 2 The compiler 131 shown may also be other compilers, and this embodiment does not limit the form of the acquisition unit 1101.

[0118] The scheduling unit 1102 is used to select a target processor from multiple processors of the computing device, wherein at least one instruction set in the instruction set set supported by at least one of the multiple processors is different from the instruction set types in the instruction set set supported by other processors, and the instruction set type of the application is a subset of the types of multiple instruction sets in the instruction set set supported by the target processor; the scheduling unit 1102 is also used to allocate the application to the target processor for execution. The specific implementation of the scheduling unit 1102 can be referred to Figure 5 The steps S504 to S506 in the above are not described in detail here. In the implementation process of the product, the acquisition unit 1101 may be Figure 2 The scheduler 133 shown may also be other schedulers, and this embodiment does not limit the form of the scheduling unit 1102.

[0119] Optionally, the scheduling unit 1102 is further configured to select a target processor from a plurality of processors according to a type of an instruction set of an application.

[0120] Optionally, before selecting the target processor, the scheduling unit 1101 is further configured to select the target scheduling domain from multiple scheduling domains, and the type of the instruction set applied is a subset of the types of multiple instruction sets in the instruction set set supported by the target scheduling domain. The target processor belongs to the target scheduling domain, and the instruction set set supported by the target scheduling domain is the same as the instruction set set supported by the target processor.

[0121] Optionally, the target scheduling domain includes only the target processor, or the target scheduling domain includes the target processor and other processors, wherein the instruction set set supported by the other processors is the same as the instruction set set supported by the target processor.

[0122] Optionally, the scheduling device 1100 further includes a loading unit 1103, which is used to write the type of the task's instruction set into the task control block of the task, and the type of the task's instruction set is the same as the type of the application's instruction set; the acquisition unit 1101 is further used to acquire the type of the task's instruction set from the task control block. The application includes at least one task. The specific implementation of the loading unit 1103 can be referred to Figure 5 The step S503 in the above embodiment will not be described in detail here. In the process of product implementation, the loading unit 1103 may be Figure 2 The loader 132 shown may also be other loaders, and this embodiment does not limit the form of the loading unit 1103.

[0123] Optionally, the scheduling unit 1102 is further configured to allocate tasks to a target processor for execution.

[0124] Optionally, the scheduling unit 1102 is further configured to allocate the task to a processing unit of the target processor for execution when the target processor supports multi-threaded parallel processing. The target processor includes at least two processing units.

[0125] Optionally, the scheduling unit 1102 is further configured to allocate the task to a processor core of the target processor when the target processor does not support multi-threaded parallel processing. The target processor includes at least one processor core.

[0126] Optionally, the loading unit 1103 is further configured to store the identifier of the target scheduling domain in the first storage unit of the task control block of the task when the target processor fails to execute the task, wherein the identifier stored in the first storage unit is used to indicate that the processor included in the target scheduling domain cannot be allocated to execute the application. Figure 8 The steps of S803 are not repeated here.

[0127] Optionally, the loading unit 1103 is further configured to store the identifier of the target scheduling domain in the second storage unit of the task control block of the task when the target processor successfully executes the task, wherein the identifier stored in the second storage unit is used to indicate that the processor included in the target scheduling domain can be allocated to execute the application. Fig. 9 The steps of S903 are not repeated here.

[0128] Optionally, the task is a process or thread generated by an application.

[0129] Optionally, the acquisition unit 1101 further includes a compilation unit 1104 and a parsing unit 1105. When the application is compilable, the compilation unit 1104 is used to obtain the instruction set type of the application through the compilation options. For specific implementation, please refer to Figure 5 The steps from S501 to S502 are not described here. When the application cannot be compiled, the parsing unit 1105 is used to obtain the instruction set type of the application through the abnormal instruction. For specific implementation, please refer to Figure 7 The steps of S702 in the above are not described here. In the implementation process of the product, the compiling unit 1104 may be Figure 2 The compiler 131 shown in FIG. 1 may also be other compilers. This embodiment does not limit the form of the compiling unit 1104. The parsing unit 1105 may be Figure 2 The parser 134 shown may also be other parsers, and this embodiment does not limit the form of the parsing unit 1105.

[0130] In summary, the scheduling device 1100 provided in the embodiment of the present application can identify the differences in instruction sets in the tasks of the application, schedule the tasks to the processing unit that can execute the instruction sets, and improve the probability of successful execution of the application.

[0131] The present application also provides a scheduling system, comprising a scheduling device for executing the scheduling method proposed in the present application and multiple processors, wherein at least one instruction set in the instruction set set supported by at least one processor among the multiple processors is of a type different from the instruction set types in the instruction set sets supported by other processors.

[0132] Optionally, the scheduling device and the multiple processors may be located in a different computing device.

[0133] Optionally, at least one of the multiple processors may also be located on a different computing device than the other processors.

[0134] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium may be a solid state drive (SSD).

[0135] The above is only a specific implementation of the present application. Those skilled in the art may conceive of changes or substitutions based on the specific implementation provided by the present application, which should all be included in the protection scope of the present application.

Claims

1. A scheduling method, characterized in that: The method is performed by a computing device, the computing device comprising a plurality of processors, at least one of the plurality of processors supporting an instruction set set having at least one instruction set of a type different from the types of instruction sets in the instruction set sets supported by other processors, the method comprising: Get the type of instruction set of the application; selecting a target processor from the plurality of processors according to a type of an instruction set of the application, wherein the type of the instruction set of the application is a subset of types of a plurality of instruction sets in an instruction set set supported by the target processor; The application is distributed to the target processor for execution.

2. The method according to claim 1, characterized in that The target processor belongs to a target scheduling domain, and the instruction set set supported by the target scheduling domain is the same as the instruction set set supported by the target processor. Before selecting the target processor, the method further includes: The target scheduling domain is selected from a plurality of scheduling domains, and the type of the instruction set of the application is a subset of the types of a plurality of instruction sets in the instruction set set supported by the target scheduling domain.

3. The method according to claim 2, characterized in that The target scheduling domain includes only the target processor, or the target scheduling domain includes the target processor and other processors, and the instruction set set supported by the other processors is the same as the instruction set set supported by the target processor.

4. The method according to any one of claims 1 to 3, characterized in that: The application includes at least one task, and the method further includes: Writing the type of the instruction set of the task into the task control block of the task, the type of the instruction set of the task being the same as the type of the instruction set of the application; The acquiring the type of the instruction set of the application specifically includes: acquiring the type of the instruction set of the task from the task control block.

5. The method according to claim 4, characterized in that The allocating the application to the target processor for execution specifically includes: The task is assigned to the target processor for execution.

6. The method according to claim 5, characterized in that The target processor includes at least two processing units, and the step of allocating the task to the target processor for execution specifically includes: When the target processor supports multi-thread parallel processing, the task is assigned to a processing unit of the target processor for execution.

7. The method according to claim 5, characterized in that The target processor includes at least one processor core, and allocating the task to the target processor for execution specifically includes: When the target processor does not support multi-thread parallel processing, the task is assigned to a processor core of the target processor.

8. The method according to any one of claims 5 to 7, characterized in that: The target processor belongs to a target scheduling domain, and the instruction set set supported by the target scheduling domain is the same as the instruction set set supported by the target processor. The method further includes: When the target processor fails to execute the task, the identifier of the target scheduling domain is stored in the first storage unit of the task control block of the task, and the identifier stored in the first storage unit is used to indicate that the processor included in the target scheduling domain cannot be allocated to execute the application.

9. The method according to any one of claims 5 to 8, characterized in that: The target processor belongs to a target scheduling domain, and the instruction set set supported by the target scheduling domain is the same as the instruction set set supported by the target processor. The method further includes: When the target processor executes the task successfully, the identifier of the target scheduling domain is stored in the second storage unit of the task control block of the task, and the identifier stored in the second storage unit is used to indicate that the processor included in the target scheduling domain can be allocated to execute the application.

10. The method according to any one of claims 3 to 9, characterized in that: The task is a process or a thread generated by the application.

11. According to any one of claims 1 to 10, obtaining the instruction set type of the application to be executed specifically comprises: When the application is compilable, obtaining the instruction set type of the application through a compilation option; Alternatively, when the application cannot be compiled, the instruction set type of the application is obtained through an abnormal instruction.

12. A computing device, characterized in that: The computing device includes a plurality of processors, wherein at least one of the plurality of processors supports an instruction set set having at least one instruction set of a type different from the instruction set types of the instruction sets supported by the other processors: A main processor among the plurality of processors is configured to: Get the type of instruction set of the application; selecting a target processor from the plurality of processors according to a type of an instruction set of the application, wherein the type of the instruction set of the application is a subset of types of a plurality of instruction sets in an instruction set set supported by the target processor; The application is distributed to the target processor for execution.

13. The computing device according to claim 12, characterized in that The target processor belongs to a target scheduling domain, the target scheduling domain supports the same instruction set set as the target processor, and before selecting the target processor, the main processor is further configured to: The target scheduling domain is selected from a plurality of scheduling domains, and the type of the instruction set of the application is a subset of the types of a plurality of instruction sets in the instruction set set supported by the target scheduling domain.

14. The computing device according to claim 13, characterized in that The target scheduling domain includes only the target processor, or the target scheduling domain includes the target processor and other processors, and the instruction set set supported by the other processors is the same as the instruction set set supported by the target processor.

15. The computing device according to any one of claims 12 to 14, characterized in that: The application includes at least one task, and the main processor is further configured to: Writing the type of the instruction set of the task into the task control block of the task, the type of the instruction set of the task being the same as the type of the instruction set of the application; The type of the instruction set of the task is obtained from the task control block.

16. The computing device according to claim 15, characterized in that The main processor is also used for: The task is assigned to the target processor for execution.

17. The computing device according to claim 16, characterized in that The target processor includes at least two processing units, and the main processor is further used for: When the target processor supports multi-thread parallel processing, the task is assigned to a processing unit of the target processor for execution.

18. The computing device according to claim 17, characterized in that The target processor includes at least one processor core, and the main processor is further used for: When the target processor does not support multi-thread parallel processing, the task is assigned to a processor core of the target processor.

19. A scheduling device, characterized in that: The scheduling device includes an acquisition unit and a scheduling unit: The acquisition unit is used to acquire the type of the instruction set of the application; The scheduling unit is used to select a target processor from multiple processors of a computing device according to the type of the instruction set of the application, wherein at least one instruction set in the instruction set sets supported by at least one of the multiple processors has a type that is different from the types of instruction sets in the instruction set sets supported by other processors, and the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set sets supported by the target processor; and to allocate the application to the target processor for execution.

20. The dispatching device according to claim 19, characterized in that: The target processor belongs to a target scheduling domain, the target scheduling domain supports the same instruction set set as the target processor, and before selecting the target processor, the scheduling unit is further configured to: The target scheduling domain is selected from a plurality of scheduling domains, and the type of the instruction set of the application is a subset of the types of a plurality of instruction sets in the instruction set set supported by the target scheduling domain.

21. The dispatching device according to claim 19 or 20, characterized in that: The application includes at least one task, and the scheduling device also includes a loading unit, and the loading unit is used to: Writing the type of the instruction set of the task into the task control block of the task, the type of the instruction set of the task being the same as the type of the instruction set of the application; The acquisition unit is further used for: acquiring the type of the instruction set of the task from the task control block.

22. A scheduling system, comprising a scheduling device as described in any one of claims 19 to 21 and multiple processors, wherein at least one of the instruction sets supported by at least one processor among the multiple processors has an instruction set type that is different from the instruction set types in the instruction set sets supported by other processors.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions, which, when executed on a computer, enable the computer to execute the operating steps of any one of the methods described in claims 1 to 11.

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