Hardware Trojan horse detection and positioning method based on graph convolutional neural network

Abstract

The invention discloses a hardware Trojan horse detection and positioning method based on a graph convolutional neural network, and the method comprises the steps: converting a circuit structure into a graph structure based on a graph learning method, and extracting the basic structure features of nodes in the process; constructing two new features Cov and Lfp based on a deep search strategy and a topological logic analysis method to perfect feature information of circuit nodes; aggregating neighbor features of the nodes based on the GCN and updating self node feature information to improve local sensing and generalization ability of the nodes; using a global feature fusion method based on an attention mechanism to extract and update global features of the graph, and fusing the global features with the node feature vectors after the neighbor features are aggregated; balancing training data based on a stochastic gradient descent thought in combination with a small-batch oversampling and undersampling method; and using a multi-layer perceptron model to train the balanced data based on a leave-one cross validation method, predicting an unknown circuit, and identifying potential HTs nodes in the circuit. According to the invention, HTs detection and positioning are realized.

Description

Technical Field

[0001] The present invention relates to a method for detecting and locating multiple types of hardware Trojans (HTs) in integrated circuits (ICs), and in particular to a method for detecting and locating hardware Trojans based on a graph convolutional neural network. Background Art

[0002] As the demand for high-performance, low-cost, and multi-functional ICs continues to increase, companies and designers are increasingly relying on introducing third-party intellectual property (3PIP) cores or outsourcing standard and universal logic design to professional design companies to stay ahead of the competition. This strategy allows them to focus on the development of new features, but it also increases the risk of chips being attacked by malicious hardware. For example, untrusted 3PIP suppliers or third-party design contractors may implant malicious Trojans in the design, and even if the supplier or contractor is trustworthy, the contaminated design tools may inadvertently add HTs or other threats. HTs are lightweight components in large-scale complex ICs, consisting of Trojan triggers and payloads. Most HTs are only triggered under special circumstances, making it difficult for traditional verification and testing methods to detect their existence. Attackers can construct and implant HTs that are not easy to detect, such as designing their triggers to be activated only when checked, so that the ICs appear to be harmless to the outside world. However, when the HTs trigger is finally activated, it may cause confidential information stored in the IC to be leaked or tampered with, or even cause the IC chip to fail or be damaged. Therefore, it is necessary to construct an efficient method to achieve rapid detection of HTs.

[0003] To achieve the above goals, researchers have proposed a variety of methods, such as logic test-based methods, side channel analysis-based methods, and code review methods, to detect HTs in ICs. The logic test-based method generates a large number of test patterns to activate potential HTs, causing them to produce observable errors or abnormal behaviors to achieve the purpose of detection; the side channel analysis-based method often uses signal features based on power, delay, and temperature analysis to detect changes in ICs to find HTs; and the code review method carefully examines the design code to find parts that do not conform to normal functions to identify HTs. Although these methods can be used to detect HTs in ICs, they often require large test vectors, complex and sophisticated hardware equipment, and a lot of time and human resources. It is also difficult to accurately locate HTs based on detection. Summary of the invention

[0004] In order to overcome the shortcomings of low accuracy and high computational complexity in the prior art when detecting HTs, the present invention provides a hardware Trojan detection and positioning method based on graph convolutional neural network. Firstly, two new features of gate nodes are constructed, and then local feature aggregation and global feature fusion are performed on circuit nodes. The problem of scarcity of HTs nodes in the circuit is solved, thereby realizing the detection and positioning of HTs. The method shows superior performance on multiple data sets and has good generalization and robustness.

[0005] The technical solution adopted by the present invention to solve its technical problem is:

[0006] A method for detecting and locating hardware Trojans based on a graph convolutional neural network, the method comprising the following steps:

[0007] Step 1: Convert the circuit structure into a graph structure based on the graph learning method, and extract the basic structural features of the nodes in the process, namely, the node type, in-degree, out-degree, the shortest distance from the node to any original input, and the shortest distance from the node to any original output;

[0008] Step 2: Based on the deep search strategy and topological logic analysis method, two new features Cov and Lfp are constructed to improve the feature information of the circuit nodes;

[0009] Step 3: Aggregate the neighbor features of the node based on GCN and update the feature information of the node itself to improve the local perception and generalization ability of the node;

[0010] Step 4: Use the global feature fusion method based on the attention mechanism to extract and update the global features of the graph, and fuse them with the node feature vector after aggregating neighbor features obtained in step 3;

[0011] Step 5: Based on the idea of ​​stochastic gradient descent and combined with small batch oversampling and undersampling methods, the training data is balanced to solve the impact of the scarcity of HTs nodes in the circuit on the model;

[0012] Step 6. Use the multi-layer perceptron model to train the balanced processed data based on the leave-one-out cross-validation method, and make predictions on unknown circuits to identify potential HTs nodes in the circuit.

[0013] Further, the process of step 2 is as follows:

[0014] 2.1. Calculate the node n by formula (1) i The number of nodes connected by paths is quantified by n i The connectivity Cov(n i ). A normalization strategy is used to eliminate the adverse effects of scale differences on the results, where i = 1, 2, ..., N, N is the number of nodes in the graph, ∑n fromRepresents all reachable nodes n in a directed graph i The number of nodes, ∑n to Represents the directed graph from node n i The number of nodes that can be reached by starting, the sum of these two is the number of nodes in the graph that are connected to the target node n i The number of all nodes with connectivity;

[0015]

[0016] 2.2. Calculate node n by formula (2) i The influence of all target nodes on the distribution of their logical values ​​is then approximately calculated by formula (3) i The logical value probability distribution of node n is then calculated using formula (4) i The logic flip probability of the target node is the AND gate and NOR gate with output logic 1, and the NAND gate and OR gate with output logic 0; in formula (2), ta i Represents the target node to node n in the graph i The influence degree of output 1 or 0 probability, n is the node n i The number of input terminals, pn k -1 quantifies the influence of multiple input paths with the largest number of target nodes on the node Lfp; in formula (3), po i For node n i Output the probability of logic 1 (or 0), tn represents the target node type, i.idg represents node n i In formula (4), Lfp i That is, node n i The probability of logical reversal of

[0017]

[0018] Lf i =po i ×(1-po i ) (4)

[0019] 2.3. The above two new features are combined with the basic structural features in step 1 to obtain the initial feature vector of the node.

[0020] Furthermore, the process of step 3 is as follows:

[0021] 3.1. Aggregate the feature vectors of nodes adjacent to node v through formula (5) and generate a message vector Then, the feature vector of node v is combined through the update function of formula (6) and the message vector Get the updated feature vector of node v Among them, N(v) represents a set of nodes adjacent to node v, AGGREGATE (l) (·) indicates the message function of layer l, COMBINE (l) (·) represents the update function of the lth layer, represents the initial feature vector of node v, Represents the neighbor information of the aggregated node v;

[0022]

[0023] 3.2. Use the message function shown in formula (5) and the update function shown in formula (6) to aggregate and update the neighbor node features within two hops from node v, while enriching the node feature information and avoiding the problems of overfitting and high computational cost. Complete the above aggregation process to obtain the node feature matrix eb.

[0024] Furthermore, the process of step 4 is as follows:

[0025] 4.1. Average Pooling GCN aggregates the feature vector matrix eb after neighbor node feature information to obtain the initial global feature vector, denoted as α0. Then, according to formula (7), each node feature vector is subjected to inner product operation with the current global feature vector α0, and all inner product results are normalized to obtain the weight vector W, which reflects the contribution of each node to the initial global feature vector α0, where ip i Representative node n i The value obtained by the inner product, eb i Representative node n i eigenvector of ; i=1,2,…,N, N is the number of nodes in the graph;

[0026] ip i =eb i ☉α0 (7)

[0027] 4.2. Use formula (8) to convert each node feature vector eb i And the corresponding weight value W i Carry out weighted summation to update the global feature vector, denoted as α1;

[0028]

[0029] 4.3. Repeat the above two steps once to extract the global feature vector that effectively integrates the feature vector information of each node, denoted as α2. Finally, α2 is weightedly integrated with the feature vector eb of each node through formula (9): i To obtain the final node feature vector matrix neb, where k is the ratio of global feature fusion;

[0030] neb=(1-k)×eb+k×α2 (9).

[0031] The process of step 5 is as follows:

[0032] 5.1. Normal node set D n Randomly divide into m equal parts, where m is the number of small batches;

[0033] 5.2. For each of From the HTs node set D t Random sampling is carried out in Place Among them, the requirements The number of nodes in is close to This achieves data balance processing, where j = 1, 2, …, m.

[0034] In the present invention, according to the abnormal performance of HTs nodes in the graph, two new features of gate nodes are extracted based on the deep search strategy and topological logic analysis method to enrich the feature information of circuit nodes; according to the influence of neighbor nodes and global information of the graph on the current node features, a local feature aggregation method based on GCN and a global feature fusion method based on attention mechanism are constructed to improve the expressiveness of circuit node features; in order to solve the impact of unbalanced data on the performance of model recognition of HTs, a data imbalance processing method is constructed based on the idea of ​​stochastic gradient descent and combined with small batch oversampling and undersampling methods to solve the problem of scarcity of HTs nodes in the circuit. Based on the above method, the rapid and effective detection and positioning of HTs in unknown circuits can be effectively realized based on limited known circuits and in a shorter training time.

[0035] In the present invention, firstly, the GL method is used to convert the circuit structure into a graph structure; then, GCN is used to aggregate the neighbor information of the nodes, and the global features of the circuit are fused through the attention mechanism; then, data balancing is performed on the node feature vector set after feature fusion to solve the adverse effects of the small number of HTs nodes on the model performance; finally, the detection and positioning of HTs in unknown circuits are realized based on the balanced training data.

[0036] The beneficial effects of the present invention are mainly manifested in: the two new features of gate nodes extracted based on the deep search strategy and the topological logic analysis method can enrich the feature information of circuit nodes to a great extent, which is conducive to the model distinguishing HTs nodes from normal nodes; the local feature aggregation method based on GCN and the global feature fusion method based on the attention mechanism can enhance the expressiveness of circuit node features, which helps to further increase the distinction of HTs nodes; the constructed data balance processing method can effectively solve the problem of HTs node scarcity. These not only help to accurately detect and locate potential HTs in the circuit, but also ensure good model generalization and robustness, which helps to greatly improve the safety and reliability of hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a flow chart of a hardware Trojan detection and positioning method based on graph convolutional neural network.

[0038] Figure 2 These are the experimental results of the method of the present invention on a large-scale data set. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings.

[0040] Reference Figure 1 and Figure 2 , a hardware Trojan detection and positioning method based on graph convolutional neural network, the method comprising the following steps:

[0041] Step 1: Based on the graph learning (GL) method, the circuit structure is converted into a graph structure, and in the process, the basic structural features of the nodes are extracted, such as node type, in-degree, out-degree, the shortest distance from the node to any original input, and the shortest distance from the node to any original output;

[0042] Step 2: Based on the deep search strategy and topological logic analysis method, two new features Cov and Lfp are constructed to improve the feature information of the circuit nodes. The process is as follows:

[0043] 2.1. Calculate the node n by formula (1) i The number of nodes connected by paths is quantified by n i The connectivity Cov(n i ). A normalization strategy is used to eliminate the adverse effects of scale differences on the results, where i = 1, 2, ..., N, N is the number of nodes in the graph, ∑n from Represents all reachable nodes n in a directed graph i The number of nodes, ∑n to Represents the directed graph from node n i The number of nodes that can be reached by starting, the sum of these two is the number of nodes in the graph that are connected to the target node ni The number of all nodes with connectivity;

[0044]

[0045] 2.2. Calculate node n by formula (2) i The influence of all target nodes on the distribution of their logical values ​​is then approximately calculated by formula (3) i The logical value probability distribution of node n is then calculated using formula (4) i The logic flip probability of the target node is the AND gate and NOR gate with output logic 1, and the NAND gate and OR gate with output logic 0. In formula (2), ta i Represents the target node to node n in the graph i The influence degree of output 1 (or 0) probability, n is the node n i The number of input terminals, pn k -1 quantifies the influence of multiple input paths with the largest number of target nodes on node Lfp. In formula (3), po i For node n i Output the probability of logic 1 (or 0), tn represents the target node type, i.idg represents node n i In formula (4), Lfp i That is, node n i The probability of logical reversal of

[0046]

[0047] Lf i =po i ×(1-po i ) (4)

[0048] 2.3. The above two new features are combined with the basic structural features of step 1 to obtain the initial feature vector of the node;

[0049] Step 3: Based on GCN, aggregate the neighbor features of the node and update the feature information of the node itself to improve the local perception and generalization ability of the node. The process is as follows:

[0050] 3.1. Aggregate the feature vectors of nodes adjacent to node v through formula (5) and generate a message vector Then, the feature vector of node v is combined through the update function of formula (6) and the message vector Get the updated feature vector of node v Among them, N(v) represents a set of nodes adjacent to node v, AGGREGATE (l)(·) indicates the message function of layer l, COMBINE (l) (·) represents the update function of the lth layer, represents the initial feature vector of node v, Represents the neighbor information of the aggregated node v;

[0051]

[0052] 3.2. Aggregate and update the neighbor node features within two hops from node v using the message function shown in formula (5) and the update function shown in formula (6), which enriches the node feature information while avoiding the problems of overfitting and high computational cost. The node feature matrix eb is obtained after completing the above aggregation process.

[0053] Step 4: Use the global feature fusion method based on the attention mechanism to extract and update the global features of the graph, and fuse them with the node feature vector after aggregating neighbor features obtained in step 3. The process is as follows:

[0054] 4.1. Average Pooling GCN aggregates the feature vector matrix eb after neighbor node feature information to obtain the initial global feature vector, denoted as α0. Then, according to formula (7), each node feature vector is subjected to inner product operation with the current global feature vector α0, and all inner product results are normalized to obtain the weight vector W, which reflects the contribution of each node to the initial global feature vector α0, where ip i Representative node n i The value obtained by the inner product, eb i Representative node n i eigenvector of ; i=1,2,…,N, N is the number of nodes in the graph;

[0055] ip i =eb i ☉α0 (7)

[0056] 4.2. Use formula (8) to convert each node feature vector eb i And the corresponding weight value W i Carry out weighted summation to update the global feature vector, denoted as α1;

[0057]

[0058] 4.3. Repeat the above two steps once to extract the global feature vector that effectively integrates the feature vector information of each node, denoted as α2. Finally, α2 is weightedly integrated with the feature vector eb of each node through formula (9): i To obtain the final node feature vector matrix neb, where k is the ratio of global feature fusion, usually set to 0.5.

[0059] neb=(1-k)×eb+k×α2 (9)

[0060] Step 5: Based on the idea of ​​stochastic gradient descent and combined with small batch oversampling and undersampling methods, balance the training data to solve the impact of the scarcity of HTs nodes in the circuit on the model. The process is as follows:

[0061] 5.1. Normal node set D n Randomly divide into m equal parts, where m is the number of small batches;

[0062] 5.2. For each of From the HTs node set D t Random sampling is carried out in Place Among them, the requirements The number of nodes in is close to Thus, data balance processing is achieved, where j = 1, 2, ..., m;

[0063] Step 6. Use the multi-layer perceptron model to train the balanced processed data based on the leave-one-out cross-validation method, and make predictions on unknown circuits to identify potential HTs nodes in the circuit.

[0064] The solution of this embodiment extracts two new features of gate nodes based on the abnormal performance of HTs nodes in the graph, based on the deep search strategy and topological logic analysis method to enrich the feature information of circuit nodes; and based on the influence of neighbor nodes and global information of the graph on the current node features, a local feature aggregation method based on GCN and a global feature fusion method based on the attention mechanism are constructed to improve the expressiveness of circuit node features; in order to solve the impact of unbalanced data on the performance of model recognition of HTs, a data imbalance processing method is constructed based on the idea of ​​stochastic gradient descent and combined with small batch oversampling and undersampling methods to solve the problem of scarcity of HTs nodes in the circuit. Based on the above method, it is possible to effectively realize the rapid and effective detection and positioning of HTs in unknown circuits based on limited known circuits and in a shorter training time.

[0065] In this embodiment, Figure 2 The experimental results of the proposed method on a large-scale data set show that the proposed method has similar performance on 4 EthernetMAC10GE circuits and 2 B19 circuits. The method not only performs well in Acc and Recall indicators, with average values ​​of approximately 100.0% and 95.15% respectively, but also has very good performance in Pre and F1-score indicators, with average values ​​of approximately 91.27% and 93.13% respectively. Compared with the latest similar methods, the performance of this method is better, which verifies its advancement and effectiveness.

[0066] The contents described in the embodiments of this specification are merely enumerations of implementation forms of the inventive concept and are for illustrative purposes only. The protection scope of the present invention should not be considered to be limited to the specific forms described in this embodiment, and the protection scope of the present invention also extends to equivalent technical means that can be thought of by ordinary technicians in this field based on the inventive concept.

Claims

1. A hardware Trojan detection and positioning method based on graph convolutional neural network, characterized in that: The method comprises the following steps: Step 1: Convert the circuit structure into a graph structure based on the graph learning method, and extract the basic structural features of the nodes in the process, namely, the node type, in-degree, out-degree, the shortest distance from the node to any original input, and the shortest distance from the node to any original output; Step 2: Based on the deep search strategy and topological logic analysis method, two new features Cov and Lfp are constructed to improve the feature information of the circuit nodes; Step 3: Aggregate the neighbor features of the node based on GCN and update the feature information of the node itself to improve the local perception and generalization ability of the node; Step 4: Use the global feature fusion method based on the attention mechanism to extract and update the global features of the graph, and fuse them with the node feature vector after aggregating neighbor features obtained in step 3; Step 5: Based on the idea of ​​stochastic gradient descent and combined with small batch oversampling and undersampling methods, the training data is balanced to solve the impact of the scarcity of HTs nodes in the circuit on the model; Step 6. Use the multi-layer perceptron model to train the balanced processed data based on the leave-one-out cross-validation method, and make predictions on unknown circuits to identify potential HTs nodes in the circuit.

2. A method for detecting and locating hardware Trojans based on a graph convolutional neural network as claimed in claim 1, characterized in that the process of step 2 is as follows: 2.

1. Calculate the node n by formula (1) i The number of nodes connected by paths is quantified by n i The connectivity Cov(n i ), a normalization strategy is used to eliminate the adverse effects of scale differences on the results, where i = 1, 2, ..., N, N is the number of nodes in the graph, ∑n from Represents all reachable nodes n in a directed graph i The number of nodes, ∑n to Represents the directed graph from node n i The number of nodes that can be reached by starting, the sum of these two is the number of nodes in the graph that are connected to the target node n i The number of all nodes with connectivity; 2.

2. Calculate node n by formula (2) i The influence of all target nodes on the distribution of their logical values ​​is then approximately calculated by formula (3) i The logical value probability distribution of node n is then calculated using formula (4) i The logic flip probability of the target node is the AND gate and NOR gate with output logic 1, and the NAND gate and OR gate with output logic 0; in formula (2), ta i Represents the target node to node n in the graph i The influence degree of output 1 or 0 probability, n is the node n i The number of input terminals, pn k -1 quantifies the influence of multiple input paths with the largest number of target nodes on the node Lfp; in formula (3), po i For node n i Output the probability of logic 1 (or 0), tn represents the target node type, i.idg represents node n i In formula (4), Lfp i That is, node n i The probability of logical reversal of Lf'p i =after i ×(1-after i )(4) 2.

3. The above two new features are combined with the basic structural features in step 1 to obtain the initial feature vector of the node.

3. A method for detecting and locating hardware Trojans based on a graph convolutional neural network as described in claim 1 or 2, characterized in that: The process of step 3 is as follows: 3.

1. Aggregate the feature vectors of nodes adjacent to node v through formula (5) and generate a message vector Then, the feature vector of node v is combined through the update function of formula (6) and the message vector Get the updated feature vector of node v in, N(v) represents a set of nodes adjacent to node v, AGGREGATE (l) (.) indicates the message function of the layer, COMBINE (l) (.) represents the update function of the ,th layer, represents the initial feature vector of node v, Represents the neighbor information of the aggregated node v; 3.

2. Use the message function shown in formula (5) and the update function shown in formula (6) to aggregate and update the neighbor node features within two hops from node v, while enriching the node feature information and avoiding the problems of overfitting and high computational cost. Complete the above aggregation process to obtain the node feature matrix eb.

4. A method for detecting and locating hardware Trojans based on graph convolutional neural networks as described in claim 1 or 2, characterized in that: The process of step 4 is as follows: 4.

1. Average pooling GCN aggregates the feature vector matrix eb after neighbor node feature information to obtain the initial global feature vector, denoted as α0. Then, according to formula (7), each node feature vector is subjected to inner product operation with the current global feature vector α0, and all inner product results are normalized to obtain the weight vector W, which reflects the contribution of each node to the initial global feature vector α0, where ip i Representative node n i The value obtained by the inner product, eb i Representative node n i eigenvector of ; i = 1, 2, ..., N, where N is the number of nodes in the graph; IP i =eb i ⊙α0 (7) 4.

2. Use formula (8) to convert each node feature vector eb i And the corresponding weight value W i Carry out weighted summation to update the global feature vector, denoted as α1; 4.

3. Repeat the above two steps once to extract the global feature vector that effectively integrates the feature vector information of each node, denoted as α2. Finally, α2 is weightedly integrated with the feature vector eb of each node through formula (9): i To obtain the final node feature vector matrix neb, where k is the ratio of global feature fusion; neb=(1-k)×eb+k×α2 (9).

5. A method for detecting and locating hardware Trojans based on graph convolutional neural networks as described in claim 1 or 2, characterized in that: The process of step 5 is as follows: 5.

1. Normal node set D n Randomly divide into m equal parts, where m is the number of small batches; 5.

2. For each of From the HTs node set D t Random sampling is carried out in Place Among them, the requirements The number of nodes in is close to This achieves data balance processing, where j=1, 2, ..., m.

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