Semiconductor device general modeling method based on weight prediction network optimization

Abstract

The invention discloses a general modeling method for a semiconductor device based on weight prediction network optimization, which is characterized by comprising the following steps of: acquiring original I-V characteristic data of the semiconductor device through actual measurement or TCAD simulation, and modeling I-V characteristics of the semiconductor device by adopting a weight prediction network model; the method comprises the following steps of: constructing and training a weight prediction network model, then converting the weight prediction network model into an SPICE model through a Verilog-A language, finally putting the SPICE model into a test circuit for simulation, and comparing with a TCAD simulation result, specifically comprising the steps of constructing and training the weight prediction network model, and converting the weight prediction network model into the SPICE model. According to the method, a complex data preprocessing process does not need to be carried out, a complex loss function does not need to be designed, the weight prediction network model is converted into a model capable of being used for SPICE simulation, and compared with a traditional neural network model, higher precision can be obtained, and the method is suitable for being applied to SPICE simulation. An efficient and reliable method is provided for academic research and industrial application of circuit design and process collaborative optimization (DTCO) of novel devices.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device modeling, and in particular to a general semiconductor device modeling method based on weight prediction network optimization for SPICE circuit simulation. Background Art

[0002] Semiconductor device modeling is the bridge between integrated circuit design and manufacturing. The commercial BSIM model is suitable for modeling conventional single-gate devices. However, with the advent of multi-gate devices under various advanced processes, the BSIM model is no longer applicable.

[0003] At present, when most researchers model semiconductor devices based on neural network models, they simply fit the transfer characteristics and output characteristics of the devices without considering the transconductance G of the devices. m and output conductance G DS Characteristics fitting, there are also a small number of researchers who have completed ultra-high precision IV characteristics fitting through complex training to achieve the fitting of transconductance and output conductance.

[0004] In the prior art, neural network models are used to model semiconductor devices. Most of them are built by building a fully connected neural network model for regression prediction. Usually, a complex data preprocessing process is required to ensure the convergence of the neural network model in circuit simulation, and a complex loss function needs to be designed to achieve IV characteristics, G m Features and G DS High-precision fitting of characteristics. Summary of the invention

[0005] The purpose of the present invention is to provide a general modeling method for semiconductor devices based on weight prediction network optimization in view of the deficiencies in the prior art. The method adopts a weight prediction network to model the IV characteristics of semiconductor devices, converts the weight prediction network model into a SPICE model through Verilog-A language, finally puts the SPICE model into a test circuit for simulation, and compares the circuit simulation result with the TCAD simulation result. The method can directly use the original IV data for training through the weight prediction network modeling, eliminates the complicated data preprocessing process, reduces the difficulty of model training, improves the accuracy of model prediction, and greatly improves the efficiency of integrated circuit design and manufacturing.

[0006] The specific technical solution for achieving the purpose of the present invention is:

[0007] A general modeling method for semiconductor devices based on weight prediction network optimization is characterized in that the method models the IV characteristics of the device by establishing a weight prediction network model. In the modeling process, the original data of the IV characteristics under a process parameter condition is first used for curve fitting to obtain the initial weight value of each layer of the weight prediction network. Then, the original data of all IV characteristics are used as the training set, and the mean square error is used as the loss function of the weight prediction network model. The learning rate is 10 -5 The Adam algorithm is used as the parameter optimizer of the weight prediction network model for training. Finally, the trained weight prediction network model is converted into a function expression of the drain current, and then the function expression of the drain current is equivalent to a current source controlled by the gate voltage and the drain voltage. Then, the Verilog-A language is used to convert it into a model that can be used for SPICE simulation, and the model is used to build a basic logic gate circuit for test verification.

[0008] The invention discloses a general semiconductor device modeling method based on weight prediction network optimization, which uses a weight prediction network model to model the IV characteristics of the semiconductor device, converts the weight prediction network model into a SPICE model through Verilog-A language, and finally puts the SPICE model into a test circuit for simulation. The modeling method specifically includes the following steps:

[0009] Step 1: Data preparation

[0010] Use Synopsys Sentaurus TCAD software to build a semiconductor device structure model and perform IV characteristic simulation under different process conditions to obtain raw IV characteristic data; First, use Sentaurus Structure Editor to build the device structure and define the size, structure area, doping type, material type, electrode position and grid size; Then, use Sentaurus Device to simulate the IV characteristics of the device, including transfer curves and output curves;

[0011] Step 2: Build a weight prediction network model

[0012] Two neural network models are established for the IV characteristics of semiconductor devices using the Tanh activation function, namely the first neural network and the second neural network. The first neural network is a single hidden layer neural network model that takes process parameters and gate voltage as input and the weight value and bias term in the second neural network as output. The second neural network is a single hidden layer neural network model that takes drain voltage as input and drain current as output. The output layer bias term of the second neural network must meet certain constraints, that is, when the input drain voltage is 0V, the drain current output by the model is 0A.

[0013] Step 3: Training of weight prediction network model

[0014] The constructed weight prediction network model is used to train the IV characteristic data, wherein the training is divided into two steps: the first step is to initialize the weight of the weight prediction network model, and the second step is to train the weight prediction network model;

[0015] Step 4: Convert the weight prediction network model to a SPICE model

[0016] Use Python scripts to extract the bias value of each node in the weight prediction network model and the weight value between nodes, then convert the weight prediction network model into a mathematical expression, and then convert the mathematical expression into a SPICE model using Verilog-A language;

[0017] Step 5: Place the SPICE model into the SPICE simulator for circuit simulation verification.

[0018] Further, the TCAD software described in step 1, the data required for simulation include: device width W, gate length L G , doping type Dope, gate voltage V GS , drain voltage V DS and drain current I DS .

[0019] Furthermore, in step 2, the constraint condition of the second neural network is defined by the following formula (a):

[0020]

[0021] Among them, b2 is the bias term of the output layer node, c i is the weight value between the i-th node in the hidden layer and the output layer node, b 1i is the weight value between the input layer node and the i-th node in the hidden layer.

[0022] Furthermore, in step 3, the weight prediction network model is initialized, that is, the initial weight value of each layer of the weight prediction network is obtained by curve fitting the IV characteristic data under a process parameter condition, and then the original data of all IV characteristics are used as the training set to train the weight prediction network model. The training strategy is: use the mean square error as the loss function of the weight prediction network model, and use a learning rate of 10 -5 The Adam algorithm is used as a parameter optimizer for training the weight prediction network model.

[0023] Furthermore, step 4 converts the weight prediction network model into a mathematical expression, which is a function expression of the drain current, and the independent variables of the function expression are the process parameters, the gate voltage and the drain voltage. The function expression is then equivalent to a current source controlled by the gate voltage and the drain voltage, and then converted into a SPICE sub-circuit equivalent model using the Verilog-A language.

[0024] Furthermore, step 5 is specifically as follows: placing the converted SPICE model into different test circuits, testing the IV characteristics under different process parameters respectively, and using the model to build basic logic gate circuit characteristics and compare them with TCAD simulation results to verify accuracy.

[0025] Compared with the prior art, the present invention has higher IV characteristic fitting accuracy and effectively optimizes the transconductance G of semiconductor devices by using a weight prediction network model. m and output conductance G DS Characteristics, at the same time, the modeling steps of the present invention are simpler, and the original IV data can be used directly for training, which saves the complicated data preprocessing process, reduces the difficulty of model training, converts the weight prediction network model into a model that can be used for SPICE simulation, reduces the cost and time of manual modeling, and provides an efficient and reliable method for academic research and industrial application of circuit design and process coordinated optimization (DTCO) of future new devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 3D schematic diagram of the RFET nanowire structure device according to Example 1 of the present invention;

[0027] Figure 2 2D cross-sectional schematic diagram of the RFET nanowire structure device of Example 1 of the present invention;

[0028] Figure 3 This is a schematic diagram of a weight prediction network model in Example 1 of the present invention;

[0029] Figure 4 The weight prediction network model of embodiment 1 of the present invention and the traditional neural network model predict D NW 6nm, L CG The transfer characteristic curve of the 10nm RFET device is compared with the TCAD simulation data;

[0030] Figure 5 The weight prediction network model of embodiment 1 of the present invention and the traditional neural network model predict D NW 6nm, L CG The output characteristic curve of the 10nm RFET device is compared with the TCAD simulation data;

[0031] Figure 6 The weight prediction network model of embodiment 1 of the present invention and the traditional neural network model predict D NW 6nm, L CG For 10nm RFET device G m Comparison chart of curve and TCAD simulation data;

[0032] Figure 7 The weight prediction network model of embodiment 1 of the present invention and the traditional neural network model predict D NW 6nm, L CG For 10nm RFET device G DS Comparison chart of the curve and TCAD simulation data. DETAILED DESCRIPTION

[0033] The present invention trains the IV characteristics of semiconductor devices in steps through a weight prediction network model, first initializes the weight of the weight prediction network model, then trains the weight prediction network model, and finally converts the trained weight prediction network model into a SPICE model through a Python script for circuit simulation verification. The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0034] The method of the present invention comprises the following steps:

[0035] Step 1: Data Preparation:

[0036] Synopsys Sentaurus TCAD software is used to simulate advanced devices, where Sentaurus Structure Editor is used to build the device structure, including defining the device's size, structural area, doping type, material type, electrode position, and grid size; Sentaurus Device is used to simulate the device's IV characteristics.

[0037] Step 2: Build a weight prediction network model

[0038] Semiconductor device modeling based on weight prediction network model requires the establishment of two neural network models, namely neural network 1 and neural network 2, where neural network 1 is used to predict the weight of neural network model 2. Since the semiconductor device model needs to ensure that the drain current is 0A when the drain voltage is 0V, and the Tanh activation function itself outputs 0 when the input is 0, in the semiconductor device modeling based on weight prediction network model, constraints are usually added to the output layer bias of neural network 2, and Tanh is used as the activation function of the weight prediction network model. Since the drain current is also required to increase with the increase of the drain voltage in semiconductor device modeling, the weight values ​​in neural network 2 are usually required to be greater than 0 when the model is built. The input of neural network 1 is process parameters and gate voltage. The selection of process parameters can be adjusted according to actual modeling requirements. The input of neural network 2 is drain voltage. In order to realize fast simulation in the test circuit after the weight prediction network model is converted into a SPICE model, only one hidden layer is usually selected, and the number of nodes in the hidden layer is determined by the complexity of the training sample. The number of nodes in the output layer of the IV model based on the weight prediction network is usually 1, that is, the drain current value.

[0039] Step 3: Train the weight prediction network model

[0040] The training of the weight prediction network model is usually divided into two steps. The first step is weight initialization, which is a key step before training the weight prediction network model. Reasonable weight initialization can effectively avoid the gradient disappearance or gradient explosion during the training process. The second step is to use the mean square error as the loss function of the weight prediction network model to train the weight prediction network model.

[0041] Step 4: Convert the weight prediction network model to a SPICE model

[0042] After the weight prediction network model training is completed, the Python script is used to extract the bias value of each node of the weight prediction network model and the weight value between the nodes, and then the weight prediction network model is converted into a mathematical expression, and then the mathematical expression is converted into a SPICE model through the Verilog-A language;

[0043] Step 5: Place the SPICE model into the SPICE simulator for circuit simulation verification.

[0044] The data preparation in step 1 generally includes the size parameters or process parameters of the device, the drain current value obtained by simulation and the voltage values ​​of each electrode corresponding thereto.

[0045] The constraint condition of the neural network 2 in step 2 is defined by the following formula (a):

[0046]

[0047] Among them, b2 is the bias term of the output layer node, c i is the weight value between the i-th node in the hidden layer and the output layer node, b 1i is the weight value between the input layer node and the i-th node in the hidden layer.

[0048] The weight initialization in step 3 is a key step before training the weight prediction network model. By curve fitting the IV characteristic data under a process parameter condition, the weight value of each layer of the weight prediction network is obtained, and the weight value is used as the weight initial value of the weight prediction network model, which effectively avoids the gradient disappearance or gradient explosion phenomenon during the training process. In the training process of the weight prediction network model, the original data of all IV characteristics obtained by actual measurement or TCAD simulation is used as the training set to train the weight prediction network model. The training strategy is: use the mean square error as the loss function of the weight prediction network model, and use a learning rate of 10 -5 The Adam algorithm is used as a parameter optimizer for training the weight prediction network model.

[0049] In step 4, the weight prediction network model is converted into a function expression of the drain current, the independent variables of which are the process parameters, the gate voltage and the drain voltage. The function expression is then equivalent to a current source controlled by the gate voltage and the drain voltage. The secondary current source is then converted into a SPICE sub-circuit equivalent model using the Verilog-A language and placed between the drain and the source.

[0050] In step 5, the converted SPICE model is placed in different test circuits to test the IV characteristics under different process parameters respectively, and the basic logic gate circuit characteristics are constructed using the model to compare with the TCAD simulation results to verify the accuracy.

[0051] Example 1

[0052] Step 1: Use TCAD to build a device structure model and perform simulation to obtain data

[0053] See also Figure 1-2 In this embodiment, a new device, a reconfigurable field effect transistor (RFET) nanowire device, is used for modeling. The 3D structure diagram of the RFET nanowire structure device constructed using TCAD is shown in FIG. Figure 1 As shown, its 2D cross-sectional structure is as follows Figure 2 As shown. For RFET nanowire structure devices, take different nanowire diameters D NW , control gate length L CG and polarity gate voltage V PG, where the control gate length is equal to the polarity gate length. When the polarity gate voltage is 1V, the device is N-type, and when the polarity gate voltage is -1V, the device is P-type. The gate isolation layer length L GI The gate oxide thickness is 14nm. OX The gate isolation layer length L is 2.75 nm. GI and gate oxide thickness T OX Other process parameters can also be used as inputs to the model and can be adjusted according to modeling requirements. After determining the required parameters, the TCAD tool is used to simulate the IV characteristics of the device under different parameters and obtain the original data.

[0054] Step 2: Use Tanh activation function to build a single hidden layer weight prediction network model

[0055] See also Figure 3 The weight prediction network model uses the Tanh function as the activation function. The number of input layer nodes of the neural network 1 is 4, corresponding to 4 features, namely, the nanowire diameter D NW , control gate length L CG , polarity gate voltage V PG , control gate voltage V CG ; The middle hidden layer of neural network 1 is selected as 1 layer, with 64 nodes; the number of nodes in the output layer of neural network 1 is three times the number of nodes in the middle hidden layer of neural network 2. The number of nodes in the input layer of neural network 2 is 1, that is, the drain voltage V DS ; The number of nodes in the middle hidden layer of neural network 2 is 5. Through experiments, it is found that when the number of nodes n in the middle hidden layer of neural network 2 is greater than or equal to 5, the accuracy is the highest; the number of nodes in the output layer of neural network 2 is 1, that is, the drain current I DS And the constraints of neural network 2 are defined by the following formula (a):

[0056]

[0057] Among them, b2 is the bias term of the output layer node, c i is the weight value between the i-th node in the hidden layer and the output layer node, b 1i is the weight value between the input layer node and the i-th node in the hidden layer.

[0058] Step 3: Train the constructed weight prediction network

[0059] The training strategy of the weight prediction network model is as follows: In the first step, the weight value of each layer of the weight prediction network is obtained by curve fitting of the IV characteristic data under a process parameter condition, and the weight value is used as the initial weight value of the weight prediction network model, which effectively avoids the gradient disappearance or gradient explosion phenomenon during the training process. In the second step, the original data of all IV characteristics obtained by actual measurement or TCAD simulation are used as the training set to train the weight prediction network model. The training strategy is: use the mean square error as the loss function of the weight prediction network model, and use a learning rate of 10 -5 The Adam algorithm is used as a parameter optimizer for training the weight prediction network model.

[0060] Step 4: Convert the weight prediction network model to a SPICE model

[0061] The weight prediction network model is extracted using Python scripts and converted into a function expression of drain current by mathematical methods. The independent variables of the function expression are process parameters, gate voltage, and drain voltage. The function expression is then equivalent to a current source controlled by gate voltage and drain voltage, and then converted into a SPICE subcircuit equivalent model using Verilog-A language. For the convenience of SPICE simulation verification, when converting to a SPICE model, dimensional parameters or process parameters such as nanowire diameter and gate length can be set as parameters in the SPICE model file in nanometers. In the test circuit, D NW Set to 6, which means the diameter of the nanowire structure is 6nm. CG A value of 10 indicates that the control gate length of the device is 10 nm.

[0062] Step 5: Place the SPICE model into the SPICE simulator for circuit simulation verification.

[0063] The converted SPICE model is placed in different test circuits to test the IV characteristics under different process parameters. The model is used to build basic logic gate circuit characteristics and compare them with TCAD simulation results to verify accuracy.

[0064] See also Figure 4 , from the weight prediction network model and the traditional neural network model prediction D NW 6nm, L CG By comparing the transfer characteristic curves of a 10nm RFET device, it was found that the error of the weight prediction network model prediction value was reduced from 1.67% to 0.11% compared with the traditional neural network model prediction value, which means that the weight prediction network model fits the transfer characteristics of the device more effectively.

[0065] See also Figure 5 , from the weight prediction network model and the traditional neural network model prediction DNW 6nm, L CG By comparing the output characteristic curves of the 10nm RFET device, it was found that the error of the weight prediction network model prediction value was reduced from 1.94% to 0.08% compared with the traditional neural network model prediction value, which means that the weight prediction network model fits the output characteristics of the device more effectively.

[0066] See also Figure 6 , from the weight prediction network model and the traditional neural network model prediction D NW 6nm, L CG By comparing the transconductance characteristic curve of a 10nm RFET device, it was found that the error of the weight prediction network model prediction value was reduced from 1.06% to 0.18% compared with the traditional neural network model prediction value, which means that the weight prediction network model fits the transconductance characteristics of the device more effectively.

[0067] See also Figure 7 , from the weight prediction network model and the traditional neural network model prediction D NW 6nm, L CG By comparing the output conductance curve of a 10nm RFET device, it was found that the output conductance predicted by the weight prediction network model was discontinuous compared with the traditional neural network model, while the output conductance predicted by the weight prediction network model was continuous with an error of 6.93%, which means that the weight prediction network model fits the output conductance characteristics of the device more effectively.

[0068] The above embodiments are only preferred implementations of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent implementation of the present invention and any changes made through non-creative work on this basis should be included in the scope of the claims of the present invention.

Claims

1. A general modeling method for semiconductor devices based on weight prediction network optimization, characterized in that: The modeling method specifically comprises the following steps: Step 1: Data preparation Use Synopsys Sentaurus TCAD software to build a semiconductor device structure model and perform IV characteristic simulation under different process conditions to obtain raw IV characteristic data; First, use Sentaurus Structure Editor to build the device structure and define the size, structure area, doping type, material type, electrode position and grid size; Then, use Sentaurus Device to simulate the IV characteristics of the device, including transfer curves and output curves; Step 2: Build a weight prediction network model Two neural network models are established for the IV characteristics of semiconductor devices using the Tanh activation function, namely the first neural network and the second neural network. The first neural network is a single hidden layer neural network model that takes process parameters and gate voltage as input and the weight value and bias term in the second neural network as output. The second neural network is a single hidden layer neural network model that takes drain voltage as input and drain current as output. The output layer bias term of the second neural network must meet certain constraints, that is, when the input drain voltage is 0V, the drain current output by the model is 0A. Step 3: Training of weight prediction network model The constructed weight prediction network model is used to train the IV characteristic data, wherein the training is divided into two steps: the first step is to initialize the weight of the weight prediction network model, and the second step is to train the weight prediction network model; Step 4: Convert the weight prediction network model to a SPICE model Use Python scripts to extract the bias value of each node in the weight prediction network model and the weight value between nodes, then convert the weight prediction network model into a mathematical expression, and then convert the mathematical expression into a SPICE model using Verilog-A language; Step 5: Place the SPICE model into the SPICE simulator for circuit simulation verification.

2. The general modeling method for semiconductor devices based on weight prediction network optimization according to claim 1, characterized in that: The TCAD software described in step 1, the data required for simulation include: device width W, gate length L G , doping type Dope, gate voltage V GS , drain voltage V DS and drain current I DS .

3. The general modeling method for semiconductor devices based on weight prediction network optimization according to claim 1, characterized in that: Step 2: The constraints of the second neural network are defined by the following formula (a): Among them, b2 is the bias term of the output layer node, c i is the weight value between the i-th node in the hidden layer and the output layer node, b 1i is the weight value between the input layer node and the i-th node in the hidden layer.

4. The general modeling method for semiconductor devices based on weight prediction network optimization according to claim 1, characterized in that: In step 3, the weight prediction network model is initialized, that is, the initial weight value of each layer of the weight prediction network is obtained by curve fitting the IV characteristic data under a process parameter condition, and then the original data of all IV characteristics are used as the training set to train the weight prediction network model. The training strategy is: use the mean square error as the loss function of the weight prediction network model, and use a learning rate of 10 -5 The Adam algorithm is used as a parameter optimizer for training the weight prediction network model.

5. The general modeling method for semiconductor devices based on weight prediction network optimization according to claim 1, characterized in that: Step 4 converts the weight prediction network model into a mathematical expression, which is a function expression of the drain current, and the independent variables of the function expression are the process parameters, the gate voltage and the drain voltage. The function expression is then equivalent to a current source controlled by the gate voltage and the drain voltage, and then converted into a SPICE sub-circuit equivalent model using the Verilog-A language.

6. The general modeling method for semiconductor devices based on weight prediction network optimization according to claim 1, characterized in that: The step 5 is specifically as follows: placing the converted SPICE model into different test circuits, testing the IV characteristics under different process parameters respectively, and using the model to build basic logic gate circuit characteristics and compare them with TCAD simulation results to verify accuracy.

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