Integrated circuit design method and device based on large proxy iteration training model

Abstract

The invention provides an integrated circuit design method and device based on an agent iteration training large model. The method comprises the steps that integrated circuit design requirements described by adopting a natural language are acquired; taking an instruction for generating an integrated circuit design demand as a question, taking a knowledge base as a knowledge reference, and inputting the question and the knowledge reference into a question and answer model based on a large language model to obtain instruction description; the instruction description is input into a code generation model based on a large language model, intermediate HDL codes are obtained and scored, grammar scores are obtained, a loss function is constructed based on the intermediate HDL codes and the grammar scores of the intermediate HDL codes, and the code generation model is trained; scoring the power consumption, the performance and the area of the middle HDL code through a comprehensive tool to obtain a performance score, constructing a loss function based on the middle HDL code and the performance score thereof, and training a question and answer model; and inputting the target circuit design requirement into the trained question and answer model, and inputting the obtained instruction description into the trained code generation model to obtain a final HDL code.

Description

Technical Field

[0001] The present invention relates to the technical field of computer-aided chip design, large model application, and electronic design automation (EDA), and in particular to an integrated circuit design automation method, device, storage medium, electronic device, and computer program product based on a multi-agent iterative training large model. Background Art

[0002] Electronic design automation (EDA) is used for integrated circuit design, including requirements analysis, function definition, design, synthesis, verification, layout, routing, layout and design rule checking.

[0003] Tools such as question-answering models, code generation models, synthesis tools, and syntax checkers are called “agents” because they act as autonomous entities or “agents” in the design workflow to perform specific tasks or make decisions on behalf of users or systems. In the field of artificial intelligence, the term “agent” generally refers to an entity that autonomously achieves a specific goal by processing inputs and producing outputs. These agents operate in complex environments and make decisions or perform actions based on predefined rules or learned knowledge. In the context of chip design, question-answering models act as agents by interpreting the user’s query and providing answers based on available data or knowledge.

[0004] Code generation models act as agents that automate the traditional manual coding process by taking in design specifications or high-level descriptions and converting them into code (such as hardware description languages ​​like Verilog or VHDL). Synthesis tools are agents that convert high-level design code into low-level representations and optimize the design to meet requirements such as performance, area, or power consumption, which is critical in chip design. Syntax checkers act as agents that ensure that the code complies with the grammatical rules of the programming or hardware description language by analyzing the generated code to find errors or inconsistencies. These systems are called agents because they interact with the design environment and take actions based on inputs (user instructions, design specifications, etc.) without frequent direct human intervention. Their ability to make autonomous decisions and perform tasks in various stages of chip design (from code generation to verification) enables them to be called "agents." In summary, the above tools are called agents because they are able to perform various tasks autonomously and make decisions on behalf of the user or system during the design process.

[0005] Large Language Models (LLMs), such as GPT-4, have made remarkable achievements in the field of natural language processing and have shown great potential in code generation in C, Python, etc. Large Multimodal Models (LMMs) have also made breakthrough progress in integrating the processing of multiple types of data. The application of LLMs and LMMs in the automated hardware design process has achieved initial success and has the potential to completely change the traditional chip design method. By enhancing the automation of the EDA process, these technologies are gradually driving the transition of chip design to "full automation".

[0006] Traditional manual coding of hardware description language (HDL) code is not only time-consuming but also prone to errors. At present, LLMs still face challenges in generating HDL code, such as compilation failure, functional errors, and power, performance, and area (PPA) optimization. The application of large model technologies such as iterative optimization, model fine-tuning, and multi-agent collaboration in EDA has not been fully explored. It is urgent to combine emerging technologies to improve the accuracy of EDA-specific models to a level that can be used in practice.

[0007] Expert question-and-answer systems based on large models can reduce design errors and rework by providing accurate technical support and solutions instantly, reducing the time spent looking for help and decisions based on wrong assumptions. However, current EDA expert question-and-answer systems have not been effectively combined with HDL generation.

[0008] For example, the prior art uses the compilation errors and simulation information in the Verilog code generated by LLMs as feedback to add prompt words to improve the code generation performance, but does not update the optimization model. Or LLM training with code quality feedback is proposed, but there is no iterative optimization model, which limits the model performance and requires more training data. Or it is proposed to guide the Transformer to generate compilable, functionally correct and PPA-optimized code by integrating Monte Carlo tree search, but it takes a long time because a tree search needs to be performed on each new module generated. The present invention further proposes to iteratively fine-tune the LLMs using the supervisory feedback provided by the EDA tool and update its parameters to generate a chip design with the desired PPA.

[0009] The applicant found the following situation in the process of implementing automated integrated circuit design during the research on large model-assisted chip design:

[0010] (1) Little data: Most high-quality register transfer level (RTL) codes are not publicly available, which results in a lack of available high-quality datasets in key technical areas such as circuit synthesis and physical design. In addition, the performance differences of integrated circuit processes and the confidentiality of process libraries further increase the difficulty of dataset construction. Existing benchmarks typically only evaluate the performance of models in generating single-file Verilog code, which cannot accurately reflect the real-world scenario of generating code in large and complex code bases. The limited number of samples in these benchmarks limits the diversity of tasks and may cause models to rely too much on specific solutions rather than truly generalize.

[0011] (2) Auxiliary tools: In the field of chip design, there are a large number of compilation and simulation tools that can provide automatic feedback, eliminating the need for manual feedback, which is an advantage in this field.

[0012] (3) The quality of the natural language description of HDL code has a great impact on the accuracy of code generation. Summary of the invention

[0013] Aiming at the problems of insufficient code generation accuracy, insufficient PPA performance and insufficient training data in large model-assisted chip design, the present invention proposes an integrated circuit design automation method and device based on a multi-agent iterative training large model.

[0014] Specifically, in view of the shortcomings of existing technologies, such as Figure 8 As shown, the present invention proposes an integrated circuit design method based on agent iterative training large model, comprising:

[0015] A construction step is to construct a knowledge base in the EDA field to obtain integrated circuit design requirements described in natural language; an instruction for generating the integrated circuit design requirements is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description;

[0016] The training step includes inputting the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scoring the intermediate HDL code to obtain a syntax score, constructing a loss function based on the intermediate HDL code and its syntax score, and training the code generation model; scoring the power consumption, performance, and area of ​​the intermediate HDL code through a synthesis tool to obtain a performance score, constructing a loss function based on the intermediate HDL code and its performance score, and training the question-answering model; and after each round of training, using the obtained new model to regenerate the HDL code for the next round of training and score it, thereby iteratively improving the model performance; in each round of generation, screening out non-self-contained HDL code or assigning it a low score to guide the model to generate high-quality self-contained HDL code;

[0017] The design steps are as follows: input the target circuit design requirements into the trained question-answering model, and input the obtained instruction description into the trained code generation model to obtain the final HDL code, and use the HDL code as the preliminary integrated circuit design result of the target circuit design.

[0018] The integrated circuit design method based on agent iterative training large model, wherein the training step includes:

[0019] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0020] or

[0021] The training step includes: calculating the power consumption, performance and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

[0022] The integrated circuit design method based on agent iterative training large model, wherein the teacher model, question-answering model and code generation model are usable open source or commercial models, an implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0023] like Fig. 9 As shown, the present invention also proposes an integrated circuit design device based on agent iterative training large model, which includes:

[0024] A construction module is provided to construct a knowledge base in the EDA field, and obtain integrated circuit design requirements described in natural language; an instruction for generating the integrated circuit design requirements is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description;

[0025] The training module inputs the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, constructs a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code through a synthesis tool to obtain a performance score, constructs a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model;

[0026] The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

[0027] The integrated circuit design device based on agent iterative training large model, wherein the training module includes:

[0028] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0029] or

[0030] The training module includes: calculating the power consumption, performance and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

[0031] The integrated circuit design device based on the agent iterative training large model, wherein the teacher model, question-answering model and code generation model are usable open source or commercial models, an implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0032] The present invention also proposes an electronic device, which includes the integrated circuit design device based on the agent iterative training large model.

[0033] The electronic device described above may be connected to an information display device, and the information display device is used to display the integrated circuit design results using display parameters and attributes set by a user or through an artificial intelligence model.

[0034] The present invention also proposes a storage medium for storing a computer program for executing any of the integrated circuit design methods based on agent iterative training large models.

[0035] The present invention also provides a computer program product, comprising a computer program, wherein the steps of any of the methods are implemented when the computer program is executed by a processor.

[0036] It can be seen from the above scheme that the advantages of the present invention are: reducing the amount of training data and improving the accuracy of model code generation and PPA quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a flow chart of an embodiment of the present invention;

[0038] Figure 2Generate large model iterative tuning diagrams for Verilog code;

[0039] Figure 3 Iteratively tune graphs for large question-answering models;

[0040] Figure 4 A schematic diagram of an implementation method for iterative tuning of large models for Verilog code generation;

[0041] Figure 5 This is a comparison chart of the model effects;

[0042] Figure 6 A graph showing the relationship between the number of iterations and the model effect;

[0043] Figure 7 The architecture diagram of the EDA question-answering model for retrieval enhancement;

[0044] Figure 8 It is the overall flow chart of the present invention;

[0045] Fig. 9 It is a module diagram of the device of the present invention;

[0046] Fig.10 This is a schematic diagram of the structure of a first electronic device of the present invention;

[0047] Fig.11 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0048] Fig.12 is a schematic structural diagram of a second electronic device of the present invention;

[0049] Fig.13 This is a schematic diagram of the screening code.

[0050] Reference numerals:

[0051] A-First electronic device;

[0052] B-IC design device based on agent iterative training large model;

[0053] C-data acquisition equipment;

[0054] D-information display device;

[0055] 1000 - second electronic device;

[0056] Ⅰ-computational unit;

[0057] II-ROM;

[0058] III-RAM;

[0059] IV-bus;

[0060] V-interface;

[0061] VI - input unit;

[0062] VII-output unit;

[0063] VIII- Storage medium;

[0064] Ⅸ-Communication unit. DETAILED DESCRIPTION

[0065] It should be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0066] Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0067] The processor described in the present invention is the control center of the electronic device, which can be a processor or a general term for multiple processing elements. For example, it can be one or more central processing units (CPUs), or application specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs).

[0068] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0069] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smart phones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0070] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0071] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0072] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0073] It should also be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0074] In the present invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0075] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0080] The present invention proposes solutions based on the above situation, including:

[0081] (1) In terms of model optimization, it is necessary to make full use of existing simulation tools to improve algorithms to reduce data requirements and optimize efficiency, thereby improving the correctness of HDL code generation and further improving performance to achieve the best in terms of power, performance, and area.

[0082] (2) Retrieval-Augmented Generation (RAG) technology improves code quality by enhancing the accuracy of question descriptions in the question-answering model. In the RAG retrieval-enhanced EDA question-answering model, a domain-adaptive algorithm is developed to enable the model to provide accurate and relevant answers in the chip design field, thereby improving code generation quality.

[0083] Therefore, the present invention proposes an integrated circuit design automation method and system based on a multi-agent iterative training large model to improve the accuracy of hardware description language (HDL) code generation and optimize performance, power consumption and area (PPA) indicators. The method uses automated tools such as syntax checkers and synthesis tools (regarded as agents) to iteratively train large models. In each iteration cycle, samples are extracted from the model trained in the previous cycle and used to train the current cycle, thereby minimizing the mismatch between the model and the training samples. In addition, a plug-and-play data filtering strategy is introduced to ensure the quality of the generated code and allow the model to explore in a wider generation space and receive more comprehensive feedback. In the instruction part, the professionalism of the instructions is improved by combining the question-and-answer large model with the EDA knowledge base, and the question-and-answer large model is iteratively optimized through relevant tools. Through the above-mentioned iterative method, the system improves the professionalism and practicality of the generated code, making the design process more efficient and automated. Specifically, the present invention includes the following key technical points:

[0084] Key point 1, question-answering model and code generation model, both are large language models, open source code generation models such as DeepSeek, open source question-answering models such as Llama3. Figure 1 As shown in the figure, the syntax checking tool PyVerilog is used to check the syntax correctness of the hardware description language Verilog code generated by the code generation model, and the PPA is calculated using comprehensive tools such as DC. The PPA is used as a supervisory signal to iteratively train the Verilog code generation model to improve the accuracy and PPA quality of the model-generated code. The model performance is gradually improved by performing multiple rounds of iterative cycles of generating data-syntax checking-training models. The supervisory signal can be provided by only one tool, or by combining the supervisory signals of multiple tools.

[0085] Calculation of loss function: You can use the teacher model to generate code to provide a supervisory signal to calculate the loss function, or you can use only the syntax checker and synthesis tool to calculate the loss function without using the teacher model.

[0086] The loss function consists of two parts, cross entropy loss and ranking loss.

[0087]

[0088] The cross entropy loss is obtained by calculating the cross entropy between the model generation results and the answers generated by the teacher model.

[0089] The calculation of the ranking loss requires the use of feedback from a grammar checker or a comprehensive tool to encourage the model to generate higher quality answers. First, the code is scored based on the tool. Taking the grammar checker as an example, if the grammar is correct, the score is 1. If the grammar is wrong, the score is between 0 and 1 based on the Rouge-L indicator between the code and the reference code generated by the teacher model. If a comprehensive tool is used, the PPA performance is used as the score. The better the performance, the higher the score. The specific ranking loss calculation formula is as follows:

[0090]

[0091] α and β are hyperparameters. z represents the score. p represents the log-likelihood of the generated answer:

[0092] s stands for design instructions and a stands for answer.

[0093] According to the calculation formula of ranking loss, if the probability corresponding to the low-scoring answer is higher than that of the high-scoring answer, the loss function is positive and the model will automatically perform gradient descent optimization.

[0094] Key point 2, such as Figure 3As shown in the figure, the Verilog code generated by the large model is checked for syntax correctness using syntax checking tools such as PyVerilog, and PPA is calculated using comprehensive tools such as DC, which is used as a supervisory signal. The higher the PPA performance, the higher the score. If the probability of generating a high-scoring answer is low, the model will automatically optimize according to the ranking loss to increase the probability of answering a high-scoring answer. The instruction description generated by the question-answering large model is iteratively trained based on the supervisory signal to improve the professionalism of the instruction description generation, thereby improving the quality of code generation.

[0095] The instruction description is the function that the RTL code needs to implement. For example, the instruction of a 4-bit full adder is as follows: Implement a 4-bit adder with full adders. The output sum should include the overflow bit.

[0096] Key point 3: Before using syntax checkers and synthesis tools to calculate PPA, filtering out low-quality code can effectively improve the model training effect. Here, filtering out low-quality code means filtering out non-self-contained modules in the reference code generated by the teacher model, that is, the modules in the code cannot contain instantiations of other modules. For example, you need to delete Fig.13 The code shown here is because the external module of full_adder is instantiated in the module. Our model focuses on generating self-contained code. At the same time, for the non-self-contained code generated by the student model (the model to be trained), we score it as -1, so as to suppress the network from generating corresponding code through the sorting loss.

[0097] In order to make the above features and effects of the present invention more clearly and understandably described, embodiments are given below and described in detail with reference to the accompanying drawings. This specification discloses one or more embodiments that include the features of the present invention. The disclosed embodiments are only for illustration. The scope of protection of the present invention is not limited to the disclosed embodiments, and the present invention is defined by the attached claims.

[0098] The overall flow chart of this application is as follows Figure 1 shown.

[0099] EDA knowledge base: systematically collects all kinds of knowledge in the EDA field, including but not limited to design specifications, best practices, FAQs, and technical documents. Build a knowledge base in the EDA field, systematically organize and present the collected knowledge points, and facilitate query and use.

[0100] Table 1 Multimodal information of EDA knowledge base:

[0101]

[0102] The present invention adopts Figure 7 The RAG retrieval enhancement technology shown in the figure, based on the RAG retrieval enhancement, the implementation of the EDA question-answering model includes: using retrieval enhancement to generate the RAG method to improve the accuracy of question answers. First, collect and organize data such as internal design documents to create a comprehensive knowledge base, and classify, annotate and index the data for effective retrieval. Secondly, analyze the engineer's query and the content in the knowledge base through language model training, intent recognition, entity extraction and question parsing.

[0103] Syntax checker: For Verilog code generated by large models, the syntax check tool PyVerilog is used to check the syntax correctness, and it is used as a supervisory signal to iteratively train the model to improve the accuracy of the model-generated code. Through multiple rounds of iterative cycles of generating data-syntax checking-training models, the user instructions input in each round are the same, and the model performance is gradually improved. In addition to full adder instructions, user instructions can also be state machine instructions:

[0104] This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-highsynchronous reset to state OFF.

[0105] / / OFF(out=0)--j=0-->OFF

[0106] / / OFF(out=0)--j=1-->ON

[0107] / / ON(out=1)--k=0-->ON

[0108] / / ON(out=1)--k=1-->OFF

[0109] And the reverse vector instruction:

[0110] Build a circuit that reverses the byte order of a 32-bit vector.

[0111] Synthesis tool: The synthesis tool Design Compiler calculates the PPA indicators: performance, power consumption, and area; uses them as supervision signals to iteratively train the model, guide the Verilog code generation model, optimize the design quality, and make the generated code design optimized in terms of performance, power, and area, and practical in real hardware design.

[0112] An iterative training scheme. Since the teacher model can only provide guidance in the text sense (cross entropy loss), and the teacher model is often closed source, such as GPT-3.5, it is not conducive to deployment in a production environment in reality and may result in expensive costs. Therefore, the present invention combines the data generated by the model itself and the data generated by the teacher model to train the model, and uses the trained model to update the training data to form an iterative loop. The training scheme of the present invention combines text and tool feedback (ranking loss) to make the trained student model more suitable for RTL code generation.

[0113] Furthermore, we introduced data screening strategies to improve data quality;

[0114] When using a stronger base model, the teacher model is no longer capable of providing guidance. In this case, we abandon the teacher model and only use the feedback signal provided by the grammar checker to further improve the generation accuracy.

[0115] In each iteration, the model generates K-1 different codes for each instruction, plus one code generated by the teacher model, so there are K codes for each instruction. Each code is input into the grammar checker for scoring, with a score of 1 for grammatically correct codes and a score of 0-1 for grammatically incorrect codes based on their similarity to the code generated by the teacher model. The model is trained using instruction-code pairs and their corresponding scores to make the model generate high-scoring answers with as high a probability as possible. When the model converges, the updated model is used to continue generating code and the training process is repeated.

[0116] Through the above iterative process, the model can continuously update the training data and use better data to improve performance. Moreover, since most of the data is generated by the model itself, the error caused by the deviation between the data distribution and the model distribution is alleviated, making the optimization direction more accurate.

[0117]

[0118] As can be seen from the table above, relying solely on the iterative training method, our model surpasses the baseline method with a small number of reference samples. Compared with GPT-3.5, our model shows significant advantages and is close to the level of GPT4. According to further experimental results, by introducing a data screening mechanism, our model achieves a Pass@1 accuracy of 45.5% on VerilogEval-Human with only 7B parameters, surpassing GPT4.

[0119] Experiments have shown that the iterative training method can gradually reduce the loss function and improve the model performance by regenerating training samples. Figure 5 As shown in Figure 1, although the loss function has reached convergence within each round of iteration, the loss function continues to decrease in the next round of iteration due to the new supervision signals brought by the regenerated samples.

[0120] Figure 6 It shows that as the number of iterations increases, the effect of our model shows a trend of first increasing and then decreasing. The increasing stage shows that iterative training can significantly improve model performance by continuously generating new training samples. However, as the iterations continue, the model overfits, so the performance decreases. This reminds us to grasp the appropriate number of iterations when using it to avoid overfitting.

[0121] On the basis of iterative training, we further significantly improved the model capabilities by introducing a data screening mechanism. By analyzing the data generated by the model, we found that the model often generates some irrelevant modules (if the code contains references and instantiations to external modules, the sample is directly deleted and does not enter the training set). We hope that the model can focus on the high-quality generation of a single module. Therefore, we introduced a data screening mechanism in the fine-tuning stage to directly remove samples containing redundant modules in the code generated by the teacher model. For samples containing redundant modules generated by the model to be trained, negative scores are assigned to them in the scoring stage to suppress the model from generating corresponding code.

[0122] By simply introducing a data screening mechanism, the model can achieve a single-shot generation accuracy of 43% after a single round of training. Combined with the iterative training strategy proposed earlier, the accuracy on the test benchmark is further improved to 45%, surpassing GPT4. The size of the model we use is only 7B, much smaller than the GPT series.

[0123] To further improve performance, we switched to the 16B base model for fine-tuning. Since the 16B model capability has surpassed the teacher model GPT-3.5, we gave up using the reference data from the teacher model and only trained with the feedback provided by the syntax checker. The experimental results show that the single-shot accuracy of the code generated by the model has increased to 50.6%. This proves that when there is a lack of a sufficiently strong teacher model, we can use Verilog's related code tools to provide feedback signals, which is of great significance in the context of the increasingly powerful basic model capabilities.

[0124] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0125] like Fig. 9 As shown, the present invention also proposes an integrated circuit design device based on agent iterative training large model, which includes:

[0126] A construction module is provided to construct a knowledge base in the EDA field, and obtain integrated circuit design requirements described in natural language; an instruction for generating the integrated circuit design requirements is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description;

[0127] The training module inputs the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, constructs a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code through a synthesis tool to obtain a performance score, constructs a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model;

[0128] The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

[0129] The integrated circuit design device based on agent iterative training large model, wherein the training module includes:

[0130] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0131] The integrated circuit design device based on the agent iterative training large model, wherein the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0132] like Fig.10 As shown, the present invention further proposes a first electronic device A in another embodiment, including the above-mentioned integrated circuit design device based on agent iterative training large model.

[0133] like Fig.11 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect integrated circuit design requirements, and the information display device D is used to display the integrated circuit design results analyzed by the present invention.

[0134] The information display device D can sort and process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll and play, etc. The user is presented with the key information specified by the user, and the user can understand the information more promptly without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present rich and necessary key information to the user.

[0135] The present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the integrated circuit design method based on the agent iterative training large model provided by the above-mentioned methods.

[0136] The present invention also proposes a storage medium VIII in another embodiment for storing a computer program for executing the integrated circuit design method based on the agent iterative training large model. It should be understood that the storage medium in the embodiment of the present invention can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0137] Fig.12 A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same or different from the first electronic device A.

[0138] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. In RAM III, various programs and data required for the operation of the device 1000 can also be stored. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0139] A plurality of components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard, a mouse, etc.; an output unit VII, such as various types of displays, speakers, etc.; a storage medium VIII, such as a disk, an optical disk, etc.; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0140] The computing unit I may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S3. For example, in some embodiments, the method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via ROM II and / or a communication unit IX. When the computer program is loaded into RAM III and executed by the computing unit I, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit I may be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0141] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. An integrated circuit design method based on agent iterative training large model, characterized in that: include: Construction steps,build a knowledge base in the EDA field to obtain integrated circuit design requirements described in natural language; The instruction for generating the integrated circuit design requirement is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description; The training step includes inputting the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scoring the intermediate HDL code to obtain a syntax score, constructing a loss function based on the intermediate HDL code and its syntax score, and training the code generation model; scoring the power consumption, performance, and area of ​​the intermediate HDL code through a synthesis tool to obtain a performance score, constructing a loss function based on the intermediate HDL code and its performance score, and training the question-answering model; and after each round of training, using the obtained new model to regenerate the HDL code for the next round of training and score it, thereby iteratively improving the model performance; in each round of generation, screening out non-self-contained HDL code or assigning it a low score to guide the model to generate high-quality self-contained HDL code; The design steps are as follows: input the target circuit design requirements into the trained question-answering model, and input the obtained instruction description into the trained code generation model to obtain the final HDL code, and use the HDL code as the preliminary integrated circuit design result of the target circuit design.

2. The integrated circuit design method based on agent iterative training large model as claimed in claim 1, characterized in that: The training steps include: The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1. or The training step includes: calculating the power consumption, performance and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

3. The integrated circuit design method based on agent iterative training large model as claimed in claim 2, characterized in that: The teacher model, question-answering model and code generation model are usable open source or commercial models. An implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

4. An integrated circuit design device based on agent iterative training large model, characterized in that: include: Building modules, constructing a knowledge base in the EDA field, and obtaining integrated circuit design requirements described in natural language; The instruction for generating the integrated circuit design requirement is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description; The training module inputs the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, builds a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code through a synthesis tool to obtain a performance score, builds a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model; after each round of training, regenerates the HDL code for the next round of training using the obtained new model and scores it, thereby iteratively improving the model performance; during each round of generation, screens out non-self-contained HDL code or assigns it a low score to guide the model to generate high-quality self-contained HDL code; The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

5. The integrated circuit design device based on agent iterative training large model as claimed in claim 4, characterized in that: This training module includes: The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1. or The training module includes: calculating the power consumption, performance and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

6. The integrated circuit design device based on agent iterative training large model as claimed in claim 5, characterized in that: The teacher model, question-answering model and code generation model are usable open source or commercial models. An implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

7. An electronic device, characterized in that: It includes an integrated circuit design device based on agent iterative training large model as described in claims 4-6.

8. The electronic device according to claim 7, characterized in that: The electronic device may be connected to an information display device, which is used to display the integrated circuit design results using display parameters and attributes set by a user or through an artificial intelligence model.

9. A storage medium for storing a computer program for executing the integrated circuit design method based on agent iterative training of a large model as described in any one of claims 1 to 3.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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