In-memory computing device

Abstract

The invention discloses an in-memory computing device. The in-memory computing device comprises a plurality of first processing modules and a second processing module, each first processing module comprises a first storage and calculation unit, a comparison unit and a second storage and calculation unit; the first storage and calculation unit, the comparison unit and the second storage and calculation unit are connected in series; the first storage and calculation unit is used for storing the first weight coefficient and the first bias coefficient, and processing the first data based on the first weight coefficient and the first bias coefficient to obtain second data; the comparison unit is used for comparing the second data with a preset value and outputting a maximum value between the second data and the preset value based on a comparison result; the second storage and calculation unit is used for storing a second weight coefficient and a second bias coefficient, and processing the maximum value output by the comparison unit based on the second weight coefficient and the second bias coefficient to obtain third data; and the second processing module is used for performing addition processing on the plurality of third data output by the plurality of first processing modules.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to an in-memory computing device. Background Art

[0002] As a representative machine learning algorithm in the current field of artificial intelligence, Deep Neural Network (DNN) has demonstrated powerful data processing capabilities in application fields such as visual systems, speech recognition, and natural language processing. Its core is to simulate the activation function of neurons in neural networks. By introducing nonlinear functions as activation functions, DNN can better approximate complex functions or mappings. With the introduction of complex activation function syntax, DNN has higher storage density and computational density. The time to run these complex activation functions takes up more than half of the total execution time, making the execution efficiency of the activation function low, which seriously affects the network's operating efficiency and processing results.

[0003] Existing methods to improve the execution efficiency of activation functions can start from hardware or the function itself. In terms of hardware, it is achieved by customizing different hardware circuits for special activation functions, but this method is too expensive and has poor versatility; in terms of the function itself, the lookup table method and piecewise linear approximation method are usually used, but executing the activation function through these methods still generates high power consumption and occupies more circuit area, making the activation function not well supported by hardware. Summary of the invention

[0004] In order to solve the existing technical problems, an embodiment of the present invention provides an in-memory computing device.

[0005] To achieve the above-mentioned purpose, the in-memory computing device of the embodiment of the present invention is implemented as follows:

[0006] An embodiment of the present invention provides an in-memory computing device, the device comprising: a plurality of first processing modules and a second processing module; each first processing module comprises: a first storage computing unit, a comparison unit and a second storage computing unit; the first storage computing unit, the comparison unit and the second storage computing unit are connected in series; wherein,

[0007] The first storage and calculation unit is used to store a first weight coefficient and a first bias coefficient, and process the first data based on the first weight coefficient and the first bias coefficient to obtain second data;

[0008] The comparison unit is used to compare the second data with a preset value, and output a maximum value between the second data and the preset value based on the comparison result;

[0009] The second storage and calculation unit is used to store a second weight coefficient and a second bias coefficient, and process the maximum value output by the comparison unit based on the second weight coefficient and the second bias coefficient to obtain third data;

[0010] The second processing module is used to perform sum processing on the multiple third data output by the multiple first processing modules.

[0011] In the above device, the first storage and calculation unit includes: a first memory, a first multiplier and a first addition tree; wherein,

[0012] The first memory is used to store a first weight coefficient and a first bias coefficient;

[0013] The first multiplier is used to perform a multiplication operation on the first data based on the first weight coefficient and output a first multiplication result;

[0014] The first addition tree is used to perform addition processing on the first multiplication operation combination and the first bias coefficient to obtain second data.

[0015] In the above device, the second storage and calculation unit includes: a second memory, a second multiplier and a second addition tree; wherein,

[0016] The second memory is used to store a second weight coefficient and a second bias coefficient;

[0017] The second multiplier is used to perform a multiplication operation on the maximum value output by the comparison unit based on the second weight coefficient, and output a second multiplication operation result;

[0018] The second addition tree is used to perform addition processing on the second multiplication result and the second bias coefficient to obtain third data.

[0019] In the above device, the device further includes: an input module, used to obtain first data, and input the first data into each first processing module for processing.

[0020] In the above device, the input module is also used to obtain a first weight coefficient, a first bias coefficient, a second weight coefficient and a second bias coefficient, and input the first weight coefficient and the first bias coefficient into the first storage unit for storage, and input the second weight coefficient and the second bias coefficient into the second storage unit for storage.

[0021] In the above device, the first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient are obtained in advance through machine learning training.

[0022] In the above device, the device further includes: an output module, used to output the summing processing result of the second processing module.

[0023] The in-memory computing device provided by an embodiment of the present invention sets a first storage computing unit, a comparison unit, and a second storage computing unit connected in series in a first processing module, and designs a hardware architecture based on the in-memory computing technology to implement the activation function, so that the power consumption and the occupied circuit area are greatly improved compared with the existing hardware method of implementing the activation function. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of realizing activation function through piecewise linear approximation;

[0025] Figure 2 A schematic diagram of the structure of an in-memory computing device according to an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a multi-layer perceptron network topology applicable to an in-memory computing device according to an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of the composition structure of the first storage and computing unit in an embodiment of the present invention;

[0028] Figure 5 Schematic diagram of the composition structure of the second storage and computing unit in an embodiment of the present invention;

[0029] Figure 6 Schematic diagram of the data processing flow of the in-memory computing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] It should be understood that the terms "system" and "network" are often used interchangeably in this article. The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0033] In neural networks, by defining nonlinear activation functions on neurons and using activation functions to simulate the necessary nonlinearity of neurons in the network, DNN can capture nonlinear relationships, thereby better approximating complex functions or mappings and improving the data processing capabilities of DNN in related fields.

[0034] For example, in the field of natural language processing (NLP), for NLP tasks, the DNN used needs to rely on more complex activation functions, rather than just introducing a single rectified linear unit (ReLU) as an activation function. Among them, if a long short-term memory network (LSTM) or its variant gated recurrent unit (GRU) is used in NLP, a hyperbolic tangent function (tanh) or a logistic (sigmoid, also known as Logistic) function can be introduced as an activation function; if the pre-trained language model used in the NLP task is a BERT (Bidirectional Encoder Representations from Transformers) model, a Gaussian Error Linear Unit (GeLU) can be introduced as an activation function. In addition, the Swish (Sigmoid-weighted Linear Unit) function, a combination of the Sigmoid function and the ReLU function, can be used as an activation function and applied to NLP tasks to improve the accuracy of the model.

[0035] The most important, expensive and difficult part of any hardware implementation of a neural network is the nonlinear activation function introduced in the neuron. When running the network, executing the above complex activation functions will waste a lot of time, usually taking up more than half of the total execution time. In addition, these nonlinear functions are hardware-incompatible and difficult to implement with unified hardware. With the development of neural networks, more and more complex activation functions will appear, and these activation functions all require good hardware support to ensure the completeness and versatility of the chip.

[0036] Currently, activation functions are usually implemented using methods such as lookup tables, piecewise linear approximation, or customizing hardware circuits for special functions.

[0037] The lookup table method is the simplest method for approximating nonlinear functions. Before approximating the nonlinear activation function, it is only necessary to store the calculation results in the lookup table in advance. When the circuit calculates the nonlinear function, it is directly necessary to look up the table according to the address. However, with the improvement of calculation accuracy, the parameters of the lookup table will increase exponentially. For example, if an activation function needs to meet the full precision of FP16, then a total of 64511 numbers (FP16) need to be stored according to the lookup table, which is about 128KB. This makes the demand for chip storage and circuit area too large, and it is unrealistic to implement an activation function in on-chip memory.

[0038] Furthermore, in order to reduce the circuit area overhead of the above-mentioned lookup table method and improve the calculation accuracy, a piecewise linear (PWL) approximation method is proposed. Figure 1 This is a schematic diagram of implementing the activation function through piecewise linear approximation, such as Figure 1 As shown, h i (x) represents multiple linear piecewise functions divided on the domain [M, N] corresponding to the target activation function f(x), each piecewise function corresponds to a different sub-interval, and each section is composed of hi(x) = kix + bi linear functions, k i is the slope, b i is the y-intercept, i is the index number i=1, 2, 3...n, and the target activation function f(x) is divided into multiple linear piecewise functions. The linear segments of these different word intervals are used to approximate the segmented nonlinear activation function.

[0039] Compared with the lookup table method that stores all calculation results, the piecewise linear approximation method only needs to store the three coefficients of the starting point, slope and y-intercept of each linear segment to obtain all values ​​within the segment interval, thereby reducing the hardware resources for storing a large number of calculation results and other parameters, that is, reducing the storage requirements of the chip. However, the algorithm quality of the piecewise linear approximation method depends on how to divide the input interval into appropriate segments and how to segment to obtain the desired accuracy. That is, the piecewise linear approximation method needs to invest a lot of effort in designing the interval division part to meet all accuracy, which greatly increases the complexity of implementing this method and is prone to unsatisfactory results.

[0040] However, the activation function that can be realized by customizing the hardware circuit is relatively simple, and the power consumption is high and the circuit area occupied is large.

[0041] Based on this, an embodiment of the present invention proposes an in-memory computing device, which aims to use in-memory computing technology to implement activation functions in neural networks, so that the device has a simple structure, occupies a smaller circuit area, generates lower power consumption, and is easy to implement on a chip.

[0042] It should be noted that in-memory computing is a technology that combines computing and storage. By using memory to perform operations on data, the "storage wall" and "power consumption wall" generated during the transfer of data between memory and processor are avoided, greatly improving data parallelism and energy efficiency. The core idea of ​​in-memory computing technology is to focus on data storage rather than computing. This technology can shorten the distance between data and processors, complete all computing work in memory, and thus increase data processing speed by thousands of times.

[0043] An embodiment of the present invention provides an in-memory computing device, Figure 2 FIG. 1 is a schematic diagram of the structure of the in-memory computing device according to an embodiment of the present invention. Figure 2 As shown, the device includes: a plurality of first processing modules 11 and a second processing module 12; each first processing module includes: a first storage unit 13, a comparison unit 14 and a second storage unit 15; the first storage unit 13, the comparison unit 14 and the second storage unit 15 are connected in series; wherein,

[0044] The first storage and calculation unit 13 is used to store a first weight coefficient and a first bias coefficient, and process the first data based on the first weight coefficient and the first bias coefficient to obtain second data;

[0045] The comparison unit 14 is used to compare the second data with a preset value, and output a maximum value between the second data and the preset value based on the comparison result;

[0046] The second storage and calculation unit 15 is used to store a second weight coefficient and a second bias coefficient, and process the maximum value output by the comparison unit based on the second weight coefficient and the second bias coefficient to obtain third data;

[0047] The second processing module 12 is used to perform sum processing on a plurality of third data outputted by a plurality of first processing modules.

[0048] Here, the present invention encapsulates all logic circuits of the multilayer perceptron (MLP, Multilayer Perceptron, also known as multi-layer feedforward neural networks) network structure that can complete DNN into a chip, and digitally modularizes the internal structure of the hardware used to implement the activation function so that the function of each digital module is highly targeted, and specifically may include multiple first processing modules and one second processing module.

[0049] Figure 3 FIG. 1 is a schematic diagram of a multi-layer perceptron network topology applicable to an in-memory computing device according to an embodiment of the present invention; Figure 3 As shown, the MLP network structure of the in-memory computing device applicable to the embodiment of the present invention includes three layers, namely, an input layer for inputting X, including L1, L2, L3, ..., L n The hidden layer and the output layer for outputting Y, Figure 3 The MLP network structure shown in is a single-layer MLP with a single input, a single hidden layer, and a single output. In the MLP network structure, different layers are fully connected, that is, any neuron in the previous layer is connected to all neurons in the next layer, and there is no same-layer connection or cross-layer connection between neurons.

[0050] This single-layer MLP can achieve most activation function calculations that meet FP16 accuracy. If the activation function requires a higher accuracy range, higher accuracy can be achieved by expanding the depth and / or the number of neurons n, that is, by increasing the number of input layers and / or hidden layers, or the number of neurons. Figure 3 The MLP network structure shown can be used to fit various neural network activation functions according to the universal approximation theorem.

[0051] It should be noted that the Universal Approximation Theorem can also be called the universal approximation theorem, which was proposed by G. Cybenko. It proves that a finite linear combination of a fixed univariate function and a set of affine functionals can consistently approximate any continuous function in the unit hypercube. In other words, it proves that a feedforward neural network has a linear output layer and at least one hidden layer. As long as the network is given a sufficient number of neurons, it can approximate any continuous function on a compact set with sufficiently high accuracy. This fitting ability is also the fundamental reason why the neural network architecture can complete complex data processing. The present invention is based on this universal approximation theorem, so that any neural network activation function can be implemented by fitting the above-mentioned MLP network structure, so as to achieve universality while ensuring energy efficiency.

[0052] In this embodiment, a plurality of first processing modules and one second processing module are hardware implementation modules for implementing the in-memory calculation result of the input first data from the input layer through the hidden layer to the output layer. The processing process from the input layer through the hidden layer to the output layer in the MLP can be implemented through a plurality of first processing modules and one second processing module in the in-memory calculation device of the present invention. Based on the above MLP network structure, the internal hardware structure of the first processing module is designed according to the neural network activation function.

[0053] As an example, if the neural network activation function adopts the ReLU function, the calculation formula of the MLP network topology can be designed as the following formula according to the implementation method of the ReLU function:

[0054]

[0055] Among them, W 0i and W 1i They represent the weight coefficients used from the input layer to the hidden layer, and from the hidden layer to the output layer; b 0i and b 1i They represent the bias coefficients used from the input layer to the hidden layer, and from the hidden layer to the output layer respectively; W 0i x+b 0i Represents the calculation rule from the input layer to the hidden layer, which is the sum of the product of the weight coefficient and the input value and the bias coefficient; where W 0i It can be equivalent to the first weight coefficient, b 0i Can be equivalent to the first bias coefficient; W 1i ×x'+b 1i represents the calculation rule from the hidden layer to the output layer, which is the product of the weight coefficient and the calculation result of the activation function and the sum of the bias coefficient. x' represents the calculation result of the activation function in the hidden layer. W 1i It can be equivalent to the first weight coefficient, b1i It can be equivalent to the first bias coefficient; max[(W 0i x+b 0i ),0] is the processing process of the activation function used in the hidden layer of the embodiment of the present invention in the MLP network topology, that is, the calculation formula of the ReLU function in the embodiment of the present invention, which means taking W 0i x+b 0i The maximum value between 0 and W 1i ×max[(W 0i x+b 0i ),0]+b 1i The corresponding hardware implementation module is the first processing module in the in-memory computing module of the embodiment of the present invention, and each first processing module can output a computing result, that is, the third data; It represents that multiple third data outputted by multiple first processing modules are added to obtain an in-memory calculation result, and its corresponding hardware implementation module is the second processing module in the in-memory calculation module in the embodiment of the present invention.

[0056] In an optional embodiment, the device further includes: an input module, configured to obtain first data, and input the first data into each first processing module for processing.

[0057] It should be noted that the input module can be used as a hardware implementation module of the input layer, for inputting the first data to the first processing module. For example, based on the above formula (1), the input module is used as a hardware implementation module of the input layer, for inputting the first data x to the first processing module.

[0058] In an optional embodiment, the device further includes: an output module, configured to output the summing result of the second processing module.

[0059] It should be noted that the output module can be used as a hardware implementation module of the output layer, for outputting the processed in-memory calculation result. For example, based on the above formula (1), the output module is used as a hardware implementation module of the output layer, for outputting the first data y.

[0060] In this embodiment, the activation function is designed in the first processing module, and the internal hardware structure of the first processing module is designed according to the activation function. Each first processing module includes a first storage-calculation module unit, a comparison unit and a second storage-calculation unit connected in series. The series connection order between the first storage-calculation module unit, the comparison unit and the second storage-calculation unit can be designed according to the calculation formula of the MLP network topology.

[0061] As an example, based on the above formula (1), the first storage unit is to realize W 0i x+b 0iThe hardware implementation unit of the processing process is based on the first weight coefficient W 0i and the first bias coefficient b 0i The first data input by the input module is processed to obtain W 0i x+b 0i The calculation result is the second data; the comparison unit is the hardware implementation unit for implementing the ReLU activation function, that is, the implementation of max[(W 0i x+b 0i ),0], by processing the second data W 0i x+b 0i Compare with the preset value 0 and output W based on the comparison result 0i x+b 0i The maximum value between and 0; the second storage unit is to realize W 1i ×x'+b 1i The hardware implementation unit is based on the second weight coefficient W 1i and the second bias coefficient b 1i The maximum value of the comparison unit output is processed to obtain W 1i ×max[(W 0i x+b 0i ),0]+b 1i The calculation result of , that is, the third data.

[0062] It should be noted that, since the device in the embodiment of the present invention refers to the in-memory computing technology, it is intended to realize the operation of data in the memory, that is, the first storage and computing unit and the second storage and computing unit can realize the data processing process of the above formula (1) through a storage medium, and the first storage and computing unit and the second storage and computing unit can be static random access memory (SRAM), variable resistance memory (RRAM or ReRAM), mobile storage device, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various storage media that can store program codes.

[0063] That is to say, in the device of the embodiment of the present invention, the first storage unit can not only be used as a memory to store the first weight coefficient and the first bias coefficient, but also can be used as a processor to process the first data based on the stored first weight coefficient and the first bias coefficient to obtain the second data. Similarly, the second storage unit can not only be used as a memory to store the second weight coefficient and the second bias coefficient, but also can be used as a processor to process the maximum value output by the comparison unit based on the stored second weight coefficient and the second bias coefficient to obtain the third data. The method for obtaining the first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient in the embodiment of the present invention will be described in detail later.

[0064] In some optional embodiments, the input module is also used to obtain a first weight coefficient, a first bias coefficient, a second weight coefficient and a second bias coefficient, and input the first weight coefficient and the first bias coefficient into the first storage unit for storage, and input the second weight coefficient and the second bias coefficient into the second storage unit for storage.

[0065] In this embodiment, since the first storage unit and the second storage unit are essentially storage media for storing data, the input module can input the acquired first weight coefficient and first bias coefficient into the first storage unit for storage by the first storage unit; and input the acquired second weight coefficient and second bias coefficient into the second storage unit for storage by the second storage unit.

[0066] It should be noted that the first weight coefficient and the first bias coefficient stored in the first storage unit of the device of the embodiment of the present invention, and the second weight coefficient and the second bias coefficient stored in the second storage unit can be obtained through an external device connected to the device. For example, the external device can be a processor such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller unit (MCU) or a field-programmable gate array (FPGA).

[0067] In this embodiment, the internal hardware structures of the first storage unit and the second storage unit are designed according to the internal hardware structure of the first processing module. First, the first storage unit may include a first memory, a first multiplier and a first addition tree. The first memory, the first multiplier and the first addition tree are connected in series according to the processing process of the first storage unit, so as to realize the processing of the first data input by the input module through the first storage unit.

[0068] Figure 4 FIG. 1 is a schematic diagram of the composition structure of the first storage and computing unit according to an embodiment of the present invention. Figure 4 As shown, the first storage and calculation unit 13 includes: a first memory 21, a first multiplier 22 and a first addition tree 23; wherein the first memory 21 is used to store a first weight coefficient and a first bias coefficient; the first multiplier 22 is used to perform multiplication operation on the first data based on the first weight coefficient and output a first multiplication operation result; the first addition tree 23 is used to add the first multiplication operation result and the first bias coefficient to obtain second data.

[0069] In this embodiment, the first storage and calculation unit can store the first weight coefficient and the first bias coefficient, and can also process the first data based on the stored first weight coefficient and the first bias coefficient to obtain the second data.

[0070] Specifically, the first storage and calculation unit may include a first memory and a first calculation unit group, wherein the first memory is used to store the first weight coefficient and the first bias coefficient input by the input module; the first calculation unit group ( Figure 4 The dashed box is used to realize the processing of the first data, and the first computing unit group includes a first multiplier and a first addition tree; the first multiplier is used to perform a multiplication operation on the first data based on the first weight coefficient stored in the first memory, and output the first multiplication result to the first addition tree; the first addition tree is used to perform an addition operation on the first multiplication result and the first bias coefficient stored in the first memory, and output the obtained second data to the comparison unit connected thereto.

[0071] In this embodiment, the second storage and computing unit may include a second memory, a second multiplier and a second addition tree. The second memory, the second multiplier and the second addition tree are connected in series according to the processing process of the second storage and computing unit to realize the processing of the maximum value of the comparison unit input through the second storage and computing unit.

[0072] Figure 5 FIG. 1 is a schematic diagram of the composition structure of the second storage and computing unit according to an embodiment of the present invention. Figure 5As shown, the second storage unit 15 includes: a second memory 31, a second multiplier 32 and a second addition tree 33; wherein the second memory 31 is used to store a second weight coefficient and a second bias coefficient; the second multiplier 32 is used to multiply the maximum value output by the comparison unit based on the second weight coefficient and output a second multiplication result; the second addition tree 33 is used to add the second multiplication result and the second bias coefficient to obtain third data.

[0073] In this embodiment, the second storage unit can store the second weight coefficient and the second bias coefficient, and can also process the maximum value output by the comparison unit based on the stored second weight coefficient and the second bias coefficient to obtain the third data.

[0074] Specifically, the second storage unit may include a second memory and a second computing unit group, wherein the second memory is used to store the second weight coefficient and the second bias coefficient input by the input module; the second computing unit group ( Figure 5 The dashed box is used to process the maximum value output by the comparison unit, and the second calculation unit group includes a second multiplier and a second addition tree; the second multiplier is used to multiply the maximum value based on the second weight coefficient stored in the second memory, and output the second multiplication result to the second addition tree; the second addition tree is used to add the second multiplication result and the second bias coefficient stored in the second memory, and output the obtained third data to the second processing module.

[0075] In some optional embodiments, the first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient are obtained in advance through machine learning training.

[0076] Here, the weight coefficient and the bias coefficient are the most important coefficients in the in-memory computing device of the embodiment of the present invention, wherein the weight coefficient is used to indicate the connection strength between neurons, and the size of the weight indicates the size of the possibility; the bias coefficient is equivalent to a "threshold" that can be adjusted by a model, which is used to increase the expressiveness of the neural network model, and help the model to make more precise adjustments to the input data so that the model can better fit the data.

[0077] In this embodiment, a machine learning method can be used to pre-train the training set, so that the first weight coefficient, the first bias coefficient, the second weight coefficient, and the second bias coefficient can be adjusted according to the training results, and finally the first weight coefficient, the first bias coefficient, the second weight coefficient, and the second bias coefficient can be determined.

[0078] It should be noted that the present invention does not impose any specific restrictions on the machine learning method used to determine the weight coefficient and the bias coefficient. For example, the weight coefficient and the bias coefficient can be obtained by a supervised training method of forward propagation and backward propagation.

[0079] Specifically, first randomly initialize the first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient; then perform forward propagation, in which the input features of all samples in the training set are used as the input layer, and for the input in all training data sets, each neuron calculates the weighted sum and passes it to the next layer through the activation function, so that all neurons in the neural network are activated, and after forward propagation, the output value is obtained; secondly, perform backward propagation, in which, according to the error between the output value of the neural network and the true label, the weight coefficient and the bias coefficient are adjusted by the gradient descent method (SGD, Stochastic Gradient Descent) to make the prediction result as close to the true value as possible; finally, after the training stop condition is reached, determine the first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient.

[0080] In some optional embodiments, the device may further include a general interface module and a control module; wherein the general interface module is used to receive first data input by an external device connected to the device, and send the first data to the input module through the control module; and is also used to receive a first weight coefficient, a first bias coefficient, a second weight coefficient, and a second bias coefficient determined by the external device connected to the device through pre-training, and send the first weight coefficient and the first bias coefficient to the first memory in the first storage unit through the input module, and send the second weight coefficient and the second bias coefficient to the second memory in the second storage unit;

[0081] The control module is used to receive the first data sent by the main interface module, send the first data to the input module, and send first control information used to drive the multiple first processing modules to obtain multiple third data to the multiple first processing modules; it is also used to send second control information used to drive the second processing module to add and process the multiple third data to obtain the calculation result in the memory.

[0082] As an example, Figure 6 FIG. 1 is a schematic diagram of a data processing flow of an in-memory computing device according to an embodiment of the present invention; Figure 6 As shown, first, the first data is input into a plurality of first processing modules through an input module. In each first processing module, the first weight coefficient W is first multiplied by a first multiplier in a first storage unit. 0i and the first data to obtain a first product operation result; and then use the first addition tree to calculate the first bias coefficient b 0iPerforming an addition operation on the result of the first multiplication operation to obtain second data;

[0083] Secondly, the obtained second data is input into the comparison unit, and the comparison unit is used to compare the second data with the preset value 0. If the second data is greater than 0, the second data is input into the second storage unit, otherwise 0 is input into the second storage unit;

[0084] Finally, in each second storage unit, the second weight coefficient W is first multiplied by the second multiplier in the second storage unit. 1i The second addition tree is used to multiply the second bias coefficient b by the maximum value of the comparator output to obtain the second product operation result; 1i The second product operation results are summed up, and the obtained third data is input into the second processing module. The second processing module performs summation processing on multiple third data, and the output module outputs the stored calculation result.

[0085] In this embodiment, an activation function is implemented using an in-memory computing device. On the one hand, compared to a lookup table method in which the circuit area increases exponentially as the parameters increase with precision, the fixed hardware structure of the device in the embodiment of the present invention only shows a quasi-linear increase relationship with the increase of precision, and the device in the embodiment of the present invention reduces power consumption and circuit area overhead through in-memory computing technology. On the other hand, compared to the piecewise linear approximation method, the device in the embodiment of the present invention has the advantages of being trainable, more generalizable, and more flexible, and implements the activation function using a universal approximation theorem, thereby achieving universality while ensuring energy efficiency.

[0086] The features disclosed in several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0087] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0088] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0089] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0090] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An in-memory computing device, characterized in that: The device comprises: a plurality of first processing modules and a second processing module; each first processing module comprises: a first storage unit, a comparison unit and a second storage unit; the first storage unit, the comparison unit and the second storage unit are connected in series; wherein, The first storage and calculation unit is used to store a first weight coefficient and a first bias coefficient, and process the first data based on the first weight coefficient and the first bias coefficient to obtain second data; The comparison unit is used to compare the second data with a preset value, and output a maximum value between the second data and the preset value based on the comparison result; The second storage and calculation unit is used to store a second weight coefficient and a second bias coefficient, and process the maximum value output by the comparison unit based on the second weight coefficient and the second bias coefficient to obtain third data; The second processing module is used to perform sum processing on the multiple third data output by the multiple first processing modules.

2. The device according to claim 1, characterized in that The first storage and calculation unit includes: a first memory, a first multiplier and a first addition tree; wherein, The first memory is used to store a first weight coefficient and a first bias coefficient; The first multiplier is used to perform a multiplication operation on the first data based on the first weight coefficient and output a first multiplication result; The first addition tree is used to perform addition processing on the first multiplication result and the first bias coefficient to obtain second data.

3. The device according to claim 1, characterized in that The second storage and calculation unit includes: a second memory, a second multiplier and a second addition tree; wherein, The second memory is used to store a second weight coefficient and a second bias coefficient; The second multiplier is used to perform a multiplication operation on the maximum value output by the comparison unit based on the second weight coefficient, and output a second multiplication operation result; The second addition tree is used to perform addition processing on the second multiplication result and the second bias coefficient to obtain third data.

4. The device according to any one of claims 1 to 3, characterized in that The device also includes: The input module is used to obtain first data and input the first data into each first processing module for processing.

5. The device according to claim 4, characterized in that The input module is also used to obtain a first weight coefficient, a first bias coefficient, a second weight coefficient and a second bias coefficient, input the first weight coefficient and the first bias coefficient into the first storage unit for storage, and input the second weight coefficient and the second bias coefficient into the second storage unit for storage.

6. The device according to claim 5, characterized in that The first weight coefficient, the first bias coefficient, the second weight coefficient and the second bias coefficient are obtained in advance through machine learning training.

7. The device according to claim 1, characterized in that The device further includes: an output module, configured to output the summing result of the second processing module.

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