Quantum circuit, method and system for preparing quantum uniform superposition state and quantum circuit for realizing parallel function

Abstract

The invention discloses a quantum circuit, a method and a system for preparing a quantum uniform superposition state and a quantum circuit for realizing a parallel function, the preparation of any circuit in the quantum uniform superposition state needs to be realized according to the constructed circuit of the parallel function, and the quantum circuit of the parallel function comprises a first function operator circuit and a second function operator circuit. The initial state of the first quantum register is subjected to # imgabs0 # transformation and then is used as the first input of the quantum circuit for realizing the parallel function; and the initial state of the second quantum register is directly used as the second input of the quantum circuit for realizing the parallel function. According to the invention, the number of three-bit quantum gates required is obviously reduced, the number of quantum bits is reduced, the calculation complexity is reduced, and the realization precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum superposition state preparation, and in particular to a quantum circuit, method, system for preparing a quantum uniform superposition state, and a quantum circuit for realizing a parallel function. Background Art

[0002] Since the concept of quantum computing was proposed, researchers have been exploring how to use quantum for our own benefit. In recent years, the development of quantum computers has progressed very rapidly, especially superconducting quantum computers, ion trap quantum computers, linear optical quantum computers, and cold atom quantum computers. Although the number of bits of these quantum computers has reached hundreds of qubits, it still does not meet the requirements for implementing large-scale quantum computing algorithms. For this reason, while developing quantum computers, researchers are also studying quantum computing algorithms to reduce the number of qubits required.

[0003] In fact, quantum computing algorithms are composed of a series of quantum transformations. As long as quantum transformations can be achieved, quantum computing algorithms can be realized. Preparing quantum superposition states is a key step in the implementation of algorithms. In particular, the quantum resources required to prepare any quantum superposition state are large. Without auxiliary bits, the circuit depth reaches exponential level O(2 n / n), and when the circuit depth is O(n), the auxiliary quantum bit scale required is O(2 n ), thus directly limiting whether the algorithm can be effectively implemented, such as the HHL algorithm (Harrow-Hassidim-Lloyd algorithm) and Hamiltonian evolution. However, the preparation of quantum superposition states with certain properties requires fewer quantum resources, such as: preparing k sparse quantum superposition states, that is, the probability amplitude of k states in the quantum superposition state is non-zero, and the circuit depth is log(nk), requiring O(nklogk) auxiliary quantum bits; preparing uniform superposition states Can be based on Z N Quantum Fourier transform is implemented. As a commonly used quantum transformation, quantum Fourier transform can not only be used to prepare uniform superposition states, but also to increase the probability of target quantum states being measured. Its implementation method has always attracted the attention of researchers. The quantum Fourier transform is the realization of Z N A method for quantum Fourier transformation on the upper side requires n qubits, n single-bit quantum gates and n 2 / 2 two-bit quantum gates, and this method has errors. Therefore, in order to improve the accuracy of preparing quantum uniform superposition states, further research is needed to reduce the number of required multi-bit quantum gates, especially the number of three-bit quantum gates, so as to provide technical support for the implementation of algorithms such as the Shor discrete logarithm problem quantum computing algorithm and the Proos-Zalka quantum computing algorithm. Moreover, the existing technology for preparing quantum uniform superposition states does not prepare quantum uniform superposition states based on parallel functions, nor does it have quantum circuits with corresponding parallel functions. Summary of the invention

[0004] In order to at least partially solve the problem of large quantum resources required for preparing quantum superposition states, the present invention provides a quantum circuit, method, system and quantum circuit for realizing parallel functions for preparing quantum uniform superposition states, by constructing parallel functions, marking quantum uniform superposition states, and then obtaining second quantum superposition states according to the parallel functions, thereby completing the preparation of quantum uniform superposition states. According to the parallel functions, quantum circuits of parallel functions are set, which greatly reduces the required quantum resources, reduces the number of three-dimensional quantum gates required to O(N), and improves the realization accuracy.

[0005] In order to achieve the above object, the technical solution of the present invention is:

[0006] In a first aspect, the present invention proposes a quantum circuit for realizing a parallel function. The parallel function is in, x and N represent the two input variables of the parallel function. Set x The binary representations of and N are (x 1 ,x 2 ,…,x n ) and (N 1 ,N 2 ,…,N n ), to reformulate the parallel function as in, Correspondingly, the quantum circuit includes: a first function operator circuit and a second function operator circuit;

[0007] The first function operator circuit is used to implement the function E;

[0008] The second function operator circuit is used to implement the function of function S.

[0009] Furthermore, the first function operator circuit includes a parameter N connected sequentially. i A quantum NOT gate and a quantum NOT gate controlled by the control; wherein the parameter N i The input of the controlled quantum NOT gate is x i, which is convenient for realizing the function E.

[0010] Furthermore, the second function operator circuit includes: two quantum NOT gates and a parameter N i Controlled quantum NOT gate;

[0011] Among them, the parameter N i The control qubit of the controlled quantum NOT gate is connected between two quantum NOT gates; the input of the previous quantum NOT gate is x i , the parameter N i The controlled quantum bit of the controlled quantum NOT gate is |0〉, which is convenient for realizing the function of function S.

[0012] The second aspect of the present invention proposes a quantum circuit for preparing a quantum uniform superposition state, comprising: a first quantum register, a second quantum register and a first aspect of the present invention proposes a quantum circuit for realizing a parallel function; wherein the initial state of the first quantum register is After the transformation, the first input of the quantum circuit for realizing the parallel function is used; the initial state of the second quantum register is directly used as the second input of the quantum circuit for realizing the parallel function;

[0013] The first quantum register is used to store the initial state of the first quantum register. The first quantum superposition state obtained after the transformation;

[0014] The second quantum register is used to store the function result obtained by the parallel function.

[0015] The third aspect of the present invention provides a method for preparing an arbitrary quantum uniform superposition state, comprising:

[0016] Step 1: Initialize the first quantum register and the second quantum register to facilitate subsequent calculations;

[0017] Step 2: Perform the first quantum register Transformation, to obtain the first quantum superposition state, which is convenient for preparing the quantum uniform superposition state;

[0018] Step 3: Construct a parallel function, calculate the parallel function, obtain the function result, store the function result in the second quantum register, obtain the second quantum superposition state, and prepare the quantum uniform superposition state;

[0019] Step 4: Measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained. Otherwise, the preparation of the quantum uniform superposition state fails. This is used to detect whether the preparation of the quantum superposition state is successful.

[0020] Further, the first quantum register state and the second quantum register state are respectively initialized to and

[0021] Furthermore, the first quantum register is Operations, including:

[0022]

[0023] Where n is the power parameter, x and N are the two input variables of the parallel function, 2 n-1 <N<2 n , θ is the probability parameter, α and β are different transformation parameters,

[0024] A fourth aspect of the present invention provides a system for preparing an arbitrary quantum uniform superposition state, comprising:

[0025] An initialization module, used to initialize the first quantum register and the second quantum register to facilitate subsequent calculations;

[0026] Transformation module, used to transform the first quantum register Transformation, to obtain the first quantum superposition state, which is convenient for preparing the quantum uniform superposition state;

[0027] The parallel function module is used to construct parallel functions, calculate parallel functions, obtain function results, store the function results in the second quantum register, obtain the second quantum superposition state, and facilitate the preparation of quantum uniform superposition states;

[0028] The measurement module is used to measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained. Otherwise, the preparation of the quantum uniform superposition state fails. It is used to detect whether the preparation of the quantum superposition state is successful.

[0029] The fifth aspect of the present invention proposes a terminal device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements a method for preparing an arbitrary quantum uniform superposition state as described in the third aspect above.

[0030] The sixth aspect of the present invention proposes a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute a method for preparing an arbitrary quantum uniform superposition state as described in the third aspect above.

[0031] Beneficial effects of the present invention:

[0032] (1) The present invention provides a method for preparing an arbitrary quantum uniform superposition state. The method constructs a special parallel function f to mark an arbitrary quantum uniform superposition state from a special quantum uniform superposition state. Compared with the method based on Z N The upper quantum Fourier transform is used to prepare any quantum uniform superposition state, which has the advantage of requiring fewer quantum bits and three-dimensional quantum gates for preparation and can prepare any quantum uniform superposition state.

[0033] (2) The present invention provides an implementation circuit for a parallel function f, which only requires one-bit quantum gate, two-bit quantum gate and three-bit quantum gate. The implementation complexity of the circuit is low, and it can effectively support the preparation of any quantum uniform superposition state and improve the accuracy of preparing any quantum uniform superposition state. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The embodiment of the present invention provides Schematic diagram of the quantum realization circuit.

[0035] Figure 2 The embodiment of the present invention provides Schematic diagram of the quantum realization circuit.

[0036] Figure 3 A schematic diagram of a quantum implementation circuit of a parallel function provided in an embodiment of the present invention.

[0037] Figure 4 A schematic diagram of a quantum implementation circuit of a method for preparing an arbitrary quantum uniform superposition state provided in an embodiment of the present invention.

[0038] Figure 5 A flow chart of a method for preparing an arbitrary quantum uniform superposition state provided in an embodiment of the present invention.

[0039] Figure 6 An architectural diagram of a system for preparing an arbitrary quantum uniform superposition state provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0041] Example 1

[0042] Based on the above embodiment, the embodiment of the present invention provides a parallel function construction process, which specifically includes:

[0043] Constructing parallel functions through proof method:

[0044] Theorem: Let (x 1 ,x 2 ,…,x n ) and (N 1 ,N 2 ,…,N n ) are the binary representations of x and N respectively, Then the parallel function f(x,N) is:

[0045] in, is a negation operation, is a modulo 2 addition operation, x and N are two input variables of the parallel function, x i is the ith binary representation of x, N i is the ith binary representation of N, e i is the modulo 2 addition operation parameter, s i It is a non-operation parameter.

[0046] Proof: When x=N, it is obvious that x i =N i , then there is e i =1,s i =0.

[0047] therefore,

[0048] When x<N, there are two situations:

[0049] ①x 1 <N 1 , that is, x 1 =0, N 1 =1, then s 1 =1, e 1 =0.

[0050] therefore,

[0051] ②x 1 =N 1 , then there must be a j such that x 1 =N 1 ,…,x j =N j And x j+1 <N j+1 , where 1≤j≤n-1, furthermore, e 1 =…=e j =1,s 1 =…=sj =0, e j+1 =0,s j+1 =1.

[0052] therefore,

[0053] When x>N, there are two situations:

[0054] ①x 1 >N 1 , that is, x 1 =1, N 1 = 0, then s 1 =0, e 1 =0.

[0055] therefore,

[0056] ②x 1 =N 1 , then there must be a j such that x 1 =N 1 ,…,x j =N j And x j+1 >N j+1 , where 1≤j≤n-1, furthermore, e 1 =…=e j =1,s 1 =…=s j =s j+1 =0, e j+1 =0.

[0057] therefore,

[0058] In summary, the theorem is proved and the construction of the parallel function is completed.

[0059] Example 2

[0060] Based on the above embodiment, the embodiment of the present invention provides a specific process of a quantum implementation circuit of a parallel function, which specifically includes:

[0061] According to the parallel function Design a quantum implementation circuit for parallel functions. In the i and i The quantum realization circuit of The quantum implementation circuits of these two functions are as follows Figure 1 and Figure 2 shown.

[0062] in, The quantum realization circuit requires two one-bit quantum gates. The quantum realization circuit requires 2 one-bit quantum gates and 1 two-bit quantum gate.

[0063] based on and The quantum implementation circuit of the parallel function f can be given as follows: Figure 3 shown.

[0064] Among them, (x 1 ,x 2 ,…,x n ) and (N 1 ,N 2 ,…,N n ) are the binary representations of x and N respectively.

[0065] When n=1, the circuit requires 1 auxiliary quantum bit, for a total of 3 quantum bits. When n>1, the circuit requires n-1 auxiliary quantum bits, for a total of 2n quantum bits.

[0066] When n=1, the circuit requires 2 one-bit quantum gates and 2 two-bit quantum gates, with a depth of 3. When n>1, the circuit requires 12n-8 one-bit quantum gates, 4n-1 two-bit quantum gates and 3n-5 three-bit quantum gates, with a depth of 9n-10.

[0067] Example 3

[0068] On the basis of the above embodiments, the embodiment of the present invention provides a specific process of implementing a circuit for preparing a method for a quantum uniform superposition state, which specifically includes:

[0069] Based on the implementation circuit of the parallel function f, the implementation circuit of the method for preparing quantum uniform superposition state is as follows Figure 4 shown. Figure 4 The value of the measurement result c is 0 or 1, and H is the Hadamard gate.

[0070] The realization circuit of the method for preparing a quantum uniform superposition state does not require additional auxiliary quantum bits. When n=1, the realization circuit of the method requires 3 quantum bits. When n>1, the realization circuit of the method for preparing a quantum uniform superposition state requires 2n quantum bits. Compared with the realization circuit of the parallel function f, the realization circuit of the method for preparing a quantum uniform superposition state requires n more H (Hadamard) gates. Therefore, when n=1, the realization circuit of the method for preparing a quantum uniform superposition state requires 3 one-bit quantum gates and 2 two-bit quantum gates, with a depth of 4. When n>1, the realization circuit of the method for preparing a quantum uniform superposition state requires 13n-8 one-bit quantum gates, 4n-1 two-bit quantum gates and 3n-5 three-bit quantum gates, with a depth of 9n-9.

[0071] Example 4

[0072] For quantum uniform superposition Where N is a parameter. When N is a power of 2, it can be obtained by The (Hadamard) transformation is obtained on the |0> state, and the process requires fewer quantum resources. However, when N is not a power of 2, the quantum uniform superposition state needs to be obtained by Z N The quantum Fourier transform is applied to the |0> state, which requires more quantum resources. In order to further reduce the quantum resources required to prepare the quantum uniform superposition state when N is not a power of 2, Rule 2 n-1 <N<2 n .like Figure 5 As shown, an embodiment of the present invention provides a method for preparing an arbitrary quantum uniform superposition state, comprising:

[0073] S101: Initialize the first quantum register and the second quantum register.

[0074] S102: Perform the first quantum register (Hadamard) transformation to obtain the first quantum superposition state.

[0075] Specifically, do this once for the first quantum register The transformations can be performed simultaneously, with a computational complexity of O(1), requiring n one-bit quantum gates.

[0076] S103: construct a parallel function, calculate the parallel function, obtain the function result, store the function result in a second quantum register, and obtain a second quantum superposition state.

[0077] Specifically, the computational complexity of executing a parallel function f is O(n).

[0078] S104: Measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained. Otherwise, the preparation of the quantum uniform superposition state fails.

[0079] Specifically, the second quantum register is measured with |sinθ 2 The probability of getting 1, at this time, the first quantum register collapses into the quantum superposition state |α>, and because 2 n-1 <N<2 n ,that is Therefore, the present invention can be greater than Probability of preparing quantum uniform superposition state

[0080] The present invention first constructs a parallel function f, which can be obtained from a quantum uniform superposition state Mark any quantum uniform superposition state in Then, a quantum circuit for realizing f is given, and the function result of f is stored in the second quantum register to obtain the second quantum superposition state. The second quantum register is measured to determine whether the quantum uniform superposition state is successfully prepared. N Compared with the preparation of quantum superposition state by quantum Fourier transformation, the number of one-bit quantum gates and two-bit quantum gates required by the present invention increases, but the number of three-bit quantum gates is significantly reduced, from O(n 2 ) is reduced to O(n), which improves the implementation accuracy and reduces the number of quantum bits by 2.

[0081] Example 5

[0082] Corresponding to the above method, such as Figure 6 As shown, an embodiment of the present invention provides a system for preparing an arbitrary quantum uniform superposition state, including:

[0083] An initialization module, used to initialize the first quantum register and the second quantum register;

[0084] Transformation module, used to transform the first quantum register Transform, and obtain the first quantum superposition state;

[0085] A parallel function module is used to construct a parallel function, calculate the parallel function, obtain the function result, store the function result in the second quantum register, and obtain the second quantum superposition state;

[0086] The measurement module is used to measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained, otherwise the preparation of the quantum uniform superposition state fails.

[0087] It should be noted that the system for preparing an arbitrary quantum uniform superposition state provided in an embodiment of the present invention is for realizing the above-mentioned method for preparing an arbitrary quantum uniform superposition state. Its specific functions can be referred to the above-mentioned method embodiments and will not be repeated here.

[0088] Example 6

[0089] Based on the above embodiments, an embodiment of the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, a method for preparing an arbitrary quantum uniform superposition state is implemented as described in the above embodiments.

[0090] Preferably, a computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute a method for preparing an arbitrary quantum uniform superposition state as described in the above embodiment.

[0091] In summary, the present invention provides a method for preparing an arbitrary quantum uniform superposition state. The method constructs a special parallel function f to mark an arbitrary quantum uniform superposition state from a special quantum uniform superposition state. Compared with the method based on Z N The upper quantum Fourier transform is used to prepare any quantum uniform superposition state, which has the advantages of a small number of quantum bits and three-dimensional quantum gates required for preparation, and can prepare any quantum uniform superposition state. The present invention provides a realization circuit of a parallel function f, which only requires one quantum gate, two quantum gates, and three-dimensional quantum gates. The realization complexity of the circuit is low, and it can effectively support the preparation of any quantum uniform superposition state and improve the accuracy of preparing any quantum uniform superposition state.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quantum circuit for realizing a parallel function, wherein the parallel function is in, x and N represent two input variables of the parallel function, characterized in that the binary representations of x and N are set to be (x1, x2, …, x n ) and (N1,N2,…,N n ), to reformulate the parallel function as in, Correspondingly, the quantum circuit includes: a first function operator circuit and a second function operator circuit; The first function operator circuit is used to implement the function E; The second function operator circuit is used to implement the function of function S.

2. A quantum circuit for realizing parallel functions according to claim 1, characterized in that: The first function operator circuit includes a parameter N connected in sequence i A quantum NOT gate and a quantum NOT gate controlled by the control; wherein the parameter N i The input of the controlled quantum NOT gate is x i .

3. A quantum circuit for realizing parallel functions according to claim 1, characterized in that: The second function operator circuit includes: two quantum NOT gates and a parameter N i Controlled quantum NOT gate; Among them, the parameter N i The control qubit of the controlled quantum NOT gate is connected between two quantum NOT gates; the input of the previous quantum NOT gate is x i , the parameter N i The controlled quantum bit of the controlled quantum NOT gate is |0〉.

4. A quantum circuit for preparing a quantum uniform superposition state, characterized in that: include: A first quantum register, a second quantum register, and a quantum circuit for realizing a parallel function as claimed in any one of claims 1 to 3; wherein the initial state of the first quantum register is After the transformation, it is used as the first input of the quantum circuit for realizing the parallel function; The initial state of the second quantum register is directly used as the second input of the quantum circuit for implementing the parallel function; The first quantum register is used to store the initial state of the first quantum register. The first quantum superposition state obtained after the transformation; The second quantum register is used to store the function result obtained after the parallel function calculation.

5. A method for preparing an arbitrary quantum uniform superposition state, characterized in that: include: Step 1: Initialize the first quantum register and the second quantum register; Step 2: Perform the first quantum register Transform, and obtain the first quantum superposition state; Step 3: Construct a parallel function, calculate the parallel function, obtain the function result, store the function result in the second quantum register, and obtain the second quantum superposition state; Step 4: Measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained, otherwise the preparation of the quantum uniform superposition state fails.

6. A method for preparing an arbitrary quantum uniform superposition state according to claim 5, characterized in that: The first quantum register state and the second quantum register state are respectively initialized as and 7. A method for preparing an arbitrary quantum uniform superposition state according to claim 5, characterized in that: The first quantum register is Operations, including: Where n is the power parameter, x and N are two input variables of the parallel function, 2 n-1 <N<2 n , θ is the probability parameter, α and β are different transformation parameters, 8. A system for preparing arbitrary quantum uniform superposition states, characterized in that: include: An initialization module, used to initialize the first quantum register and the second quantum register; Transformation module, used to transform the first quantum register Transform, and obtain the first quantum superposition state; A parallel function module is used to construct a parallel function, calculate the parallel function, obtain the function result, store the function result in the second quantum register, and obtain the second quantum superposition state; The measurement module is used to measure the second quantum register. If the measurement result is 1, the quantum uniform superposition state is successfully obtained, otherwise the preparation of the quantum uniform superposition state fails.

9. A terminal device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, a method for preparing an arbitrary quantum uniform superposition state as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The storage medium includes a stored computer program, wherein when the computer program is executed, the device where the storage medium is located is controlled to execute a method for preparing an arbitrary quantum uniform superposition state as claimed in any one of claims 1 to 7.

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