Fault detection device based on fast edge pulse frequency scanning

Abstract

The application discloses a fault detection device based on fast edge pulse frequency scanning, comprising: a digital code type generation module configured to generate a controllable square wave signal based on a preset fast edge pulse period; a delay line module configured to apply two different delay times to the controllable square wave signal to obtain two delay signals; a combination logic module configured to perform logic operation on the two delay signals to obtain a fast edge pulse signal; a signal shaping module configured to shape the fast edge pulse signal; a signal synthesis and distribution module for synthesizing the shaped signal; a collection and spectrum analysis module configured to obtain an input reference spectrum and an output spectrum; and an ADC data processing module configured to calculate a frequency response function based on the input reference spectrum and the output spectrum, and a host computer configured to obtain a fault condition of a measured system according to the spectrum result. The application effectively reduces the system hardware cost and implementation complexity while improving the frequency scanning capability.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a fault detection device based on fast-edge pulse frequency scanning. Background Technology

[0002] Frequency sweep testing is a crucial method in electronic systems, communication systems, and electromagnetic compatibility and signal integrity testing, widely applied in frequency response analysis, filter and amplifier characteristic evaluation, and other scenarios. By applying an excitation signal to the system under test within a certain frequency range and analyzing its output response, the amplitude and phase characteristics of the system under different frequency conditions can be obtained, thereby enabling a quantitative evaluation of the system performance.

[0003] Existing frequency scanning devices typically rely on arbitrary waveform signal generators, radio frequency signal sources, or swept-frequency sinusoidal sources to generate continuously varying frequency excitation signals, and then combine them with spectrum analyzers or acquisition systems to measure the output of the system under test. While these approaches have a certain degree of maturity in the low- or mid-frequency range, they still have significant shortcomings in practical applications.

[0004] On the one hand, traditional frequency sweeping schemes are highly dependent on the sampling rate of the signal generator module and the performance of the digital-to-analog converter (DAC). According to the limitations of the Nyquist sampling theorem, as the scanning frequency range continues to increase, the sampling rate and bandwidth required by the signal generator increase significantly. This not only leads to a substantial increase in equipment costs, but also makes it difficult to guarantee the amplitude stability and spectral purity of the swept signal under high-frequency conditions, thus limiting the applicability of frequency sweeping devices.

[0005] On the other hand, existing frequency scanning methods typically employ point-by-point or narrow-band frequency scanning, meaning that only a single frequency point or a limited frequency band is measured at any given time. While this method achieves high-resolution frequency response, it often requires a long scanning time, resulting in low testing efficiency and failing to meet the engineering requirements of wide-band, rapid testing. Furthermore, due to the lack of gain adjustment capability, the excitation signal energy spectrum is also unevenly distributed, occupying a large portion of the measurement system's dynamic range and reducing the accuracy of effective data within the frequency band. Moreover, when the system under test exhibits time-varying characteristics or nonlinear behavior, traditional point-by-point frequency scanning methods may introduce additional measurement errors.

[0006] Furthermore, during the measurement of the frequency response function, measurement accuracy is often hampered by the system's random noise. In practical fault monitoring, different fault models correspond to different measurement accuracy requirements. Existing fault detection equipment's feedback adjustment mechanism adjusts the test excitation signal strength according to the needs of different test frequencies and test scenarios. In scenarios with low measurement accuracy requirements, it cannot reduce the test excitation power to lower equipment power consumption; in scenarios with high accuracy requirements, it cannot automatically increase the measurement excitation strength to achieve better fault identification.

[0007] Therefore, how to achieve wide-range, high-efficiency frequency scanning without being limited by the sampling rate of traditional signal generators, while ensuring measurement accuracy and reducing system complexity and implementation cost, has become a pressing technical problem in the field of frequency scanning testing. Summary of the Invention

[0008] The purpose of this application is to provide a fault detection device based on fast-edge pulse frequency scanning to solve the aforementioned technical problems in the prior art. The various technical effects of the preferred technical solutions provided in this application are detailed below.

[0009] To achieve the above objectives, this application provides the following technical solutions: The first aspect of this application provides a fault detection device based on fast-edge pulse frequency scanning, comprising: a digital code generation module, several delay line modules, several combinational logic modules, several signal shaping and allocation modules, a signal synthesis and allocation module, a system under test interface module, an acquisition and spectrum analysis module, and an ADC data processing module; the several delay line modules are all connected to the digital code generation module, each combinational logic module is connected to a corresponding delay line module and the signal shaping module, and the signal synthesis and allocation module is connected to the several signal shaping modules, the system under test interface module, and the acquisition and spectrum analysis module. All modules are connected. The acquisition and spectrum analysis module is connected to the interface module of the system under test and the ADC data processing module. The digital code generation module is configured to receive instruction information from the host computer, obtain preset fast-edge pulse parameters according to the instruction information, and generate a controllable square wave signal based on the preset fast-edge pulse parameters. The delay line module is configured to apply two different delay times to the controllable square wave signal according to a preset pulse width and a preset duty cycle to obtain two delayed signals. The combinational logic module is configured to perform logical operations on the two delayed signals to obtain a fast-edge pulse signal. The signal shaping module is configured to... To shorten the rise and fall times of the fast-edge pulse signal, a shaped fast-edge pulse signal is obtained, wherein each shaped fast-edge pulse signal has a different pulse repetition period, duty cycle, and pulse amplitude; the signal synthesis and distribution module is configured to synthesize multiple shaped fast-edge pulse signals, and input the synthesized fast-edge pulse signal as the final test excitation signal to the acquisition and spectrum analysis module and the system under test interface module; the system under test interface module is configured to input the final test excitation signal from the signal synthesis and distribution module to the system under test, and obtain the output signal of the system under test. The output signal is input to the acquisition and spectrum analysis module. The acquisition and spectrum analysis module is configured to perform discrete Fourier transform on the final test excitation signal from the signal synthesis and distribution module and the output signal respectively to obtain the input reference spectrum and the output spectrum, and output them to the ADC data processing module. The ADC data processing module is configured to calculate the frequency response function based on the input reference spectrum and the output spectrum, and send the spectrum result corresponding to the frequency response function of the current parameter combination to the host computer. The host computer obtains the fault status of the system under test based on the spectrum result.

[0010] In some embodiments, the signal shaping and distribution module includes a MOS switch driving unit and a clamping bias; the MOS switch driving unit receives a fast-edge pulse signal from the combinational logic module and amplifies the power of the fast-edge pulse signal; the clamping bias is used to adjust the output level of the signal shaping module.

[0011] In some embodiments, the signal shaping module further includes an isolation protection unit, which includes at least a series current-limiting resistor, a diode clamp, a MOS buffer isolation circuit, and an overvoltage / overcurrent protection circuit.

[0012] In some embodiments, the acquisition and spectrum analysis module includes multiple sub-ADC channels, which have a preset phase interleaving relationship, and each sub-ADC channel samples the same signal according to a sampling clock with a different phase.

[0013] In some embodiments, the acquisition and spectrum analysis module further includes a unified triggering and clock synchronization circuit and a digital calibration logic circuit. The unified triggering and clock synchronization circuit is used to synchronously acquire the final test excitation signal and the output signal, and the digital calibration logic circuit is used to compensate for inter-channel gain / bias / time offset errors.

[0014] In some embodiments, the acquisition and spectrum analysis module includes a reference sampling branch and a system under test excitation branch, wherein the reference sampling branch is used to receive the final test excitation signal, and the system under test excitation branch is used to receive the output signal.

[0015] In some embodiments, the preset parameters of the delay line module include at least the delay time, delay difference, minimum delay line resolution, pulse repetition period, duty cycle, and pulse amplitude.

[0016] In some embodiments, the host computer dynamically adjusts the preset pulse width and preset duty cycle of each delay line module according to the input reference spectrum until the flatness of the final test excitation signal meets the preset design requirements and covers all frequencies of interest.

[0017] In some embodiments, the host computer obtains the signal-to-noise ratio of each frequency point based on the spectrum result. If there are frequency points that do not meet the preset threshold, the host computer instructs the digital code generation module to generate a new controllable square wave signal until all frequency points meet the preset threshold.

[0018] The second aspect of this application discloses a fault detection method based on fast-edge pulse frequency scanning. This method is applied to the fault detection device based on fast-edge pulse frequency scanning described above, and includes: receiving instruction information from a host computer; obtaining preset fast-edge pulse parameters according to the instruction information; generating a controllable square wave signal based on the preset fast-edge pulse parameters; applying two different delay times to the controllable square wave signal according to a preset pulse width and a preset duty cycle to obtain two delayed signals; performing logical operations on the two delayed signals to obtain a fast-edge pulse signal; and shortening the rise and fall times of the fast-edge pulse signal to obtain a shaped signal. The system generates fast-edge pulse signals, each of which has a different pulse repetition period, duty cycle, and pulse amplitude. Multiple shaped fast-edge pulse signals are synthesized, and the synthesized fast-edge pulse signal is used as the final test excitation signal. This final test excitation signal is input to the system under test (SUT) to obtain the SUT's output signal. Discrete Fourier transforms are performed on both the final test excitation signal and the output signal to obtain the input reference spectrum and the output spectrum. Based on the input reference spectrum and the output spectrum, a frequency response function is calculated. The fault condition of the SUT is obtained based on the spectrum result corresponding to the frequency response function.

[0019] Implementing one of the above-mentioned technical solutions of this application has the following advantages or beneficial effects: In this application, the delay line module first applies two different delay times to the controllable square wave signal to obtain two delayed signals. Then, the combinational logic module performs logical operations to obtain a fast-edge pulse signal. Subsequently, the signal shaping module shapes the fast-edge pulse signal, and the signal synthesis and distribution module synthesizes multiple shaped fast-edge pulse signals as the final test excitation signal, which is divided into two final test excitation signals. One signal is directly input to the acquisition and spectrum analysis module, and the other signal is first input to the system under test to obtain the output signal and then input to the acquisition and spectrum analysis module. Finally, the acquisition and spectrum analysis module obtains the spectrum response function based on the two signals, and the host computer obtains the fault information based on the spectrum result corresponding to the spectrum response function.

[0020] In this context, compared to traditional schemes that rely on high-speed digital-to-analog converters to generate wideband sweep signals, this application generates fast-edge pulse signals by applying different delays to the same rising edge and combining them logically. The supported frequency range and resolution are determined by the minimum delay resolution of the delay line. Since delay lines are easier to control at the picosecond level, this application achieves high-frequency scanning capability without requiring a high-sampling-rate, high-cost signal generator module, thus effectively reducing system hardware costs and implementation complexity while improving frequency scanning capability.

[0021] Furthermore, this application not only acquires the output signal of the system under test, but also the spectral information of the excitation signal generated by the signal source branch. By analyzing the difference in the spectra of the two, the frequency response function is obtained to determine the fault status of the system under test. Compared with existing time-division or step-by-step measurement methods, this application can effectively reduce the impact of signal source drift, environmental changes, and other factors on the measurement results, thereby improving the accuracy and consistency of the system frequency response measurement. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a structural block diagram of a fault detection device based on fast-edge pulse frequency scanning according to an embodiment of this application; Figure 2 This is a schematic diagram of a fast-edge pulse signal according to an embodiment of this application; Figure 3 This is a circuit diagram of the signal shaping module and the signal synthesis and distribution module according to an embodiment of this application.

[0023] In the diagram: 1. Fault detection device based on fast edge pulse frequency scanning; 2. Host computer; 3. System under test; 10. Digital code generation module; 20. Delay line module; 30. Combinational logic module; 40. Signal shaping module; 41. MOS switch driving unit; 42. Clamping biaser; 43. Isolation protection unit; 50. Signal synthesis and distribution module; 60. System under test interface module; 70. Acquisition and spectrum analysis module; 71. Sub-ADC channel; 72. Unified trigger and clock synchronization circuit; 73. Digital calibration logic circuit; 80. ADC data processing module; CH1. Reference sampling branch; CH2. Excitation branch of system under test. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments and depict various exemplary embodiments that may be adopted to implement this application. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this application disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this application.

[0025] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] To illustrate the technical solutions described in this application, specific embodiments are provided below, showing only the parts related to the embodiments of this application.

[0027] This application relates to a fault detection device 1 based on fast-edge pulse frequency scanning, which can also be simply referred to as a fault detection device. It is used to measure the spectral response of the system under test 3 in a wide frequency range, and obtain the frequency response function and the corresponding spectral result by comparing the spectral difference between the excitation signal and the output signal of the system under test 3. Then, by controlling the pulse parameter update, a full-spectrum scan is achieved to obtain the fault information of the system under test 3.

[0028] like Figures 1 to 3 As shown, this application provides a fault detection device 1 based on fast-edge pulse frequency scanning, comprising: The system includes a digital code generation module 10, several delay line modules 20, several combinational logic modules 30, several signal shaping modules 40, a signal synthesis and distribution module 50, a system under test interface module 60, an acquisition and spectrum analysis module 70, and an ADC data processing module 80.

[0029] In some embodiments, several delay line modules 20 are connected to the digital code generation module 10, each combinational logic module 30 is connected to the corresponding delay line module 20 and signal shaping module 40, the signal synthesis and distribution module 50 is connected to several signal shaping modules 40, the system under test interface module 60 and the acquisition and spectrum analysis module 70, and the acquisition and spectrum analysis module 70 is connected to the system under test interface module 60 and the ADC data processing module 80.

[0030] The digital code generation module 10 can be configured to receive instruction information from the host computer 2, obtain preset fast-edge pulse parameters according to the instruction information, and generate a controllable square wave signal based on the preset fast-edge pulse parameters. The controllable square wave signal serves as a wideband excitation source, that is, a signal source capable of generating electrical signals or energy covering an extremely wide frequency range (from DC / low frequency to high frequency / RF).

[0031] The delay line module 20 can be configured to apply two different delay times to a controllable square wave signal according to a preset pulse width and a preset duty cycle, thereby obtaining two delayed signals. The delayed signal is a square wave signal with a definite time delay difference.

[0032] The combinational logic module 30 can be configured to perform logical operations on two delayed signals to obtain a fast-edge pulse signal, such as performing an XOR operation. The fast-edge pulse signal is a fast-edge narrow pulse signal with controlled pulse width.

[0033] The signal shaping module 40 can be configured to shorten the rise and fall times of the fast-edge pulse signal to obtain shaped fast-edge pulse signals, wherein each shaped fast-edge pulse signal has a different pulse repetition period, duty cycle, and pulse amplitude. By shaping the fast-edge pulse signal, the rise and fall times are reduced, thereby increasing the driving capability.

[0034] The signal synthesis and distribution module 50 can be configured to synthesize multiple shaped fast-edge pulse signals and input the synthesized fast-edge pulse signal as the final test excitation signal to the acquisition and spectrum analysis module 70 and the interface module 60 of the system under test. Specifically, the signal synthesis and distribution module 50 can divide the final test excitation signal into two paths: one final test excitation signal is used for reference measurement of the excitation source spectrum, and the other final test excitation signal is input to the system under test 3 to obtain the output signal of the system under test 3.

[0035] The interface module 60 of the system under test can be configured to input the final test excitation signal from the signal synthesis and distribution module 50 to the system under test 3, acquire the output signal of the system under test 3, and input the output signal to the acquisition and spectrum analysis module 70.

[0036] The acquisition and spectrum analysis module 70 can be configured to perform discrete Fourier transform on the final test excitation signal from the signal synthesis and distribution module 50 and the output signal respectively to obtain the input reference spectrum and the output spectrum, and output them to the ADC data processing module 80.

[0037] The ADC data processing module 80 is configured to calculate the frequency response function based on the input reference spectrum and the output spectrum, and send the spectrum result corresponding to the frequency response function of the current parameter combination to the host computer 2. The host computer 2 obtains the fault status of the system under test 3 based on the spectrum result.

[0038] In addition, the host computer 2 can complete the interaction between the instrument and the user through interfaces such as PCIe and network port, and send commands such as pulse width, preset pulse period, and trigger.

[0039] In some embodiments, the host computer 2 can dynamically adjust the preset pulse width and preset duty cycle of each delay line module 20 according to the input reference spectrum until the flatness of the final test excitation signal meets the preset design requirements and covers all frequencies of interest.

[0040] Specifically, to ensure the test excitation signal spectrum is flat, the signal synthesis and distribution module 50 synthesizes fast-edge pulse signals with different pulse repetition periods, duty cycles, and pulse amplitudes generated by multiple signal shaping modules 40. Based on the test excitation signal spectrum analysis acquired by the acquisition and spectrum analysis module 70, the pulse width information of each delay line module 20 is continuously adjusted until the flatness of the test excitation signal meets the design requirements and covers all frequency points of interest to the user.

[0041] To acquire frequency response values ​​from multiple frequency points more quickly, this application sets up multiple fast-edge pulse signal generation channels, including a delay line module 20, a combinational logic module 30, and a signal shaping module 40. These fast-edge pulse signals are then combined in the signal synthesis and distribution module 50 to generate the final test excitation signal. Based on the test excitation signal spectrum obtained from the acquisition and spectrum analysis module 70 (i.e., the input reference spectrum), the pulse width, amplitude, and frequency of each fast-edge pulse signal generation channel are dynamically adjusted to obtain a flat test excitation signal spectrum containing all required frequency points, thereby improving fault detection efficiency.

[0042] In some embodiments, the fault detection device 1 based on fast-edge pulse frequency scanning may further include a clock module (not shown in the figure), which may be configured to send a synchronized clock signal to the digital code generation module 10 and the ADC data processing module 80.

[0043] In some embodiments, the acquisition and spectrum analysis module 70 may include a reference sampling branch CH1 and a system under test excitation branch CH2. The reference sampling branch CH1 is used to receive the final test excitation signal, and the system under test excitation branch CH2 is used to receive the output signal.

[0044] Specifically, the delay line module 20 can send square wave signals of the same period into two delay channels respectively, applying different delay times to the two channels, denoted as τ1 and τ2. Therefore, the delay difference can be expressed as Δτ=|τ2-τ1|. Subsequently, the combinational logic module 30 performs an XOR operation on the two delayed signals, and outputs a pulse formed within the time window when the logic levels of the two signals are inconsistent, resulting in a fast-edge pulse signal. Therefore, the output pulse width can be expressed as: Tp=|τ2-τ1|, that is, the delay difference can determine the pulse width. This pulse has fast rise / fall characteristics, and the output spectrum covers a wide frequency range, which can be used as a broadband excitation signal source. Compared with the prior art, this application changes the frequency sweep excitation signal from a sine wave to a square wave signal with adjustable pulse width, that is, the fast-edge pulse signal of this application, thereby reducing hardware costs.

[0045] like Figure 2 As shown, line a represents the signal waveform with an applied delay time τ1, line b represents the signal waveform with an applied delay time τ2, and line c represents the fast-edge pulse signal obtained by performing logical operations, such as XOR operations, on the two delayed signals through the combinational logic module 30.

[0046] In some embodiments, the preset parameters of the delay line module 20 include at least the two-channel delay times τ1 and τ2 (configurable), the delay difference Δτ = |τ2-τ1| (which determines the pulse width Tp), the minimum resolution of the delay line δτ (typically at the ps level), which determines the pulse width adjustment accuracy, the pulse repetition period T (PRT), which is determined by the trigger frequency or frequency division counting, the duty cycle D = Tp / T, and the pulse amplitude A (determined by the output drive and the load).

[0047] Compared to traditional frequency sweeping, which excites only one frequency point (or narrow band) at a time and requires sweeping the frequency point by point, the single fast-edge pulse signal of this application contains rich spectral components, and the system response of multiple frequency points can be obtained simultaneously in one acquisition; by changing parameters such as pulse width Tp and pulse repetition period T, the spectral energy distribution can be changed to achieve full-spectrum scanning.

[0048] To address issues such as slowed edges, insufficient drive, uncontrollable output levels, and susceptibility of the core controller (FPGA) to backflow / overvoltage from the system under test (SUT) during actual output of fast-edge pulse signals, this application incorporates several signal shaping modules 40, signal synthesis and distribution modules 50, and a SUT interface module 60 between the combinational logic module 30 and the SUT. The core controller includes a digital code generation module 10, a delay line module 20, a combinational logic module 30, and an ADC data processing module 80.

[0049] The signal shaping module 40 is used to perform secondary shaping and level driving on the fast-edge pulse signal. The signal synthesis and distribution module 50 distributes the synthesized and shaped signal to the reference sampling branch CH1 and the excitation branch CH2 of the system under test, while providing electrical isolation and protection for the FPGA.

[0050] In some embodiments, the signal shaping module 40 may include a MOS switch driving unit 41 and a clamping bias unit 42.

[0051] The MOS switch driver unit 41 receives fast-edge pulse signals from the combinational logic module 30 and amplifies the power of the fast-edge pulse signals. The MOS switch driver unit 41 can use MOS transistors as switching devices, such as high-side / low-side or push-pull structures, which can convert input control signals into pulse outputs with strong driving capabilities.

[0052] like Figure 3 As shown, the MOS switch driving unit 41 may include a two-stage shaping circuit composed of PMOS2 and NMOS2. The periodic square wave generated by the FPGA is the fast-edge pulse signal mentioned above. The MOS switch driving unit 41 can be used to increase the driving capability of the fast-edge pulse signal and can obtain steeper rising and falling edges. Further, the output signal V of the MOS switch driving unit 41 out The amplitude can be determined by V1, which can be adjusted according to actual needs. While maintaining measurement accuracy, adjusting V1 can save power consumption.

[0053] Clamping bias unit 42 is used to adjust the output level of signal shaping module 40. Specifically, clamping bias unit 42 replaces the fixed power supply bias section and uses diode clamping or equivalent limiting structure to adjust the output level relative to programmable bias V. bias Related, where V bias The output is provided by the DAC and buffered / regulated to enable in-system programmable setting of the output pulse level. The high and low levels of the output pulse can be determined by the power supply rail or bias voltage, thus achieving configurable output level. For example, Figure 3 As shown, NMOS1 is used to enhance the drive capability of the voltage source output; V biasGenerated by a DAC, V1 is the drive level automatically selected by the user or test process based on accuracy requirements, as shown in the formula below: In some embodiments, the signal shaping module 40 may further include an isolation protection unit 43, which may include at least a series current-limiting resistor, a diode clamp, a MOS buffer isolation circuit, and an overvoltage / overcurrent protection circuit. The isolation protection unit 43 may be located between the FPGA / control terminal and an external high-energy / unknown impedance load to suppress the effects of reverse current flow, level over-limit, and ESD / transient impacts on the FPGA from the system under test.

[0054] In one specific embodiment, a fast-edge pulse signal enters the MOS switch driving unit 41. The MOS switch driving unit 41 can control the MOS switching device to turn on / off according to the moment when the input amplitude crosses the threshold, so that the output terminal switches quickly between high and low levels, thereby realizing pulse edge regeneration, that is, shaping and drive enhancement. The high / low level of the output stage is determined by the clamping bias unit 42, specifically through a programmable bias V. bias (From DAC output) Adjust the clamp level to achieve online setting of output swing / level.

[0055] Meanwhile, the isolation protection unit 43 is used to ensure that reflected, overvoltage or transient currents from the external system under test do not directly act on the FPGA output pins, thereby protecting the core device.

[0056] In some embodiments, the acquisition and spectrum analysis module 70 may include multiple sub-ADC channels 71, which have a preset phase interleaving relationship. Each sub-ADC channel 71 samples the same signal according to a sampling clock with a different phase.

[0057] In some embodiments, the acquisition and spectrum analysis module 70 may further include a unified trigger and clock synchronization circuit 72 and a digital calibration logic circuit 73. The unified trigger and clock synchronization circuit 72 is used to synchronously acquire the final test excitation signal and the output signal to ensure the synchronous acquisition of the reference sampling branch CH1 and the excitation branch CH2 of the system under test. The digital calibration logic circuit 73 is used to compensate for the gain / bias / time offset errors between channels, thereby improving spectrum consistency.

[0058] In one specific embodiment, the acquisition and spectrum analysis module 70 can perform Discrete Fourier Transform (DFT / FFT) on the reference sampling branch CH1 and the excitation branch CH2 of the system under test respectively to obtain the input reference spectrum. X ( jw and output spectrum Y ( jwThe frequency response function can be calculated in amplitude / phase frequency form, and can be expressed as: H(jw) = Y(jw) / X(jw). In engineering implementation, multiple acquisition results can be averaged or a window function can be used to improve the signal-to-noise ratio and spectral resolution.

[0059] The set of scanning parameters for the acquisition and spectrum analysis module 70 includes at least: the set of delay differences {Δτ} k} (corresponding to different pulse widths T) p,k ), pulse repetition period set {Tm} or trigger frequency set {ftr, m}, number of sampling points N, sampling duration Tacq, average number of times M, and spectral resolution target Δf=1 / Tacq (or equivalent).

[0060] In summary, this application sets different delay times τ1 and τ2 for the two-channel delay lines using the delay line module 20, forming a delay difference Δτ. This difference is then processed by the combinational logic module 30 to obtain a fast-edge pulse signal with a pulse width of Tp = Δτ. Subsequently, the fast-edge pulse signal is shaped by the signal shaping module 40, and the signal synthesis and distribution module 50 synthesizes the shaped fast-edge pulse signals to obtain the final test excitation signal. This final test excitation signal is then distributed to the reference sampling branch CH1, and the output signal obtained based on the final test excitation signal is distributed to the excitation branch CH2 of the system under test. Simultaneously, the waveform xin(t) of the reference sampling branch CH1 and the output waveform xout(t) of the system under test are acquired within the same sampling window. Discrete Fourier transforms are then performed on the two sampled data streams to obtain the input reference spectrum. X ( jw ) and output spectrum Y ( jw Based on the input reference spectrum X ( jw ) and output spectrum Y ( jw Calculate the frequency response function H(jw) = Y(jw) / X(jw) and record the current parameter combination (pulse width T). p The spectral response results are obtained under the pulse repetition period T and duty cycle D. Then, the pulse parameters are updated, for example, by changing the delay difference Δτ or the pulse repetition period T. The above steps are repeated until the parameter delay difference set {Δτ} is completely traversed. k The system uses a set of pulse repetition periods {Tm} to achieve full spectrum coverage or enhanced scanning of a specified frequency band. Finally, it outputs the amplitude response, phase response, or equivalent frequency response function curves, and provides the response "envelope" under multiple parameter combinations to evaluate the system performance boundaries.

[0061] In some embodiments, the host computer 2 can obtain the signal-to-noise ratio (SNR) of each frequency point based on the response result. If there are frequency points that do not meet the preset threshold, the host computer 2 instructs the digital code generation module 10 to generate a new controllable square wave signal until all frequency points meet the preset threshold. By dynamically adjusting the controllable square wave signal according to different scenario requirements to adjust the subsequent fast-edge pulse signal, the system power consumption and measurement time can be reduced as much as possible while meeting the measurement accuracy requirements.

[0062] Traditional frequency scanning methods typically employ point-by-point or narrow-band scanning, exciting only a single frequency point or a limited frequency band at any given time, resulting in a lengthy overall scanning process. This application utilizes the wide-spectrum characteristics of fast-edge pulse signals, which contain abundant high-frequency harmonic components, to simultaneously cover multiple frequency components under a single excitation condition. Furthermore, it obtains the response characteristics of the system under test (SUT) at multiple frequency points through spectrum analysis, thereby transforming the process from "point-by-point frequency scanning" to "parallel spectrum measurement," significantly improving frequency scanning efficiency.

[0063] In this application, the delay line module 20 first applies two different delay times to the controllable square wave signal to obtain two delayed signals. Then, the combinational logic module 30 performs logic operations to obtain a fast-edge pulse signal. Subsequently, the signal shaping module 40 shapes the fast-edge pulse signal. Based on the signal synthesis and distribution module 50, multiple shaped fast-edge pulse signals are synthesized as the final test excitation signal and divided into two final test excitation signals. One of them is directly input to the acquisition and spectrum analysis module 70, and the other is first input to the system under test 3 to obtain the output signal and then input to the acquisition and spectrum analysis module 70. Finally, the acquisition and spectrum analysis module 70 obtains the spectrum response function based on the two signals, and the host computer 2 obtains the fault information according to the spectrum result corresponding to the spectrum response function.

[0064] In this context, compared to traditional schemes that rely on high-speed digital-to-analog converters to generate wideband sweep signals, this application generates fast-edge pulse signals by applying different delays to the same rising edge and combining them logically. The supported frequency range and resolution are determined by the minimum delay resolution of the delay line. Since delay lines are easier to control at the picosecond level, this application achieves high-frequency scanning capability without requiring a high-sampling-rate, high-cost signal generator module, thus effectively reducing system hardware costs and implementation complexity while improving frequency scanning capability.

[0065] Furthermore, this application not only acquires the output signal of the system under test 3, but also acquires the spectral information of the excitation signal generated by the signal source branch. By analyzing the difference in the spectra of the two, the frequency response function is obtained to acquire the fault status of the system under test. Compared with existing time-division or step-by-step measurement methods, this application can effectively reduce the impact of signal source drift, environmental changes, and other factors on the measurement results, and improve the accuracy and consistency of the system frequency response measurement.

[0066] This application also relates to a fault detection method based on fast-edge pulse frequency scanning, which is applied to the aforementioned fault detection device 1 based on fast-edge pulse frequency scanning, and includes the following steps: Receive instruction information from host computer 2, obtain preset fast edge pulse parameters according to the instruction information, and generate a controllable square wave signal based on the preset fast edge pulse parameters; Based on the preset pulse width and preset duty cycle, two different delay times are applied to the controllable square wave signal to obtain two delayed signals. Logical operations are performed on the two delayed signals to obtain a fast-edge pulse signal. The rise and fall times of the fast edge pulse signal are shortened to obtain the shaped fast edge pulse signal. Each shaped fast edge pulse signal has a different pulse repetition period, duty cycle and pulse amplitude. Multiple shaped fast edge pulse signals are synthesized and the synthesized fast edge pulse signal is used as the final test excitation signal. The final test excitation signal is input to the system under test 3 to obtain the output signal of the system under test 3. Discrete Fourier transforms are performed on the final test excitation signal and the output signal to obtain the input reference spectrum and the output spectrum. Based on the input reference spectrum and the output spectrum, the frequency response function is calculated, and the fault status of the tested system 3 is obtained according to the spectrum result corresponding to the frequency response function.

[0067] Those skilled in the art will understand that all or part of the features / steps of the above-described method embodiments can be implemented by methods, data processing systems, or computer programs. These features may be implemented without hardware, entirely in software, or in a combination of hardware and software. The aforementioned computer program may be stored in one or more computer-readable storage media. When the computer program is executed (e.g., by a processor), it performs the steps of the above-described fault detection method embodiments based on fast-edge pulse frequency scanning.

[0068] The aforementioned storage media capable of storing program code include: static hard disks, solid-state hard disks, random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), optical storage devices, magnetic storage devices, flash memory, magnetic disks or optical disks, and / or combinations of the above devices, that is, they can be implemented by any type of volatile or non-volatile storage devices or combinations thereof.

[0069] This application also provides a processing device embodiment, including one or more processors and a memory; wherein the memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processors perform the features / steps of the above-described fault detection method embodiment based on fast edge pulse frequency scanning.

[0070] The above description is merely a preferred embodiment of this application. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this application. Furthermore, under the teachings of this application, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this application. Therefore, this application is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this application.

Claims

1. A fault detection device based on fast-edge pulse frequency scanning, characterized in that, include: The system includes a digital code generation module, several delay line modules, several combinational logic modules, several signal shaping modules, a signal synthesis and distribution module, a system under test interface module, an acquisition and spectrum analysis module, and an ADC data processing module. The plurality of delay line modules are all connected to the digital code generation module, each of the combinational logic modules is connected to the corresponding delay line module and the signal shaping module, the signal synthesis and distribution module is connected to the plurality of signal shaping modules, the system under test interface module and the acquisition and spectrum analysis module, and the acquisition and spectrum analysis module is connected to the system under test interface module and the ADC data processing module. The digital code generation module is configured to receive instruction information from the host computer, obtain preset fast edge pulse parameters according to the instruction information, and generate a controllable square wave signal based on the preset fast edge pulse parameters. The delay line module is configured to apply two different delay times to the controllable square wave signal according to a preset pulse width and a preset duty cycle, thereby obtaining two delayed signals. The combinational logic module is configured to perform logical operations on the two delayed signals to obtain a fast-edge pulse signal; The signal shaping module is configured to shorten the rise and fall times of the fast-edge pulse signal to obtain shaped fast-edge pulse signals, wherein each shaped fast-edge pulse signal has a different pulse repetition period, duty cycle and pulse amplitude. The signal synthesis and distribution module is configured to synthesize multiple shaped fast-edge pulse signals, and input the synthesized fast-edge pulse signal as the final test excitation signal to the acquisition and spectrum analysis module and the interface module of the system under test; The interface module of the system under test is configured to input the final test excitation signal from the signal synthesis and distribution module to the system under test, acquire the output signal of the system under test, and input the output signal to the acquisition and spectrum analysis module; The acquisition and spectrum analysis module is configured to perform discrete Fourier transform on the final test excitation signal from the signal synthesis and distribution module and the output signal respectively to obtain the input reference spectrum and the output spectrum, and output them to the ADC data processing module. The ADC data processing module is configured to calculate the frequency response function based on the input reference spectrum and the output spectrum, and send the spectrum result corresponding to the frequency response function of the current parameter combination to the host computer. The host computer obtains the fault status of the system under test based on the spectrum result.

2. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The signal shaping module includes a MOS switch driving unit and a clamping biaser; The MOS switch driving unit receives a fast-edge pulse signal from the combinational logic module and amplifies the power of the fast-edge pulse signal; The clamping bias is used to adjust the output level of the signal shaping module.

3. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The signal shaping module also includes an isolation protection unit, which includes at least a series current-limiting resistor, a diode clamp, a MOS buffer isolation circuit, and an overvoltage / overcurrent protection circuit.

4. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The acquisition and spectrum analysis module includes multiple sub-ADC channels, which have a preset phase interleaving relationship. Each sub-ADC channel samples the same signal according to a sampling clock with a different phase.

5. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The acquisition and spectrum analysis module also includes a unified trigger and clock synchronization circuit and a digital calibration logic circuit. The unified trigger and clock synchronization circuit is used to synchronously acquire the final test excitation signal and the output signal, and the digital calibration logic circuit is used to compensate for inter-channel gain / bias / time offset errors.

6. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The acquisition and spectrum analysis module includes a reference sampling branch and a system under test excitation branch. The reference sampling branch is used to receive the final test excitation signal, and the system under test excitation branch is used to receive the output signal.

7. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The preset parameters of the delay line module include at least the delay time, delay difference, minimum delay line resolution, pulse repetition period, duty cycle, and pulse amplitude.

8. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The host computer dynamically adjusts the preset pulse width and preset duty cycle of each delay line module according to the input reference spectrum until the flatness of the final test excitation signal meets the preset design requirements and covers all frequencies of interest.

9. The fault detection device based on fast-edge pulse frequency scanning according to claim 1, characterized in that, The host computer obtains the signal-to-noise ratio of each frequency point based on the spectrum results. If there are frequency points that do not meet the preset threshold, the host computer instructs the digital code generation module to generate a new controllable square wave signal until all frequency points meet the preset threshold.

10. A fault detection method based on fast-edge pulse frequency scanning, wherein the fault detection method based on fast-edge pulse frequency scanning is applied to the fault detection device based on fast-edge pulse frequency scanning as described in any one of claims 1 to 9, characterized in that, include: Receive instruction information from the host computer, obtain preset fast edge pulse parameters according to the instruction information, and generate a controllable square wave signal based on the preset fast edge pulse parameters; Based on the preset pulse width and preset duty cycle, two different delay times are applied to the controllable square wave signal to obtain two delayed signals. Logical operations are performed on the two delayed signals to obtain a fast-edge pulse signal. The rise and fall times of the fast-edge pulse signal are shortened to obtain a shaped fast-edge pulse signal, wherein each shaped fast-edge pulse signal has a different pulse repetition period, duty cycle and pulse amplitude. Multiple shaped fast-edge pulse signals are synthesized, and the synthesized fast-edge pulse signal is used as the final test excitation signal. The final test excitation signal is input to the system under test to obtain the output signal of the system under test. The final test excitation signal and the output signal are subjected to discrete Fourier transform to obtain the input reference spectrum and the output spectrum. Based on the input reference spectrum and the output spectrum, the frequency response function is calculated, and the fault status of the system under test is obtained according to the spectrum result corresponding to the frequency response function.

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