Memory system and method of programming memory system

Abstract

The invention relates to a memory system and a method for programming the memory system. The memory system may include a memory device and a memory controller. The memory device includes a memory cell for storing data and a plurality of latches for storing code values indicating the data. The memory device may be configured to program data into each memory cell, store an original code value indicating the data in the plurality of latches, and change the original code value stored in the plurality of latches to an erase code value in response to a verification pass. The memory controller is configured to output to the memory device at least a pause command to pause programming and a recovery command to recover the code value changed to the erase code value in response to detecting the sudden power-off.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0091214 filed on July 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory system, and more particularly, to a memory system and a method of programming the memory system. Background Art

[0004] A memory system is a device that stores data under the control of a host device such as a computer or a smart phone. A memory device may include a memory device that stores data and a memory controller that controls the memory device. Such memory devices are classified into volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when the power supply is interrupted. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] A nonvolatile memory device is a memory device that retains stored data even when power supply is interrupted. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), and flash memory.

[0007] During a programming operation of a memory device, a sudden power off (SPO) may occur. The memory device may suspend the programming operation in response to the sudden power off and store information related to the suspended programming operation, thereby resuming the suspended programming operation when power is restored. The accuracy of the programming operation to be performed after power is restored may vary according to data stored in the memory device before power of the memory device is turned off. Summary of the invention

[0008] Various embodiments of the present disclosure are directed to a memory system and a method of programming the memory system, which recover and store data changed during a programming operation in response to the occurrence of a sudden power failure.

[0009] Embodiments of the present disclosure may provide a memory system. The memory system may include a memory device and a memory controller. The memory device includes a memory cell for storing data and a plurality of latches for storing a code value indicating the data. The memory device may be configured to program data into each memory cell, store the original code value indicating the data in a plurality of latches, and change the original code value stored in the plurality of latches to an erase code value in response to verification. The memory controller may be configured to output to the memory device a pause command for at least suspending programming in response to detecting a sudden power failure and a resume command for restoring the code value changed to the erase code value. The memory device may be configured to restore the changed code value to the original code value based on the threshold voltage of the memory cell in response to the resume command.

[0010] Embodiments of the present disclosure may provide a method for operating a memory system, the memory system including a memory device and a memory controller, the memory device including a memory cell storing data and a plurality of latches storing a code value indicating the data. The memory device may be configured to program data into each memory cell, store the original code value indicating the data in the plurality of latches, and in response to verification, change the original code value stored in the plurality of latches to an erase code value, and the memory controller is configured to generate a control command to control the memory device. The method may include: detecting a sudden power failure occurring in the memory system; outputting a suspend command for suspending at least programming in response to detecting a sudden power failure and a restore command for restoring the code value changed to the erase code value to the memory device; and performing a restore operation in response to the restore command, the restore operation including restoring the changed code value to the original code value based on the result of comparing the read voltage corresponding to the programming state of each memory cell with the threshold voltage of the memory cell, respectively.

[0011] Embodiments of the present disclosure may provide a memory system. The memory system may include a memory device and a memory controller. The memory device includes a plurality of memory cells storing data and a plurality of latches for storing code values ​​indicating data. The memory device may be configured to perform a first programming operation, the first programming operation including programming multi-bit data into each memory cell, storing the original code value indicating the multi-bit data in a plurality of latches, and changing the original code value stored in the plurality of latches to an erase code value in response to the verification passing within the first programming operation. The memory controller is configured to output a pause command for suspending the first programming operation in response to the occurrence of a sudden power failure and a recovery command for recovering the code value changed to the erase code value among the code values ​​stored in the plurality of latches to the memory device. The memory device may be configured to perform a recovery operation in response to a recovery command, the recovery operation including recovering the changed code value to the original code value based on the threshold voltage of the memory cell, dividing the recovered original code value into 1-bit units, and programming the 1-bit unit into a plurality of memory cells.

[0012] An embodiment of the present disclosure may provide a method for operating a memory system, the memory system including a memory device and a memory controller, the memory device including a plurality of memory cells storing data and a plurality of latches storing code values ​​indicating the data, the memory device being configured to perform a first programming operation, the first programming operation including programming multi-bit data into each memory cell, storing an original code value indicating the multi-bit data in a plurality of latches, and changing the original code value stored in the plurality of latches to an erase code value in response to verification passing in the first programming operation. The memory controller is configured to generate a control command for controlling the memory device. The method may include: detecting a sudden power failure occurring in the memory system, outputting a pause command for suspending the first programming operation in response to detecting the sudden power failure and a recovery command for recovering the code value changed to the erase code value among the code values ​​stored in the plurality of latches to the memory device; in response to the recovery command, performing a recovery operation, recovering the changed code value to the original code value based on the result of comparing the read voltage corresponding to the programming state of each memory cell with the threshold voltage of the memory cell respectively; and performing a second programming operation of dividing the recovered original code value into 1-bit units and programming the 1-bit units into a plurality of memory cells.

[0013] Embodiments of the present disclosure may provide a memory system, the memory system comprising a memory device and a controller, the memory device comprising a plurality of memory cells for programming data and a plurality of latches for storing bits of the data. The memory device may be configured to store the code value of the data whose programming operation is interrupted by a sudden power failure in the plurality of latches, and to restore the code value of the data to the original code value of the data before the programming operation in response to a recovery command of the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram illustrating threshold voltage distributions and code values ​​of a triple-level cell stored in a plurality of latches according to an embodiment of the present disclosure.

[0016] Figure 3 is a diagram illustrating a code value changed in response to a verification pass within a program operation on a triple-level cell according to an embodiment of the present disclosure.

[0017] Figure 4 is a diagram illustrating restoring and programming a code value changed in response to detecting the occurrence of a sudden power failure according to an embodiment of the present disclosure.

[0018] Figure 5 is a diagram illustrating a target code value restored based on a threshold voltage of a memory cell according to an embodiment of the present disclosure.

[0019] Figure 6 is a table showing code values ​​stored in a plurality of latches according to an embodiment of the present disclosure.

[0020] Figure 7 is a table showing the time during which code values ​​stored in a plurality of latches are maintained according to an embodiment of the present disclosure.

[0021] Figure 8 is a diagram illustrating an operation of resuming a suspended program operation after power restoration according to an embodiment of the present disclosure.

[0022] Fig. 9 is a flowchart illustrating a method of programming data in a program operation suspended in response to a sudden power failure according to an embodiment of the present disclosure.

[0023] Fig.10 is a flowchart illustrating a method of restoring a changed code value according to an embodiment of the present disclosure.

[0024] Fig.11 is a diagram illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The specific structure or function description in the embodiment of the disclosed concept introduced in this specification or application is only used for the purpose of describing the embodiment according to the disclosed concept. The embodiment according to the disclosed concept can be practiced in various forms, and the claims should not be interpreted as being limited to the embodiments described in this specification or application.

[0026] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , the memory system 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100. The memory system 50 may be a device that stores data under the control of a host such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet computer, or an in-vehicle infotainment system.

[0028] The memory device 100 stores data. The memory device 100 may operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array 110 including memory cells storing data; an address decoder 120 decoding a column address; an input / output circuit 130 transmitting / receiving data to / from an external system of the memory device 100; a control logic 140; and a voltage generator 150 generating a plurality of voltages having different voltage levels.

[0029] Each memory cell included in the memory cell array 110 may be a single-layer cell (SLC) storing 1-bit data, or may be a memory cell storing multi-bit data. Depending on the number of bits in the multi-bit data, the memory cell storing the multi-bit data may be a multi-layer cell (MLC) storing 2-bit data, a triple-layer cell (TLC) storing 3-bit data, or a quad-layer cell (QLC) storing 4-bit data. Hereinafter, although an example in which each memory cell is a triple-layer cell (TLC) is used for convenience of description, the memory cell is not limited thereto and may be a multi-layer cell (MLC) or a quad-layer cell (QLC).

[0030] The input / output circuit 130 may include a page buffer that reads data stored in the memory cell and temporarily stores the read data. The input / output circuit 130 may output the data stored in the page buffer to an external system of the memory device 100, or may store data received from the external system in the page buffer and then store the data in the memory cell.

[0031] The control logic 140 may control the overall operation of the memory device 100. The control logic 140 may control the address decoder 120, the input / output circuit 130, and the voltage generator 150 to perform a read operation, a program operation, and an erase operation on the memory cell array 110. The control logic 140 may determine whether a verification result of the program operation indicates a pass.

[0032] The memory device 100 may receive a command and an address from the memory controller 200 and may access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by the command on the region selected by the address.

[0033] The memory controller 200 may control the overall operation of the memory system 50. The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request received from a host.

[0034] In an embodiment of the present disclosure, the memory device 100 may perform a first programming operation including programming multi-bit data into each memory cell. The memory device 100 may store original code values ​​indicating that the multi-bit data is programmed into the corresponding memory cell in a plurality of latches.

[0035] The memory controller 200 may detect a sudden power outage (SPO) occurring in the memory device 100. SPO is a power condition including an unexpected power loss, which typically occurs without warning, due to, for example, a power failure of a host of the memory system, a power outage or brownout condition of a host of the memory system, an accidental or unintentional power outage of the memory system, etc. The memory controller 200 may output a suspend command and a resume command to the memory device 100 in response to detecting the sudden power outage.

[0036] The memory device 100 may restore the code value changed according to a verification pass within the program operation in response to the restore command, and may store the restored original code value in each of the plurality of memory cells.

[0037] In the disclosed embodiment, when the changed code value is not restored, the memory device 100 needs to receive and program the original code value again. In this case, when a sudden power failure occurs, the power required to receive new data may be insufficient. In addition, when programming the unrestored changed code value, an error correction operation cannot be performed based on the changed code value, thereby reducing the reliability of the programming operation to be performed after power recovery.

[0038] Figure 2 is a diagram showing distribution of threshold voltages and code values ​​of a tri-level cell stored in a plurality of latches.

[0039] Reference Figure 2 , can depict the programming state of a memory cell and a code value indicating the multi-bit data programmed into the memory cell. Figure 2 In the example of , each memory cell is a triple-level cell (TLC) in which 3 bits of data are programmed into one memory cell. Figure 2 In FIG. 1 , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of the memory cells.

[0040] The memory cells may have a threshold voltage distribution corresponding to an erased state before a program operation is performed.

[0041] Each code value indicating multi-bit data can be stored in the first latch, the second latch and the third latch respectively. The first latch can store data corresponding to the least significant bit (LSB). The second latch can store data corresponding to the middle significant bit (CSB). The third latch can store data corresponding to the most significant bit (MSB).

[0042] like Figure 2 As shown, the code values ​​stored in the first latch, the second latch, and the third latch are not limited thereto and may vary. Figure 2 , examples of read voltages R1, R2, R3, R4, R5, R6, and R7 and code values ​​are depicted, which correspond to programming states PV1, PV2, PV3, PV4, PV5, PV6, and PV7 of the memory cells shown, respectively. For example, the seventh programming state PV7 may correspond to the seventh read voltage R7, and the code value corresponding to the seventh read voltage R7 may be 101. "1" may be stored in the first latch, "0" may be stored in the second latch, and "1" may be stored in the third latch.

[0043] Figure 3 is a diagram illustrating a code value that changes in response to a verification pass within a program operation on a triple-level cell.

[0044] Reference Figure 3 , when the threshold voltage distribution 310 of the programmed memory cell changes to the seventh programming state 320, the code values ​​stored in the first latch, the second latch, and the third latch may change from 101 to 111. When the threshold voltage of the memory cell is equal to or higher than the seventh read voltage R7, verification of the program operation performed on the memory cell may pass.

[0045] The memory device 100 may change the code values ​​stored in the first latch, the second latch, and the third latch to an erase code value 111 corresponding to an erase state. Changing the code values ​​stored in the first latch, the second latch, and the third latch to the erase code value 111 may indicate that the programming operation has been completed. The memory device 100 does not need to store information about whether the programming operation has passed in a separate latch by changing the code values ​​stored in the first latch, the second latch, and the third latch, thereby saving at least one latch. In an embodiment of the present disclosure, the memory device 100 may indicate whether the programming operation of the memory cell has been completed or whether the verification within the programming operation has passed by changing the code values ​​stored in the first latch, the second latch, and the third latch.

[0046] Figure 4 is a diagram illustrating an operation of restoring and programming a code value changed in response to the occurrence of a sudden power off according to an embodiment of the present disclosure.

[0047] Reference Figure 4 , the memory controller 200 can detect a sudden power failure occurring in the memory system, and the memory device can restore the code value changed due to the programming operation, divide the code value into 1-bit units, and program the 1-bit units to multiple memory cells respectively. Figure 4 Can be Figure 2 programming state operation.

[0048] The memory device 100 may be configured to perform a first programming operation 410 including one or more of the following. Multi-bit data may be programmed into each memory cell. The memory device 100 may store original code values ​​indicating that the multi-bit data is programmed into the corresponding memory cell in a plurality of latches. The memory device 100 may change the original code values ​​stored in the plurality of latches to erase code values ​​420 in response to a verification pass within the first programming operation. The erase code value may optionally be a preset value or a predetermined value.

[0049] The memory controller 200 may generate a suspend command for suspending the first program operation and a resume command for recovering the code value changed to the erased code value among the code values ​​stored in the plurality of latches in response to detecting the occurrence of the sudden power failure 430. In other words, the detection of the SPO triggers the generation of the suspend command and the resume command. The memory controller 200 may output the suspend command and the resume command 440 to the memory device 100.

[0050] The memory device 100 may perform a recovery operation 450 including restoring the code value changed based on the threshold voltage of the corresponding memory cell to the original code value in response to the recovery command. The memory device 100 may perform the recovery operation based on the result 460 of comparing the read voltage corresponding to the programming state of the memory cell with the threshold voltage of the corresponding memory cell. In response to the threshold voltage of the memory cell being equal to or higher than the first target read voltage and lower than the second target read voltage higher than the first target read voltage, the memory device 100 may restore the changed code value to the code value corresponding to the first target read voltage.

[0051] The memory device 100 may sequentially compare the read voltage with the threshold voltage of the memory cell starting from the highest read voltage. The memory device 100 may perform a recovery operation until the changed code value is recovered or the programming state of the memory cell is detected as an erased state. Because the memory cell performing the first programming operation in this example is a three-layer cell (TLC), the memory device 100 may compare the seventh read voltage R7 having the highest level among the read voltages R1, R2, R3, R4, R5, R6, and R7 with the threshold voltage of the target memory cell performing the recovery operation. The memory device 100 may sequentially compare the read voltage with the threshold voltage of the target memory cell in accordance with the level (amplitude) order of the read voltage until it is detected that the read voltage is lower than or equal to the threshold voltage of the target memory cell among the read voltages R1, R2, R3, R4, R5, R6, and R7.

[0052] In the disclosed embodiment, the plurality of latches storing the code value indicating the multi-bit data may include a sense latch storing information indicating whether the original code value is changed and a code latch storing the original code value or the erase code value. The number of code latches may be determined based on the number of bits in the multi-bit data. Since the memory cell performing the first programming operation in this example is a triple-layer cell (TLC), the number of code latches is 3.

[0053] When the code value stored in the code latch is the same as the erase code value, the memory device 100 may store a first value in the sense latch. In an embodiment of the present disclosure, the first value may be 1. The memory device 100 may perform a recovery operation on the changed code value in response to the first value stored in the sense latch. In an embodiment of the present disclosure, when the code value stored in the code latch is different from the erase code value, the memory device 100 may store a second value in the sense latch and maintain the code value stored in the code latch.

[0054] When the highest read voltage among the read voltages R1, R2, R3, R4, R5, R6, and R7 is higher than the threshold voltage of the target memory cell, the memory device 100 may maintain the code value stored in the code latch and store the second value in the sense latch. In the embodiment of the present disclosure, the second value may be 0. When the value stored in the sense latch is the second value and the code value stored in the code latch is the erase code value, the memory device 100 may compare the second highest read voltage among the read voltages R1, R2, R3, R4, R5, R6, and R7 with the threshold voltage of the target memory cell. The memory device 100 may maintain the code value stored in the code latch and compare the read voltage with the threshold voltage of the target memory cell until the threshold voltage of the target memory cell is compared with a read voltage lower than or equal to the threshold voltage of the target memory cell. The memory device 100 may restore the changed code value to a code value corresponding to a read voltage lower than or equal to the threshold voltage of the target memory cell.

[0055] The memory device 100 may perform a second programming operation 470, which includes dividing the restored original code value 480 into 1-bit units and programming the 1-bit units into a plurality of memory cells. Because the original code value is a 3-bit value, the memory device 100 may divide the 3-bit original code value into three 1-bit data. The memory device 100 may program each 1-bit data into one single-level cell (SLC). The restored original code value may be programmed into three single-level cells (SLCs).

[0056] After the second program operation 470, the memory device 100 may perform a third program operation 490 of dividing the suspension information 495 related to the suspension of the first program operation into 1-bit units and programming the 1-bit units into a plurality of memory cells in response to the suspension command. The suspension information may include information required to resume the first program operation suspended due to sudden power failure after power restoration.

[0057] After programming the restored original code value and the suspend information to the plurality of memory cells, the power of the memory system can be turned off. Even if the occurrence of a sudden power failure is detected, the memory device 100 can restore the changed code value, program the restored code value, and program the suspend information before the power is turned off. The auxiliary power supply may include a large-capacity capacitor that can provide enough power to maintain the operation after the sudden power failure is detected, and the power supports, for example, a suspend operation, which includes at least restoring the changed code value, programming the restored code value, and programming the suspend information before the power is turned off. The memory device 100 can perform a programming operation on a single-layer cell (SLC) to increase the programming speed and reduce the power consumed by the programming operation.

[0058] Figure 5 is a diagram illustrating a target code value restored based on a threshold voltage of a memory cell according to an embodiment of the present disclosure.

[0059] Reference Figure 5 , depicts an example of a threshold voltage 510 of a target memory cell whose code value is restored. The threshold voltage 510 of the target memory cell may be determined by the programming state of the target memory cell. Figure 5 , the program state of the target memory cell may be a fourth program state PV4.

[0060] exist Figure 5 In this example, it is assumed that the threshold voltage 510 of the target memory cell is equal to or higher than the fourth read voltage R4 and lower than the fifth read voltage R5. Figure 5 The threshold voltage 510 of the target memory cell shown is merely an example provided for convenience of description and may be applicable to different threshold voltages. Figure 5 The example can be applied to Figure 2 and Figure 3 .

[0061] Assuming that the programming operation to the target memory cell has been completed, the original code value indicating the multi-bit data programmed to the target memory cell may be changed.The original code value may be stored in a code latch among the plurality of latches.

[0062] The target programming state of the target memory cell may be a fourth programming state. The original code value may be 010. The memory device 100 may change the original code value to an erase code value 111 based on a verification pass within a programming operation on the target memory cell. The memory device 100 may restore the changed code value 111 to the original code value 010 in response to a restore command.

[0063] The memory device 100 may determine whether the code value stored in the code latch is the erase code value 111. The fact that the code value stored in the code latch is not the erase code value 111 may indicate that the programming operation on the memory cell has not been completed. When the code value stored in the code latch is not the erase code value 111, the memory device 100 may keep the code value stored in the code latch unchanged.

[0064] When the code value stored in the code latch is the erase code value 111, the memory device 100 may compare the threshold voltage 510 of the target memory cell with the seventh read voltage R7 having the highest level among the read voltages R1, R2, R3, R4, R5, R6, and R7. Since the seventh read voltage R7 is higher than the threshold voltage 510 of the target memory cell, the memory device 100 may compare the threshold voltage 510 of the target memory cell with the sixth read voltage R6. The operation of comparing the threshold voltage 510 of the target memory cell with each of the read voltages R1, R2, R3, R4, R5, R6, and R7 may be performed until the fourth read voltage R4, which is lower than the threshold voltage 510 of the target memory cell, is compared with the threshold voltage 510 of the target memory cell.

[0065] Since the threshold voltage 510 of the target memory cell is between the fourth read voltage R4 and the fifth read voltage R5, according to Figure 2 For example, the memory device 100 may determine the original code value of the target memory cell to be 010. The memory device 100 may change the code value of the target memory cell stored in the code latch from 111 to 010.

[0066] exist Figure 5 In the embodiment, when the threshold voltage 510 of the target memory cell changes, the determined original code value may change. For example, when the threshold voltage of the target memory cell is higher than the seventh read voltage, the operation of comparing the threshold voltage with the read voltage may be performed only once, and the original code value may be determined according to the threshold voltage 510 of the target memory cell. Figure 2 The original code value may be determined to be 101. When the program state of the target memory cell is the erase state ERASE, the operation of comparing the threshold voltage with the read voltage is performed seven times, and the original code value may be determined to be 111.

[0067] Figure 6 is a table showing code values ​​stored in a plurality of latches according to an embodiment of the present disclosure.

[0068] exist Figure 6 The example of FIG. 1 depicts values ​​stored in a plurality of latches according to a result of comparing a threshold voltage of a target memory cell with read voltages R1, R2, R3, R4, R5, R6, and R7. The plurality of latches may include a sense latch and three code latches. The three code latches may be a first latch, a second latch, and a third latch, respectively. In this example, assuming Figure 6 The threshold voltage of the target memory cell in Figure 5The threshold voltages of the target memory cells in are the same, and the code values ​​stored in the code latches have been changed to the erase code value 111 according to a verification pass within a program operation on the target memory cells.

[0069] When the memory device 100 receives a recovery command in response to the occurrence of a sudden power failure, "1" may be stored in each of the first latch, the second latch, and the third latch. When the erase code value 111 is stored in the code latch, the memory device 100 may check the code value stored in the code latch of the target memory cell, and may store the first value in the sense latch. In the embodiment of the present disclosure, the first value is 1.

[0070] The memory device 100 may compare the threshold voltage of the target memory cell with the seventh read voltage R7. Since the seventh read voltage R7 is higher than the threshold voltage of the target memory cell, the code value stored in the code latch may be maintained and the value stored in the sense latch may be changed to a second value. In the embodiment of the present disclosure, the second value may be 0. The memory device 100 may sequentially perform operations including comparing a read voltage lower than the seventh read voltage with the threshold voltage of the target memory cell until the program state of the target memory cell is detected as an erase state or the original code value is determined.

[0071] When the code value stored in the code latch is the erase code value 111, the memory device 100 may perform an operation including changing the value stored in the sense latch to the first value and comparing the threshold voltage of the target memory cell with the sixth read voltage R6. Because the threshold voltage of the target memory cell is lower than the sixth read voltage R6, the memory device 100 may maintain the code value stored in the code latch and may change the value stored in the sense latch to the second value.

[0072] The operation including comparing the threshold voltage of the target memory cell with the corresponding read voltages R1, R2, R3, R4, R5, R6 and R7 may be continuously performed until the fourth read voltage R4 is compared with the threshold voltage of the target memory cell. Before the operation of comparing the threshold voltage of the target memory cell with the fifth read voltage R5 is performed, only the value stored in the sense latch may be changed, and the code value stored in the code latch may be maintained.

[0073] When the threshold voltage of the target memory cell is equal to or higher than the fourth read voltage R4, the memory device 100 may maintain the first value stored in the sense latch and may determine the code value 010 corresponding to the fourth read voltage R4 as the original code value. The memory device 100 may change the values ​​stored in the first latch and the third latch to 0 and may maintain the value stored in the second latch to 1.

[0074] Since the code value stored in the code latch is not the erase code value 111, an operation including comparing the threshold voltage of the target memory cell with the third read voltage R3 may not be performed. The memory device 100 may restore the code value changed due to a verification pass within a program operation to the original code value.

[0075] Figure 7 is a table showing the time during which code values ​​stored in a plurality of latches are maintained according to an embodiment of the present disclosure.

[0076] Figure 7 Depicted is a case where a recovery operation is not performed based on the code value stored in the code latch. When the code value stored in the code latch is not an erase code value, a value of 111 may be assumed. When a "1" is stored in the first latch and a "0" is stored in the second latch, a third latch may be assumed.

[0077] The memory device 100 can determine the value to be stored in the sense latch by checking the code value stored in the code latch. Because the code value stored in the code latch is not the erase code value 111, the memory device 100 can store 0 in the sense latch and can maintain the code value stored in the code latch.

[0078] When the code value stored in the code latch is not the erase code value 111, the programming operation on the target memory cell may not be completed. Because the programming operation is not completed, the memory device 100 may not change the original code value. Because the original code value has not changed, the memory device 100 may skip the recovery operation. The operation of comparing the threshold voltage of the target memory cell with the read voltages R1, R2, R3, R4, R5, R6, and R7 may not be performed.

[0079] Figure 8 is a diagram illustrating an operation including resuming a suspended program operation after power restoration according to an embodiment of the present disclosure.

[0080] Reference Figure 8 , after the power of the memory system is restored, the first program operation suspended due to the occurrence of the sudden power failure can be resumed.

[0081] The memory controller 200 may output a first read command for reading the original code values ​​programmed to the plurality of memory cells and a resume command 810 for resuming the first program operation suspended by the suspend command to the memory device 100 in response to power restoration. The memory controller 200 may output a read command for reading suspend information and address information indicating a location to program the suspend information into the memory device 100 in response to power restoration.

[0082] The memory device 100 may read 820 the restored original code values ​​830 from the plurality of memory cells in response to the first read command. The restored original code values ​​are programmed into a single level cell (SLC).

[0083] The memory device 100 may receive the address information and the second read command. The memory device 100 may read 840 the pause information 850 programmed into the location indicated by the address information in response to the second read command.

[0084] The memory device 100 may perform an error correction operation on the read original code value and the pause information 860. The error correction operation performed by the memory device 100 may correspond to the previously disclosed technology.

[0085] The memory device 100 resumes 870 the suspended first program operation based on the original code value and the suspension information 880 in response to the resume command. The memory device 100 may perform the suspended first program operation by continuing the first program operation from its previous operating point.

[0086] Fig. 9 is a flowchart illustrating an example of a method of programming data in a program operation suspended in response to a sudden power failure according to an embodiment of the present disclosure.

[0087] Reference Fig. 9 , the memory system 50 can perform operations including detecting the occurrence of sudden power failure, suspending the programming operation, and resuming the suspended programming operation after power is restored. The memory system can program a plurality of memory cells to restore the code values ​​changed by performing the programming operation before the power is disconnected due to the sudden power failure.

[0088] The memory controller 200 detects S910 a sudden power failure occurring in the memory system 50. The memory controller 200 may use a separate device or may independently monitor the sudden power failure. When a sudden power failure is detected, for example, in order to protect data and storage information, the memory system does not immediately shut down the power of the memory system 50.

[0089] The memory controller 200 generates S920 a suspend command for suspending a first programming operation of programming multi-bit data to each memory cell in response to the occurrence of a sudden power failure. The memory controller 200 generates S920 a resume command in response to a verification pass within the first programming operation, the resume command for restoring the original code value indicating the multi-bit data changed to the erase code value. The memory controller 200 outputs the suspend command and the resume command to the memory device 100.

[0090] The memory device 100 performs S930 a recovery operation in response to the recovery command, the recovery operation including restoring the changed code value to the original code value based on the result of comparing the read voltage corresponding to the program state of the corresponding memory cell with the threshold voltage of the memory cell, respectively.

[0091] The memory device 100 performs S940 an optional second program operation including dividing the restored original code value into 1-bit units and programming the 1-bit units into the plurality of memory cells 110 .

[0092] The memory device 100 performs S950 an optional third program operation in response to the suspend command, the third program operation including dividing the suspend information related to the suspend of the first program operation into 1-bit units and programming the 1-bit units into the plurality of memory cells 110 .

[0093] After S950, the memory device 100 may resume the suspended first program operation after power is restored ( Fig. 9 100. After a sudden power failure, the memory device 100 reads the original code values ​​programmed to the plurality of memory cells 110 according to power recovery. The memory device 100 receives address information indicating the location where the pause information is stored. After reading the original code values, the memory device 100 optionally reads the pause information.

[0094] The memory device 100 may resume the first program operation suspended in response to the suspend command. The memory device 100 may resume the suspended first program operation based on the suspend information and the address information.

[0095] Fig. 9 The example can be applied to Figure 4 , Figure 5 , Figure 6 and Figure 7 .

[0096] Fig.10 is a flowchart illustrating an example of a method of restoring a changed code value according to an embodiment of the present disclosure.

[0097] Reference Fig.10, the memory device 100 performs a recovery operation in response to the recovery command, the recovery operation including restoring the changed code value to the original code value based on the result of comparing the read voltage corresponding to the program state of the corresponding memory cell with the threshold voltage of the memory cell, respectively. The plurality of latches storing each code value may include a sense latch storing information indicating whether the original code value has been changed and a code latch storing the original code value or the erase code value.

[0098] The memory device 100 determines S1010 whether the code value is a target of a recovery operation based on the code value stored in the code latch. When the code value stored in the code latch is the same as the erase code value, the memory device 100 stores a first value in the sense latch. When the code value stored in the code latch is different from the erase code value, the memory device 100 stores a second value in the sense latch and maintains the code value stored in the code latch.

[0099] The memory device 100 compares the threshold voltage of the target memory cell in which the code value stored in the code latch is the same as the erase code value with each read voltage S1020. When the threshold voltage of the target memory cell is lower than the read voltage to be compared, the memory device 100 maintains the code value stored in the code latch. The memory device 100 may sequentially compare the read voltage with the threshold voltage of the target memory cell in the order of voltage levels until a read voltage lower than or equal to the threshold voltage of the target memory cell is detected.

[0100] When the threshold voltage of the target memory cell is equal to or higher than the first target read voltage and lower than a second target read voltage higher than the first target read voltage, the memory device 100 determines S1030 the target code value as a code value corresponding to the first target read voltage.

[0101] The memory device 100 restores S1040 the changed code value to a target code value determined based on the comparison result.

[0102] Fig.10 The flowchart can be applied to Figure 4 , Figure 5 , Figure 6 and Figure 7 .

[0103] Fig.11 is a diagram illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure.

[0104] exist Fig.11 In the example of FIG. 2 , the data processing system 2000 may include a host device 2100 and a solid state drive (SSD) 2200. Figures 1 to 10 The described method can be applied to SSDs.

[0105] The SSD 2200 may include a controller 2210 , a buffer memory device 2220 , nonvolatile memories 2231 to 223 n , a power supply 2240 , a signal connector 2250 , and a power connector 2260 .

[0106] The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memories 2231 to 223n. The buffer memory device 2220 may temporarily store data read from the nonvolatile memories 2231 to 223n. The data temporarily stored in the buffer memory device 2220 may be transmitted to the host device 2100 or the nonvolatile memories 2231 to 223n under the control of the controller 2210.

[0107] The nonvolatile memories 2231 to 223n may be used as storage media of the SSD 2200. The nonvolatile memories 2231 to 223n may be connected to the controller 2210 through a plurality of channels CH1 to CHn, respectively. One or more nonvolatile memories may be connected to one channel. The nonvolatile memories connected to one channel may be connected to the same signal bus and the same data bus.

[0108] The controller 2210 may control the overall operation of the SSD 2200. In an embodiment of the present disclosure, the controller 2210 may detect a sudden power failure that occurs in the SSD 2200. The controller 2210 may generate a suspend command for suspending the program operation being executed in response to detecting the occurrence of the sudden power failure and a resume command for recovering the code value changed due to the execution of the program operation. The generated suspend command and resume command may be output to the SSD 2200.

[0109] In the embodiment of the present disclosure, each of the non-volatile memories 2231 to 223n may include a plurality of memory cells. The SSD 2200 may program multi-bit data to each memory cell. The SSD 2200 may change the original code value indicating the multi-bit data of the programming to an erase code value in response to a verification pass within the programming operation. The SSD 2200 may suspend the programming operation in response to a suspend command, and may perform a recovery operation including restoring the changed code value to the original code value in response to a resume command. The SSD 2200 may perform a recovery operation based on the result of comparing the read voltage corresponding to the programming state of the corresponding memory cell with the threshold voltage of the memory cell, respectively.

[0110] The power supply 2240 may provide the power PWR received through the power connector 2260 to the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. When a sudden power outage occurs, the auxiliary power supply 2241 may supply power so that the SSD 2200 is normally shut down. The auxiliary power supply 2241 may include a large-capacity capacitor capable of charging the power PWR sufficient to facilitate the suspend and resume operations.

[0111] In an embodiment of the present disclosure, the SSD 2200 may program the restored original code value into each of the plurality of memory cells using power supplied from the power supply 2240 before being shut down due to a sudden power failure.

[0112] The controller 2210 may exchange a signal SGL with the host device 2100 through the signal connector 2250. The signal SGL may include a command, an address, data, etc. According to an interface scheme of the host device 2100 and the SSD 2200, the signal connector 2250 may be implemented as any one of one or more types of connectors.

[0113] According to the present disclosure, a memory system and a method of programming the memory system are provided, which can resume a suspended program operation after power restoration by restoring changed code values ​​stored in a plurality of latches according to verification passed within the program operation to original code values.

[0114] The scope of the present disclosure is defined by the appended claims rather than the detailed description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be construed as falling within the scope of the present disclosure.

Claims

1. A memory system, comprising: a memory device including memory cells storing data and a plurality of latches storing code values ​​indicating the data, the memory device programming the data into each of the memory cells, storing original code values ​​indicating the data in the plurality of latches, and changing the original code values ​​stored in the plurality of latches to erase code values ​​in response to a verification pass; as well as a memory controller that outputs to the memory device at least a suspend command for suspending programming in response to detecting a sudden power failure and a resume command for resuming a code value changed to the erased code value; The memory device restores the changed code value to the original code value based on the threshold voltage of the memory cell in response to the restore command.

2. The memory system according to claim 1, wherein: The memory device restores the changed code value based on a result of respectively comparing a read voltage corresponding to a program state of the memory cell with a threshold voltage of the memory cell.

3. The memory system according to claim 2, wherein: The memory device restores the changed code value to a code value corresponding to a first target read voltage when a threshold voltage of the memory cell is equal to or higher than a first target read voltage and lower than a second target read voltage higher than the first target read voltage.

4. The memory system according to claim 2, wherein: The memory device compares read voltages with threshold voltages of the memory cells sequentially starting from a highest read voltage.

5. The memory system according to claim 4, wherein: The memory device performs a recovery operation until the changed code value is restored or a program state of the memory cell is detected as an erased state.

6. The memory system according to claim 2, wherein: The plurality of latches include a sense latch storing information identifying whether the original code value has been changed, and a code latch storing the original code value or the erase code value, and The number of the code latches is determined based on the number of bits in the multi-bit data.

7. The memory system according to claim 6, wherein: The memory device stores a first value in the sense latch and performs the recovery operation when a code value stored in the code latch is identical to the erase code value.

8. The memory system according to claim 7, wherein: The memory device maintains a code value stored in the code latch and stores a second value in the sense latch when a highest read voltage among the read voltages is higher than a threshold voltage of the memory cell.

9. The memory system according to claim 8, wherein: The memory device compares a second highest read voltage among the read voltages with a threshold voltage of the memory cell while the code value stored in the code latch is maintained.

10. The memory system according to claim 6, wherein: The memory device maintains the code value stored in the code latch and compares the read voltage with a threshold voltage of the memory cell until the read voltage is lower than or equal to the threshold voltage of the memory cell.

11. The memory system according to claim 6, wherein: The memory device restores the changed code value to a code value corresponding to a read voltage lower than or equal to a threshold voltage of the memory cell.

12. The memory system according to claim 6, wherein: The memory device stores a second value in the sense latch and maintains the code value stored in the code latch when the code value stored in the code latch is different from the erase code value.

13. The memory system according to claim 1, wherein: The memory controller outputs, in response to power restoration after sudden power failure, to the memory device a first read command to read original code values ​​programmed into the plurality of memory cells and a resume command to resume at least programming suspended in response to the suspend command; and The memory device reads restored original code values ​​from the plurality of memory cells in response to the first read command, and performs at least the programming based on the original code values ​​in response to the restore command.

14. The memory system according to claim 1, wherein: The memory device divides the restored original code value into 1-bit units and programs the 1-bit units into a plurality of memory cells, and in response to the suspend command, divides the suspension information related to the suspension of the programming into 1-bit units and programs the 1-bit units into the plurality of memory cells.

15. The memory system according to claim 1, wherein: the memory controller outputting a second read command to the memory device in response to power restoration, the second read command being used to read the suspend information and address information indicating a location where the suspend information is stored; and The memory device reads the suspend information in response to the second read command, and resumes the suspended programming based on the suspend information and the address information.

16. A method of operating a memory system, the memory system comprising a memory device and a memory controller, the memory device comprising a memory cell storing data and a plurality of latches storing code values ​​indicating the data, the memory device programming the data into each of the memory cells, storing an original code value indicating the data in the plurality of latches, and in response to verification, the memory controller generating a control command to control the memory device by changing the original code value stored in the plurality of latches to an erase code value, the method comprising: detecting a sudden power failure occurring in the memory system; outputting to the memory device at least a suspend command for suspending programming in response to detecting the sudden power failure and a resume command for resuming a code value changed to the erased code value; and In response to the restore command, a restore operation is performed, the restore operation including restoring the changed code value to the original code value based on a result of comparing a read voltage corresponding to a program state of each memory cell with a threshold voltage of the memory cell, respectively.

17. The method according to claim 16, wherein: The plurality of latches include a sense latch storing information identifying whether the original code value has been changed, and a code latch storing the original code value or the erase code value, and Executing the recovery operation includes: determining, based on a code value stored in the code latch, whether the code value is a target of the restore operation; comparing a threshold voltage of a target memory cell in which a code value stored in the code latch is the same as the erase code value with each of the read voltages; and The changed code value is restored to a target code value determined based on the comparison result.

18. The method according to claim 17, wherein: The comparison includes: When the threshold voltage of the target memory cell is lower than the read voltage to be compared, maintaining the code value stored in the code latch; and Each of the read voltages is sequentially compared with the threshold voltage of the target memory cell in order of voltage levels until it is detected that the read voltage is lower than or equal to the threshold voltage of the target memory cell.

19. The method according to claim 17, wherein: The recovery includes: When a threshold voltage of the memory cell is equal to or higher than a first target read voltage and lower than a second target read voltage higher than the first target read voltage, the target code value is determined as a code value corresponding to the first target read voltage.

20. The method according to claim 17, wherein: The determination includes: storing a first value in the sense latch when the code value stored in the code latch is the same as the erasure code value; or When the code value stored in the code latch is different from the erase code value, a second value is stored in the sense latch and the code value stored in the code latch is maintained.

21. The method of claim 16, further comprising: After the restored original code value is divided into 1-bit units and the 1-bit units are programmed into the plurality of memory cells, suspend information related to the suspension of the programming operation is divided into 1-bit units in response to the suspend command and the 1-bit units are programmed into the plurality of memory cells.

22. The method according to claim 21, further comprising: In response to power restoration after the occurrence of the sudden power outage, reading original code values ​​programmed into the plurality of memory cells; as well as The program operation suspended in response to the suspend command is resumed.

23. The method according to claim 22, wherein: Reading the raw code value includes: receiving address information indicating a location where the pause information is stored; and After reading the original code value, reading the pause information; and Resuming the program operation includes resuming the suspended program operation based on the suspend information and the address information.

24. A memory system comprising: a memory device including a plurality of memory cells storing data and a plurality of latches storing code values ​​indicating the data, the memory device performing a first programming operation, the first programming operation including programming multi-bit data into each of the memory cells, storing original code values ​​indicating the multi-bit data in the plurality of latches, and changing the original code values ​​stored in the plurality of latches to erase code values ​​in response to a verification pass within the first programming operation; as well as a memory controller that outputs to the memory device a suspend command for suspending the first program operation in response to occurrence of a sudden power failure and a restore command for restoring a code value changed to the erased code value among code values ​​stored in the plurality of latches, The memory device performs a recovery operation in response to the recovery command, the recovery operation including restoring the changed code value to the original code value based on the threshold voltage of the memory cell, dividing the restored original code value into 1-bit units, and programming the 1-bit units into the multiple memory cells.

25. A method of operating a memory system, the memory system comprising a memory device and a memory controller, the memory device comprising a plurality of memory cells storing data and a plurality of latches storing code values ​​indicating the data, the memory device performing a first programming operation, the first programming operation comprising programming multi-bit data into each of the memory cells, storing an original code value indicating the multi-bit data in the plurality of latches, and changing the original code value stored in the plurality of latches to an erase code value in response to a verification passing in the first programming operation, the memory controller generating a control command to control the memory device, the method comprising: detecting a sudden power failure occurring in the memory system; outputting to the memory device a suspend command for suspending the first program operation in response to detecting the sudden power off and a resume command for restoring a code value changed to the erased code value among code values ​​stored in the plurality of latches; In response to the restore command, performing a restore operation, the restore operation including restoring the changed code value to the original code value based on a result of comparing a read voltage corresponding to a program state of each memory cell with a threshold voltage of the memory cell, respectively; as well as A second program operation is performed, the second program operation including dividing the restored original code value into 1-bit units and programming the 1-bit units into the plurality of memory cells.

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