Memory fault detection method and device based on target fault type

Abstract

The invention provides a memory fault detection method and device based on a target fault type, and the method comprises the steps: determining a to-be-detected fault type of a memory, and constructing a fault detection sequence library of the memory; for any target fault type in the to-be-detected fault types, determining a corresponding target detection sequence from a fault detection sequence library; performing sequence recombination based on write operation types on each target detection sequence to obtain an integral write operation detection sequence, inserting read operation sequence elements to obtain a to-be-optimized fault detection sequence, and finally performing screening processing based on the read operation sequence elements to obtain a final fault detection sequence. The fault detection module is used for detecting any target fault type in to-be-detected fault types. Through the memory fault detection method and device, the defect that the test coverage rate for specific fault types cannot reach 100% due to the fact that a memory fault detection method in the prior art has numerous memory fault types and all the fault types of the memory are difficult to detect is overcome.

Description

Technical Field

[0001] The present invention relates to the field of memory testing technology, and in particular to a memory fault detection method and device based on a target fault type. Background Art

[0002] In today's information age, the transmission and storage of digital information require the use of memory as a carrier, and the irreplaceable advantages and functions of memory are becoming more and more prominent. With the development trend of high integration, the capacity of memory chips has increased, the number of interfaces has increased, and the transmission speed has increased. The accuracy, stability and long-term availability of memory chips are the primary considerations, because failures bring huge economic losses, which sometimes cannot even be measured by economic costs. This requires efficient and accurate testing of memory chips, as well as the updating and iteration of test methods, and requires test algorithms to increase fault coverage as much as possible.

[0003] Some memory test algorithms are proposed in the prior art, such as the all-0 all-1 method, the chessboard method, the March algorithm, the diagonal method, etc. These methods occupy an important position in the memory test algorithm. Although they can achieve very high fault coverage and linear test complexity in the memory fault detection process, due to the large number of memory fault types, these methods are difficult to detect all fault types of the memory, and the test coverage for a specific fault type cannot reach 100%. Summary of the invention

[0004] The present invention provides a memory fault detection method and device based on target fault types, so as to overcome the defect that the memory fault detection method in the prior art is difficult to detect all fault types of the memory due to the large number of memory fault types, and thus the test coverage for specific fault types cannot reach 100%.

[0005] The present invention provides a memory fault detection method based on a target fault type, the method specifically comprising the following steps: Determine the type of fault to be detected existing in the memory, and build a fault detection sequence library of the memory according to the type of fault to be detected; For any target fault type among the fault types to be detected, determining a target detection sequence of the target fault type from the fault detection sequence library; Performing sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; The fault detection sequence to be optimized is screened based on the read operation sequence elements to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0006] In some embodiments, the fault types to be detected include single fault types and coupled fault types. The single fault type is a fault type caused by a fault in a single storage unit in the memory. The coupled fault type is a fault type caused by an attacking storage unit in the memory attacking a victim storage unit. The single fault type includes a fixed fault, a state fault, a conversion fault, a write-destruction fault, a read-destruction fault, a pseudo-read-destruction fault, and an erroneous read-destruction fault. The coupled fault types include a state coupling fault, an interference coupling fault, a conversion coupling fault, a write-destruction coupling fault, a read-destruction coupling fault, a pseudo-read-destruction coupling fault, and an erroneous read coupling fault.

[0007] In some embodiments, the step of constructing a fault detection sequence library of the memory according to the fault type to be detected includes: Determine a single fault primitive for each single fault in the single fault type, and construct a single fault detection sequence according to the single fault primitive; Determine a coupling fault primitive for each coupling fault in the coupling fault type, and construct a coupling fault detection sequence according to the coupling fault primitive; The single fault detection sequence and the coupled fault detection sequence are combined to obtain a fault detection sequence library of the memory.

[0008] In some embodiments, each sequence element in the target detection sequence includes a detection direction and an operation type, the detection direction includes from bottom to top or from top to bottom, the operation type includes a read operation type or a write operation type, and the sequence reorganization based on the write operation type of each target detection sequence to obtain the overall write operation detection sequence of the fault type to be detected includes: Based on the first sequence element in the target detection sequence whose detection direction is from bottom to top and whose operation type is a write operation type, construct a first write operation detection sequence; Based on a second sequence element in the target detection sequence whose detection direction is from top to bottom and whose operation type is a write operation type, construct a second write operation detection sequence; The second write operation detection sequence is spliced ​​to the first write operation detection sequence to obtain an overall write operation detection sequence of the fault type to be detected.

[0009] In some embodiments, the constructing a first write operation detection sequence based on a first sequence element in the target detection sequence whose detection direction is from bottom to top and whose operation type is a write operation type includes: For each of the target detection sequences, determining a first sequence element whose detection direction is from bottom to top and whose operation type is a write operation type; Determine the state values ​​of the first sequence elements, and combine the state values ​​to obtain a state value sequence of the target detection sequence; The state value sequences of each target detection sequence are sequentially merged to obtain a first write operation detection sequence.

[0010] In some embodiments, the overall write operation detection sequence includes multiple detection sequence elements, the detection sequence elements include multiple operation sequence elements, the operation sequence elements have state values, and inserting the read operation sequence elements into the overall write operation detection sequence to obtain the fault detection sequence to be optimized includes: For each detection sequence element in the overall write operation detection sequence, determine the number of write operation sequence elements in the detection sequence element, wherein the write operation sequence element is an operation sequence element whose operation type is a write operation type; When the number of elements is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain a fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element, and the read operation sequence element is an operation sequence element whose operation type is a read operation type; When the number of elements is 2, a read operation sequence element is inserted into the overall write operation detection sequence according to the state values ​​of two write operation sequence elements to obtain a fault detection sequence to be optimized.

[0011] In some embodiments, according to the status values ​​of the two write operation sequence elements, inserting the read operation sequence element into the overall write operation detection sequence to obtain the fault detection sequence to be optimized includes: When the state values ​​of two write operation sequence elements are the same, two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at a later position in the detection sequence element to obtain a fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element; When the status values ​​of two write operation sequence elements are different, insert a read operation sequence element after one of the write operation sequence elements that is located at the front in the detection sequence element, wherein the status value of the read operation sequence element is the same as the status value of the write operation sequence element; After one of the write operation sequence elements at a later position in the detection sequence elements, two consecutive read operation sequence elements are inserted, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element.

[0012] In some embodiments, the screening process based on the read operation sequence elements of the fault detection sequence to be optimized to obtain a final fault detection sequence includes: According to a preset fault detection rule, the read operation sequence elements having no fault detection function are filtered out from the fault detection sequence to be optimized to obtain a filtered detection sequence; According to the position of the read operation sequence element in each target detection sequence, the element position of the read operation sequence element in the screening detection sequence is adjusted to obtain a final fault detection sequence.

[0013] The present invention also provides a memory fault detection device based on a target fault type, the device specifically comprising the following modules: A construction module, used to determine the type of fault to be detected existing in the memory, and to construct a fault detection sequence library of the memory according to the type of fault to be detected; A determination module, configured to determine, for any target fault type among the fault types to be detected, a target detection sequence of the target fault type from the fault detection sequence library; A reorganization module, configured to perform sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and insert a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; The screening module is used to perform screening processing on the fault detection sequence to be optimized based on the read operation sequence elements to obtain a final fault detection sequence, wherein the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the memory fault detection method based on the target fault type as described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for detecting a memory fault based on a target fault type as described above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned methods for detecting memory faults based on target fault types.

[0017] The memory fault detection method based on target fault type provided by the present invention constructs a fault detection sequence library through the fault types to be detected existing in the memory. In the fault detection sequence library, for the target detection sequence of any target fault type, a sequence reorganization based on the write operation type is performed to obtain an overall write operation detection sequence, and a read operation sequence element is inserted therein to obtain a fault detection sequence to be optimized. Finally, the fault detection sequence to be optimized is screened based on the read operation sequence element to obtain a final fault detection sequence. Thus, under the known fault types to be detected existing in the memory, a final fault detection sequence that can detect any of the target fault types is designed. Therefore, by performing a memory test based on the final fault detection sequence, each target fault type of the memory can be covered, and the coverage rate of the target fault type to be detected can be achieved to 100%. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of a memory fault detection method based on a target fault type provided by the present invention.

[0020] Figure 2 It is a schematic diagram of constructing a single fault detection sequence based on a single fault type provided by the present invention.

[0021] Figure 3 It is a schematic diagram of constructing a coupling fault detection sequence based on the coupling fault types provided by the present invention.

[0022] Figure 4 It is a schematic diagram of constructing a fault detection sequence for interference coupling faults provided by the present invention.

[0023] Figure 5 It is a state transition diagram of the target detection sequence provided by the present invention for reorganization.

[0024] Figure 6 It is a processing flow chart of inserting a read operation sequence element into the overall write operation detection sequence provided by the present invention.

[0025] Figure 7It is a structural schematic diagram of a memory fault detection device based on a target fault type provided by the present invention.

[0026] Figure 8 It is a schematic diagram of the physical structure of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Combine the following Figure 1 Describe the memory fault detection method based on target fault type of the present invention,

[0029] Figure 1 FIG. 1 is a flow chart of a memory fault detection method based on a target fault type provided by the present invention. Figure 1 As shown, the method includes the following steps.

[0030] In step 101, the type of fault to be detected existing in the memory is determined, and a fault detection sequence library of the memory is constructed according to the type of fault to be detected.

[0031] In an embodiment of the present invention, it is first necessary to determine the types of faults to be detected that exist in the memory during operation. In order to achieve 100% coverage of detected faults, the embodiment of the present invention will predetermine all common specific fault types that may occur in the memory and make statistics. After statistically analyzing the fault types, it is determined that the fault types to be detected include two categories: single fault types and coupled fault types. Among them, the single fault type is the fault type caused by the failure of a single storage unit in the memory, and the coupled fault type is the fault type caused by the attacking storage unit in the memory attacking the victim storage unit. Since different fault types require different detection sequences for detection and verification, after counting and determining all common fault types to be detected in the memory, a fault detection sequence library of the memory is constructed according to the fault types to be detected.

[0032] The fault detection sequence library needs to record the fault detection sequence of each fault type. Therefore, the corresponding fault primitive must be determined for each fault type, and then the corresponding fault detection sequence is constructed based on the fault primitive. The fault types to be detected in the memory are divided into two categories: single fault type and coupled fault type, so the fault detection sequence library is constructed for these two types of fault types.

[0033] It should be noted that the fault detection sequence in the embodiment of the present invention is constructed according to the standard of the March algorithm. The processing process of the March algorithm is to detect whether the storage unit has a fault by reading and writing 0 and reading and writing 1 for each storage unit in the memory. For the convenience of description, the change of the state value of the two storage units (represented by two digits, such as 00), each read and write operation (called operation type, read or write) and operation data (operation value, 0 or 1) are all recorded as a March element in the March algorithm. The operation direction during the memory test is also recorded in the March element, that is, the search forward direction of the March algorithm on the storage unit. In the search forward direction, the state values ​​of the two storage units will be changed by executing the operation type and operation value. In the test operation according to the March element, the detection direction from bottom to top is defined as the "↑" direction, and the detection direction change from top to bottom is defined as the "↓" direction. When the detection direction is available or not limited, it is called the "↕" direction.

[0034] The write operation type is write, represented by w, and the read operation type is read, represented by r. The operation value is the value input during the test, specifically a pair of opposite values, that is, 0 and 1. Therefore, the fault detection sequence is composed of multiple March elements. A March element represents a test operation, that is, a test operation in the March element is performed on all storage units in the storage. For example, "↑w1" means that 1 is written to two storage units from bottom to top.

[0035] First, the single fault primitive of each single fault in the single fault type is determined, and a single fault detection sequence is constructed based on the single fault primitive. Here, the single fault primitive is a form of representing the memory fault type. The expression of the single fault primitive of a storage unit in the memory can be <s f r>. Among them, S represents the state or operation that triggers the memory fault. The state here is the state value of the memory cell, expressed as 0 or 1. The operation refers to the read and write operations that can be performed on the state value of the memory cell, including reading 0 (r0), reading 1 (r1), writing 0 in 0 (0w0), writing 1 in 0 (0w1), writing 0 in 1 (1w0), and writing 1 in 1 (1w1). Therefore, the single fault type of the memory S∈{0, 1, r0, r1, 0w0, 0w1, 1w0, 1w1}; F represents the state value of the faulty unit, F∈{0, 1}; R represents the logical output level of the read operation. When S is a read operation, R represents the result of the read, which has two states of 0 and 1. When S is not a read operation, R represents "-", and R∈{0, 1, -}.

[0036] In an embodiment of the present invention, single fault types include seven categories: stuck-at fault (SAF), state fault (SF), transition fault (TF), write disturb fault (WDF), read destructive fault (RDF), deceptive read destructive fault (DRDF) and state coupling fault (CFST), which are explained below respectively.

[0037] (1) Stuck-at fault SAF: The faulty unit constantly maintains a storage state (0 or 1) and the state cannot be changed.

[0038] (2) State fault SF is a fault that can be manifested without any read or write operations. When the storage state of the faulty unit is 0 or 1, it will automatically jump to the opposite state 1 or 0.

[0039] (3) When the fault TF is converted and the opposite value is written to the faulty cell, the state value of the faulty cell will not change. That is, when the state value of the faulty cell is 0 or 1, a 1 or 0 operation is performed, but the faulty cell does not change from 0 to 1 or 1 to 0 and remains in its original state.

[0040] (4) Write failure fault WDF: When a write operation is performed on the faulty cell in the same state as the original state, the state of the faulty cell changes. That is, when the state of the faulty cell is 0 or 1, when a write operation of 0 or 1 is performed on the faulty cell again, the state of the faulty cell changes to 1 or 0.

[0041] (5) Read-destruction fault RDF: When a read operation is performed on a faulty cell, the state of the faulty cell will change, and the changed state value will be read out. That is, when the initial state of the storage cell is 0 or 1, a read 0 or 1 operation is performed, and the read state value is 1 or 0.

[0042] (6) Pseudo-read failure DRDF: Reading the faulty cell will cause the state of the faulty cell to change, but the read state value is the state value before the faulty cell changes. That is, the initial state value of the faulty cell is 0 or 1. After the read operation, the state value of the faulty cell changes to 1 or 0, but the read state value is 0 or 1.

[0043] (7) Incorrect read fault CFST: When a read operation is performed on the faulty cell, the state value of the faulty cell does not change, but the read state value is an incorrect state value. That is, the initial state value of the faulty cell is 0 or 1. After the read operation, the state value of the faulty cell is still 0 or 1, but the read state value is 1 or 0.

[0044] See also Figure 2 , Figure 2 Schematic diagram of constructing a single fault detection sequence using a single fault type provided by the present invention, such as Figure 2 As shown in FIG. 1 , for the above seven single fault types, the single fault primitives of each single fault in the single fault type are first determined respectively, and then the corresponding single fault detection sequence is generated based on each single fault primitive using the principle of memory fault. Figure 2 It can be seen that there are multiple single fault primitives corresponding to each single fault type, and there are also multiple single fault detection sequences constructed by each unit single fault primitive. This is to ensure that all fault conditions of single fault types can be involved, making the coverage of the fault detection sequence library more comprehensive.

[0045] For the coupling fault type, similar to the single fault type processing method, first determine the coupling fault primitives of each coupling fault in the coupling fault type, and build a coupling fault detection sequence based on the coupling fault primitives. Here, the coupling fault primitive is also a form of representing the memory fault type. The coupling fault primitive of the memory unit (one attacking memory unit and one victim memory unit) in the memory can be expressed as<Sa,Sv / F / R> , where Sa represents the state or operation of the attacking storage unit fault sensitization, and Sv represents the state or operation of the victim storage unit fault sensitization. Here, the memory coupling fault type Sa, Sv ∈{0, 1, r0, r1, 0w0, 0w1, 1w0, 1w1}; F represents the state of the faulty unit, F ∈{0, 1, ↑, ↓}, where "0, 1" means that the faulty unit with states 0 and 1 remains in the state of 0 and 1 after the operation, ↑ means that the state of the faulty unit changes from 0 to 1, and ↓ means that the state of the faulty unit changes from 1 to 0; if S is a read operation, then R represents the result of the read, which has two states of 0 and 1. If S is not a read operation, then R is represented as "-", and R∈{0, 1, -}.

[0046] In the embodiment of the present invention, coupling fault types include seven categories: state coupling fault (CFst), disturbance coupling fault (CFds), transition coupling fault (CFtr), write destructive coupling fault (CFwd), read destructive coupling fault (CFrd), deceptive read destructive coupling fault (CFdrd) and incorrect read coupling fault (CFir).

[0047] For the above seven coupling fault types, the coupling fault primitives of each coupling fault in the coupling fault type are determined respectively, and based on the coupling fault primitives, the corresponding coupling fault detection sequence is generated using the memory fault principle. There may be multiple coupling fault detection sequences generated, and each coupling fault detection sequence can be used to detect the corresponding coupling fault type. For details, please refer to Figure 3 , Figure 3 The schematic diagram of the coupling fault detection sequence constructed by the coupling fault type provided by the present invention is as follows. Figure 3 Let's explain them separately.

[0048] (1) State coupling fault CFst: the state of the attacking storage unit will cause the state value of the victim storage unit to flip (state value flipping means abnormal change of state value, for example, 0 flips to 1 or 1 flips to 0. The state value flipping involved in the following text is applicable to this explanation and will not be repeated). That is, when the initial state value of the victim storage unit is 0 or 1, due to the influence of the state value of the attacking storage unit, the state value of the victim storage unit flips to 1 or 0. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (a).

[0049] (2) Interference coupling fault CFds, the read or write operation of the attacking storage unit will cause the state value of the victim storage unit to flip. According to the different operation states of the attacking storage unit, the interference coupling fault is further divided into three categories. The fault primitives and fault detection sequences of each type of interference coupling fault can be found in Figure 4 , Figure 4 It is a schematic diagram of the fault primitive and fault detection sequence of the interference coupling fault provided by the present invention.

[0050] The first category is , which means that the read operation of the attacking storage unit will cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, the state value of the victim storage unit flips to 1 or 0 due to the r0 or r1 operation of the attacking storage unit. The fault primitive and fault detection sequence are as follows Figure 4 As shown in (a).

[0051] The second category is , which means that the attack storage unit performs certain xwx operations (writes the same value as the initial state value) to cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, the state value of the victim storage unit flips to 1 or 0 due to the 1w1 or 0w0 operation of the attack storage unit. The fault primitive and fault detection sequence are as follows Figure 4 As shown in (b).

[0052] The third category is , indicating that the attack storage unit performs certain The operation (writing a value different from the initial state value) will cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, the state value of the victim storage unit flips to 1 or 0 due to the 0w1 or 1w0 operation of the attack storage unit. The fault primitive and fault detection sequence are as follows: Figure 4 As shown in (c).

[0053] (3) Conversion coupling fault CFtr: When the victim storage unit performs a write operation, the state change of the victim storage unit will be affected by the state value of the attack storage unit and cannot be flipped. That is, when the initial state value of the victim storage unit is 0 or 1, a write 1 or 0 operation is performed. Due to the influence of the state value of the attack storage unit, the state value of the victim storage unit cannot be flipped to 1 or 0. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (b).

[0054] (4) Write-corruption coupling fault CFwd: When the victim storage unit performs a write operation without changing the state value, it will be affected by the state value of the attacking storage unit, causing the state value of the victim storage unit to flip. That is, the initial state value of the victim storage unit is 0 or 1. When the w0 or w1 operation is performed, the state value of the victim storage unit flips to 1 or 0 because the state value of the attacking storage unit is 0 or 1. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (c).

[0055] (5) Read-destruction coupling fault CFrd: When the attacking storage unit is in a certain state, the read operation on the victim storage unit will cause the state value of the victim storage unit to flip, and the read state value is also the flipped value. That is, the initial state value of the victim storage unit is 0 or 1. When the r0 or r1 operation is performed, since the state value of the attacking storage unit is 0 or 1, the state value of the victim storage unit flips to 1 or 0, making the state value read from the victim storage unit 1 or 0. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (d).

[0056] (6) Pseudo-read destructive coupling fault CFdrd: When the state value of the attacking storage unit is a specific state, the read operation on the victim storage unit will cause the state value of the victim storage unit to flip, and the read state value is the state value before the flip. That is, the initial state value of the victim storage unit is 0 or 1. When the r0 or r1 operation is performed, since the state value of the attacking storage unit is 0 or 1, the state value of the victim storage unit flips to 1 or 0, but the read state value is 0 or 1. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (e).

[0057] (7) False read coupling fault CFir: When the state value of the attacking storage unit is a specific state, the read operation on the victim storage unit will not cause the state value of the victim storage unit to flip, but the read state value is the state value after the flip. That is, the initial state value of the victim storage unit is 0 or 1. When the r0 or r1 operation is performed, since the state value of the attacking storage unit is 0 or 1, the state value of the victim storage unit is still 0 or 1, but the read state value is 1 or 0. The fault primitive and the corresponding detection sequence are as follows: Figure 3 As shown in (f).

[0058] After constructing the single fault detection sequence and the coupled fault detection sequence, the single fault detection sequence and the coupled fault detection sequence are merged to obtain the fault detection sequence library of the memory. Therefore, the fault detection sequence library records the detection sequences of all fault types to be detected.

[0059] Continue to see Figure 1 In step 102, for any target fault type among the fault types to be detected, a target detection sequence of the target fault type is determined from a fault detection sequence library.

[0060] When it is necessary to perform fault detection on the memory, for any target fault type among the fault types to be detected, a target detection sequence of the target fault type can be determined from the fault detection sequence library. Since the fault detection sequence library records the detection sequences of all common fault types, the coverage of the fault types can reach 100%.

[0061] In step 103, each target detection sequence is reorganized based on the write operation type to obtain an overall write operation detection sequence of the fault type to be detected, and a read operation sequence element is inserted into the overall write operation detection sequence to obtain a fault detection sequence to be optimized.

[0062] Therefore, in order to detect all the fault types to be detected in the memory, the embodiment of the present invention reorganizes all the target detection sequences in the fault detection sequence library, that is, reorganizes each target detection sequence based on the write operation type to obtain the overall write operation detection sequence of the fault type to be detected. The specific process of reorganizing the target detection sequence is described in detail below.

[0063] Since the target detection sequence is actually the fault detection sequence in the fault detection sequence library, and the fault detection sequence is composed of sequence elements, each sequence element in the target detection sequence includes a detection direction and an operation type. The detection direction includes from bottom to top ("↑") or from top to bottom ("↓"), indicating a change in state value from left to right or from right to left. The operation type includes a read operation type (w) or a write operation type (r). Considering the memory unit test process of the memory, the read operation type will not change the state value of the memory unit, and only the write operation type will change the state value of the memory unit, so the write operation type in the target detection sequence is first reorganized.

[0064] In the embodiment of the present invention, the write operation is reorganized through the state transition diagram. However, during the reorganization process, the reorganization is performed according to two detection directions (i.e., from bottom to top "↑" and from top to bottom "↓"), and then the reorganization results of the two detection directions are spliced. When reorganizing, the target detection sequence of each target fault type is first formed into a state transition diagram, see Figure 5 , Figure 5 It is a state transition diagram of the target detection sequence provided by the present invention for reorganization. Figure 5 As shown, each node in the state transition diagram represents a state value, and the edges between nodes represent the corresponding test operations. First, the initial state "00" is still "00" after the ↕w0 / ↑w0 / ↓w0 operation; the state changes to "10" after the ↑w1 operation; and the state changes to "01" after the ↓w1 operation. The state of state "10" changes to "00" after the ↓w0 operation; the state changes to "01" after the ↑w0 operation; and the state changes to "11" after the ↑w1 operation. The state of state "11" is still "11" after the ↕w1 / ↑w1 / ↓w1 operation; the state changes to "01" after the ↑w0 operation; and the state changes to "10" after the ↓w0 operation. The state of state "01" changes to "11" after the ↓w1 operation; the state changes to "00" after the ↑w0 operation; and the state changes to "10" after the ↓w0 operation. Finally, a state transition diagram with the "00" state as the starting point can be obtained.

[0065] For the "↑" direction from bottom to top, based on the first sequence element in the target detection sequence whose detection direction is from bottom to top and whose operation type is a write operation type, a first write operation detection sequence is constructed.

[0066] Here, each target detection sequence is first converted into a state transition diagram, and for each target detection sequence, the first sequence element whose detection direction is from bottom to top and whose operation type is a write operation type is determined from the state transition diagram. That is, for each target fault type target detection sequence, the test operations whose detection direction is from bottom to top "↑" and whose operation type is a write operation type are counted from the state transition diagram (specifically, the edge of the state transition diagram) as the first sequence element.

[0067] Then, the state value of the first sequence element is determined, and the state values ​​are combined to obtain the state value sequence of the target detection sequence. Here, the state value of each first sequence element is first determined, specifically, each first sequence element is converted into a state value, and then all the state values ​​are combined to obtain the state value sequence of the target detection sequence.

[0068] Finally, the state value sequences of each target detection sequence are sequentially merged to obtain the first write operation detection sequence. Here, the state value sequences corresponding to different fault types are merged to obtain the first write operation detection sequence in the "↑" direction from bottom to top.

[0069] For the "↓" direction from top to bottom, similar to the above-mentioned process from bottom to top "↑", the second write operation detection sequence is constructed based on the second sequence element in the target detection sequence whose detection direction is from top to bottom and whose operation type is a write operation type. The process is still to first convert each target detection sequence into a state transition diagram, and for each target detection sequence, determine the second sequence element whose detection direction is from top to bottom and whose operation type is a write operation type from the state transition diagram. Then determine the state value of the second sequence element, and merge the state values ​​to obtain the state value sequence of the target detection sequence. Finally, merge the state value sequence of each target detection sequence to obtain the second write operation detection sequence. Here, the state value sequences corresponding to different fault types are merged to obtain the second write operation detection sequence in the "↑" direction from top to bottom. Since the specific process of constructing the second write operation detection sequence is similar to that of the first write operation detection sequence, it will not be repeated here.

[0070] After determining the second write operation detection sequence and the first write operation detection sequence in the two detection directions, the second write operation detection sequence is spliced ​​after the first write operation detection sequence to obtain an overall write operation detection sequence of the fault type to be detected.

[0071] Next, the read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. However, the read operation sequence elements cannot be inserted arbitrarily, and certain detection rules must be followed. For example, after analyzing each target fault type in the memory fault type to be detected, it is found that there is no need to write or read the opposite state value (1 or 0) after the state value (0 or 1) is written, because this is an invalid operation in the detection process and has no effect on the detection of the fault type.

[0072] To comply with this detection rule, in the embodiment of the present invention, a read operation sequence element is inserted according to the number of write operations in the overall write operation detection sequence. The read operation sequence element is an operation sequence element whose operation type is a read operation type. Figure 6 , Figure 6 This is a processing flow chart of inserting a read operation sequence element into the overall write operation detection sequence provided by the present invention. Figure 6 The steps in are described in detail.

[0073] In step 601, start inserting read operation sequence elements into the overall write operation detection sequence.

[0074] In step 602, the number of elements of the write operation sequence element is determined.

[0075] Here, the overall write operation detection sequence includes multiple detection sequence elements, the detection sequence elements include multiple operation sequence elements, and the operation sequence elements have state values. Therefore, for each detection sequence element in the overall write operation detection sequence, the number of elements of the write operation sequence elements in the detection sequence element is determined, and the write operation sequence element is an operation sequence element whose operation type is a write operation type.

[0076] When it is determined that the number of write operation sequence elements in the detection sequence elements is 1, the process proceeds to step 603 ; when it is determined that the number of write operation sequence elements in the detection sequence elements is 2, the process proceeds to step 604 .

[0077] In step 603, two consecutive read operation sequence elements are inserted after the write operation sequence element.

[0078] Here, when it is determined that the number of write operation sequence elements in the detection sequence element is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain the fault detection sequence to be optimized, and then the process proceeds to step 607. During the insertion process, it is necessary to ensure that the state values ​​of the two consecutive read operation sequence elements inserted are the same as the state value of the write operation sequence element.

[0079] In step 604, it is determined whether the status values ​​of the two write operation sequence elements are the same.

[0080] Here, when it is determined that the number of elements of the write operation sequence elements in the detection sequence element is 2, the read operation sequence element is inserted into the overall write operation detection sequence according to the state values ​​of the two write operation sequence elements to obtain the fault detection sequence to be optimized. Here, when it is determined that the number of elements of the write operation sequence element is 2, it is necessary to judge whether the state values ​​of the two write operation sequence elements are the same, and then according to the state values ​​of the two write operation sequence elements, the read operation sequence element is inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. When the state values ​​of the two write operation sequence elements are the same, the process proceeds to step 605, and when the state values ​​of the two write operation sequence elements are different, the process proceeds to step 606.

[0081] In step 605, two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at a later position in the detection sequence elements.

[0082] Here, when the status values ​​of two write operation sequence elements are the same, two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at a later position in the detection sequence elements to obtain a fault detection sequence to be optimized, and the process proceeds to step 607. In addition, during the insertion process, it is still necessary to ensure that the status values ​​of the two consecutive read operation sequence elements input are the same as the status value of the write operation sequence element.

[0083] In step 606, a read operation sequence element is inserted after one of the write operation sequence elements at a front position in the detection sequence elements, and two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at a back position in the detection sequence elements.

[0084] Here, when the status values ​​of two write operation sequence elements are different, a read operation sequence element is inserted after one of the write operation sequence elements at the front position in the detection sequence elements, and the status value of the inserted read operation sequence element is ensured to be the same as the status value of the write operation sequence element. At the same time, two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at the back position in the detection sequence elements, and the process goes to step 607. During the insertion process, it is still necessary to ensure that the status values ​​of the two consecutive read operation sequence elements inserted are the same as the status value of the write operation sequence element.

[0085] In step 607, a fault detection sequence to be optimized is obtained.

[0086] By executing steps 603, 605, and 606, that is, according to the number of write operation sequence elements in the detection sequence elements and the status values ​​of the write operation sequence elements, the read operation sequence elements are respectively inserted at the corresponding positions, thereby finally obtaining the fault detection sequence to be optimized under the condition of following the detection rules.

[0087] Continue to see Figure 1 In step 104, the fault detection sequence to be optimized is screened based on the read operation sequence elements to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0088] Here, through Figure 6 After obtaining the fault detection sequence to be optimized in step 607, considering that the read operation sequence elements are inserted according to the write operation sequence elements, there may be the following redundant read operation sequence elements that have no fault detection function in the detection sequence. Therefore, the fault detection sequence to be optimized is screened based on the read operation sequence elements to obtain the final fault detection sequence.

[0089] Continue to see Figure 6 , in step 608, read operation sequence elements that have no fault detection function are filtered out.

[0090] Here we can analyze the detection sequence in the previous memory detection algorithm, set a fault detection rule in advance, and determine the read operation sequence elements that have no fault detection function based on all the fault types to be detected. This step is also the process of optimizing the fault detection sequence to be optimized, and also the screening of the read operation sequence elements to obtain the screened detection sequence.

[0091] In step 609, the position of the read operation sequence element is determined.

[0092] Here, the element position of the read operation sequence element in the screening detection sequence is adjusted according to the position of the read operation sequence element in each target detection sequence to obtain the final fault detection sequence. Specifically, the number of elements of the read operation sequence elements in the screening detection sequence is first counted, and then the element position of each read operation sequence element in the screening detection sequence is determined.

[0093] Since the screening detection sequence is still composed of multiple detection sequence elements, the position of the read operation sequence element in each target detection sequence can be used to determine whether the read operation sequence element is the end of the detection sequence element or the beginning of the next detection sequence element, thereby ensuring that 100% fault type detection coverage is achieved. Here, the position of the read operation sequence element in the detection sequence element is calibrated according to the position of the read operation in the fault detection sequence of each fault type (i.e., the above-mentioned 7 single fault types and 7 coupled fault types).

[0094] In step 610, a final fault detection sequence is obtained.

[0095] Through step 609, after adjusting the positions of the read operation sequence elements in the screening detection sequence, the final fault detection sequence can be obtained.

[0096] In the embodiment of the present invention, the final fault detection sequence obtained can be exemplarily represented as the following sequence: "{↑(w0);↑(r0,w0,r0) ;↑(r0,w1,w1,r1),↑(r1,w1),↑(r1,w0,w0,r0);↑(r0);↑(w1,r1);↑(w0 , r0); ↑ (w0, r0, w1); ↑ (w1, r1, w0); ↑ (r0, r0, w1), ↑ (r1, r1, w0); ↓ (r0, w 0, r0); ↓ (r0, w1, w1, r1); ↓ (r1, w1), ↓ (r1, w0, w0, r0), ↓ (r0); ↓ (w1, r1) ;↓(w0, r0); ↓(w0, r0, w1); ↓(w1, r1, w0); ↓(r0, r0, w1); ↓(r1, r1, w0)}".

[0097] The above-mentioned final fault detection sequence can detect any target fault type among the fault types to be detected, that is, only one fault detection sequence can be used to detect the fault types to be detected in the memory during operation (that is, the above-mentioned 7 single fault types and 7 coupled fault types), and can ensure that the fault type detection coverage reaches 100%, as shown in the following Table 1: Table 1

[0098] The memory fault detection device based on target fault type provided by the present invention is described below. The memory fault detection device based on target fault type described below and the memory fault detection method based on target fault type described above can refer to each other.

[0099] Figure 7 is a schematic diagram of the structure of a memory fault detection device based on a target fault type provided by the present invention, such as Figure 7 As shown, the present invention provides a memory fault detection device based on target fault type, and the device specifically includes: a construction module 701, a determination module 702, a reorganization module 703, and a screening module 704. Among them, the construction module 701 is used to determine the fault type to be detected in the memory, and to construct a fault detection sequence library of the memory according to the fault type to be detected; the determination module 702 is used to determine the target detection sequence of the target fault type from the fault detection sequence library for any target fault type among the fault types to be detected; the reorganization module 703 is used to perform sequence reorganization based on the write operation type on each of the target detection sequences to obtain the overall write operation detection sequence of the fault type to be detected, and insert the read operation sequence element into the overall write operation detection sequence to obtain the fault detection sequence to be optimized; the screening module 704 is used to perform screening processing on the fault detection sequence to be optimized based on the read operation sequence element to obtain the final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0100] Figure 8 is a schematic diagram of the physical structure of an electronic device provided by the present invention, such as Figure 8 As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a memory fault detection method based on a target fault type, the method comprising: determining the fault type to be detected existing in the memory, and constructing a fault detection sequence library of the memory according to the fault type to be detected; for any target fault type among the fault types to be detected, determining a target detection sequence of the target fault type from the fault detection sequence library; performing sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; performing screening processing based on the read operation sequence element on the fault detection sequence to be optimized to obtain a final fault detection sequence, the final fault detection sequence being used to detect any target fault type among the fault types to be detected.

[0101] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0102] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the memory fault detection method based on the target fault type provided by the above methods, the method including: determining the fault type to be detected in the memory, and constructing a fault detection sequence library of the memory according to the fault type to be detected; for any target fault type among the fault types to be detected, determining the target detection sequence of the target fault type from the fault detection sequence library; performing sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; performing screening processing on the fault detection sequence to be optimized based on the read operation sequence element to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0103] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the memory fault detection method based on the target fault type provided by the above-mentioned methods, the method comprising: determining the fault type to be detected existing in the memory, and constructing a fault detection sequence library of the memory according to the fault type to be detected; for any target fault type among the fault types to be detected, determining the target detection sequence of the target fault type from the fault detection sequence library; performing sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; performing screening processing on the fault detection sequence to be optimized based on the read operation sequence element to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

[0104] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.< / s>

Claims

1. A memory fault detection method based on target fault type, characterized in that: The method comprises: Determine the type of fault to be detected existing in the memory, and build a fault detection sequence library of the memory according to the type of fault to be detected; For any target fault type among the fault types to be detected, determining a target detection sequence of the target fault type from the fault detection sequence library; Performing sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; The fault detection sequence to be optimized is screened based on the read operation sequence elements to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

2. The memory fault detection method based on target fault type according to claim 1, characterized in that: The fault types to be detected include single fault types and coupled fault types. The single fault type is a fault type caused by a fault in a single storage unit in the memory. The coupled fault type is a fault type caused by an attacking storage unit in the memory attacking a victim storage unit. The single fault type includes a fixed fault, a state fault, a conversion fault, a write-destruction fault, a read-destruction fault, a pseudo-read-destruction fault, and an erroneous read-destruction fault. The coupled fault types include a state coupling fault, an interference coupling fault, a conversion coupling fault, a write-destruction coupling fault, a read-destruction coupling fault, a pseudo-read-destruction coupling fault, and an erroneous read coupling fault.

3. The memory fault detection method based on target fault type according to claim 2, characterized in that: The step of constructing a fault detection sequence library of the memory according to the fault type to be detected includes: Determine a single fault primitive for each single fault in the single fault type, and construct a single fault detection sequence according to the single fault primitive; Determine a coupling fault primitive for each coupling fault in the coupling fault type, and construct a coupling fault detection sequence according to the coupling fault primitive; The single fault detection sequence and the coupled fault detection sequence are combined to obtain a fault detection sequence library of the memory.

4. The memory fault detection method based on target fault type according to claim 1, characterized in that: Each sequence element in the target detection sequence includes a detection direction and an operation type, the detection direction includes from bottom to top or from top to bottom, the operation type includes a read operation type or a write operation type, and the sequence reorganization based on the write operation type of each target detection sequence is performed to obtain the overall write operation detection sequence of the fault type to be detected, including: Based on the first sequence element in the target detection sequence whose detection direction is from bottom to top and whose operation type is a write operation type, construct a first write operation detection sequence; Based on a second sequence element in the target detection sequence whose detection direction is from top to bottom and whose operation type is a write operation type, construct a second write operation detection sequence; The second write operation detection sequence is spliced ​​to the first write operation detection sequence to obtain an overall write operation detection sequence of the fault type to be detected.

5. The memory fault detection method based on target fault type according to claim 4, characterized in that: The constructing a first write operation detection sequence based on a first sequence element in the target detection sequence whose detection direction is from bottom to top and whose operation type is a write operation type includes: For each of the target detection sequences, determining a first sequence element whose detection direction is from bottom to top and whose operation type is a write operation type; Determine the state values ​​of the first sequence elements, and combine the state values ​​to obtain a state value sequence of the target detection sequence; The state value sequences of each target detection sequence are sequentially merged to obtain a first write operation detection sequence.

6. The memory fault detection method based on target fault type according to claim 1, characterized in that: The overall write operation detection sequence includes a plurality of detection sequence elements, the detection sequence elements include a plurality of operation sequence elements, the operation sequence elements have state values, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized includes: For each detection sequence element in the overall write operation detection sequence, determine the number of write operation sequence elements in the detection sequence element, wherein the write operation sequence element is an operation sequence element whose operation type is a write operation type; When the number of elements is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain a fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element, and the read operation sequence element is an operation sequence element whose operation type is a read operation type; When the number of elements is 2, a read operation sequence element is inserted into the overall write operation detection sequence according to the state values ​​of two write operation sequence elements to obtain a fault detection sequence to be optimized.

7. The memory fault detection method based on target fault type according to claim 6, characterized in that: According to the state values ​​of the two write operation sequence elements, a read operation sequence element is inserted into the overall write operation detection sequence to obtain a fault detection sequence to be optimized, including: When the state values ​​of two write operation sequence elements are the same, two consecutive read operation sequence elements are inserted after one of the write operation sequence elements at a later position in the detection sequence element to obtain a fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element; When the status values ​​of two write operation sequence elements are different, insert a read operation sequence element after one of the write operation sequence elements that is located at the front in the detection sequence element, wherein the status value of the read operation sequence element is the same as the status value of the write operation sequence element; After one of the write operation sequence elements at a later position in the detection sequence elements, two consecutive read operation sequence elements are inserted, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state value of the write operation sequence element.

8. The memory fault detection method based on target fault type according to claim 1, characterized in that: The screening process of the fault detection sequence to be optimized based on the read operation sequence elements to obtain a final fault detection sequence includes: According to a preset fault detection rule, the read operation sequence elements having no fault detection function are filtered out from the fault detection sequence to be optimized to obtain a filtered detection sequence; According to the position of the read operation sequence element in each target detection sequence, the element position of the read operation sequence element in the screening detection sequence is adjusted to obtain a final fault detection sequence.

9. A memory fault detection device based on target fault type, characterized in that: The device comprises: A construction module, used to determine the type of fault to be detected existing in the memory, and to construct a fault detection sequence library of the memory according to the type of fault to be detected; A determination module, configured to determine, for any target fault type among the fault types to be detected, a target detection sequence of the target fault type from the fault detection sequence library; A reorganization module, configured to perform sequence reorganization based on the write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and insert a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; The screening module is used to perform screening processing on the fault detection sequence to be optimized based on the read operation sequence elements to obtain a final fault detection sequence, wherein the final fault detection sequence is used to detect any target fault type among the fault types to be detected.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the memory fault detection method based on the target fault type according to any one of claims 1 to 8 is implemented.

Images