Memory fault detection method and apparatus based on target fault type

Abstract

The application provides a memory fault detection method and device based on a target fault type, which comprises the following steps: determining a fault type to be detected existing in a memory, and constructing a fault detection sequence library of the memory; determining a corresponding target detection sequence from the fault detection sequence library for any target fault type in the fault type to be detected; performing sequence recombination based on a write operation type for each target detection sequence to obtain an overall write operation detection sequence, inserting a read operation sequence element to obtain a fault detection sequence to be optimized, and finally performing screening processing based on the read operation sequence element to obtain a final fault detection sequence for detecting any target fault type in the fault type to be detected. Through the application, the defect that the test coverage rate for a specific fault type cannot reach 100% due to the fact that the memory fault detection method in the prior art is difficult to detect all fault types of the memory because of the numerous fault types of the memory is overcome.

Description

Technical Field

[0001] This invention relates to the field of memory testing technology, and in particular to a memory fault detection method and apparatus based on target fault type. Background Technology

[0002] In today's information age, the transmission and storage of digital information all require memory as a carrier, highlighting the irreplaceable advantages and role of memory. With the trend towards high integration, memory chips are experiencing increased capacity, more interfaces, and faster transmission speeds. The accuracy, stability, and long-term availability of memory chips are primary considerations, as failures can lead to substantial economic losses, sometimes exceeding mere economic cost. This necessitates efficient and accurate testing of memory chips, as well as the continuous updating and iteration of testing methods, requiring testing algorithms to maximize fault coverage.

[0003] Existing technologies have proposed several memory testing algorithms, such as the all-zero and all-one method, the chessboard method, the March algorithm, and the diagonal method. These methods play an important role in memory testing algorithms. Although they can achieve high fault coverage and linear test complexity in the process of memory fault detection, due to the large number of memory fault types, these methods are difficult to detect all types of memory faults, and the test coverage for specific fault types cannot reach 100%. Summary of the Invention

[0004] This invention provides a memory fault detection method and apparatus based on target fault type, which overcomes the shortcomings of existing memory fault detection methods, which are difficult to detect all types of memory faults due to the large number of memory fault types, and thus cannot achieve 100% test coverage for specific fault types.

[0005] This invention provides a memory fault detection method based on a target fault type, the method specifically including the following steps:

[0006] Determine the types of faults to be detected in the memory, and construct a fault detection sequence library for the memory based on the types of faults to be detected;

[0007] For any one of the target fault types to be detected, a target detection sequence for the target fault type is determined from the fault detection sequence library;

[0008] Each target detection sequence is reorganized based on the write operation type to obtain the overall write operation detection sequence of the fault type to be detected, and read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized.

[0009] Screening processing based on read operation sequence elements is performed on the to-be-optimized fault detection sequence, and a final fault detection sequence is obtained, the final fault detection sequence being used to detect any one of the target fault types in the to-be-detected fault types.

[0010] In some embodiments, the to-be-detected fault types include a single fault type and a coupling fault type, the single fault type being a fault type caused by a single storage unit in the memory, and the coupling fault type being a fault type caused by an attack on a victim storage unit by an aggressor storage unit in the memory, the single fault type including a fixed fault, a state fault, a transition fault, a write disturb fault, a read disturb fault, a false read disturb fault, and a false read disturb fault, and the coupling fault type including a state coupling fault, an interference coupling fault, a transition coupling fault, a write disturb coupling fault, a read disturb coupling fault, a false read disturb coupling fault, and a false read coupling fault.

[0011] In some embodiments, the constructing of the fault detection sequence library of the memory according to the to-be-detected fault types includes:

[0012] determining a single fault primitive of each single fault in the single fault type, and constructing a single fault detection sequence according to the single fault primitive;

[0013] determining a coupling fault primitive of each coupling fault in the coupling fault type, and constructing a coupling fault detection sequence according to the coupling fault primitive;

[0014] merging the single fault detection sequence and the coupling fault detection sequence to obtain the fault detection sequence library of the memory.

[0015] In some embodiments, each sequence element in the target detection sequence includes a detection direction and an operation type, the detection direction including from bottom to top or from top to bottom, and the operation type including a read operation type or a write operation type, and the sequence recombination based on the write operation type is performed on each of the target detection sequences to obtain an overall write operation detection sequence of the to-be-detected fault types, including:

[0016] a first write operation detection sequence is constructed based on a first sequence element in the target detection sequence, the detection direction of the first sequence element being from bottom to top and the operation type of the first sequence element being a write operation type;

[0017] a second write operation detection sequence is constructed based on a second sequence element in the target detection sequence, the detection direction of the second sequence element being from top to bottom and the operation type of the second sequence element being a write operation type;

[0018] the second write operation detection sequence is spliced after the first write operation detection sequence to obtain the overall write operation detection sequence of the to-be-detected fault types.

[0019] In some embodiments, constructing a first write operation detection sequence based on first sequence elements in the target detection sequence whose detection direction is from bottom to top and whose operation type is write operation includes:

[0020] For each target detection sequence, a first sequence element is determined with a detection direction from bottom to top and an operation type of write operation.

[0021] Determine the state value of the first sequence element, and merge the state values ​​to obtain the state value sequence of the target detection sequence;

[0022] The state value sequences of each target detection sequence are merged to obtain the first write operation detection sequence.

[0023] In some embodiments, the overall write operation detection sequence includes multiple detection sequence elements, each detection sequence element includes multiple operation sequence elements, and each operation sequence element has a status value. Inserting read operation sequence elements into the overall write operation detection sequence to obtain the fault detection sequence to be optimized includes:

[0024] For each detection sequence element in the overall write operation detection sequence, determine the number of write operation sequence elements in the detection sequence element, wherein the write operation sequence elements are operation sequence elements with the operation type of write operation.

[0025] When the number of elements is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain the fault detection sequence to be optimized. The state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements. The read operation sequence elements are operation sequence elements with the operation type of read operation.

[0026] When the number of elements is 2, read operation sequence elements are inserted into the overall write operation detection sequence according to the state values ​​of the two write operation sequence elements to obtain the fault detection sequence to be optimized.

[0027] In some embodiments, based on the state values ​​of two write operation sequence elements, read operation sequence elements are inserted into the overall write operation detection sequence to obtain a fault detection sequence to be optimized, including:

[0028] When the state values ​​of two write operation sequence elements are the same, after the write operation sequence element that is later in the detection sequence element, two consecutive read operation sequence elements are inserted to obtain the fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements.

[0029] When the state values of two write operation sequence elements are different, one read operation sequence element is inserted after one of the write operation sequence elements in the front of the detection sequence element, wherein the state value of the read operation sequence element is the same as the state value of the write operation sequence element.

[0030] Two read operation sequence elements are inserted after one of the write operation sequence elements in the rear of the detection sequence element, wherein the state values of the two read operation sequence elements are the same as the state value of the write operation sequence element.

[0031] In some embodiments, the read operation sequence element-based screening processing of the to-be-optimized fault detection sequence is performed to obtain a final fault detection sequence, including:

[0032] According to a preset fault detection rule, a read operation sequence element without a fault detection effect is screened out from the to-be-optimized fault detection sequence to obtain a screening detection sequence.

[0033] According to the position of the read operation sequence element in each target detection sequence, the element position of the read operation sequence element in the screening detection sequence is adjusted to obtain the final fault detection sequence.

[0034] The application further provides a memory fault detection device based on a target fault type, and the device specifically comprises the following modules:

[0035] A construction module is configured to determine a to-be-detected fault type existing in a memory, and construct a fault detection sequence library of the memory according to the to-be-detected fault type.

[0036] A determination module is configured to determine a target detection sequence of a target fault type from the fault detection sequence library for any target fault type in the to-be-detected fault type.

[0037] A recombination module is configured to perform write operation type-based sequence recombination on each target detection sequence to obtain an overall write operation detection sequence of the to-be-detected fault type, and insert a read operation sequence element into the overall write operation detection sequence to obtain a to-be-optimized fault detection sequence.

[0038] A screening module is configured to perform read operation sequence element-based screening processing on the to-be-optimized fault detection sequence to obtain a final fault detection sequence, and the final fault detection sequence is used to detect any target fault type in the to-be-detected fault type.

[0039] The application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the memory fault detection method based on a target fault type according to any one of the above description when executing the program.

[0040] The application further provides a non-transitory computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the memory fault detection method based on a target fault type according to any one of the above description.

[0041] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the memory fault detection method based on a target fault type according to any one of the above description.

[0042] The memory fault detection method based on a target fault type provided by the application is to construct a fault detection sequence library by the fault types to be detected existing in the memory, in the fault detection sequence library, for the target detection sequence of any one of the target fault types, sequence recombination based on the write operation type is performed to obtain an overall write operation detection sequence, and a read operation sequence element is inserted into the overall write operation detection sequence to obtain a fault detection sequence to be optimized, and finally, screening based on the read operation sequence element is performed on the fault detection sequence to be optimized to obtain a final fault detection sequence. Therefore, under the condition that the fault types to be detected existing in the memory are known, the final fault detection sequence capable of detecting any one of the target fault types is designed, and therefore, memory testing according to the final fault detection sequence can cover every target fault type of the memory, and the coverage rate of the target fault types to be detected reaches 100%. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0044] Figure 1 is a flowchart of the memory fault detection method based on a target fault type provided by the application.

[0045] Figure 2 is a schematic diagram of constructing a single fault detection sequence for a single fault type provided by the application.

[0046] Figure 3 is a schematic diagram of constructing a coupling fault detection sequence for a coupling fault type provided by the application.

[0047] Figure 4is a schematic diagram of the fault detection sequence constructed by the interference coupling fault provided by the present application.

[0048] Figure 5 is a state transition diagram of the target detection sequence provided by the present application.

[0049] Figure 6 is a process flow chart of the read operation sequence element inserted in the whole write operation detection sequence provided by the present application.

[0050] Figure 7 is a structural schematic diagram of the memory fault detection device based on the target fault type provided by the present application.

[0051] Figure 8 is a physical structure schematic diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0052] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0053] The present application will be described below with reference to the drawings. Figure 1 The present application provides a memory fault detection method based on a target fault type,

[0054] Figure 1 is a flow schematic diagram of the memory fault detection method based on a target fault type provided by the present application, as shown in the figure, the method comprises the following steps. Figure 1

[0055] In step 101, the type of fault to be detected existing in the memory is determined, and a fault detection sequence library of the memory is constructed according to the type of fault to be detected.

[0056] ​In the embodiment of the present application, firstly, it is necessary to determine the types of faults to be detected existing in the memory during operation, and in order to make the coverage of the detected faults reach 100%, the embodiment of the present application will determine some specific fault types of all common possible faults of the memory in advance and make statistics. After the analysis of the fault types through statistics, the types of faults to be detected include two categories of single fault types and coupled fault types, wherein the single fault type is a fault type caused by a single storage unit in the memory, and the coupled fault type is a fault type caused by an attack on a victim storage unit by an attack storage unit in the memory. Since different fault types need to use different detection sequences for detection and verification, after the statistics and determination of all common types of faults to be detected existing in the memory, the fault detection sequence library of the memory is constructed according to the types of faults to be detected.

[0057] The fault detection sequence library needs to record the fault detection sequence of each fault type, so the corresponding fault primitive is determined for each fault type, and then the corresponding fault detection sequence is constructed according to the fault primitive. The types of faults to be detected of the memory include two categories of single fault types and coupled fault types, so the fault detection sequence library is constructed for the two categories of fault types respectively.

[0058] It should be noted that the fault detection sequence in the embodiment of the present application is constructed according to the standard of March algorithm. The processing process of March algorithm is that, for each storage unit in the memory, the change of the state value of the two storage units (represented by two digits, for example, 00), the operation of each read and write (referred to as operation type, read or write) and the operation data (operation value, 0 or 1) are recorded as a March element, and the operation direction of the memory test is also recorded in the March element, that is, the search direction of March algorithm on the storage unit. In the search direction, the state value of the two storage units is changed by performing the operation type and the operation value. In the test operation according to the March element, the detection direction from bottom to top is defined as “↑” direction, the detection direction from top to bottom is defined as “↓” direction, and the detection direction is not limited when it is called “↕” direction.

[0059] The write operation type is write, represented as w, the read operation type is read, represented as r, and the operation value is the value input in the test process, specifically a pair of opposite values, that is, 0 and 1. Therefore, the fault detection sequence is composed of multiple March elements, and one March element represents one test operation, that is, one March element in the test operation is performed on all storage units in the memory. For example, “↑w1” represents that two storage units are written with 1 from bottom to top.

[0060] First, a single fault primitive of each single fault in a single fault type is determined, and a single fault detection sequence is constructed according to the single fault primitive. Here, the single fault primitive is a form representing a memory fault type. An expression of the single fault primitive of one memory cell in the memory can be <s f r>Wherein, S represents the state or operation that excites the memory fault, the state here is the state value of the memory cell of the memory, expressed as 0 or 1. And the operation refers to the read-write operation that can be done to the state value of the memory cell, including reading 0 (r0), reading 1 (r1), writing 0 in 0 (0w0), writing 1 in 0 (0w1), writing 0 in 1 (1w0), writing 1 in 1 (1w1). Therefore, the single fault type of the memory is S∈{0, 1, r0, r1, 0w0, 0w1, 1w0, 1w1}; F represents the state value of the fault cell, F∈{0, 1}; R represents the logic output level of the read operation. When S is a read operation, R represents the result of reading, which has two states of 0 and 1, and when S is not a read operation, R represents "-", and R∈{0, 1, -}.

[0061] In the embodiment of the application, the single fault type includes seven types of stuck-at fault (SAF), state fault (SF), transition fault (TF), write disturb fault (WDF), read destructive fault (RDF), deceptive read destructive fault (DRDF) and state coupling fault (CFST), which are described below.

[0062] (1) The stuck-at fault SAF is that the fault cell constantly maintains a storage state (0 or 1) and the state cannot be changed.

[0063] (2) The state fault SF is a fault that can be manifested without any read-write operation, when the storage state of the fault cell is 0 or 1, it will automatically jump to the opposite state 1 or 0.

[0064] (3) The transition fault TF is that when the opposite value operation is performed on the fault cell, the state value of the fault cell does not change. That is, when the state value of the fault cell is 0 or 1, the write 1 or 0 operation is performed, but the fault cell does not have the state change of 0→1 or 1→0, and still maintains the original state.

[0065] (4) The write disturb fault WDF is that when the same operation as the original state is performed on the fault cell, the state of the fault cell changes. That is, when the state of the fault cell is 0 or 1, the write 0 or 1 operation is performed on the fault cell again, and the state of the fault cell changes to 1 or 0.

[0066] (5) Read disturb fault RDF, when reading the fault unit, the state of the fault unit will change and the changed state value will be read out. That is, when the initial state of the storage unit is 0 or 1, the read 0 or 1 operation is performed, and the read state value is 1 or 0.

[0067] (6) Pseudo read disturb fault DRDF, when reading the fault unit, the state of the fault unit will change, but the read state value is the state value before the change of the fault unit. That is, the initial state value of the fault unit is 0 or 1, and after the read operation, the state value of the fault unit becomes 1 or 0, but the read state value is 0 or 1.

[0068] (7) False read fault CFST, when reading the fault unit, the state value of the fault unit does not change, but the read state value is an error state value. That is, the initial state value of the fault unit is 0 or 1, and after the read operation, the state value of the fault unit is still 0 or 1, but the read state value is 1 or 0.

[0069] Referring to Figure 2 , Figure 2 is a schematic diagram of constructing a single fault detection sequence according to the single fault type provided by the application, as shown in Figure 2 , for the above seven single fault types, first determine the single fault primitive of each single fault in the single fault type, and then generate the corresponding single fault detection sequence according to each single fault primitive. According to Figure 2 , it can be known that there are multiple single fault primitives corresponding to each single fault type, and there are multiple single fault detection sequences constructed by each single fault primitive. This is to ensure that all single fault types can be involved, so that the coverage of the fault detection sequence library is more comprehensive.

[0070] For the coupling fault type, similar to the single fault type, first determine the coupling fault primitive of each coupling fault in the coupling fault type, and construct the coupling fault detection sequence according to the coupling fault primitive. Here, the coupling fault primitive is also a form of indicating the memory fault type. The coupling fault primitive of the storage unit (one attack storage unit, one victim storage unit) in the memory can be represented as <Sa, Sv / F / R>, wherein Sa represents the state or operation of the attack storage unit fault sensitization, and Sv represents the state or operation of the victim storage unit fault sensitization. Here, the coupling fault type of the memory is Sa, Sv ∈ {0, 1, r0, r1, 0w0, 0w1, 1w0, 1w1}; F represents the state of the fault unit, F ∈ {0, 1, ↑, ↓}, wherein "0, 1" represents that the state of the fault unit is 0 and 1, and the state of the fault unit is still 0 and 1 after operation, ↑ represents that the state of the fault unit changes from 0 to 1, and ↓ represents that the state of the fault unit changes from 1 to 0; if S is a read operation, R represents the read result, which has two states of 0 and 1, and if S is not a read operation, R is represented as "-", and R ∈ {0, 1, -}.

[0071] In the embodiment of the present application, the coupling fault type includes seven types of state coupling fault (CFst), disturb coupling fault (CFds), transition coupling fault (CFtr), write destructive coupling fault (CFwd), read destructive coupling fault (CFrd), deceptive read destructive coupling fault (CFdrd) and incorrect read destructive coupling fault (CFir).

[0072] For the above seven coupling fault types, the coupling fault primitive of each coupling fault in the coupling fault type is determined respectively, and the corresponding coupling fault detection sequence is generated based on the coupling fault primitive and the memory fault principle. The generated coupling fault detection sequence can be multiple, and each coupling fault detection sequence can be used to detect the corresponding coupling fault type. For details, see Figure 3 , Figure 3 is a schematic diagram of constructing a coupling fault detection sequence for a coupling fault type provided by the present application, which will be described below in combination with Figure 3 .

[0073] (1) State-coupling fault CFst, the state of the attacking storage unit will cause the state value of the victim storage unit to flip (state value flip means abnormal change of state value, for example, 0 flips to 1 or 1 flips to 0, the state value flip referred to below is subject to this explanation, and will not be repeated here). That is, when the initial state value of the victim storage unit is 0 or 1, due to the influence of the state value of the attacking storage unit, the state value of the victim storage unit flips to 1 or 0. The fault primitive and the corresponding detection sequence are as shown in (a). Figure 3

[0074] (2) Disturb-coupling fault CFds, the attacking storage unit performs a read operation or a write operation, which will cause the state value of the victim storage unit to flip. According to the different operation states of the attacking storage unit, the disturb-coupling fault is further divided into three categories. The fault primitive and the fault detection sequence of each category of disturb-coupling fault can be seen from Figure 4 Figure 4 is a schematic diagram of the fault primitive and the fault detection sequence of the disturb-coupling fault provided by the present application.

[0075] The first category is , which means that the attacking storage unit performs a read operation, which will cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, due to the r0 or r1 operation of the attacking storage unit, the state value of the victim storage unit flips to 1 or 0. The fault primitive and the fault detection sequence are as shown in (a). Figure 4

[0076] The second category is , which means that the attacking storage unit performs some xwx operation (writing the same value as the initial state value) which will cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, due to the 1w1 or 0w0 operation of the attacking storage unit, the state value of the victim storage unit flips to 1 or 0. The fault primitive and the fault detection sequence are as shown in (b). Figure 4

[0077] The third category is , which means that the attacking storage unit performs some operation (writing a value different from the initial state value) which will cause the state value of the victim storage unit to flip. That is, when the initial state value of the victim storage unit is 0 or 1, due to the 0w1 or 1w0 operation of the attacking storage unit, the state value of the victim storage unit flips to 1 or 0. The fault primitive and the fault detection sequence are as shown in (c). Figure 4

[0078] ​​​​​(3) Conversion coupling fault CFtr, when the victim storage unit performs a write operation, the state change of the victim storage unit cannot be completed due to the influence of the state value of the attack storage unit. That is, when the initial state value of the victim storage unit is 0 or 1, the write 1 or 0 operation is performed, and due to the influence of the state value of the attack storage unit, the state value of the victim storage unit cannot be flipped to 1 or 0. The fault primitive and the corresponding detection sequence are as shown in Figure 3 (b) shown.

[0079] (4) Write destructive coupling fault CFwd, when the victim storage unit performs a write operation without changing the state value, the state value of the victim storage unit will be flipped due to the influence of the state value of the attack storage unit. That is, when the initial state value of the victim storage unit is 0 or 1, the w0 or w1 operation is performed, and due to the state value of the attack storage unit being 0 or 1, the state value of the victim storage unit is flipped to 1 or 0. The fault primitive and the corresponding detection sequence are as shown in Figure 3 (c) shown.

[0080] (5) Read destructive coupling fault CFrd, when the state of the attack storage unit is a certain state, the read operation on the victim storage unit will cause the state value of the victim storage unit to flip, and the read state value is the flipped value. That is, when the initial state value of the victim storage unit is 0 or 1, the r0 or r1 operation is performed, and due to the state value of the attack storage unit being 0 or 1, the state value of the victim storage unit is flipped to 1 or 0, so that the read state value of the victim storage unit is 1 or 0. The fault primitive and the corresponding detection sequence are as shown in Figure 3 (d) shown.

[0081] (6) Pseudo read destructive coupling fault CFdrd, when the state value of the attack storage unit is a certain state, the read operation on the victim storage unit will cause the state value of the victim storage unit to flip, and the read state value is the state value before flipping. That is, when the initial state value of the victim storage unit is 0 or 1, the r0 or r1 operation is performed, and due to the state value of the attack storage unit being 0 or 1, the state value of the victim storage unit is flipped to 1 or 0, but the read state value is 0 or 1. The fault primitive and the corresponding detection sequence are as shown in Figure 3 (e) shown.

[0082] (7) Error read coupling fault CFir, when the state value of the attack storage unit is a certain state, the read operation on the victim storage unit will not cause the state value of the victim storage unit to flip, but the read state value is the state value after flipping. That is, when the initial state value of the victim storage unit is 0 or 1, the r0 or r1 operation is performed, and due to the state value of the attack storage unit being 0 or 1, the state value of the victim storage unit is still 0 or 1, but the read state value is 1 or 0. The fault primitive and the corresponding detection sequence are as shown in Figure 3 (f) shown.

[0083] After the single fault detection sequence and the coupling fault detection sequence are constructed, the single fault detection sequence and the coupling fault detection sequence are merged to obtain a fault detection sequence library of the memory. Therefore, the detection sequences of all the fault types to be detected are recorded in the fault detection sequence library.

[0084] Continuing to refer to Figure 1 In step 102, for any target fault type in the fault types to be detected, a target detection sequence of the target fault type is determined from the fault detection sequence library.

[0085] When the memory needs to be detected, for any target fault type in the fault types to be detected, a target detection sequence of the target fault type can be determined from the fault detection sequence library. Since the detection sequences of all the common fault types are recorded in the fault detection sequence library, the coverage of the fault types can reach 100%.

[0086] In step 103, each target detection sequence is subjected to sequence recombination based on the write operation type to obtain an overall write operation detection sequence of the fault type to be detected, and a read operation sequence element is inserted into the overall write operation detection sequence to obtain an optimized fault detection sequence.

[0087] Therefore, in order to detect all the fault types to be detected in the memory, the target detection sequences in the fault detection sequence library are recombined, that is, each target detection sequence is subjected to sequence recombination based on the write operation type to obtain an overall write operation detection sequence of the fault type to be detected. The specific process of sequence recombination of the target detection sequence is described below.

[0088] Since the target detection sequence is actually a fault detection sequence in the fault detection sequence library, and the fault detection sequence is composed of sequence elements, each sequence element in the target detection sequence includes a detection direction and an operation type. The detection direction includes from bottom to top ("↑") or from top to bottom ("↓"), which represents the state value change from left to right or from right to left. The operation type includes a read operation type (w) or a write operation type (r). Considering the storage unit test process of the memory, the read operation type does not change the state value of the storage unit, and only the write operation type changes the state value of the storage unit, so the write operation type in the target detection sequence is first subjected to sequence recombination.

[0089] In the embodiment of the application, the write operation is recombined by the state transition graph, but in the recombination process, the recombination is performed according to two detection directions (i.e. from bottom to top "↑" and from top to bottom "↓"), and the results of the recombination of the two detection directions are spliced. In the recombination, a state transition graph is first formed for each target detection sequence of the target fault type, as shown in Figure 5 Figure 5 is a state transition diagram of the target detection sequence provided by the present application. As shown in Figure 5 , each node in the state transition diagram represents a state value, and the edges between the nodes represent the corresponding test operations. First, the initial state "00" is subjected to the operations of ↕w0 / ↑w0 / ↓w0, and the state remains "00"; after the operation of ↑w1, the state becomes "10"; and after the operation of ↓w1, the state becomes "01". The state "10" is subjected to the operation of ↓w0, and the state becomes "00"; after the operation of ↑w0, the state becomes "01"; and after the operation of ↑w1, the state becomes "11". The state "11" is subjected to the operations of ↕w1 / ↑w1 / ↓w1, and the state remains "11"; after the operation of ↑w0, the state becomes "01"; and after the operation of ↓w0, the state becomes "10". The state "01" is subjected to the operation of ↓w1, and the state becomes "11"; after the operation of ↑w0, the state becomes "00"; and after the operation of ↓w0, the state becomes "10". Finally, the state transition diagram with "00" as the starting point can be obtained.

[0090] For the "↑" direction from bottom to top, the first sequence element with the detection direction from bottom to top and the operation type of write operation type in the target detection sequence is constructed to obtain the first write operation detection sequence.

[0091] Here, each target detection sequence is first converted into a state transition diagram, and for each target detection sequence, the first sequence element with the detection direction from bottom to top and the operation type of write operation type is determined from the state transition diagram. Here, for each target fault type of the target detection sequence, the test operation with the detection direction from bottom to top and the operation type of write operation type is counted from the state transition diagram (specifically, the edges of the state transition diagram) as the first sequence element.

[0092] Then, the state value of the first sequence element is determined, and the state value sequence of the target detection sequence is obtained by merging the state values. Here, the state value of each first sequence element is first determined, specifically by converting each first sequence element into a state value form, and then all the state values are merged to obtain the state value sequence of the target detection sequence.

[0093] Finally, the state value sequence of each target detection sequence is merged to obtain the first write operation detection sequence. Here, the state value sequences corresponding to different fault types are merged to obtain the first write operation detection sequence in the "↑" direction from bottom to top.

[0094] ​Similar to the process for the "↑" direction from top to bottom, the second write operation detection sequence is constructed based on the second sequence elements in the target detection sequence that have a detection direction from top to bottom and an operation type of write. The process involves first converting each target detection sequence into a state transition diagram. For each target detection sequence, the second sequence elements with a detection direction from top to bottom and an operation type of write are determined from the state transition diagram. Then, the state values ​​of the second sequence elements are determined and merged to obtain the state value sequence of the target detection sequence. Finally, the state value sequences of each target detection sequence are merged to obtain the second write operation detection sequence. This also involves merging the state value sequences corresponding to different fault types to obtain the second write operation detection sequence in the "↑" direction from top to bottom. Since the specific construction process of the second write operation detection sequence is similar to that of the first write operation detection sequence, it will not be repeated here.

[0095] After determining the second write operation detection sequence and the first write operation detection sequence in two detection directions, the second write operation detection sequence is concatenated to the first write operation detection sequence to obtain the overall write operation detection sequence of the fault type to be detected.

[0096] Next, read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. However, read operation sequence elements cannot be inserted arbitrarily and must follow certain detection rules. For example, after analyzing each target fault type in the memory fault types to be detected, it is found that there is no need to perform a write state value (0 or 1) operation followed by a write or read operation with the opposite state value (1 or 0), because this is an invalid operation in the detection process and has no effect on detecting the fault type.

[0097] To comply with this detection rule, in this embodiment of the invention, read operation sequence elements are inserted based on the number of write operations in the overall write operation detection sequence. Read operation sequence elements are those whose operation type is read. See details... Figure 6 , Figure 6 This is a flowchart of the process for inserting read operation sequence elements into the overall write operation detection sequence provided by the present invention. The following is in conjunction with... Figure 6 The steps in the document will be explained in detail.

[0098] In step 601, read operation sequence elements are inserted into the overall write operation detection sequence.

[0099] In step 602, the number of elements in the write operation sequence is determined.

[0100] Here, the whole write operation detection sequence includes a plurality of detection sequence elements, the detection sequence element includes a plurality of operation sequence elements, and the operation sequence element has a state value. Therefore, for each detection sequence element in the whole write operation detection sequence, the number of write operation sequence elements in the detection sequence element is determined, and the write operation sequence element is an operation sequence element with a write operation type as the operation type.

[0101] When it is determined that the number of write operation sequence elements in the detection sequence element is 1, step 603 is executed, and when it is determined that the number of write operation sequence elements in the detection sequence element is 2, step 604 is executed.

[0102] In step 603, two read operation sequence elements are inserted in succession after the write operation sequence element.

[0103] Here, when it is determined that the number of write operation sequence elements in the detection sequence element is 1, two read operation sequence elements are inserted in succession after the write operation sequence element to obtain the to-be-optimized fault detection sequence, and then step 607 is executed. During the insertion, it is necessary to ensure that the state values of the inserted two read operation sequence elements in succession are the same as the state value of the write operation sequence element.

[0104] In step 604, it is determined whether the state values of the two write operation sequence elements are the same.

[0105] Here, when it is determined that the number of write operation sequence elements in the detection sequence element is 2, a read operation sequence element is inserted in the whole write operation detection sequence according to the state values of the two write operation sequence elements to obtain the to-be-optimized fault detection sequence. Here, when it is determined that the number of write operation sequence elements is 2, it is necessary to determine whether the state values of the two write operation sequence elements are the same, and then a read operation sequence element is inserted in the whole write operation detection sequence according to the state values of the two write operation sequence elements to obtain the to-be-optimized fault detection sequence. When the state values of the two write operation sequence elements are the same, step 605 is executed, and when the state values of the two write operation sequence elements are different, step 606 is executed.

[0106] In step 605, two read operation sequence elements are inserted in succession after one of the write operation sequence elements located at the rear in the detection sequence element.

[0107] Here, when the state values of the two write operation sequence elements are the same, two read operation sequence elements are inserted in succession after one of the write operation sequence elements located at the rear in the detection sequence element to obtain the to-be-optimized fault detection sequence, and then step 607 is executed. During the insertion, it is still necessary to ensure that the state values of the inserted two read operation sequence elements in succession are the same as the state value of the write operation sequence element.

[0108] In step 606, after detecting one of the write operation sequence elements in the front of the sequence elements, one read operation sequence element is inserted, and after detecting one of the write operation sequence elements in the rear of the sequence elements, two read operation sequence elements are inserted in succession.

[0109] Here, when the state values of the two write operation sequence elements are different, after detecting one of the write operation sequence elements in the front of the sequence elements, one read operation sequence element is inserted, and the state value of the inserted read operation sequence element is ensured to be the same as the state value of the write operation sequence element. Meanwhile, after detecting one of the write operation sequence elements in the rear of the sequence elements, two read operation sequence elements are inserted in succession, and the process goes to step 607. During the insertion, the state values of the inserted two read operation sequence elements in succession are still ensured to be the same as the state value of the write operation sequence element.

[0110] In step 607, the fault detection sequence to be optimized is obtained.

[0111] By performing step 603, step 605 and step 606, that is, inserting read operation sequence elements in the corresponding positions according to the number of write operation sequence elements in the sequence elements and the state values of the write operation sequence elements, the fault detection sequence to be optimized is finally obtained under the condition of complying with the detection rule.

[0112] Continuing to refer to Figure 1 In step 104, the read operation sequence element-based screening processing is performed on the fault detection sequence to be optimized, and the final fault detection sequence is obtained, which is used to detect any target fault type in the fault types to be detected.

[0113] Here, after obtaining the fault detection sequence to be optimized by step 607 in Figure 6 , considering that the read operation sequence elements are inserted according to the write operation sequence elements, there may be redundant read operation sequence elements in the detection sequence that have no fault detection effect, therefore, the read operation sequence element-based screening processing is performed on the fault detection sequence to be optimized, and the final fault detection sequence is obtained.

[0114] Continuing to refer to Figure 6 In step 608, the read operation sequence elements without fault detection effect are screened out.

[0115] Here, the detection sequence in the previous memory detection algorithm can be analyzed, a fault detection rule is set in advance, and the read operation sequence elements without fault detection effect are determined from all the fault types to be detected, which is also the process of optimizing the fault detection sequence to be optimized and the screening of the read operation sequence elements, and the screened detection sequence is obtained.

[0116] In step 609, the position of the read operation sequence element is determined.

[0117] Here, the element position of the read operation sequence element in the screening detection sequence is adjusted according to the position of the read operation sequence element in each target detection sequence to obtain the final fault detection sequence. Specifically, the number of elements of the read operation sequence element in the screening detection sequence is counted first, and then the element position of each read operation sequence element in the screening detection sequence is determined.

[0118] Since the screening detection sequence is still composed of multiple detection sequence elements, the read operation sequence element therein can be determined as the end of the detection sequence element or the beginning of the next detection sequence element according to the position of the read operation sequence element in each target detection sequence, so that the fault type detection coverage rate of 100% can be ensured. Here, the position of the read operation sequence element in the detection sequence element is calibrated according to the position of the read operation in the fault detection sequence of each fault type (i.e., the above-mentioned 7 single fault types and 7 coupled fault types).

[0119] In step 610, the final fault detection sequence is obtained.

[0120] After the position of the read operation sequence element in the screening detection sequence is adjusted through step 609, the final fault detection sequence can be obtained.

[0121] In the embodiment of the present application, the obtained final fault detection sequence can be exemplarily represented as the following sequence: "{↑(w0); ↑(r0, w0, r0); ↑(r0, w1, w1, r1), ↑(r1, w1), ↑(r1, w0, w0, r0); ↑(r0); ↑(w1, r1); ↑(w0, r0); ↑(w0, r0, w1); ↑(w1, r1, w0); ↑(r0, r0, w1), ↑(r1, r1, w0); ↓(r0, w0, r0); ↓(r0, w1, w1, r1); ↓(r1, w1), ↓(r1, w0, w0, r0), ↓(r0); ↓(w1, r1); ↓(w0, r0); ↓(w0, r0, w1); ↓(w1, r1, w0); ↓(r0, r0, w1); ↓(r1, r1, w0)}".

[0122] The above-mentioned final fault detection sequence can detect any one of the target fault types in the to-be-detected fault types, that is, only one fault detection sequence can detect the to-be-detected fault types (i.e., the above-mentioned 7 single fault types and 7 coupled fault types) existing in the memory during the running process, and the fault type detection coverage rate can be ensured to reach 100%, as shown in Table 1:

[0123] Table 1

[0124]

[0125] The target fault type-based memory fault detection device provided by the present application is described below, and the target fault type-based memory fault detection device described below can be referred to in correspondence with the target fault type-based memory fault detection method described above.

[0126] Figure 7 is a structural schematic diagram of the target fault type-based memory fault detection device provided by the present application, as Figure 7 As shown in the figure, the present application provides a target fault type-based memory fault detection device, which specifically comprises: a construction module 701, a determination module 702, a recombination module 703, and a screening module 704. Among them, the construction module 701 is used to determine the fault type to be detected existing in the memory, and construct a fault detection sequence library of the memory according to the fault type to be detected; the determination module 702 is used to determine a target detection sequence of a target fault type from the fault detection sequence library for any target fault type in the fault type to be detected; the recombination module 703 is used to perform sequence recombination based on the write operation type on each target detection sequence to obtain an overall write operation detection sequence of the fault type to be detected, and insert a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; and the screening module 704 is used to perform screening processing based on the read operation sequence element on the fault detection sequence to be optimized to obtain a final fault detection sequence, which is used to detect any target fault type in the fault type to be detected.

[0127] Figure 8 is a structural schematic diagram of an electronic device provided by the present application, as Figure 8 As shown, the electronic device can include a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 complete mutual communication through the communications bus 840. The processor 810 can invoke a logic instruction in the memory 830 to execute a memory fault detection method based on a target fault type, which includes determining a to-be-detected fault type present in the memory, and constructing a fault detection sequence library of the memory according to the to-be-detected fault type; determining a target detection sequence of a target fault type from the fault detection sequence library for any one of the to-be-detected fault types; performing sequence recombination based on a write operation type for each target detection sequence to obtain an overall write operation detection sequence of the to-be-detected fault type, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a to-be-optimized fault detection sequence; and performing screening processing based on the read operation sequence element for the to-be-optimized fault detection sequence to obtain a final fault detection sequence, which is used to detect any one of the target fault types in the to-be-detected fault type.

[0128] In addition, the logic instruction in the memory 830 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0129] In another aspect, the present application also provides a computer program product comprising a computer program, which can be stored on a non-transitory computer readable storage medium, and the computer program, when executed by a processor, enables a computer to perform the memory fault detection method based on a target fault type provided by the above-mentioned methods, which comprises: determining a fault type to be detected existing in a memory, and constructing a fault detection sequence library of the memory according to the fault type to be detected; determining a target detection sequence of a target fault type from the fault detection sequence library for any one of the target fault types; performing sequence recombination based on a write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; and performing screening processing based on the read operation sequence element on the fault detection sequence to be optimized to obtain a final fault detection sequence, which is used to detect any one of the target fault types of the fault type to be detected.

[0130] In another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, and the computer program, when executed by a processor, enables a computer to perform the memory fault detection method based on a target fault type provided by the above-mentioned methods, which comprises: determining a fault type to be detected existing in a memory, and constructing a fault detection sequence library of the memory according to the fault type to be detected; determining a target detection sequence of a target fault type from the fault detection sequence library for any one of the target fault types; performing sequence recombination based on a write operation type on each of the target detection sequences to obtain an overall write operation detection sequence of the fault type to be detected, and inserting a read operation sequence element into the overall write operation detection sequence to obtain a fault detection sequence to be optimized; and performing screening processing based on the read operation sequence element on the fault detection sequence to be optimized to obtain a final fault detection sequence, which is used to detect any one of the target fault types of the fault type to be detected.

[0131] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0132] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0133] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.< / s>

Claims

1. A memory fault detection method based on target fault type, characterized in that, The method includes: Determine the types of faults to be detected in the memory, and construct a fault detection sequence library for the memory based on the types of faults to be detected; For any one of the target fault types to be detected, a target detection sequence for the target fault type is determined from the fault detection sequence library; Each target detection sequence is reorganized based on the write operation type to obtain the overall write operation detection sequence of the fault type to be detected, and read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. The fault detection sequence to be optimized is subjected to filtering processing based on read operation sequence elements to obtain the final fault detection sequence, which is used to detect any one of the target fault types among the fault types to be detected; The fault types to be detected include single fault types and coupled fault types. The single fault type is a fault type caused by a fault in a single memory cell in the memory. The coupled fault type is a fault type caused by an attacking memory cell attacking a victim memory cell. The single fault type includes fixed faults, state faults, transition faults, write corruption faults, read corruption faults, pseudo-read corruption faults, and erroneous read corruption faults. The coupled fault types include state coupled faults, interference coupled faults, transition coupled faults, write corruption coupled faults, read corruption coupled faults, pseudo-read corruption coupled faults, and erroneous read coupled faults. The feature is that constructing the fault detection sequence library of the memory according to the type of fault to be detected includes: Identify the single fault primitive for each single fault in a single fault type, and construct a single fault detection sequence based on the single fault primitive; Determine the coupling fault primitives for each type of coupling fault, and construct a coupling fault detection sequence based on the coupling fault primitives; The single fault detection sequence is merged with the coupled fault detection sequence to obtain the fault detection sequence library of the memory; Each sequence element in the target detection sequence includes a detection direction and an operation type. The detection direction includes bottom-up or top-down, and the operation type includes a read operation or a write operation. The step of recombining each target detection sequence based on the write operation type to obtain the overall write operation detection sequence for the fault type to be detected includes: Based on the first sequence elements in the target detection sequence whose detection direction is from bottom to top and whose operation type is write operation, a first write operation detection sequence is constructed. Based on the second sequence elements in the target detection sequence whose detection direction is from top to bottom and whose operation type is write operation, a second write operation detection sequence is constructed. The second write operation detection sequence is concatenated to the first write operation detection sequence to obtain the overall write operation detection sequence of the fault type to be detected; The overall write operation detection sequence includes multiple detection sequence elements, each detection sequence element includes multiple operation sequence elements, and each operation sequence element has a state value. Inserting read operation sequence elements into the overall write operation detection sequence to obtain the fault detection sequence to be optimized includes: For each detection sequence element in the overall write operation detection sequence, determine the number of write operation sequence elements in the detection sequence element, wherein the write operation sequence elements are operation sequence elements with the operation type of write operation. When the number of elements is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain the fault detection sequence to be optimized. The state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements. The read operation sequence elements are operation sequence elements with the operation type of read operation. When the number of elements is 2, according to the state values ​​of the two write operation sequence elements, read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. The step of performing a filtering process based on read operation sequence elements on the fault detection sequence to obtain the final fault detection sequence includes: According to the preset fault detection rules, read operation sequence elements that do not have fault detection function are filtered out from the fault detection sequence to be optimized to obtain the filtered detection sequence; Based on the position of the read operation sequence element in each target detection sequence, the element positions of the read operation sequence elements in the filtered detection sequence are adjusted to obtain the final fault detection sequence.

2. The memory fault detection method based on target fault type according to claim 1, characterized in that, The first write operation detection sequence is constructed based on the first sequence elements in the target detection sequence whose detection direction is from bottom to top and whose operation type is write operation, including: For each target detection sequence, a first sequence element is determined with a detection direction from bottom to top and an operation type of write operation. Determine the state value of the first sequence element, and merge the state values ​​to obtain the state value sequence of the target detection sequence; The state value sequences of each target detection sequence are merged to obtain the first write operation detection sequence.

3. The memory fault detection method based on target fault type according to claim 1, characterized in that, Based on the state values ​​of the two write operation sequence elements, read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized, including: When the state values ​​of two write operation sequence elements are the same, after the write operation sequence element that is later in the detection sequence element, two consecutive read operation sequence elements are inserted to obtain the fault detection sequence to be optimized, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements. When the state values ​​of two write operation sequence elements are different, after detecting the write operation sequence element that is earlier in the sequence, a read operation sequence element is inserted, wherein the state value of the read operation sequence element is the same as the state value of the write operation sequence element. After detecting one of the later write operation sequence elements in the sequence, insert two consecutive read operation sequence elements, wherein the state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements.

4. A memory fault detection device based on a target fault type, characterized in that, The device includes: A construction module is used to determine the types of faults to be detected in the memory, and to construct a fault detection sequence library for the memory based on the types of faults to be detected; The determination module is used to determine the target detection sequence of any target fault type from the fault detection sequence library for any one of the target fault types to be detected; The recombination module is used to recombine each target detection sequence based on the write operation type to obtain the overall write operation detection sequence of the fault type to be detected, and to insert read operation sequence elements into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. The filtering module is used to perform filtering processing on the fault detection sequence to be optimized based on the read operation sequence elements to obtain the final fault detection sequence, which is used to detect any one of the target fault types among the fault types to be detected. The fault types to be detected include single fault types and coupled fault types. The single fault type is a fault type caused by a fault in a single memory cell in the memory. The coupled fault type is a fault type caused by an attacking memory cell attacking a victim memory cell. The single fault type includes fixed faults, state faults, transition faults, write corruption faults, read corruption faults, pseudo-read corruption faults, and erroneous read corruption faults. The coupled fault types include state coupled faults, interference coupled faults, transition coupled faults, write corruption coupled faults, read corruption coupled faults, pseudo-read corruption coupled faults, and erroneous read coupled faults. The building module is specifically used for: Identify the single fault primitive for each single fault in a single fault type, and construct a single fault detection sequence based on the single fault primitive; Determine the coupling fault primitives for each type of coupling fault, and construct a coupling fault detection sequence based on the coupling fault primitives; The single fault detection sequence is merged with the coupled fault detection sequence to obtain the fault detection sequence library of the memory; Each sequence element in the target detection sequence includes a detection direction and an operation type. The detection direction includes bottom-up or top-down, and the operation type includes a read operation or a write operation. The reassembly module is specifically used for: Based on the first sequence elements in the target detection sequence whose detection direction is from bottom to top and whose operation type is write operation, a first write operation detection sequence is constructed. Based on the second sequence elements in the target detection sequence whose detection direction is from top to bottom and whose operation type is write operation, a second write operation detection sequence is constructed. The second write operation detection sequence is concatenated to the first write operation detection sequence to obtain the overall write operation detection sequence of the fault type to be detected; The overall write operation detection sequence includes multiple detection sequence elements, each detection sequence element includes multiple operation sequence elements, and each operation sequence element has a state value. The reassembly module is specifically used for: For each detection sequence element in the overall write operation detection sequence, determine the number of write operation sequence elements in the detection sequence element, wherein the write operation sequence elements are operation sequence elements with the operation type of write operation. When the number of elements is 1, two consecutive read operation sequence elements are inserted after the write operation sequence element to obtain the fault detection sequence to be optimized. The state values ​​of the two consecutive read operation sequence elements are the same as the state values ​​of the write operation sequence elements. The read operation sequence elements are operation sequence elements with the operation type of read operation. When the number of elements is 2, according to the state values ​​of the two write operation sequence elements, read operation sequence elements are inserted into the overall write operation detection sequence to obtain the fault detection sequence to be optimized. The step of performing a filtering process based on read operation sequence elements on the fault detection sequence to obtain the final fault detection sequence includes: According to the preset fault detection rules, read operation sequence elements that do not have fault detection function are filtered out from the fault detection sequence to be optimized to obtain the filtered detection sequence; Based on the position of the read operation sequence element in each target detection sequence, the element positions of the read operation sequence elements in the filtered detection sequence are adjusted to obtain the final fault detection sequence.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the memory fault detection method based on the target fault type as described in any one of claims 1 to 3.

Images