Methods for graphene layer growth and simultaneous molybdenum silicide formation on semiconductor devices

Abstract

Embodiments of the present disclosure relate to a method for graphene layer growth and simultaneous molybdenum silicide formation on a semiconductor device. A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode using the graphene layer forming method, and an optoelectronic semiconductor device also using the graphene layer forming method are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may also include promoting a graphene growth process on the exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms a graphene layer on the exposed surface of the one or more metal catalyst layer structures.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to graphene growth processes on semiconductor substrates, and more particularly to simultaneous graphene layer growth and molybdenum silicide formation on semiconductor devices. Background Art

[0002] Graphene has several unique properties that make it attractive for use in semiconductor technology. For example, graphene has high electron mobility, high thermal conductivity, is flexible and transparent, and resists degradation. However, the use of graphene in electronics is subject to several limitations, primarily the complexity associated with growing graphene directly onto semiconductor devices.

[0003] Applicants have identified many technical challenges and difficulties associated with growing graphene layers on semiconductor devices. Through unremitting efforts, ingenuity and innovation, applicants have solved the problems associated with growing graphene on semiconductor devices by developing the solutions embodied in the present disclosure, which will be described in detail below. Summary of the invention

[0004] Various embodiments relate to a method for forming a graphene layer on a semiconductor substrate, a semiconductor diode using the graphene layer forming method, and an optoelectronic semiconductor device using the graphene layer forming method.

[0005] An example method of providing a graphene layer on a semiconductor substrate is provided. In some embodiments, the example method includes depositing a metal catalyst layer on a top surface of the semiconductor substrate; patterning the metal catalyst layer so that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures; and promoting a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms a graphene layer on the exposed surface of the one or more metal catalyst layer structures.

[0006] In some embodiments, the semiconductor substrate includes silicon carbide.

[0007] In some embodiments, the metal catalyst layer forms a metal silicide, wherein one or more portions of the semiconductor substrate are covered by the one or more metal catalyst layer structures.

[0008] In some embodiments, the semiconductor substrate includes one or more contact points, wherein one or more of the one or more metal catalyst layer structures are patterned in alignment with the one or more contact points.

[0009] In some embodiments, the one or more contact points include an n-type or p-type semiconductor region having a low doping concentration, and the metal catalyst layer forms a Schottky contact between the graphene layer and the semiconductor substrate.

[0010] In some embodiments, the one or more contact points include an n-type or p-type semiconductor region having a high doping concentration, and the metal catalyst layer forms an ohmic contact between the graphene layer and the semiconductor substrate.

[0011] In some embodiments, the one or more metal catalyst layer structures are patterned such that during the graphene growth process, the entire one or more metal catalyst layer structures beneath the graphene layer are converted to metal silicide.

[0012] In some embodiments, the thickness of the metal catalyst layer is between 45 nanometers and 55 nanometers.

[0013] In some embodiments, the metal catalyst layer includes molybdenum.

[0014] In some embodiments, the metal catalyst layer includes nickel.

[0015] In some embodiments, the metal catalyst layer is deposited by sputtering.

[0016] In some embodiments, one or more metal catalyst layer structures are patterned using a metal etch photolithography process.

[0017] In some embodiments, the graphene growth process is facilitated using a chemical vapor deposition process that utilizes a carbon precursor.

[0018] In some embodiments, methane gas is used as a carbon precursor in a chemical vapor deposition process.

[0019] In some embodiments, during the chemical vapor deposition process, the metal catalyst layer is exposed to the carbon precursor for a duration between 600 seconds and 700 seconds.

[0020] An example semiconductor diode is further provided. In some embodiments, the example semiconductor diode includes a cathode terminal, the cathode terminal including a back ohmic contact adjacent to a first doped silicon substrate, wherein the first doped silicon substrate includes a first doping concentration of a first doping type. The example semiconductor diode also includes a drift layer, the drift layer including a second doped silicon substrate, wherein the second doped silicon substrate includes a second doping concentration of a second doping type. The example semiconductor diode also includes a Schottky contact adjacent to a top surface of the drift layer, opposite to the first doped silicon substrate, wherein the Schottky contact is formed by: depositing a metal catalyst layer on the top surface of the drift layer; patterning the metal catalyst layer so that one or more portions of the top surface of the drift layer are covered by one or more metal catalyst layer structures; and promoting a graphene growth process on an exposed surface of the one or more metal catalyst layer structures. In some embodiments, the graphene growth process forms a graphene layer on an exposed surface of the one or more metal catalyst layer structures, and the one or more metal catalyst layer structures are patterned so that during the graphene growth process, the entire one or more metal catalyst layer structures below the graphene layer are converted to metal silicide. In some embodiments, the example semiconductor diode further includes an anode terminal disposed on a top surface of the graphene layer, wherein a Schottky contact is formed between the graphene layer and the drift layer through a metal silicide, wherein the first doping type is the same as the second doping type, and wherein the first doping concentration is greater than the second doping concentration.

[0021] In some embodiments, the first doped silicon substrate and the second doped silicon substrate include silicon carbide.

[0022] In some embodiments, the metal catalyst layer includes molybdenum.

[0023] An example optoelectronic semiconductor device is further provided. In some embodiments, the example optoelectronic semiconductor device includes a graphene layer configured to collect photogenerated current from one or more photons. In some embodiments, the graphene layer is formed by depositing a metal catalyst layer on the top surface of a semiconductor substrate; patterning the metal catalyst layer so that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures; and promoting a graphene growth process on the exposed surfaces of the one or more metal catalyst layer structures. In some embodiments, the graphene growth process forms a graphene layer on the exposed surfaces of the one or more metal catalyst layer structures. In some embodiments, the one or more metal catalyst layer structures are patterned so that during the graphene growth process, the entire one or more metal catalyst layer structures below the graphene layer are converted into metal silicide. In some embodiments, the example optoelectronic semiconductor device also includes an anode terminal electrically contacting the graphene layer; a semiconductor diode junction electrically contacting the metal silicide on the top surface of the semiconductor diode junction; and a cathode terminal electrically contacting the semiconductor diode junction on the bottom surface opposite to the metal silicide. In some embodiments, where the graphene layer collects photogenerated current from one or more photons, the current flows from the anode terminal to the cathode terminal through the semiconductor diode junction.

[0024] In some embodiments, the semiconductor diode junction includes a first doped silicon substrate, wherein the first doped silicon substrate includes a first doping concentration of a first doping type; and a drift layer including a second doped silicon substrate. In some embodiments, the second doped silicon substrate includes a second doping concentration of a second doping type, wherein the first doping type is the same as the second doping type, the first doping concentration is greater than the second doping concentration, and the first doped silicon substrate and the drift layer include silicon carbide. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Reference will now be made to the drawings. The components shown in the drawings may or may not be present in certain embodiments described herein. According to example embodiments of the present disclosure, some embodiments may include fewer (or more) components than shown in the drawings.

[0026] Figure 1 A flowchart illustrating an example process for forming a graphene layer on a semiconductor substrate according to one or more embodiments of the present disclosure is shown;

[0027] Figure 2-Figure 4 A cross-sectional view illustrating an example process for forming a graphene layer on a semiconductor substrate according to one or more embodiments of the present disclosure;

[0028] Figure 5 An example process of graphene growth using a chemical vapor deposition process according to one or more embodiments of the present disclosure is shown;

[0029] Figure 6 Additional embodiments of a process for forming a graphene layer while catalyzing metal silicide formation according to one or more embodiments of the present disclosure are shown;

[0030] Figure 7 An example semiconductor diode utilizing a graphene layer formed according to one or more embodiments of the present disclosure is shown;

[0031] Figure 8 An example optoelectronic semiconductor device utilizing a graphene layer formed according to one or more embodiments of the present disclosure is shown;

[0032] Fig. 9 An example semiconductor device according to an example embodiment of the present disclosure is shown, showing an uneven top surface covered by a graphene layer and a metal silicide layer; and

[0033] Fig.10 An example semiconductor device showing an uneven top surface covered by a graphene layer is shown according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Example embodiments will be described more fully below with reference to the accompanying drawings, in which some but not all embodiments of the invention of the present disclosure are shown. In fact, embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. The same reference numerals refer to the same elements throughout.

[0035] As used herein, and in the examples provided below, terms such as "front," "rear," "back," "top," "vertical," "horizontal," "above," "below," "over," "below," and the like are used for explanation purposes to describe the relative position of certain components or component parts of an electrical device with respect to a local reference system using an arbitrary global reference system.

[0036] Various example embodiments solve technical problems associated with forming a graphene layer on a semiconductor device and simultaneously generating a metal silicide contact. As will be appreciated by those skilled in the art, there are many example scenarios where a user wishes to form a graphene layer on a semiconductor device. And other example scenarios where it is beneficial to simultaneously form a metal silicide contact during the formation of the graphene layer.

[0037] For example, graphene has several unique properties that make it attractive in semiconductor technology. In general, graphene is a single layer of carbon atoms formed into a tightly bound hexagonal lattice. Graphene has high electron and hole mobility to allow these molecules to increase freedom of movement, thereby obtaining better device performance. Graphene has excellent thermal properties in semiconductor devices, including high thermal conductivity along the plane and low thermal conductivity perpendicular to the plane. Therefore, the graphene layer in the semiconductor device can act as a thermal barrier. Graphene is flexible and transparent, which means that graphene can be used in applications that require transparent optical collectors, such as optoelectronic semiconductor devices. The transparent properties of graphene can also enable applications that require emitted light output, such as laser diodes. Graphene also has a high resistance to degradation, which enables graphene to be used as a protective layer on semiconductor devices.

[0038] However, the practicality of graphene electronic devices is subject to several limitations. The increase in the main limitation of the use of graphene in semiconductor devices is the complexity associated with growing graphene directly on the semiconductor substrate of the semiconductor device. Previous examples have attempted to grow graphene layers separately and mechanically transfer the graphene layers to the semiconductor substrate of the semiconductor device. Growing graphene alone enables the use of copper as a catalyst layer. Copper is very suitable as a basis for graphene growth, however, copper is characterized by high diffusivity in semiconductor materials, which is further caused by the presence of carbon. Therefore, since the high diffusivity of copper not only causes contamination, but also causes the crystal structure of the semiconductor substrate to degrade, copper cannot be brought into direct contact with the semiconductor substrate. In microelectronics manufacturing, mixing of copper and semiconductor materials must be avoided. Copper contamination changes the mobility characteristics of the underlying semiconductor material and has a negative impact on the operation of the semiconductor device. By growing graphene alone, copper contamination of semiconductor devices can be avoided.

[0039] In addition, growing graphene alone protects components of the semiconductor device from damage caused by high annealing temperatures. High annealing temperatures can be used to achieve the graphene growth process, especially on copper. High annealing temperatures may damage the underlying semiconductor components of the semiconductor device. Therefore, growing graphene alone and mechanically transferring the graphene can prevent exposing the semiconductor components to high annealing temperatures.

[0040] Unfortunately, the mechanical transfer of the graphene layer may be complicated, inaccurate, and cause the graphene layer to be damaged. For example, the transfer of the graphene layer may cause wrinkles, cracks or tears in the graphene layer. The damaged graphene layer may affect the beneficial properties of graphene. In addition, in some embodiments, the graphene layer is aligned with the underlying components of the semiconductor device. It may be difficult to align the graphene layer by mechanical transfer, and the resulting alignment may be inaccurate. In addition, once the graphene layer is placed, the polymethyl methacrylate (PMMA) layer used to help transfer the graphene layer may be dissolved. Dissolving the PMMA layer may damage the underlying semiconductor components and may move the graphene layer laterally, resulting in misalignment of the graphene layer. In addition, it is impossible to transfer the patterned graphene layer without error, especially when aligning features at the micrometer and / or nanometer scale.

[0041] Furthermore, the graphene layer grown separately on copper must be processed to avoid the presence of any copper after mechanical transfer, which contaminates the underlying semiconductor substrate and semiconductor device components.

[0042] Other examples have attempted to grow a graphene layer directly on a silicon carbide substrate or on a protective dielectric layer. Epitaxial growth of graphene on silicon carbide may require high temperatures, such as above 1600 degrees Celsius. Such temperatures may damage semiconductor components on a semiconductor device and require the use of a protective dielectric layer in some embodiments. The use of a protective dielectric layer prevents direct electrical connection of the graphene layer to the underlying semiconductor substrate.

[0043] Various embodiments of the present disclosure provide a process for growing a graphene layer on a semiconductor substrate such as silicon or silicon carbide using a catalyst metal layer and performing epitaxial growth by chemical vapor deposition.

[0044] As described herein, a process for growing graphene includes first depositing a metal catalyst layer on a semiconductor substrate. The metal catalyst layer can be deposited using a sputtering process. The metal catalyst can include, for example, molybdenum or nickel.

[0045] The process for growing graphene also includes patterning the metal catalyst layer. Patterning the metal catalyst layer can involve a well-known and reliable lithography process. The lithography process can include a photolithography process or any type of patterning method for creating micro- and nanostructures. In this way, the metal catalyst layer can be defined by etching or by a stripping process to form a metal catalyst layer structure aligned with the underlying semiconductor component. Graphene growth can be restricted so that graphene is only formed on the metal catalyst layer structure, so that graphene growth and alignment can occur in a single step.

[0046] The graphene growth process is continued by performing an epitaxial growth process such as chemical vapor deposition (CVD) to promote the growth of graphene on the deposited metal catalyst layer structure. The CVD process forms a material layer, such as a metal catalyst layer, on a support layer using molecular precursors introduced in gaseous form. The precursor for forming graphene on the metal catalyst can be, for example, methane gas, which is used as a carbon precursor. Using a metal catalyst layer such as molybdenum, the CVD process can be performed at 900 degrees Celsius or about 900 degrees Celsius, compared to a temperature of 1600 degrees Celsius when using a thermal growth process. In addition to forming graphene during CVD, the metal catalyst layer can be converted into a metal silicide by reacting with the silicon of the underlying substrate layer. For example, molybdenum can be converted into molybdenum silicide.

[0047] The technology described herein enables the metal catalyst layer to be structured so that the entire metal catalyst layer structure is converted to a silicide. This can be achieved by reducing the thickness of the metal catalyst layer and / or increasing the time of the CVD process. The conversion of the entire metal catalyst layer to a metal silicide can enable the formation of certain electrical contacts, such as Schottky contacts between a graphene layer and a lightly doped silicon or silicon carbide substrate, or ohmic contacts between a graphene layer and a heavily doped region of a silicon or silicon carbide substrate.

[0048] By utilizing a process involving growing a graphene layer on a metal catalyst layer using chemical vapor deposition, the complex process of mechanical transfer of a separately grown graphene layer, which results in inaccurate and inefficient graphene layers, is eliminated. In addition, the high temperatures required for thermal growth of graphene, which is detrimental to the manufacture of semiconductor devices, can be avoided.

[0049] Reference now Figure 1 , an example process 100 for providing a graphene layer on a semiconductor substrate is provided. At block 102, a metal catalyst layer is deposited on a top surface of a semiconductor substrate. The semiconductor substrate can be any semiconductor material on or in which components of a semiconductor device are fabricated or attached. The semiconductor substrate can include silicon, germanium, gallium arsenide, gallium nitride, silicon carbide (SiC), or other similar semiconductor materials. The components of the semiconductor device can be formed by doping, for example, via implantation, material deposition, masking, etching, epitaxial growth, sputtering, annealing, and other lithographic techniques.

[0050] Semiconductor substrates can be prepared from pure semiconductor material and grown into ingots. The semiconductor ingot can then be sliced ​​into wafers to facilitate the manufacture of one or more semiconductor devices. The sliced ​​wafers can be etched and polished to produce a surface (e.g., top surface) prepared for further semiconductor manufacturing operations.

[0051] One such semiconductor operation is the deposition of a metal, such as a metal catalyst layer. Metal deposition can be achieved by any process that deposits a metal starting material on the surface of a semiconductor substrate. Common techniques for depositing metals on semiconductor substrates include physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD can typically be achieved by sputtering or evaporation. CVD can typically be achieved by exposing the surface of a semiconductor substrate to one or more precursors that are configured to react and / or decompose on the surface of the substrate to produce a desired deposit.

[0052] The metal catalyst layer may include any metal material deposited on the surface of the semiconductor substrate without contaminating the semiconductor substrate. In addition, the metal catalyst layer includes a metal material configured to form a basis for CVD growth of graphene on the surface of the metal material and forming a silicide with the semiconductor substrate.

[0053] In box 104, the metal catalyst layer is patterned so that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The metal catalyst layer can be patterned using any photolithography patterning technique. Metal patterning techniques may include lift-off techniques, evaporation using a shadow mask, dry or wet etching techniques, or any other metal patterning techniques. Wet and / or dry etching techniques may include depositing a protective layer, such as a photoresist, on the surface of the metal catalyst layer, and patterning the protective layer to expose the surface of the metal catalyst layer to be etched. Wet etching techniques may include using an acid or chemical solution. Dry etching techniques may include chemical dry etching, such as plasma dry etching. Etching portions of the metal catalyst layer that are not protected by the protective layer causes a metal catalyst layer structure to be deposited on the top surface of the semiconductor substrate, the metal catalyst layer structure including the remaining portion of the metal catalyst layer.

[0054] The metal catalyst layer structure is any portion of the metal catalyst layer that remains on the surface of the semiconductor substrate and is configured to facilitate one or more functions of the semiconductor device. For example, on a transistor semiconductor device, the metal catalyst layer structure may include a drain, source, gate, or other electrical contact of the transistor. In a Schottky diode, the metal catalyst layer structure may include a metal portion connected to the anode of the Schottky diode. In some embodiments, the metal catalyst layer structure may be an electrical contact, such as an ohmic contact, between a contact pad and an underlying structure in the semiconductor substrate.

[0055] At block 106, a graphene growth process is promoted on the exposed surfaces of the one or more metal catalyst layer structures, wherein the graphene growth process forms a graphene layer on the exposed surfaces of the one or more metal catalyst layer structures. The graphene growth may be promoted on the exposed surfaces of the metal catalyst layer structures via CVD. The CVD process may be performed on the exposed surfaces of the metal catalyst layer structures. Figure 5 Further described. By utilizing the exposed surface of the patterned metal catalyst layer structure to promote the growth of graphene, the graphene is aligned with the metal catalyst layer structure, and thus with the underlying components of the semiconductor device, without the need for additional alignment steps.

[0056] Furthermore, during the graphene growth process, a portion of the metal catalyst layer is converted into metal silicide between the metal catalyst layer and the silicon substrate. Thus, the formation of the metal silicide occurs in synergy with the growth of graphene.

[0057] Reference now Figure 2-Figure 4 , provides an example process for providing a graphene layer on a semiconductor substrate according to an example embodiment of the present disclosure. Figure 2 , an example semiconductor device 200 is provided. Figure 2 As shown, the example semiconductor device 200 includes a semiconductor substrate 202 having a top surface 206 and a metal catalyst layer 204 disposed adjacent to the top surface 206 of the metal catalyst layer 204 .

[0058] like Figure 2 As shown, semiconductor device 200 includes semiconductor substrate 202. As described herein, semiconductor substrate 202 may be any semiconductor material on which or into which components of a semiconductor device are fabricated or attached. Figure 2 As shown, semiconductor substrate 202 includes silicon carbide. SiC substrates can produce many benefits, especially in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more tolerant to higher frequencies, have low reverse leakage current and power consumption, be more stable over a wide temperature range, have lower electromagnetic radiation, and provide other related advantages.

[0059] like Figure 2 As further shown, a metal catalyst layer 204 is deposited on the top surface 206 of the semiconductor substrate 202. The metal catalyst layer 204 can be deposited using any metallization technique that enables the catalyst metal to be uniformly deposited on the top surface 206 of the semiconductor substrate 202, for example, a sputtering technique. Sputtering is a form of PVD that can be used to deposit a thin metal layer on the semiconductor substrate 202. In sputtering, a source metal material can be placed in a vacuum chamber with the semiconductor substrate 202. A sputtering gas can be used to bombard the source, causing particles of the source metal material to escape and be deposited on the surface of the semiconductor substrate 202. Sputtering can deposit a layer of material (e.g., a metal catalyst layer 204) on the surface of the semiconductor substrate 202.

[0060] In some embodiments, the metal catalyst layer 204 includes molybdenum. Molybdenum provides a base surface for uniform graphene growth. Molybdenum is a particularly effective substrate for graphene growth for many reasons. First, molybdenum can make graphene grow uniformly over a large area. Molybdenum also has a high melting point of about 2600 degrees Celsius, so that the metal catalyst layer 204 can withstand high temperatures. Simple solutions such as hydrogen peroxide (H2O2) and nitric acid (HNO3) can be used to further etch the metal catalyst layer 204 including molybdenum. In addition, during graphene growth, the use of molybdenum as a metal catalyst layer promotes the formation of metal silicide between the semiconductor substrate 202 (SiC) and the metal catalyst layer 204 (molybdenum). The formation of metal silicide results in a mechanically and chemically stable layer and optoelectronic contact between graphene and the semiconductor substrate 202. In some embodiments, the metal catalyst layer 204 includes nickel.

[0061] Reference now Figure 3 , further depicting the semiconductor device 200, wherein the metal catalyst layer 204 has been etched to form one or more metal catalyst layer structures 308 on the top surface 206 of the semiconductor substrate 202. In addition, one or more exposed surfaces 310 of the metal catalyst layer structures 308 are exposed to the external environment.

[0062] like Figure 3 As shown, semiconductor device 300 includes one or more metal catalyst layer structures 308. As described herein, patterning metal catalyst layer 204 to form metal catalyst layer structure 308 can be achieved using any photolithographic patterning technique, such as a metal etching photolithography process using a wet etching technique. In some embodiments, a patterned protective layer or mask can be applied to the surface of metal catalyst layer 204. The patterned protective mask can protect areas of metal catalyst layer 204 from the etchant while defining exposed areas of metal to be etched or removed. Figure 3 In the example shown, where the metal catalyst layer 204 includes molybdenum, various etching techniques can be used to remove portions of the metal catalyst layer 204 that are not protected by the patterned protective mask. For example, stripping resist patterning, sputtering and resist stripping, evaporation and resist stripping, wet etching techniques using etchants such as hydrogen peroxide and nitric acid, dry etching techniques, shadow mask and evaporation techniques, etc. Once etching is complete, the patterned protective mask can be removed, leaving the metal catalyst layer structure 308.

[0063] As described herein, the metal catalyst layer structure 308 may include any conductive structure that performs the function of the semiconductor device 300. For example, in some embodiments, the metal catalyst layer structure 308 may perform the function of an active layer of a transistor on the semiconductor device 300, such as on a graphene field effect transistor. By placing the metal catalyst layer structure 308 and subsequently forming a graphene layer between the source and drain of the transistor, the transistor may exhibit exceptional thermal and conductive properties, including lower resistive losses and better heat dissipation compared to silicon.

[0064] Reference now Figure 4 , another embodiment of an exemplary semiconductor device 400 is provided. Figure 4 As shown, the example semiconductor device 400 includes a graphene layer 412 formed on the exposed surface 310 of the metal catalyst layer structure 308. In addition, a metal silicide layer 414 is formed between the top surface 206 of the semiconductor substrate 202 and the metal catalyst layer structure 308.

[0065] The graphene layer 412 is formed on the exposed surface 310 of the metal catalyst layer structure 308 using a CVD process. Figure 5 An example CVD process 500 is shown. Figure 5 , the example CVD process 500 is configured to expose a semiconductor device 506 to one or more precursor gases 502a - 502c at elevated temperatures provided by one or more furnaces.

[0066] like Figure 5 As shown, a semiconductor device 506 (e.g., semiconductor device 300) can be placed in a reaction chamber 508. The reaction chamber 508 includes a gas inlet 504 configured to carry a precursor gas 502 and one or more carrier gases 516a-516b into the reaction chamber 508. The reaction chamber 508 also includes a gas outlet 510 configured to generate a gas flow through the reaction chamber 508 so that the precursor gas 502 can continue to react with the exposed surface of the semiconductor device 506 and remove volatile byproducts of the CVD process 500.

[0067] In addition, a vacuum is created in the reaction chamber 508, and the temperature is elevated by one or more furnaces 512. The vacuum created by the reaction chamber 508 and the elevated temperature created by the furnaces 512 create an environment in which, when reacting with the precursor gas 502, a graphene layer (e.g., Figure 4 The graphene layer 412 as shown may be grown on the exposed surface 310 of the metal catalyst layer structure 308 on the semiconductor device 506 .

[0068] In some embodiments, the pressure in the reaction chamber 508 can be controlled, for example, in some embodiments, a low pressure chemical vapor deposition (LPCVD) technique can be used. The reduced pressure in the reaction chamber 508 can reduce undesirable gas reactions and can increase the uniformity of deposition on the semiconductor device 506. In some embodiments, the pressure of the reaction chamber 508 can be maintained between 1 mbar and 15 mbar; preferably between 1.5 mbar and 12.5 mbar; more preferably between 2 mbar and 10 mbar.

[0069] like Figure 5 As further shown, the example CVD process 500 includes releasing a precursor gas 502 into a reaction chamber 508. The precursor gas 502 may include any gas or combination of gases including a carbon precursor that forms a graphene layer (e.g., graphene layer 412) when exposed to the surface of the metal catalyst layer 204 of the semiconductor device 506. In some embodiments, the carbon precursor gas 502 may include methane gas. In some embodiments, the CVD process 500 may also include releasing carrier gases 516a-516b into the reaction chamber 508. The carrier gases 516a-516b may enhance the surface reaction of graphene on the surface of the metal catalyst layer structure 308. In some embodiments, the carrier gases 516a-516b may include hydrogen, argon, acetylene, other carbon gases, or combinations thereof.

[0070] like Figure 5 As shown, the release of the precursor gas 502 and one or more carrier gases 516a-516b is controlled by one or more mass flow controllers (MFCs) 518. Further control of the concentration of the precursor gas 502 and the carrier gases 516a-516b can be controlled by one or more valves 514, which are used to control the flow of gases from the precursor gas source 502 and the carrier gas source 516a-516b into the reaction chamber 508 through the gas inlet 504.

[0071] In some embodiments, the temperature of reaction chamber 508 is heated to a range between 800 degrees Celsius and 1000 degrees Celsius; preferably between 850 degrees Celsius and 950 degrees Celsius; more preferably between 875 degrees Celsius and 925 degrees Celsius. In some embodiments, semiconductor device 506 is exposed to precursor gas 502 for a duration between 550 seconds and 750 seconds; preferably between 575 seconds and 725 seconds; more preferably between 600 seconds and 700 seconds.

[0072] return Figure 4, the example semiconductor device 400 also includes a metal silicide layer 414. The metal comprising the metal catalyst layer structure 308 is selected so that during the CVD process, the metal catalyst layer structure 308 forms a metal silicide with the semiconductor substrate 202, thereby enabling the growth of graphene. In the presence of heat, the metal silicide can be formed at the contact surface between the semiconductor substrate 202 and the metal catalyst layer structure 308. For example, atoms of the metal catalyst layer structure 308 can diffuse through the boundaries of the metal catalyst layer structure 308 and fuse with particles of the semiconductor substrate 202. The metal silicide exhibits reduced contact resistance, thereby enabling the improvement of the performance of electrical contacts within the semiconductor device 400. In addition, the metal silicide can withstand high temperatures, enabling its use on high temperature electrical devices.

[0073] In some embodiments, the metal catalyst layer structure 308 may include molybdenum. In such embodiments, the metal catalyst layer structure 308 may be combined with the silicon or silicon carbide semiconductor substrate 202 to form molybdenum disilicide (MoSi2) with different stoichiometries. x Si y ) or another molybdenum silicide. In some embodiments, the metal catalyst layer structure 308 may include nickel. In such an embodiment, the metal catalyst layer structure 308 may be combined with the silicon or silicon carbide semiconductor substrate 202 to form nickel silicide (Ni x Si y ) or another nickel silicide with a different stoichiometry.

[0074] Reference now Figure 6 , an example semiconductor device 600 is provided. Figure 6 As shown, the semiconductor device 600 includes a metal silicide layer 414 disposed on the top surface 206 of the semiconductor substrate 202. In addition, a graphene layer is disposed on all exposed surfaces 310 of the metal silicide layer 414.

[0075] like Figure 6 As shown, the example semiconductor device 600 includes a metal silicide layer 414 formed during the graphene growth process, the metal silicide layer being in direct contact with the graphene layer 412 and the semiconductor substrate 202. Figure 3 As shown, the metal catalyst layer structure 308 is patterned on the surface of the semiconductor substrate 202. Based on the thickness of the metal catalyst layer structure 308 and the duration and temperature of the graphene growth process, the entire metal catalyst layer structure 308 can be converted into metal silicide, such as Figure 6 For example, in the case where the metal catalyst layer structure 308 includes molybdenum, the entire metal catalyst layer structure 308 can be converted into molybdenum silicide (Mo silicide) during the graphene growth process. x Si yAlternatively, in the case where the metal catalyst layer structure 308 includes nickel, the entire metal catalyst layer structure 308 may be converted to nickel silicide (Ni silicide) during the graphene growth process. x Si y ).

[0076] In some embodiments, the metal catalyst layer 204 and the metal catalyst layer structure 308 can be formed so that the entire metal catalyst layer structure 308 is converted into a metal silicide layer 414 during the graphene growth process. For example, in some embodiments, the metal catalyst layer 204 can be deposited with a uniform thickness on the top surface 206 of the semiconductor substrate 202 using a metallization technique (e.g., sputtering). In some embodiments, the thickness of the metal catalyst layer 204 can be between 35 nanometers and 65 nanometers; preferably between 40 nanometers and 60 nanometers; more preferably between 45 nanometers and 55 nanometers. Depositing the metal catalyst layer 204 with such a thickness can enable the entire resulting metal catalyst layer structure 308 to be converted into silicide, thereby forming a metal silicide layer 414.

[0077] Furthermore, in some embodiments, Figure 5 As described above, the temperature and duration of the graphene growth process can partially affect the conversion of the metal catalyst layer structure 308 to a silicide. For example, in some embodiments, the temperature of the reaction chamber (e.g., reaction chamber 508) during the graphene growth process can be between 875 degrees Celsius and 925 degrees Celsius. In addition, the semiconductor device can be exposed to the precursor and the carrier gas for 600 seconds to 700 seconds. In combination with the thickness of the metal catalyst layer structure 308, the conditions present during the graphene growth process can convert the entire metal catalyst structure 308 into a metal silicide layer.

[0078] Converting the entire metal catalyst layer structure 308 to metal silicide places the graphene layer in direct contact with the metal silicide layer 414, which in turn contacts the semiconductor substrate 202. The metal silicide layer 414 that creates an electrical contact (e.g., a contact point) between the graphene layer 412 and the semiconductor substrate can provide a number of benefits. As described herein, the metal silicide layer 414 contact exhibits reduced contact resistance compared to metal semiconductor contacts. In addition, the metal silicide layer 414 contact achieves sustained performance at high temperatures. In addition, as described with respect to Figure 7As described, the metal silicide layer 414 contact can be used as a passive layer in a semiconductor device, thereby providing a Schottky contact between graphene and a semiconductor substrate. In addition, the metal silicide layer 414 can provide an ohmic contact between a metal layer (e.g., graphene layer 412) of a semiconductor device and a semiconductor substrate. Ohmic contact is based on the work function of metal and semiconductor. For example, for metal and n-type semiconductors, when the metal work function is less than or equal to the semiconductor work function, an ohmic contact is formed. Similarly, for metal and p-type semiconductors, when the metal work function is greater than or equal to the semiconductor work function, an ohmic contact is formed. Therefore, in a highly doped semiconductor, since the Fermi level is located near the conduction band and valence band of n-type and p-type semiconductors, respectively, it is easier to form an ohmic contact than in a low-doped semiconductor. Compared with metal contacts, metal silicide contacts form more stable contacts (both ohmic contacts or Schottky contacts). In some embodiments, when the region of the semiconductor substrate 202 contacting the metal catalyst layer structure 308 is a p-type semiconductor having a high doping concentration, an ohmic contact may be formed between the graphene layer 412 and the semiconductor substrate 202 .

[0079] Reference now Figure 7 , an example Schottky diode semiconductor device 700 is provided. Figure 7 As shown, the example Schottky diode semiconductor device 700 includes a semiconductor drift layer 770 on top of a semiconductor substrate 702. As further shown, a metal silicide Schottky contact 714 is disposed on top of the semiconductor drift layer 770, and an electrical contact is formed between the semiconductor drift layer 770 and a graphene layer 712 disposed on top of the metal silicide Schottky contact 714. On the top surface of the graphene layer 712, an anode terminal 774 is disposed. In addition, an ohmic contact is formed at a cathode terminal 772 (e.g., a backside ohmic contact) on the bottom surface of the semiconductor substrate 702.

[0080] like Figure 7 As shown, the example Schottky diode semiconductor device 700 includes a semiconductor substrate 702. The semiconductor substrate 702 (e.g., a wafer) can be any semiconductor material used as a base layer of a semiconductor component (e.g., Schottky diode semiconductor device 700). In some embodiments, the semiconductor substrate 702 can include silicon, silicon carbide (SiC), or other similar semiconductor materials. SiC substrates can provide many advantages in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more tolerant at higher frequencies, have low reverse leakage current and power dissipation, be more stable over a wide temperature range, have lower electromagnetic radiation, and provide other related advantages.

[0081] In some embodiments, the semiconductor substrate 702 may be doped with a first dopant type to produce a semiconductor having a particular conductivity type, such as an n-type dopant. A dopant may be any impurity that is intentionally added to a semiconductor to change the conductivity of the semiconductor. Adding a dopant to the semiconductor substrate 702 having extra valence electrons produces a semiconductor having n-type doping or an n-doped semiconductor. Dopants having extra valence electrons may include phosphorus, arsenic, antimony, etc. Alternatively, adding a dopant to the semiconductor substrate 702 lacking valence electrons produces a semiconductor having p-type doping or a p-doped semiconductor. Dopants lacking valence electrons may include boron, aluminum, gallium, etc. As Figure 7 As shown, the semiconductor substrate 702 of the example Schottky diode semiconductor device 700 is an n-type semiconductor substrate 702 .

[0082] In some embodiments, the semiconductor substrate 702 may include a doping concentration. The doping concentration may refer to the number of impurities introduced into the structure of the semiconductor substrate 702 relative to the number of intrinsic semiconductor atoms. A high doping concentration means that a greater number of impurities are introduced into the semiconductor substrate 702 relative to the number of intrinsic semiconductor atoms. In some embodiments, the doping concentration of the semiconductor substrate 702 may be higher than the doping concentration of the semiconductor drift layer 770. Figure 7 As shown, the semiconductor substrate 702 includes a high doping concentration of n-type dopants compared to the semiconductor drift layer 770 .

[0083] like Figure 7 As further shown, the example Schottky diode semiconductor device 700 includes a semiconductor drift layer 770. The semiconductor drift layer 770 can be any semiconductor material configured to enable current to flow from the graphene layer 712 to the cathode terminal 772 due to drift of majority carriers. When the barrier voltage of the Schottky diode semiconductor device 700 is exceeded, the semiconductor drift layer 770 enables current to flow from the graphene layer 712 to the cathode terminal 772. In addition, the semiconductor drift layer 770 blocks or limits the flow of current in the opposite direction, such as from the cathode terminal 772 to the anode terminal. Figure 7 As shown, the semiconductor drift layer 770 and the semiconductor substrate 702 have the same dopant type, for example, n-type semiconductor. Figure 7 As further shown, the semiconductor drift layer 770 has a lower doping concentration than the semiconductor substrate 702 .

[0084] like Figure 7As further shown, the example Schottky diode semiconductor device 700 includes a graphene layer 712. The graphene layer 712 is a layer through which current enters the Schottky diode semiconductor device 700, or equivalently, a layer through which electrons leave the Schottky diode semiconductor device 700. The portion of the graphene layer 712 that contacts the top surface of the semiconductor drift layer 770 forms a metal silicide Schottky contact 714 between the graphene layer 712 and the semiconductor drift layer 770. The metal silicide Schottky contact 714 can be any semiconductor diode formed by a junction of a semiconductor and a metal. In general, the metal silicide Schottky contact 714 combines a low voltage drop characteristic with negligible recovery. Therefore, the metal silicide Schottky contact 714 is less likely to overheat at high voltages, can allow current to be transmitted with higher efficiency, and can perform well at high frequencies.

[0085] like Figure 7 As further shown, the example Schottky diode semiconductor device 700 also includes a cathode terminal 772 (e.g., an ohmic contact). The cathode terminal 772 can be any conductive material (e.g., back metal) through which current leaves the Schottky diode semiconductor device 700, or equivalently, through which electrons enter the Schottky diode semiconductor device 700. In some embodiments, the cathode terminal 772 can include a metal or a combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the cathode terminal 772 can be disposed below the semiconductor substrate 702 and adjacent to the bottom surface of the semiconductor substrate 702.

[0086] like Figure 7 As further shown, the example Schottky diode semiconductor device 700 includes an anode terminal 774. The anode terminal 774 can be any conductive surface configured to provide an electrical connection to the graphene layer 712 of the Schottky diode semiconductor device 700. The anode terminal 774 can include any conductive material, including gold, copper, aluminum, or other similar materials. The anode terminal 774 provides a contact point to an external source through which current enters the Schottky diode semiconductor device 700, or equivalently, through which electrons leave the Schottky diode semiconductor device 700.

[0087] Due to the effective carrier collection and in-plane transport of the graphene layer 712, the physical size of the anode terminal 774 can be reduced. For example, a thinner metal layer can be used compared to a non-graphene layer. In addition, using the technology described herein, the graphene layer 712 can be aligned with the underlying features of the Schottky diode semiconductor device 700 during the graphene growth process. In addition, using the graphene layer 712 as a passive layer in the Schottky diode semiconductor device 700 can obtain a higher performance Schottky diode semiconductor device 700, especially in high-power applications. In addition, the graphene layer 712 provides a protective layer that can prevent oxidation, ion diffusion, or other destructive conditions caused by the surrounding environment. Therefore, electronic devices using a graphene layer (e.g., a graphene layer 712) can be used in environments that are usually harsh for electronic devices.

[0088] Reference now Figure 8 , an example optoelectronic semiconductor device 800 is provided. Figure 8 As shown, the exemplary optoelectronic semiconductor device 800 includes a semiconductor drift layer 870 on top of a semiconductor substrate 802. As further shown, a metal silicide contact 814 is disposed on top of the semiconductor drift layer 870, and an electrical contact is formed between the semiconductor drift layer 870 and a graphene layer 812 disposed on top of the metal silicide contact 814. On the top surface of the graphene layer 812, an anode terminal 874 is disposed. In addition, an ohmic contact (e.g., a backside ohmic contact) is formed at a cathode terminal 872 on the bottom surface of the semiconductor substrate 802. As shown in FIG. Figure 8 As further shown, the graphene layer 812 may be exposed to photons 880 from an external environment.

[0089] like Figure 8 As shown, the exemplary optoelectronic semiconductor device 800 includes a semiconductor substrate 802. Figure 7 As described, semiconductor substrate 802 (eg, wafer) may be any semiconductor material used as a base layer of a semiconductor component (eg, optoelectronic semiconductor device 800). In some embodiments, semiconductor substrate 802 may include silicon, silicon carbide (SiC), or other similar semiconductor materials.

[0090] In some embodiments, the semiconductor substrate 802 may be doped with a first dopant type to produce a semiconductor having a specific conductivity type. Figure 8 As shown, the semiconductor substrate 802 of the example optoelectronic semiconductor device 800 is an n-type semiconductor substrate 802 .

[0091] In some embodiments, the semiconductor substrate 802 may include a doping concentration of . Figure 8 As shown, the semiconductor substrate 802 includes a high doping concentration of n-type dopants compared to the semiconductor drift layer 870 .

[0092] like Figure 8 As further shown, the exemplary optoelectronic semiconductor device 800 includes a semiconductor drift layer 870. Figure 7 As described above, the semiconductor drift layer 870 can be any semiconductor material configured to enable current to flow from the graphene layer 812 to the cathode terminal 872 due to the drift of the majority carriers. When the barrier voltage of the optoelectronic semiconductor device 800 is exceeded, the semiconductor drift layer 870 enables current to flow from the graphene layer 812 to the cathode terminal 872. In addition, the semiconductor drift layer 870 blocks or limits the flow of current in the opposite direction, for example, from the cathode terminal 872 to the anode terminal. Figure 8 As shown, the semiconductor drift layer 870 and the semiconductor substrate 802 have the same dopant type, for example, n-type semiconductor. Figure 8 As further shown, the semiconductor drift layer 870 has a lower doping concentration than the semiconductor substrate 802 .

[0093] like Figure 8 As further shown, the example optoelectronic semiconductor device 800 includes a graphene layer 812. Due to the high conductivity and transparency of the graphene layer 812, the graphene layer 812 can be used as a transparent conductive electrode to enable optical collection of photons 880 and charge collection from the optoelectronic semiconductor device 800. Many semiconductor devices, including photodiodes and solar cells, convert received optical photons 880 into electrical signals. The graphene layer 812 can be used as a transparent conductive electrode in any situation that benefits from a low resistance electrical contact that does not block light.

[0094] Additionally, due to the transparency of the graphene layer 812, photons 880 can be emitted from the graphene layer 812. For example, a laser diode, a vertical cavity surface emitting laser (VCSEL), or other light source can utilize the graphene layer 812 as a transparent conductive electrode to allow an electronic device to collect current and emit photons 880.

[0095] like Figure 8 As further shown, the example optoelectronic semiconductor device 800 also includes a cathode terminal 872 (e.g., a back-end contact pad). The cathode terminal 872 can be any conductive material through which current leaves the optoelectronic semiconductor device 800, or equivalently, through which electrons enter the optoelectronic semiconductor device 800. In some embodiments, the cathode terminal 872 can include a metal or a combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the cathode terminal 872 can be disposed below the semiconductor substrate 802 and adjacent to the bottom surface of the semiconductor substrate 802.

[0096] like Figure 8As further shown, the example optoelectronic semiconductor device 800 includes an anode terminal 874. The anode terminal 874 (e.g., a front contact pad) can be any conductive surface configured to provide an electrical connection to the graphene layer 812 of the optoelectronic semiconductor device 800. The anode terminal 874 can include any conductive material, including gold, copper, aluminum, or other similar materials. In some embodiments of the optoelectronic semiconductor device 800, the anode terminal 874 provides a contact point to an external load, to which current can be provided when photons 880 are received and transmitted into electrical energy.

[0097] Reference now Fig. 9 , another embodiment of an exemplary semiconductor device 900 having an uneven top surface 902 is provided. Fig. 9 As shown, the example semiconductor device 900 includes a graphene layer 412 formed on an exposed surface 310 of a metal catalyst layer 204. A metal silicide layer 414 is formed between the uneven top surface 902 of the semiconductor substrate 202 and the metal catalyst layer 204.

[0098] The production of graphene layers using mechanical transfer techniques is not effective on uneven top surfaces such as Fig. 9 The uneven top surface 902 is shown. However, using the techniques described herein, by Figure 5 The CVD process described deposits the graphene layer 412 on the uneven top surface 902. Using the techniques described herein, the graphene layer 412 is not only isolated from the portion on the exposed surface 310 of the metal silicide layer 414, but the graphene layer 412 can also be formed on various trenches and voids on the uneven top surface 902 of the semiconductor substrate 202.

[0099] like Fig. 9 As further shown, the example semiconductor device 900 further shows a metal silicide layer 414 formed between the metal catalyst layer 204 and the graphene layer 412 on the uneven top surface 902 of the semiconductor substrate 202. The metal silicide layer 414 exhibits reduced contact resistance, enabling improved performance of electrical contacts within the semiconductor device 900. In addition, the metal silicide layer 414 is able to withstand high temperatures, thereby enabling use on high temperature electrical devices.

[0100] Reference now Fig.10 , an example semiconductor device 1000 having an uneven top surface 902 is provided. Fig.10 As shown, the semiconductor device 1000 includes a metal silicide layer 414 disposed on the uneven top surface 902 of the semiconductor substrate 202. In addition, a graphene layer is disposed on all exposed surfaces 310 of the metal silicide layer 414.

[0101] like Fig.10 As shown, the example semiconductor device 1000 includes a metal silicide layer 414 that is formed during the graphene growth process and is in direct contact with the graphene layer 412 and the uneven top surface 902 of the semiconductor substrate 202. As described herein, various methods involving mechanical transfer techniques for producing a graphene layer are not feasible on the uneven top surface 902 of the semiconductor substrate 202. However, using various embodiments of the present disclosure described herein, by Figure 5 The CVD process described deposits the graphene layer 412 on the uneven top surface 902. Using the techniques described herein, the graphene layer 412 can be formed on various channels and voids on the uneven top surface 902 of the semiconductor substrate 202.

[0102] As described herein, based on the thickness of the metal catalyst layer and the duration and temperature of the graphene growth process, the entire metal catalyst layer can be converted into a metal silicide layer 414, such as Fig.10 For example, in the case where the metal catalyst layer includes molybdenum, the entire metal catalyst layer can be converted into molybdenum silicide (Mo silicide) during the graphene growth process. x Si y Alternatively, in the case where the metal catalyst layer includes nickel, the entire metal catalyst layer may be converted to nickel silicide (Ni silicide) during the graphene growth process. x Si y ).

[0103] Converting the entire metal catalyst layer to a metal silicide layer 414 establishes a silicide contact between the graphene layer 412 and the semiconductor substrate 202. The metal silicide layer 414 that creates an electrical contact (e.g., a contact point) between the graphene layer 412 and the semiconductor substrate can provide many benefits. As described herein, the metal silicide layer 414 contact exhibits reduced contact resistance compared to metal semiconductor contacts. In addition, the metal silicide layer 414 contact achieves sustained performance at high temperatures.

[0104] Although this detailed description describes some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements. For example, those skilled in the art will recognize that such principles can be applied to any electronic or optoelectronic device that utilizes semiconductor devices that need to withstand high temperatures, high power and / or high frequencies. For example, diodes and Schottky diodes in high-power electronic devices; solar panels, photodiodes, and other devices configured to convert photons into electrical energy; and so on.

[0105] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted under 35 U.S.C. § 112, paragraph 6.

[0106] The use of broader terms such as "comprises," "includes," and "having" should be understood to support narrower terms such as "consisting of," "consisting essentially of," and "consisting essentially of." The use of the terms "optionally," "may," "might," "possibly," and the like with respect to any element of an embodiment means that the element is not required, or, alternatively, the element is required. Both alternatives are within the scope of the embodiments. Furthermore, references to examples are provided for illustrative purposes only and are not exclusive.

Claims

1. A method for providing a graphene layer on a semiconductor substrate, the method comprising: depositing a metal catalyst layer on a top surface of the semiconductor substrate; patterning the metal catalyst layer so that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures; as well as promoting a graphene growth process on the exposed surfaces of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures. The method of claim 1 , wherein the semiconductor substrate comprises silicon carbide. 3 . The method of claim 2 , wherein the metal catalyst layer forms a metal silicide, wherein the one or more portions of the semiconductor substrate are covered by the one or more metal catalyst layer structures.

4. The method of claim 3, wherein the semiconductor substrate comprises one or more contact points, and One or more of the one or more metal catalyst layer structures are patterned in alignment with the one or more contact points.

5. The method of claim 4, wherein the one or more contact points comprise an n-type or p-type semiconductor region having a low doping concentration, and The metal catalyst layer forms a Schottky contact between the graphene layer and the semiconductor substrate.

6. The method of claim 4, wherein the one or more contact points comprise an n-type or p-type semiconductor region having a high doping concentration, and The metal catalyst layer forms an ohmic contact between the graphene layer and the semiconductor substrate.

7. The method of claim 3, wherein the one or more metal catalyst layer structures are patterned such that during the graphene growth process, the entire one or more metal catalyst layer structures below the graphene layer are converted into the metal silicide.

8. The method according to claim 7, wherein the thickness of the metal catalyst layer is between 45 nanometers and 55 nanometers.

9. The method of claim 1, wherein the metal catalyst layer comprises molybdenum.

10. The method of claim 1, wherein the metal catalyst layer comprises nickel. The method of claim 1 , wherein the metal catalyst layer is deposited by sputtering.

12. The method of claim 1, wherein the one or more metal catalyst layer structures are patterned using a metal etch lithography process.

13. The method of claim 1, wherein the graphene growth process is facilitated using a chemical vapor deposition process, and The chemical vapor deposition process described herein utilizes a carbon precursor.

14. The method of claim 13, wherein methane gas is used as the carbon precursor during the chemical vapor deposition process.

15. The method of claim 14, wherein during the chemical vapor deposition process, the metal catalyst layer is exposed to the carbon precursor for a duration between 600 seconds and 700 seconds.

16. A semiconductor diode, comprising: a cathode terminal comprising a backside ohmic contact adjacent to the first doped silicon substrate, wherein the first doped silicon substrate comprises a first doping concentration of a first doping type; A drift layer including a second doped silicon substrate, wherein the second doped silicon substrate comprises a second doping concentration of a second doping type; a Schottky contact adjacent to a top surface of the drift layer and opposite to the first doped silicon substrate, The Schottky contact is formed by: depositing a metal catalyst layer on the top surface of the drift layer; patterning the metal catalyst layer so that one or more portions of the top surface of the drift layer are covered by one or more metal catalyst layer structures; as well as promoting a graphene growth process on the exposed surfaces of the one or more metal catalyst layer structures, wherein the graphene growth process forms a graphene layer on the exposed surfaces of the one or more metal catalyst layer structures, and wherein the one or more metal catalyst layer structures are patterned such that during the graphene growth process, the entire one or more metal catalyst layer structures beneath the graphene layer are converted into metal silicide; as well as an anode terminal disposed on a top surface of the graphene layer, wherein the Schottky contact is formed between the graphene layer and the drift layer through the metal silicide, wherein the first doping type is the same as the second doping type, and The first doping concentration is greater than the second doping concentration. 17 . The semiconductor diode of claim 16 , wherein the first doped silicon substrate and the second doped silicon substrate comprise silicon carbide.

18. The semiconductor diode of claim 16, wherein the metal catalyst layer comprises molybdenum.

19. An optoelectronic semiconductor device, comprising: A graphene layer configured to collect photocurrent from one or more photons, wherein the graphene layer is formed by: depositing a metal catalyst layer on a top surface of the semiconductor substrate; patterning the metal catalyst layer so that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures; as well as promoting a graphene growth process on the exposed surfaces of the one or more metal catalyst layer structures, wherein the graphene growth process forms a graphene layer on the exposed surfaces of the one or more metal catalyst layer structures, and wherein the one or more metal catalyst layer structures are patterned such that during the graphene growth process, the entire one or more metal catalyst layer structures beneath the graphene layer are converted into metal silicide; an anode terminal in electrical contact with the graphene layer; a semiconductor diode junction in electrical contact with the metal silicide on a top surface of the semiconductor diode junction; as well as a cathode terminal in electrical contact with the semiconductor diode junction on a bottom surface opposite the metal silicide; Wherein, in the case where the graphene layer collects the photogenerated current from the one or more photons, current flows from the anode terminal to the cathode terminal through the semiconductor diode junction.

20. The optoelectronic semiconductor device of claim 19, wherein the semiconductor diode junction comprises: A first doped silicon substrate, wherein the first doped silicon substrate comprises a first doping concentration of a first doping type; as well as A drift layer including a second doped silicon substrate, wherein the second doped silicon substrate comprises a second doping concentration of a second doping type; wherein the first doping type is the same as the second doping type, wherein the first doping concentration is greater than the second doping concentration, and The first doped silicon substrate and the drift layer include silicon carbide.

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