Position determination method and device of ion implantation structure, equipment and medium

Abstract

The invention relates to an ion implantation structure position determination method and device, equipment and a medium, and the position of each ion implantation structure is determined through the following steps: obtaining a first distance value and a second distance value of the two sides of the ion implantation structure and the current electrical data of a memory; determining the position offset direction of the ion implantation structure according to the difference value between the current electrical data and the target electrical data of the memory; and adjusting the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure so as to enable the electrical data of the memory to reach the target electrical data. At least after the structure size of the SRAM is reduced, the correct position of the ion implantation structure can be accurately determined, and the performance of the SRAM is ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and detection, and in particular to a method, device, equipment and medium for determining the position of an ion implantation structure. Background Art

[0002] Static random access memory (SRAM) is widely used due to its low voltage operation and high speed. Among them, the SRAM structure with 6T (6 transistors) as a storage unit is the most common (such as Figure 1 The 6T-SRAM layout consists of three types of MOS including PU, PD, and PG, among which two PMOS form PU and four NMOS form PD and PG.

[0003] The structure of a static random access memory (SRAM) memory includes an ion implantation structure (AA), a polysilicon layer (POLY), and a metal wiring layer, wherein the ion implantation structure and the polysilicon layer are used to define transistors. Therefore, the setting of the formation position of the ion implantation structure is more important.

[0004] With the improvement of etching accuracy, the structural size of random access static memory (SRAM) memory has been reduced again and again. In the actual etching process of the ion implantation structure, after reducing the structural size of the random access static memory (SRAM) memory, how to determine the position of the ion implantation structure and ensure the electrical data of the random access static memory (SRAM) memory has become an urgent problem to be solved. Summary of the invention

[0005] Based on this, it is necessary to provide a method, device, equipment and medium for determining the position of an ion implantation structure in response to the above-mentioned technical problems, which can at least accurately determine the correct position of the ion implantation structure after reducing the structural size of the random access static memory (SRAM) memory to ensure the performance of the random access static memory (SRAM) memory.

[0006] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides a method for determining the position of an ion implantation structure, wherein the ion implantation structure is formed in a memory, and the memory includes multiple ion implantation structures, multiple polysilicon layers and multiple metal wiring layers, wherein the polysilicon layer is located above the ion implantation structure, and the metal wiring layer is located above the polysilicon layer; wherein the position of each ion implantation structure is determined by the following steps: obtaining a first distance value, a second distance value and current electrical data of the memory on both sides of the ion implantation structure; determining a position offset direction of the ion implantation structure according to a difference between the current electrical data of the memory and target electrical data; and adjusting a formation position of the ion implantation structure according to the position offset direction of the ion implantation structure so that the electrical data of the memory reaches the target electrical data.

[0007] In the method for determining the position of the ion implantation structure in the above-mentioned embodiment, the position of the ion implantation structure is adjusted by measuring the electrical data of the memory so that the electrical data of the memory reaches the target electrical data. Therefore, the embodiment of the present disclosure can at least accurately determine the correct position of the ion implantation structure after reducing the structural size of the random access static memory (SRAM) memory, thereby ensuring the performance of the random access static memory (SRAM) memory.

[0008] In one embodiment, the step of obtaining the first distance value and the second distance value on both sides of each ion implantation structure includes: performing a dimension scan on the ion implantation structure based on a critical dimension scanning electron microscope to determine the first distance value and the second distance value between the two sides of the ion implantation structure and other ion implantation structures.

[0009] In the method for determining the position of the ion implantation structure in the above embodiment, the ion implantation structure is scanned by a critical dimension scanning electron microscope to determine the specific position of the ion implantation structure.

[0010] In one embodiment, the position offset direction of each ion implantation structure is determined according to the difference between the current electrical property data and the target electrical property data, including: determining the offset direction of the ion implantation structure according to the positive or negative value of the difference between the current electrical property data and the target electrical property data.

[0011] In the method for determining the position of the ion implantation structure in the above embodiment, the offset direction of the ion implantation structure is determined by the difference between the current electrical data and the target electrical data, and the direction for adjusting the ion implantation structure can be given. At the same time, the staff can also determine the moving distance of the ion implantation structure based on the size of the difference data.

[0012] In one of the embodiments, the formation position of each ion implantation structure is adjusted, including: adjusting the etching parameters multiple times according to the offset direction of the ion implantation structure, and detecting the current electrical data of the memory after each adjustment of the etching parameters; when the current electrical data of the memory is the target electrical data, determining the position of the ion implantation structure formed under the etching parameters as the target position of the ion implantation structure.

[0013] In the method for determining the position of the ion implantation structure in the above embodiment, the target position of the ion implantation structure is determined by adjusting the etching parameters multiple times, thereby ensuring the accuracy of the position of each ion implantation structure.

[0014] In one embodiment, the step of adjusting the etching parameters includes: determining the adjusted etching parameters based on a preset adjustment distance and an offset direction of the ion implantation structure; and determining the target etching parameters based on the etching parameters and the adjusted etching parameters so that the ion implantation structure is offset by an adjustment distance in a direction opposite to the offset direction.

[0015] In the method for determining the position of the ion implantation structure in the above embodiment, the etching parameters are adjusted so that the ion implantation structure is offset by an adjustment distance in a direction opposite to the offset direction, thereby ensuring the accuracy of the ion implantation structure formed after etching.

[0016] In one embodiment, the electrical property data of the memory includes a threshold voltage and a saturation current.

[0017] In the method for determining the position of the ion implantation structure in the above embodiment, the accuracy of electrical data detection is ensured by controlling the threshold voltage and the saturation current.

[0018] In one embodiment, the method further includes: detecting the first angle and the second angle on both sides of the ion implantation structure based on a critical dimension scanning electron microscope.

[0019] In the method for determining the position of the ion implantation structure in the above embodiment, by detecting the first angle and the second angle on both sides of the ion implantation structure, the size of the ion implantation structure is further detected, which can provide data support for adjusting the etching parameters.

[0020] In a second aspect, an embodiment of the present disclosure further provides a device for determining the position of an ion implantation structure, wherein the ion implantation structure is formed in a memory, and the memory includes a plurality of ion implantation structures, a plurality of polysilicon layers, and a plurality of metal wiring layers, wherein the polysilicon layer is located above the ion implantation structure, and the metal wiring layer is located above the polysilicon layer; wherein the device includes:

[0021] A data acquisition module, used to acquire the first distance value, the second distance value and the current electrical property data of the memory on both sides of the ion implantation structure;

[0022] A position offset direction determination module, used to determine the position offset direction of the ion implantation structure according to the difference between the electrical property data of the memory and the target electrical property data;

[0023] The position determination module is used to adjust the formation position of the ion implantation structure according to the position deviation direction of the ion implantation structure so that the electrical data of the memory reaches the target electrical data. At least after reducing the structural size of the random static memory (SRAM) memory, the correct position of the ion implantation structure can be accurately determined to ensure the performance of the random static memory (SRAM) memory.

[0024] An embodiment of the present disclosure also provides an electronic device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the method for determining the position of the ion implantation structure as described above are performed.

[0025] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method for determining the position of an ion implantation structure as described above are executed.

[0026] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A flow chart for determining the position of an ion implantation structure provided in one embodiment of the present application;

[0029] Figure 2 A schematic diagram of a memory provided in an embodiment of the present application;

[0030] Figure 3 A global schematic diagram of a memory provided in an embodiment of the present application;

[0031] Figure 4 A partial enlarged view of a memory provided in an embodiment of the present application;

[0032] Figure 5 A partially enlarged schematic diagram of a storage unit of a memory provided in an embodiment of the present application;

[0033] Figure 6 A comparative schematic diagram of the ion implantation structure adjustment of a memory provided in an embodiment of the present application.

[0034] Description of reference numerals:

[0035] M1, first NMOS; M2, first PMOS; M3, second NMOS; M4, second PMOS; M5, third NMOS; M6, fourth NMOS; 301, PU; 302, PD; 303, PG; 401, ion implantation structure; 402, polysilicon layer; 403, metal wiring layer; 601, metal contact hole; 602, ion implantation structure. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0042] See also Figure 1-Figure 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] See also Figure 2 , Figure 2The schematic diagram of the memory provided in one embodiment of the present application is given as an example. Taking 6T-SRAM as an example, the present application gives a schematic diagram of 6T-SRAM, wherein the first NMOSM1, the first PMOSM2, the second NMOSM3, and the second PMOSM4 constitute a bistable circuit for latching digital signals. The third NMOSM5 and the fourth NMOSM6 are transmission tubes, which are used to complete the connection or disconnection of the memory with the peripheral circuit when performing read / write operations on the memory. The access action to the memory is enabled by the word line (WL, Word Line). When the word line WL is at a high level, the transmission tube is turned on, so that the content of the memory is transferred to the bit line BL, and the update of the memory is transferred to the bit line ¯BL, and the peripheral circuit reads the information through BL and ¯BL. During the write operation, the peripheral circuit of the SRAM cell array transfers the voltage to BL and ¯BL as input. After the word line WL is enabled, the information is written into the memory.

[0044] The memory includes a plurality of storage units.

[0045] As an example, see Figure 3-5 , Figure 3 This is a global schematic diagram of the memory provided in one embodiment of the present application. Among them, the smallest SRAM unit is called a bit, which can only store a signal 0 or 1. Such a bit is composed of 6 transistors, divided into 2 PMOS (PU301), 4 NMOS (PD302, PG303), where PU301 and PD302 form an inverter, and the two inverters form an interlocking structure, and data preservation is achieved through such characteristics. PU301 (pull up) is also called load transistor, and the function of PU301 is to achieve the high potential of the node, that is, the state of 1. PD302 (pull down) is also called drive transistor, and the function of PD302 is to achieve the low potential of the node, that is, the state of 0. In this way, the high and low potentials of the two nodes in a bit are interchanged, and the storage of the two states of 0 and 1 can be achieved. PG303 (pass gate) is also called access transistor, and the function of PG303 is to achieve the access of the bitline to achieve the read and write functions.

[0046] See also Figure 5 , Figure 5 FIG. 1 is a partially enlarged schematic diagram of a storage unit of a memory provided in an embodiment of the present application. Figure 5As shown in , the size of PU301 is 110-89.5=20.5nm, the size of PD302 is 211-110=101nm, and the size of PG303 is 229-141=88nm. The deviation of PD302 will lead to the load effect of etching, which will eventually affect the characteristic size of PD302 after etching and the angles on both sides of the ion implantation structure 401 after etching, as shown in Figure 4 As shown in Figure 4 This is a partial enlarged view of a memory provided in an embodiment of the present application. A metal wiring layer 403 is formed on a polysilicon layer 402 , and the polysilicon layer 402 is formed on an ion implantation structure 401 . Figure 4 After etching, the angles of the two sides of the ion implantation structure 401 are different, which will lead to a series of problems such as reducing the current (Ioff) of the PD 302 in the off state. Therefore, when the environment on both sides of the ion implantation structure 401 changes, it is particularly critical to determine the correct etching parameters so that the ion implantation structure 401 is formed at the correct position and the electrical data of each storage unit reaches the target electrical data.

[0047] See also Figure 1 As an example, one aspect of the present application provides a method for determining a position of an ion implantation structure 401, comprising:

[0048] S1000 , obtaining a first distance value, a second distance value and current electrical property data of a memory at two sides of the ion implantation structure 401 .

[0049] S2000 , determining a position offset direction of the ion implantation structure 401 according to a difference between current electrical property data and target electrical property data of the memory.

[0050] S3000 , adjusting the formation position of the ion implantation structure 401 according to the position offset direction of the ion implantation structure 401 , so that the electrical data of the memory reaches the target electrical data.

[0051] In the method for determining the position of the ion implantation structure 401 in the above-mentioned embodiment, the position of the ion implantation structure 401 is adjusted by measuring the electrical data of the memory so that the electrical data of the memory reaches the target electrical data. Therefore, the embodiment of the present disclosure can at least accurately determine the correct position of the ion implantation structure 401 after reducing the structural size of the random access static memory (SRAM) memory, thereby ensuring the performance of the random access static memory (SRAM) memory.

[0052] In step S1000, as an example, the ion implantation structures 401 may be etched first, so that each ion implantation structure 401 is at a target position, and the current electrical property data of each ion implantation structure 401 at the target position is detected. For example, see Figure 6, Figure 6 Each ion implantation structure 401 in FIG. a is in a standard position.

[0053] In step S1000, since the etching situation will deviate when the environment on both sides of the ion implantation structure 401 changes, the memory can be inspected by CD-SEM, and the size of the ion implantation structure 401 can be increased by DOE splitting experiment, and the size of PG303 can be increased so that the post-etching inspection (AEI) size of PD302 reaches the standard position.

[0054] Here, CD-SEM (Critical Dimension Scanning Electron Microscopy) is a technology used for critical dimension measurement in the semiconductor manufacturing process. It combines the functions of scanning electron microscopy (SEM) and critical dimension (CD) measurement. CD-SEM is used to accurately measure the dimensions of various structures on semiconductor chips, especially tiny graphic features. Critical dimension (CD) refers to the dimension that needs to be strictly controlled in semiconductor devices. CD-SEM uses the high-resolution characteristics of scanning electron microscopes to perform fine dimension measurements at the nanometer level. In the semiconductor manufacturing process, CD-SEM can monitor and measure the critical dimension changes in process steps such as lithography and etching in real time. CD-SEM uses an electron beam to scan the sample surface. The electron beam interacts with the atoms on the sample surface to generate secondary electrons, which are received by the detector and converted into images. By scanning different areas, a high-resolution image of the sample is generated. In the obtained image, the critical dimension is measured using image processing software. The software can automatically identify and measure the size of specific graphic features and calculate the deviation between the actual size and the designed size.

[0055] Among them, due to the reduction in memory size, the environment on both sides of the ion implantation structure 401 will become more complicated. The change in the environment on both sides of the ion implantation structure 401 will cause a large difference between the size of the ion implantation structure 401 after etching and the size after development. Therefore, CD-SEM is needed to detect the position of the ion implantation structure 401.

[0056] Specifically, when adjusting the etching parameters of the ion implantation structure 401 , the etching parameters of the ion implantation structure 401 can be adjusted by using a DOE splitting experiment, and the post-etching inspection (AEI) size of the PD302 reaches a standard position by gradually changing the post-etching position of the ion implantation structure 401 .

[0057] Here, DOE (Design of Experiments) split experiment is an experimental design method in semiconductor manufacturing and process development, which is used to study the impact of different factors on the production process or product performance. DOE is a statistical method that aims to systematically plan experiments and analyze the impact of multiple variables on the output results. Through DOE, it is effective to find out which variables have a significant impact on the output and to discover the interaction between variables. It is widely used in the semiconductor field, including material selection, equipment parameter optimization and process optimization. The typical structure of split experiment is divided into two levels: (1) Whole-Plot: For factors that are difficult to change, the whole-plot determines the combination of these factors and then tests them in a larger experimental unit; (2) Sub-Plot: For factors that are easy to adjust, the sub-plot is conducted on the basis of the whole-plot. The sub-plot is changed multiple times in the same whole-plot to examine the impact of these easily adjustable factors on the results. For example, etching machine type, etching time, etc. In the split experiment, different etcher types (overall experiment) were firstly tested, and then the etching time was changed under each etcher type (sub-experiment) to observe the effect of time on the etching effect so that the PDSEM reached the standard position.

[0058] In one embodiment, the step of obtaining the first distance value and the second distance value on both sides of each ion implantation structure 401 includes: performing a dimension scan on the ion implantation structure 401 based on a critical dimension scanning electron microscope to determine the first distance value and the second distance value between the two sides of the ion implantation structure 401 and other ion implantation structures 401.

[0059] In the method for determining the position of the ion implantation structure 401 in the above embodiment, the ion implantation structure 401 is scanned by a critical dimension scanning electron microscope to determine the specific position of the ion implantation structure 401 .

[0060] In one embodiment, the method further includes: detecting the first angle and the second angle on both sides of the ion implantation structure 401 based on a critical dimension scanning electron microscope.

[0061] In the method for determining the position of the ion implantation structure 401 in the above embodiment, by detecting the first angle and the second angle on both sides of the ion implantation structure 401 , the size of the ion implantation structure 401 is further detected, which can provide data support for adjusting the etching parameters.

[0062] Here, by detecting the first angle and the second angle on both sides of the ion implantation structure 401 , the size data of the ion implantation structure 401 can be determined, and the characteristic size of the PD 302 can be determined.

[0063] In step S2000 , the position offset direction of each ion implantation structure 401 is determined according to the difference between the current electrical property data and the target electrical property data, including: determining the offset direction of the ion implantation structure 401 according to the positive or negative value of the difference between the current electrical property data and the target electrical property data.

[0064] In the method for determining the position of the ion implantation structure 401 in the above embodiment, the offset direction of the ion implantation structure 401 is determined by the difference between the current electrical data and the target electrical data, and the direction for adjusting the ion implantation structure 401 can be given. At the same time, the staff can also determine the moving distance of the ion implantation structure 401 based on the size of the difference data.

[0065] As an example, the offset direction of the ion implantation structure 401 may be determined according to the positive and negative values ​​of the difference, wherein the positive value and the negative value correspond to two opposite directions on both sides of the ion implantation structure 401 .

[0066] In step S3000, the formation position of each ion implantation structure 401 is adjusted, including: adjusting the etching parameters multiple times according to the offset direction of the ion implantation structure 401, and detecting the current electrical data of the memory after each adjustment of the etching parameters; when the current electrical data of the memory is the target electrical data, determining the position of the ion implantation structure 401 formed under the etching parameters as the target position of the ion implantation structure 401.

[0067] In the method for determining the position of the ion implantation structure 401 in the above embodiment, the target position of the ion implantation structure 401 is determined by adjusting the etching parameters multiple times, thereby ensuring the accuracy of the position of each ion implantation structure 401 .

[0068] As an example, the position of the ion implantation structure 401 may be shifted 2 nm to one side of the ion implantation structure 401 by adjusting the parameters each time, and the electrical data of the memory may be detected after each parameter adjustment until the target position of the ion implantation structure 401 is determined.

[0069] As an example, see Figure 6 In Figure b, Figure 6 In Figure b, the distances between the two sides of an ion implantation structure 401 and other ion implantation structures 401 are X1 and X2 respectively. Here, it should be noted that, under normal circumstances, the distances between the two sides of an ion implantation structure 401 and other ion implantation structures 401 should be the same. However, when the size of the memory is reduced, the changes in the environment on both sides of the ion implantation structure 401 will affect the electrical data of the memory. At this time, the target position of the ion implantation structure 401 can only be determined through DOE experiments.

[0070] Please continue reading Figure 6 A metal contact hole 601 is also formed on the ion implantation structure 401 .

[0071] In step S3000, the step of adjusting the etching parameters includes: determining the adjusted etching parameters according to a pre-set adjustment distance and an offset direction of the ion implantation structure 401; determining the target etching parameters according to the etching parameters and the adjusted etching parameters so that the ion implantation structure 401 is offset by an adjustment distance in a direction opposite to the offset direction.

[0072] In the method for determining the position of the ion implantation structure 401 in the above embodiment, the etching parameters are adjusted so that the ion implantation structure 401 is offset by an adjusted distance in a direction opposite to the offset direction, thereby ensuring the accuracy of the ion implantation structure 401 formed after etching.

[0073] In one embodiment, the electrical property data of the memory includes a threshold voltage and a saturation current.

[0074] In the method for determining the position of the ion implantation structure 401 in the above embodiment, the accuracy of electrical data detection is ensured by measuring the threshold voltage and the saturation current.

[0075] On the second aspect, the embodiment of the present disclosure also provides a device for determining the position of an ion implantation structure 401, wherein the ion implantation structure 401 is formed in a memory, and the memory includes multiple ion implantation structures 401, multiple polysilicon layers 402 and multiple metal wiring layers 403, wherein the polysilicon layer 402 is located above the ion implantation structure 401, and the metal wiring layer 403 is located above the polysilicon layer 402.

[0076] Wherein, the position determination device of the ion implantation structure comprises:

[0077] The data acquisition module is used to acquire the first distance value, the second distance value and the current electrical property data of the memory on both sides of the ion implantation structure.

[0078] The position shift direction determination module is used to determine the position shift direction of the ion implantation structure according to the difference between the electrical property data of the memory and the target electrical property data.

[0079] The position determination module is used to adjust the formation position of the ion implantation structure according to the position deviation direction of the ion implantation structure so that the electrical data of the memory reaches the target electrical data. At least after reducing the structural size of the random static memory (SRAM) memory, the correct position of the ion implantation structure can be accurately determined to ensure the performance of the random static memory (SRAM) memory.

[0080] The embodiment of the present disclosure also provides an electronic device, including: a processor, a memory and a bus, the memory stores machine-readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the method for determining the position of the ion implantation structure 401 as described above are performed.

[0081] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method for determining the position of an ion implantation structure as described above are executed.

[0082] The present application provides a method, device, equipment and medium for determining the position of an ion implantation structure 401, which can at least accurately determine the correct position of the ion implantation structure 401 after reducing the structural size of the random access static memory (SRAM) memory, and ensure the performance of the random access static memory (SRAM) memory. The present application provides a method, device, equipment and medium for determining the position of an ion implantation structure, which can at least accurately determine the correct position of the ion implantation structure after reducing the structural size of the random access static memory (SRAM) memory, and ensure the performance of the random access static memory (SRAM) memory.

[0083] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features of the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above embodiments only express several implementation methods of the present disclosure, and their descriptions are relatively specific and detailed, but they cannot be understood as limitations on the scope of the patent application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present disclosure, several variations and improvements can be made, which all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed in this disclosure shall be based on the attached claims.

Claims

1. A method for determining the position of an ion implantation structure, characterized in that: The ion implantation structure is formed in a memory, and the memory includes a plurality of ion implantation structures, a plurality of polysilicon layers, and a plurality of metal wiring layers, wherein the polysilicon layer is located above the ion implantation structure, and the metal wiring layer is located above the polysilicon layer; The position of each ion implantation structure is determined by the following steps: Acquire a first distance value, a second distance value and current electrical property data of the memory at two sides of the ion implantation structure; Determining the position offset direction of the ion implantation structure according to the difference between the current electrical property data and the target electrical property data of the memory; According to the position deviation direction of the ion implantation structure, the formation position of the ion implantation structure is adjusted so that the electrical data of the memory reaches the target electrical data.

2. The method for determining a position according to claim 1, characterized in that: The step of obtaining a first distance value and a second distance value on both sides of each ion implantation structure comprises: The ion implantation structure is scanned based on a critical dimension scanning electron microscope to determine a first distance value and a second distance value between two sides of the ion implantation structure and other ion implantation structures.

3. The method for determining a position according to claim 1, characterized in that: According to the difference between the current electrical property data and the target electrical property data, the position offset direction of each ion implantation structure is determined, including: The offset direction of the ion implantation structure is determined according to the positive or negative value of the difference between the current electrical property data and the target electrical property data.

4. The method for determining a position according to claim 1, characterized in that: Adjust the formation position of each ion implantation structure, including: According to the offset direction of the ion implantation structure, the etching parameters are adjusted multiple times, and after each adjustment of the etching parameters, the current electrical data of the memory is detected; When the current electrical property data of the memory is the target electrical property data, the position of the ion implantation structure formed under the etching parameters is determined as the target position of the ion implantation structure.

5. The method for determining a position according to claim 4, characterized in that: The steps for adjusting the etching parameters include: Determine and adjust etching parameters according to a preset adjustment distance and a deviation direction of the ion implantation structure; According to the etching parameter and the adjusted etching parameter, a target etching parameter is determined to cause the ion implantation structure to shift an adjusted distance in a direction opposite to the shift direction.

6. The method for determining a position according to claim 1, characterized in that: The electrical property data of the memory includes a threshold voltage and a saturation current.

7. The position determination method according to claim 1, characterized in that: The method further comprises: Based on a critical dimension scanning electron microscope, a first angle and a second angle on both sides of the ion implantation structure are detected.

8. A device for determining the position of an ion implantation structure, characterized in that: The ion implantation structure is formed in a memory, and the memory includes a plurality of ion implantation structures, a plurality of polysilicon layers, and a plurality of metal wiring layers, wherein the polysilicon layer is located above the ion implantation structure, and the metal wiring layer is located above the polysilicon layer; Wherein, the device comprises: A data acquisition module, used for acquiring a first distance value, a second distance value and current electrical property data of the memory at two sides of the ion implantation structure; A position offset direction determination module, used to determine the position offset direction of the ion implantation structure according to the difference between the electrical property data of the memory and the target electrical property data; The position determination module is used to adjust the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure so that the electrical data of the memory reaches the target electrical data.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of any method as claimed in claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are executed.

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