Conversion circuit, receiver circuit, and conversion method of conversion circuit

Abstract

A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of the conversion circuit comprises a first phase inverter, a first-stage amplifier and a second-stage amplifier. The input terminal of the first inverter is short-circuited to the output terminal of the first inverter. The second stage amplifier of the replica feedback loop circuit is a replica of the CML to half of the differential amplifier of the CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage for biasing a differential amplifier of the CML-to-CMOS converter such that a common mode (CM) voltage output by the differential amplifier is the same as a switching threshold voltage of a second inverter of the CML-to-CMOS converter.

Description

Technical Field

[0001] The present disclosure relates to a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter capable of converting a CML signal into a CMOS signal with high gain, high bandwidth and low jitter. Background Art

[0002] In a communication system such as a passive optical network system, a transmitter may communicate with a receiver via a channel. The receiver may include a continuous time linear equalization (CTLE) circuit and a voltage-controlled oscillator (VCO) circuit, wherein the CTLE circuit outputs a current mode logic (CML) signal and the VCO circuit operates based on a complementary metal oxide semiconductor (CMOS) signal. A CML to CMOS conversion circuit may be required to convert the CML signal into a CMOS signal.

[0003] However, the conversion operation of conventional CML to CMOS conversion circuits may suffer from problems of low gain, low bandwidth and data jitter. Summary of the invention

[0004] The present disclosure introduces a conversion circuit, a receiver circuit and a conversion method capable of converting a CML signal into a CMOS signal with high gain, high bandwidth and low jitter.

[0005] In some embodiments, a conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit includes a first inverter having a switching threshold voltage and is configured to generate a bias voltage based on the switching threshold voltage of the first inverter. The input terminal of the first inverter is electrically connected to the output terminal of the first inverter. The CML to CMOS converter is coupled to the replica feedback loop circuit and is configured to convert a CML signal into a CMOS signal based on the bias voltage. The CML to CMOS converter includes a second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit. The bias voltage is configured to set a common mode (CM) voltage input to the second inverter of the CML to CMOS converter to be the same as the switching threshold voltage of the second inverter.

[0006] In some embodiments, a receiver circuit includes a continuous time linear equalization (CTLE) circuit and a conversion circuit. The CTLE circuit is configured to generate a first CML signal, a second CML signal, and a direct current (DC) CML signal. The conversion circuit is coupled to the CTLE circuit, and the conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit includes a first inverter having a switching threshold voltage and is configured to generate a bias voltage based on the switching threshold voltage of the first inverter. The input terminal of the first inverter is electrically connected to the output terminal of the first inverter. The CML to CMOS converter is coupled to the replica feedback loop circuit and is configured to convert the CML signal into a CMOS signal based on the bias voltage. The CML to CMOS converter includes a second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit. The bias voltage is configured to set the common mode (CM) voltage of the second inverter input to the CML to CMOS converter to be the same as the switching threshold voltage of the second inverter.

[0007] In some embodiments, a conversion method of a conversion circuit is introduced, the conversion circuit includes a replica feedback loop circuit and a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter. The conversion method includes the following steps: generating a bias voltage (PBIAS) based on a switching threshold voltage of a first inverter by the replica feedback loop circuit, wherein the input terminal of the first inverter is electrically connected to the output terminal of the first inverter; and converting a CML signal into a CMOS signal based on the bias voltage by the CML to CMOS converter, wherein the CML to CMOS converter includes a second inverter (2231 / 2232), and the second inverter (2231 / 2232) has a switching threshold voltage that is the same as the switching threshold voltage (VTH) of the first inverter of the replica feedback loop circuit. The bias voltage is configured to set a common mode (CM) voltage input to the second inverter of the CML to CMOS converter to be the same as the switching threshold voltage of the second inverter.

[0008] According to an embodiment of the present disclosure, a conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of the conversion circuit includes a first inverter, wherein the input terminal of the first inverter is short-circuited to the output terminal of the first inverter, so that the output voltage of the first inverter is equal to the switching threshold voltage of the first inverter. The replica feedback loop circuit also includes a first-stage amplifier and a second-stage amplifier. The second-stage amplifier of the replica feedback loop circuit is a replica of half of the differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage, which is used to bias the differential amplifier of the CML to CMOS converter so that the common mode (CM) voltage output by the differential amplifier is the same as the switching threshold voltage of the second inverter of the CML to CMOS converter. Since the CM voltage input to the second inverter is the same as the switching threshold voltage of the second inverter of the CML to CMOS converter, the conversion circuit can convert the CML signal into a CMOS signal with high gain and low jitter. In addition, a resistor is coupled to the second inverter of the CML to CMOS converter in parallel to enhance the bandwidth of the second inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram illustrating a system including a transmitter circuit and a receiver circuit according to some embodiments.

[0010] Figure 2 is a schematic diagram illustrating a CML to CMOS conversion circuit according to some embodiments.

[0011] Figure 3 is a graph showing a voltage transfer characteristic curve of an inverter according to some embodiments.

[0012] Figure 4 is a waveform diagram of a CML signal output by a CTLE circuit according to some embodiments.

[0013] Figure 5 is a flow chart illustrating a conversion method of a conversion circuit according to some embodiments.

[0014] [Explanation of Symbols]

[0015] 100: system;

[0016] 110: Receiver circuit;

[0017] 111: On-die termination (ODT) circuit;

[0018] 113: Continuous Time Linear Equalization (CTLE) Circuit;

[0019] 115, 200: CML to CMOS conversion circuit;

[0020] 117: Clock and data recovery (CDR) voltage controlled oscillator (VCO);

[0021] 119: sampling circuit;

[0022] 120: transmitter circuit;

[0023] 210: Replicate feedback loop circuit;

[0024] 211: first inverter;

[0025] 213: first stage amplifier;

[0026] 215: second stage amplifier;

[0027] 220: CML to CMOS converter;

[0028] 221: differential amplifier;

[0029] 223: output circuit;

[0030] 310: Voltage transfer characteristic curve;

[0031] 311: point;

[0032] 510, 520: blocks;

[0033] 2231, 2232: inverter / second inverter;

[0034] 2233, 2234: inverter;

[0035] CH: channel;

[0036] CLK: clock signal;

[0037] CM1, CM2: CM voltage;

[0038] CS1: first current source / current source;

[0039] CS2: second current source;

[0040] GND: ground voltage;

[0041] I1: current;

[0042] I2: second current source / current;

[0043] M1, M2, M3, M4: transistors;

[0044] M12: first transistor / transistor;

[0045] M34: second transistor / transistor;

[0046] N1, N2, N3, N4, N5: nodes;

[0047] OUT1, OUT2: CMOS output voltage;

[0048] PBIAS: bias voltage;

[0049] R1, R2: resistors;

[0050] S1, S2: signal;

[0051] S3, VCML_INN, VCML_INP: CML signals;

[0052] S4: CMOS signal;

[0053] S5: output signal;

[0054] VCML_DC: direct current (DC) voltage;

[0055] VTH: switching threshold voltage;

[0056] Vdd: power supply voltage;

[0057] Vin: input voltage;

[0058] Vout: output voltage. DETAILED DESCRIPTION

[0059] Reference will now be made in detail to the presently preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] Figure 1A schematic diagram of a system 100 including a receiver circuit 110 and a transmitter circuit 120 according to some embodiments is shown. The transmitter circuit 120 may send a signal S1 to the receiver circuit 110 via a channel CH. The receiver circuit 110 may include an on-die termination (ODT) circuit 111, a continuous time linear equalization (CTLE) circuit 113, a CML to CMOS conversion circuit 115, a clock and data recovery (CDR) voltage-controlled oscillator (VCO) 117, and a sampling circuit 119. The ODT circuit 111 may receive the signal S1 from the transmitter circuit 120 and calibrate the impedance of the ODT circuit 111 to match the impedance of the transmission line of the channel CH, thereby minimizing signal reflection and enhancing the signal integrity of the received signal. The ODT circuit 111 is configured to generate a signal S2 and output the signal S2 to the CTLE circuit 113. The CTLE circuit 113 may equalize the frequency response of the signal S2 to reduce the distortion caused by the channel CH, thereby generating a CML signal S3, and then output the CML signal S3 to the CML to CMOS conversion circuit 115. The CML to CMOS conversion circuit 115 is configured to convert the CML signal S3 into a CMOS signal S4. In some embodiments, the receiver circuit 110 may operate in a clock and data recovery (CDR) burst mode, in which the CML signal S3 is converted into a CMOS signal S4 and directly input to the CDR VCO 117. The CDR VCO 117 is coupled to the CML to CMOS conversion circuit 115 to receive the CMOS signal S4, and is configured to output a clock signal CLK based on the CMOS signal S4. The sampling circuit 119 is coupled to the CML to CMOS conversion circuit 115 and the CDR VCO 117, and is configured to sample the CMOS signal S4 based on the clock signal CLK to generate an output signal S5.

[0061] Figure 2 A schematic diagram of a CML to CMOS conversion circuit 200 is shown in accordance with some embodiments. Figure 2 The CML to CMOS conversion circuit 200 in Figure 1 The CML to CMOS conversion circuit 200 may include a replica feedback loop circuit 210 and a CML to CMOS converter 220 coupled to the replica feedback loop circuit 210.

[0062] The replica feedback loop circuit 210 may include a first inverter 211, a first stage amplifier 213, and a second stage amplifier 215. The first inverter 211 includes an input terminal and an output terminal, wherein the input terminal of the first inverter 211 is electrically coupled to the output terminal of the first inverter 211. Since the input terminal and the output terminal of the first inverter 211 are short-circuited, the output voltage of the first inverter 211 is substantially the same as the switching threshold voltage VTH of the first inverter 211. The switching threshold voltage of an inverter such as the first inverter 211 is defined as a point in a voltage transfer characteristic curve of the inverter where the input voltage and the output voltage are the same. The voltage transfer characteristic curve of the inverter represents the relationship between the input voltage and the output voltage of the first inverter. Figure 3 An example of a voltage transfer characteristic curve 310 of an inverter is shown according to some embodiments. Figure 3 The vertical axis of the graph in FIG. 1 shows the output voltage Vout of the inverter, and Figure 3 The horizontal axis of the graph in FIG. 1 shows the input voltage Vin of the inverter. Figure 3 As shown in , the switching threshold voltage of the inverter is defined by a point 311 where the input voltage is equal to the output voltage in the voltage transfer characteristic curve 310. The voltage level of the switching threshold voltage VTH of the inverter may depend on the voltage level of the power supply voltage Vdd and / or the characteristics of the electronic components forming the inverter. For example, the inverter may include at least one transistor, and the switching threshold voltage VTH may depend on the channel width of the at least one transistor.

[0063] Reference Figure 2 , the first stage amplifier 213 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first stage amplifier 213 is coupled to the output terminal of the first inverter 211, the second input terminal of the first stage amplifier 213 is coupled to the node N2, and the output terminal of the first stage amplifier 213 is coupled to the node N1. The first stage amplifier 213 receives a switching threshold voltage VTH and a feedback voltage VFB from the first input terminal and the second input terminal, and is configured to compare the switching threshold voltage VTH with the feedback voltage VFB to generate a bias voltage PBIAS at the node N1. The first stage amplifier 213 may be a differential amplifier configured to amplify the difference between the switching threshold voltage VTH and the feedback voltage VFB to generate a bias voltage PBIAS at the node N1.

[0064] The second stage amplifier 215 may include a first transistor M12, a second transistor M34, and a first current source CS1. The first transistor M12 is coupled between the node N2 and a reference node for receiving a power supply voltage Vdd, and a control terminal (i.e., a gate terminal) of the first transistor M12 is biased by a bias voltage PBIAS. The second transistor M34 is coupled between the node N2 and the first current source CS1, and a control terminal (i.e., a gate terminal) of the second transistor M34 is biased by a direct current (DC) voltage VCML_DC. The CTLE circuit (i.e., Figure 1 In some embodiments, based on the CTLE circuit (ie, Figure 1 The level of the DC voltage VCML_DC is determined by the CML signals VCML_INP and VCML_INN output by the CTLE circuit 113 in the circuit. The current source CS1 is coupled between the second transistor M34 and a reference node receiving the ground voltage GND. The current source CS1 is configured to supply a current I1 flowing through the second stage amplifier 215 of the replica feedback loop circuit 210. Figure 2 In FIG. 1 , the first transistor M12 is represented as a p-channel metal oxide semiconductor (PMOS) and the transistor M34 is represented as an n-channel metal oxide semiconductor (NMOS), but the present disclosure is not limited thereto.

[0065] The CML to CMOS converter 220 may include a differential amplifier 221 and an output circuit 223. The differential amplifier 221 includes transistors M1, M2, M3, and M4 and a second current source CS2. The differential amplifier 221 is biased by a bias voltage PBIAS and is configured to output CM voltages CM1 and CM2 via nodes N5 and N4, respectively. The transistor M1 is coupled between the node N4 and a reference node for receiving a power supply voltage Vdd, the transistor M2 is coupled between the node N5 and a reference node for receiving a power supply voltage Vdd, and a control terminal (gate terminal) of the transistor M1 and a control terminal (gate terminal) of the transistor M2 are coupled to each other via a node N3. The node N3 is coupled to a node N1 of the replica feedback loop circuit 210 to receive the bias voltage PBIAS from the node N1. In this way, the control terminals of the transistors M1 and M2 are biased by the bias voltage PBIAS.

[0066] The transistor M3 is coupled between the node N4 and the second current source CS2, the transistor M4 is coupled between the node N5 and the second current source CS2, and the control terminals (gate terminals) of the transistors M3 and M4 are configured to receive CML signals VCML_INP and VCML_INN, respectively. The CML signals VCML_INP and VCML_INN may be generated by the CTLE circuit (i.e., Figure 1 The differential signal output by the CTLE circuit 113 in FIG. Figure 4 2 shows the waveforms of CML signals VCML_INP and VCML_INN output by the CTLE circuit according to some embodiments. Figure 4 , Figure 4 The vertical axis of the middle figure shows the voltage level and Figure 4 The horizontal axis of the middle graph shows time. The DC components of the CML signals VCML_INP and VCML_INN are shown as a DC voltage VCML_DC input to the control terminal of the transistor M34.

[0067] In some embodiments, each of the transistors M3 and M4 of the differential amplifier 221 is identical to the transistor M34 of the second stage amplifier 215, and each of the transistors M1 and M2 of the differential amplifier 221 is identical to the transistor M12 of the second stage amplifier 215. In other words, the transistors M3, M4, and M34 have the same design, and the transistors M12, M1, and M2 have the same design.

[0068] The second current source CS2 is coupled between the transistors M3, M4 and a reference node receiving the ground voltage GND. The second current source CS2 is configured to supply a current I2 flowing through the differential amplifier 221. In some embodiments, the current I1 supplied by the first current source CS1 is half of the current I2 supplied by the second current source I2. In this way, the second stage amplifier 215 of the replica feedback loop circuit is a replica of half of the differential amplifier 221 of the CML to CMOS converter 220.

[0069] In the operation of the CML to CMOS conversion circuit 200, the first stage amplifier 213 of the replica feedback loop circuit 210 is configured to compare the switching threshold voltage VTH with the feedback voltage VFB to generate a bias voltage PBIAS. When the feedback voltage VFB is greater than the switching threshold voltage VTH, the bias voltage PBIAS decreases, thereby increasing the voltage drop across the first transistor M12. The increased voltage drop across the first transistor M12 reduces the voltage at the node N2 until the voltage at the node N2 is substantially equal to the switching threshold voltage VTH. When the feedback voltage VFB is lower than the switching threshold voltage VTH, the bias voltage PBIAS increases, thereby reducing the voltage drop across the first transistor M12. The reduced voltage drop across the first transistor M12 increases the voltage at the node N2 until the voltage at the node N2 is substantially equal to the switching threshold voltage VTH. In this way, the feedback mechanism of the replica feedback loop circuit 210 can maintain the voltage level at the node N2 at the voltage level of the switching threshold voltage VTH.

[0070] At the same time, the bias voltage PBIAS is also input to the control terminals of the transistors M1 and M3 of the differential amplifier 221. The transistors M1 and M2 of the differential amplifier 221 are controlled in a similar manner to the transistor M12, so a detailed description of the operation of the transistors M1 and M2 based on the bias voltage PBIAS is omitted below. The feedback mechanism of the replica feedback loop circuit 210 can maintain the voltage levels of the CM voltages CM1 and CM2 at the voltage level of the switching threshold voltage VTH.

[0071] The output circuit 223 may include inverters 2231, 2233 and a resistor R1. The resistor R1 is coupled between the input terminal and the output terminal of the inverter 2231. In other words, the resistor R1 is coupled to the inverter 2231 in parallel. The input terminal of the inverter 2231 is coupled to the node N5, and the output terminal of the inverter 2231 is coupled to the input terminal of the inverter 2233. The inverter 2231 may receive the CM voltage CM1 from the node N5 and invert the logic state of the CM voltage CM1. The inverter 2233 is coupled to the inverter 2231 in series and is configured to invert the logic state of the voltage output from the inverter 2231 to generate the CMOS output voltage OUT1.

[0072] The output circuit 223 may further include inverters 2232, 2234 and a resistor R2. The resistor R2 is coupled to the inverter 2232 in parallel. The input terminal of the inverter 2232 is coupled to the node N4, and the output terminal of the inverter 2232 is coupled to the input terminal of the inverter 2234. The inverter 2232 may receive the CM voltage CM2 from the node N4 and invert the logic state of the CM voltage CM2. The inverter 2234 is coupled to the inverter 2232 in series and is configured to invert the logic state of the voltage output from the inverter 2232 to generate the CMOS output voltage OUT2.

[0073] In some embodiments, the switching threshold voltages of the inverters 2231 and 2232 of the CML to CMOS converter 220 are the same as the switching threshold voltage VTH of the first inverter 211 of the replica feedback loop circuit 210. Since the voltage levels of the CM voltages CM1 and CM2 are the same as the switching threshold voltage of the inverter 2231, the gain of the inverter 2231 is enhanced. Therefore, the gain of the CML to CMOS conversion is enhanced and the jitter of the CML to CMOS conversion is reduced.

[0074] Furthermore, since resistor R1 is coupled in parallel to the output terminal of inverter 2231 and resistor R2 is coupled in parallel to the output terminal of inverter 2232, the bandwidth of inverter 2231 is improved. Therefore, the bandwidth of CML to CMOS conversion of CML to CMOS conversion circuit 200 is improved.

[0075] Figure 5 FIG. 1 is a block diagram showing a converter circuit (ie, Figure 2 A flowchart of a conversion method of a CML to CMOS conversion circuit 200 in FIG. 1 . The CML to CMOS conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. In block 510, the replica feedback loop circuit of the conversion circuit generates a bias voltage based on a switching threshold voltage of a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first inverter. In block 520, the CML to CMOS converter of the conversion circuit is configured to convert a CML signal into a CMOS signal based on the bias voltage, wherein the CML to CMOS converter includes a second inverter, the second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit, wherein the bias voltage is configured to set a common mode (CM) voltage input to the second inverter of the CML to CMOS converter to be the same as the switching threshold voltage of the second inverter.

[0076] In summary, the conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of the conversion circuit includes a first inverter, wherein the input terminal of the first inverter is short-circuited to the output terminal of the first inverter, so that the output voltage at the output terminal of the first inverter is equal to the switching threshold voltage of the first inverter. The replica feedback loop circuit also includes a first-stage amplifier and a second-stage amplifier, and the CML to CMOS converter includes a differential amplifier. The second-stage amplifier of the replica feedback loop circuit is a replica of half of the differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage, which is used to bias the differential amplifier of the CML to CMOS converter so that the common mode (CM) voltage output by the differential amplifier of the CML to CMOS converter is the same as the switching threshold voltage of the second inverter of the CML to CMOS converter. Since the CM voltage input to the second inverter is the same as the switching threshold voltage of the second inverter of the CML to CMOS converter, the conversion circuit can convert the CML signal into a CMOS signal with high gain and low jitter. In addition, a resistor is coupled to the second inverter of the CML to CMOS converter in parallel. In this way, the CML to CMOS converter achieves high bandwidth.

[0077] Although the embodiments of the present disclosure have been described in detail, the present disclosure is not limited to the specific embodiments, and various modifications and changes may be made within the scope of the present disclosure disclosed in the claims.

Claims

1. A conversion circuit, comprising: a replica feedback loop circuit including a first inverter having a switching threshold voltage, configured to generate a bias voltage based on the switching threshold voltage of the first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first inverter; as well as a current mode logic to complementary metal oxide semiconductor converter, coupled to the replica feedback loop circuit, configured to convert a current mode logic signal into a complementary metal oxide semiconductor signal based on the bias voltage, wherein the current mode logic to complementary metal oxide semiconductor converter includes a second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit, Wherein the bias voltage is configured to set a common mode voltage input to the second inverter of the current mode logic to complementary metal oxide semiconductor converter to be the same as the switching threshold voltage of the second inverter.

2. The conversion circuit according to claim 1, wherein The first inverter is configured to output a voltage equal to the switching threshold voltage of the first inverter to the output terminal of the first inverter, and The switching threshold voltage of the first inverter is determined based on a voltage transfer characteristic curve representing a relationship between an input voltage of the first inverter and an output voltage of the first inverter.

3. The conversion circuit according to claim 2, wherein the replica feedback loop circuit further comprises: a first stage amplifier configured to compare the switching threshold voltage of the first inverter with a feedback voltage; as well as A second stage amplifier is coupled to the first stage amplifier via a first node, wherein the second stage amplifier comprises: a first transistor, wherein a control terminal of the first transistor is coupled to the first node; a second transistor coupled to the first transistor in series via a second node, wherein a control terminal of the second transistor receives a DC voltage; and A current source, coupled to the second transistor in series, is configured to supply a first current flowing through the second stage amplifier. 4 . The conversion circuit according to claim 3 , wherein the second-stage amplifier is configured to provide the feedback voltage to a second input terminal of the first-stage amplifier via the second node.

5. The conversion circuit of claim 4, wherein the current mode logic to complementary metal oxide semiconductor converter comprises: A differential amplifier, wherein the differential amplifier comprises: a first differential transistor; a second differential transistor, wherein a control terminal of the first differential transistor is coupled to a control terminal of the second differential transistor via a third node, and the third node is coupled to the first node to receive the bias voltage from the replica feedback loop circuit; a third differential transistor coupled to the first differential transistor via a fourth node, wherein a control terminal of the third differential transistor receives a first current mode logic signal; a fourth differential transistor coupled to the second differential transistor via a fifth node, wherein a control terminal of the fourth differential transistor receives a second current mode logic signal; and a second current source, coupled to the third differential transistor and the fourth differential transistor, configured to supply a second current to the differential amplifier, The differential amplifier is configured to generate a first common-mode voltage and a second common-mode voltage, and the differential amplifier is further configured to output the first common-mode voltage and the second common-mode voltage to the fifth node and the fourth node, respectively.

6. The conversion circuit according to claim 5, wherein The current mode logic signal includes the first current mode logic signal and the second current mode logic signal, and The first current generated by the current source is half of the second current generated by the second current source.

7. The conversion circuit of claim 5, wherein the current mode logic to complementary metal oxide semiconductor converter further comprises an output circuit, and the output circuit comprises: the second inverter, coupled to the fifth node to receive the first common mode voltage, configured to invert the first common mode voltage, wherein the first common mode voltage is the same as the switching threshold voltage of the second inverter; a first resistor coupled in parallel to the second inverter; as well as The third inverter, coupled to the output terminal of the second inverter in series, is configured to invert the voltage output from the second inverter to generate a first complementary metal oxide semiconductor output voltage.

8. The conversion circuit of claim 7, wherein the current mode logic to complementary metal oxide semiconductor converter further comprises an output circuit, and the output circuit further comprises: a fourth inverter coupled to the fourth node to receive the second common mode voltage, configured to invert the second common mode voltage, wherein the second common mode voltage is the same as a switching threshold voltage of the fourth inverter; a second resistor coupled to the fourth inverter in parallel; as well as A fifth inverter, coupled to an output terminal of the fourth inverter in series, is configured to invert a voltage output from the fourth inverter to generate a second CMOS output voltage.

9. The conversion circuit according to claim 8, wherein The switching threshold voltage of the first inverter is the same as the switching threshold voltage of the second inverter, and The switching threshold voltage of the second inverter is the same as the switching threshold voltage of the fourth inverter.

10. A receiver circuit comprising: a continuous time linear equalization circuit configured to generate a first current mode logic signal, a second current mode logic signal, and a DC current mode logic voltage; as well as A conversion circuit is coupled to the continuous time linear equalization circuit, wherein the conversion circuit comprises: a replica feedback loop circuit including a first inverter having a switching threshold voltage, configured to generate a bias voltage based on the switching threshold voltage of the first inverter; as well as a current mode logic to complementary metal oxide semiconductor converter, coupled to the replica feedback loop circuit, configured to convert the first current mode logic signal and the second current mode logic signal into a first complementary metal oxide semiconductor signal and a second complementary metal oxide semiconductor signal, respectively, based on the bias voltage, wherein the current mode logic to complementary metal oxide semiconductor converter includes a second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit, Wherein the bias voltage is configured to set a common mode voltage input to the second inverter of the current mode logic to complementary metal oxide semiconductor converter to be the same as the switching threshold voltage of the second inverter.

11. The receiver circuit of claim 10, wherein The first inverter is configured to output a voltage equal to the switching threshold voltage of the first inverter at an output terminal of the first inverter, and The switching threshold voltage of the first inverter is determined based on a voltage transfer characteristic curve representing a relationship between an input voltage of the first inverter and an output voltage of the first inverter.

12. The receiver circuit of claim 11 , wherein the replica feedback loop circuit further comprises: a first stage amplifier configured to compare the switching threshold voltage of the first inverter with a feedback voltage; as well as A second stage amplifier is coupled to the first stage amplifier via a first node, wherein the second stage amplifier comprises: a first transistor, wherein a control terminal of the first transistor is coupled to the first node; a second transistor coupled to the first transistor in series via a second node, wherein a control terminal of the second transistor receives a DC voltage; and A current source, coupled to the second transistor in series, is configured to supply a first current flowing through the second stage amplifier. 13 . The receiver circuit of claim 12 , wherein the second stage amplifier is configured to provide the feedback voltage to a second input terminal of the first stage amplifier via the second node.

14. The receiver circuit of claim 13, wherein the current mode logic to complementary metal oxide semiconductor converter comprises: A differential amplifier, wherein the differential amplifier comprises: a first differential transistor; a second differential transistor, wherein a control terminal of the first differential transistor is coupled to a control terminal of the second differential transistor via a third node, and the third node is coupled to the first node to receive the bias voltage from the replica feedback loop circuit; a third differential transistor coupled to the first differential transistor via a fourth node, wherein A control terminal of the third differential transistor receives the first current mode logic signal; a fourth differential transistor coupled to the second differential transistor via a fifth node, wherein A control terminal of the fourth differential transistor receives the second current mode logic signal; and a second current source, coupled to the third differential transistor and the fourth differential transistor, configured to supply a second current to the differential amplifier, The differential amplifier is configured to generate a first common-mode voltage and a second common-mode voltage, and the differential amplifier is further configured to output the first common-mode voltage and the second common-mode voltage to the fifth node and the fourth node, respectively.

15. The receiver circuit of claim 14, wherein The first current generated by the current source is half of the second current generated by the second current source.

16. The receiver circuit of claim 14, wherein the current mode logic to complementary metal oxide semiconductor converter further comprises an output circuit, and the output circuit comprises: the second inverter, coupled to the fifth node to receive the first common mode voltage, configured to invert the first common mode voltage, wherein the first common mode voltage is the same as the switching threshold voltage of the second inverter; a first resistor coupled in parallel to the second inverter; as well as The third inverter, coupled to the output terminal of the second inverter in series, is configured to invert the voltage output from the second inverter to generate a first complementary metal oxide semiconductor output voltage.

17. The receiver circuit of claim 13, wherein the current mode logic to complementary metal oxide semiconductor converter further comprises an output circuit, and the output circuit further comprises: a fourth inverter coupled to the fourth node to receive the second common mode voltage, configured to invert the second common mode voltage, wherein the second common mode voltage is the same as a switching threshold voltage of the fourth inverter; a second resistor coupled to the fourth inverter in parallel; as well as A fifth inverter, coupled to an output terminal of the fourth inverter in series, is configured to invert a voltage output from the fourth inverter to generate a second CMOS output voltage.

18. The receiver circuit according to claim 17, in The switching threshold voltage of the first inverter is the same as the switching threshold voltage of the second inverter, and The switching threshold voltage of the second inverter is the same as the switching threshold voltage of the fourth inverter.

19. A method for converting a conversion circuit, the conversion circuit comprising a replica feedback loop circuit and a current mode logic to a complementary metal oxide semiconductor converter, the conversion method comprising: generating a bias voltage by the replica feedback loop circuit based on a switching threshold voltage of a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first inverter; as well as converting a current mode logic signal into a complementary metal oxide semiconductor signal based on the bias voltage by the current mode logic to complementary metal oxide semiconductor converter, wherein the current mode logic to complementary metal oxide semiconductor converter includes a second inverter having a switching threshold voltage that is the same as the switching threshold voltage of the first inverter of the replica feedback loop circuit, Wherein the bias voltage is configured to set a common mode voltage input to the second inverter of the current mode logic to complementary metal oxide semiconductor converter to be the same as the switching threshold voltage of the second inverter.

20. The conversion method according to claim 19, further comprising: outputting a voltage equal to the switching threshold voltage of the first inverter to the output terminal of the first inverter by the first inverter of the replica feedback loop circuit, The switching threshold voltage of the first inverter is determined according to a voltage transfer characteristic curve representing a relationship between an input voltage of the first inverter and an output voltage of the first inverter.

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