Clock calibration method and device

Abstract

The invention relates to a clock calibration method and device. The method comprises the following steps: obtaining a corresponding relation between a reference clock frequency generated by an internal oscillator and a baud rate frequency of a universal asynchronous transceiver; obtaining a time sequence error of each bit time in a transmission period of the universal asynchronous transceiver according to the corresponding relationship, and accumulating the time sequence errors into an accumulated error; and compensating the accumulative error to calibrate the Baud rate frequency.

Description

Technical Field

[0001] The present invention relates to the field of Universal Asynchronous Receiver / Transmitter Controller (UART Controller), and in particular to a method and device for calibrating an internal clock of a Universal Asynchronous Receiver / Transmitter Controller. Background Art

[0002] In traditional computer communications, the Universal Asynchronous Receiver / Transmitter (UART) interface is a very popular asynchronous communication interface. Based on the UART physical bus definition (such as Figure 1 As shown in the figure, it has derived multiple "industrial standard communication protocols" specifications such as RS232, RS449, RS423, RS422, and RS485.

[0003] By establishing these communication standards, the industry has invested a lot of money on top of these standards and built a lot of internal structures for human life. For example, public power systems, public water supply systems, automated manufacturing systems and other systems.

[0004] An important key point of most of these applications and systems is that their data rates are relatively low compared to modern computer systems. But they are all coupled to "absolute time periods". For example, the public power system wants to check "how much electricity was used in an hour". On the other hand, the power company may need to check the power system every minute.

[0005] In the UART transmission rate, the original UART definition uses multiples of 1200 bits per second (bit / sec) (Baud Rate frequency). For example, multiples such as 1200bit / sec, 2400bit / sec, 4800bit / sec, and 9600bit / sec. However, in the low-power Universal Asynchronous Receiver / Transmitter Controller (UART Controller) system single chip design, in order to calculate the correct time, the clock frequency is usually 32.768kHz to run the Universal Asynchronous Receiver / Transmitter Controller system with correct time calculation.

[0006] Since 32768 is not a multiple of 1200, many single-chip systems that use 32.768kHz general-purpose asynchronous transceiver controllers will experience long-term cumulative errors when simulating UART data transmission at a baud rate of 1200.

[0007] Therefore, how to enable a low-power universal asynchronous transceiver controller single chip to use a 32.768kHz clock frequency to support accurate UART baud rate frequency communication (eg, 9600bit / sec or 4800bit / sec) is an urgent problem to be solved. Summary of the invention

[0008] The following invention contents are exemplary only and are not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features, other aspects, embodiments and features will also be apparent by reference to the accompanying drawings and the following detailed description. That is, the following invention contents are provided to introduce the concepts, key points, benefits and novel and non-obvious technical advantages described herein. Selected, not all, embodiments will be further described in detail as follows. Therefore, the following invention contents are not intended to be essential features of the claimed subject matter, nor are they intended to be used in determining the scope of the claimed subject matter.

[0009] Therefore, the main purpose of the present invention is to provide a method and device for clock calibration.

[0010] The present invention provides a clock calibration device, comprising: a universal asynchronous receiver / transmitter controller (UART controller); and an internal oscillator coupled to the universal asynchronous receiver / transmitter controller, used to generate a reference clock frequency for the universal asynchronous receiver / transmitter controller to operate; wherein the universal asynchronous receiver / transmitter controller performs the following steps: obtaining a corresponding relationship between the reference clock frequency and a baud rate frequency of a universal asynchronous receiver / transmitter (UART); obtaining a timing error of each bit time during a transmission period of the universal asynchronous receiver / transmitter according to the corresponding relationship, and accumulating the timing error into a cumulative error; and compensating the cumulative error to calibrate the baud rate frequency.

[0011] In some embodiments, the above correspondence is expressed as:

[0012]

[0013] Where T BaudRate is a time unit of the above baud rate frequency, T 32K It is a time unit of the above-mentioned reference clock frequency.

[0014] In some embodiments, the transmission period includes 10 bit-times.

[0015] In some embodiments, the step of compensating for the above-mentioned cumulative error includes:

[0016] (a) controlling the output time error of a bit group to be minimum, and obtaining a first number of bit group transmissions required for the cumulative error;

[0017] (b) determining whether the accumulated error can be compensated after accumulating the first amount after transmitting a plurality of bit groups;

[0018] (c) When the accumulated error cannot be compensated, the accumulated error is updated and steps (a) to (c) are repeated until the accumulated error can be compensated after the first amount is accumulated.

[0019] In some embodiments, the step of compensating the accumulated error is achieved by a second number n of triggers, where 2 to the power of n ≧ the first number.

[0020] In some embodiments, the reference clock frequency is generated at a frequency of 32768 Hz, wherein the baud rate is 1200, 2400, 4800 or 9600 bit / sec.

[0021] The present invention provides a clock calibration method, comprising: obtaining a corresponding relationship between a reference clock frequency generated by an internal oscillator and a baud rate frequency of a universal asynchronous receiver / transmitter (UART) by a universal asynchronous receiver / transmitter controller; obtaining a timing error of each bit time during a transmission period of the universal asynchronous receiver / transmitter according to the corresponding relationship, and accumulating the timing error into a cumulative error; and compensating the cumulative error to calibrate the baud rate frequency.

[0022] The present invention can realize the correction of the UART transmission baud rate frequency and achieve the purpose of zero cumulative timing error. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram showing a transmission data frame format according to a universal asynchronous transceiver transmitter.

[0024] Figure 2 is a schematic diagram showing a clock calibration device according to an embodiment of the present invention.

[0025] Figure 3 is a flow chart showing a clock calibration method according to a first embodiment of the present invention.

[0026] Figure 4 is a flow chart showing a clock calibration method according to a first embodiment of the present invention.

[0027] Figure 5 is a flow chart showing a clock calibration method according to an embodiment of the present invention.

[0028] Figure 6 An exemplary operating environment for implementing an embodiment of the present invention is shown.

[0029] Figure Number:

[0030] 200: Installation

[0031] 210: Universal asynchronous transceiver controller

[0032] 220: Internal Oscillator

[0033] 230: Universal asynchronous transceiver transmitter

[0034] 300: Methods

[0035] S305, S310, S315, S320, S325, S330, S335, S340, S350, S355, S360, S365, S370, S375, S380: Step 400: Method

[0036] S405, S410, S415, S420, S425, S430, S435, S440, S450, S455, S460, S465, S470, S475, S480: Step 500: Method

[0037] S505, S510, S515: Step 600: Electronic device

[0038] 610: Bus

[0039] 612: Memory

[0040] 614: Universal asynchronous transceiver controller

[0041] 616: Display device

[0042] 618:I / O interface

[0043] 620:I / O Devices

[0044] 622: Power supply DETAILED DESCRIPTION

[0045] Various aspects of the present invention will be described more fully below with reference to the accompanying drawings. However, the present invention can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present invention. On the contrary, providing these aspects will make the present invention comprehensive and complete, and the present invention will fully convey the scope of the present invention to those skilled in the art. Based on the content taught herein, those skilled in the art should be aware that, whether it is implemented alone or in combination with any other aspect of the present invention, any aspect of the present invention is intended to be covered by the scope of the present invention. For example, any number of devices or execution methods proposed herein can be used to implement. In addition, in addition to the multiple aspects of the present invention proposed herein, the scope of the present invention is more intended to cover devices or methods implemented using other structures, functions, or structures and functions. It should be understood that any aspect of the present invention can be embodied by one or more devices of the scope of the patent application.

[0046] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect of the invention or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the invention or design. In addition, like numerals refer to like devices throughout the several figures, and the articles "a," "an," and "above" include plural references unless otherwise specified in the description.

[0047] It is understood that when a device is referred to as being "connected" or "coupled" to another device, the device may be directly connected or coupled to the other device or there may be an intermediate device. Conversely, when the device is referred to as being "directly connected" or "directly coupled" to another device, there are no intermediate devices. Other words used to describe the relationship between devices should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0048] The embodiment of the present invention provides a clock calibration method and device, which has multi-order calculation with the lowest power consumption, so as to realize the correction of UART transmission baud rate frequency and achieve the purpose of zero cumulative timing error.

[0049] Figure 2 2 is a schematic diagram showing a clock calibration device 200 according to an embodiment of the present invention. The device 200 may include at least a UART 210 and an internal oscillator 220, wherein the internal oscillator 220 is coupled to the UART 210 and used to generate a reference clock frequency for operating the UART 210, and the reference clock frequency is 32768 Hz.

[0050] The types of the device 200 range from small handheld devices (e.g., mobile phones / portable computers) to large host systems (e.g., mainframe computers). Examples of portable computers include personal digital assistants (PDAs), notebook computers, and the like. The universal asynchronous transceiver controller 210 of the device 200 can obtain a baud rate frequency (Baud Rate baud rate frequency) of a universal asynchronous receiver / transmitter (UART) 230.

[0051] The transmission data frame format of the universal asynchronous transceiver transmitter 230 is as follows: Figure 1 As shown, the data frame format may consist of a start bit, 8 data bits (bit 0 to bit 7) and a stop bit. The baud rate of the universal asynchronous transceiver transmitter 230 refers to the number of bits transmitted per second, which essentially gives the time taken by each bit of data during UART communication, and may be 1200, 2400, 4800 or 9600 bit / sec.

[0052] It should be understandable. Figure 2 The clock calibration device 200 shown is a simple example, which can be implemented by any type of computing device, such as a reference Figure 6 The electronic device 600 described, as Figure 6 shown.

[0053] The following will describe in detail how the clock calibration device calibrates the baud rate frequency of the universal asynchronous receiver / transmitter using the reference clock frequency.

[0054] First, in order to better describe the embodiments of the present invention, the time units used in the present invention are defined below.

[0055] T 4800 = 1sec / 4800 = 208.334 us (1)

[0056] T 9600 = 1sec / 9600 = 104.167 us (2)

[0057] T 32k = 1sec / 32768 = 30.5176 us (3)

[0058] From (1), (2), and (3), we can infer that T 4800 、T 9600 With T 32k The relationship is as follows:

[0059]

[0060]

[0061] The following will be based on T 32k The clock is used to simulate 1×T 9600 and 1×T 4800 to explain.

[0062] First embodiment: With T 32k The clock is used to simulate 1×T 9600

[0063] According to the definition of UART transmission, it can be known that a "one-byte transfer" will include 10 bit-times (a start bit, 8 data bits (bit 0 to bit 7) and a stop bit. According to (4), if the clock calibration device uses 3×T 32k The clock is used to simulate 1×T 9600 cycle time, each bit time will generate -0.413×T 32k timing error.

[0064] Therefore, in order to achieve the minimum cumulative error, when using 34×T 32k To simulate 10×T 9600 (ten bit times), the accumulated timing error is -0.133T 32k , which is the minimum cumulative error.

[0065] First stage compensation

[0066] In the first stage compensation, when using 34×T 32k To simulate 10×T 9600 bit time, will cause -0.133×T 32k (i.e., -2 / 15×T 32k ) is the cumulative timing error. It should be noted that this timing error is calculated using T 32k The minimum error of the simulated 9600 bit / sec baud rate frequency. Table 1 lists the symmetrical timing method using the first stage compensation method. In Table 1, the clock calibration device calculates a timing error for each bit time and accumulates each timing error as a cumulative error to illustrate the compensation result. For example, at bit time 0, using 3 T 32k Clock to simulate 1×T 9600 There will be a minimum timing error of -0.413. In another embodiment, the first stage compensation method can be applied to a finite state machine.

[0067] Table 1

[0068]

[0069]

[0070] Second stage compensation

[0071] In the second stage of compensation, the clock calibration device can calculate how many bits of data to transmit to minimize the cumulative error. In this embodiment, when 8 bits of data are transmitted continuously, the cumulative error will reach -1.044×T 32k [8×(-0.133)]. Since the cumulative error exceeds one T 32k , so the clock calibration device will add another T 32k In this embodiment, when transmitting 8-bit data continuously, we should add another T when the last compensation stage in the second stage compensation stops. 32k clock to minimize the cumulative error (-0.066T 32k ). In other words, it should be understood that the cumulative error of 8-bit group transmission is the smallest error.

[0072] Table 2 lists the symmetric timing method using the second stage compensation method. In Table 2, the clock calibration device calculates a timing error for each bit group transmission and accumulates each timing error as a cumulative error to illustrate the compensation result. In Table 2, the cumulative error is expressed as a fraction (e.g., -(2 / 15)). In one embodiment, the second stage compensation can be achieved using three flip-flops.

[0073] Table 2

[0074]

[0075]

[0076] Third stage compensation

[0077] Since in the second stage compensation, if the continuous transmission of UART data exceeds 8 bit groups, it can be known from Table 2 that the cumulative error will still gradually increase. Therefore, the third stage compensation is required to eliminate the cumulative error in the second stage compensation. In the third stage compensation, the clock calibration device can achieve zero cumulative error. The detailed calculation is shown in Table 3.

[0078] Table 3

[0079]

[0080]

[0081] Table 3 shows that if 8-bit data is transmitted 15 times in succession, the cumulative error will be -1×T 32k Therefore, only one more T 32k The clock can compensate for this accumulated error to achieve "zero accumulated timing error". In fact, this multi-stage approximation correction method shows that if the data is continuously transmitted until 125ms and this multi-stage compensation method is followed, the accumulated timing error will be "zero". The following formula shows the detailed calculation information. In this embodiment, the third stage compensation can be achieved using four flip-flops.

[0082] 125ms=1200bit-time=4096×T 32k ={[(34×8)+1]×15+1}×T 32k

[0083] From the above formula, we can see that 1200×T 9800 =4096×T 32k .

[0084] It should be noted that in the second and third stage compensation, a T is added to compensate for the cumulative error. 32k The clock can be placed in the start bit and stop bit of the transmission data frame of the universal asynchronous transceiver transmitter. For example, a T 32k The clock can be placed in the start position, and the T added in the third stage compensation 32k The clock can be put into a stop position. Alternatively, a T is added in the second stage compensation 32k The clock can be put into the stop position, and the T added in the third stage compensation 32k The clock can be put into the start position.

[0085] Figure 3 FIG. 3 is a flow chart showing a method 300 for clock calibration according to a first embodiment of the present invention. The method may be performed as follows: Figure 2 The clock calibration apparatus 200 shown is implemented by the UART controller 210 to calibrate the Baud Rate of 9600 Bit / sec.

[0086] It should be noted that this process Figure 3 T 32k The clock is used to simulate 1×T 9600 In other words, the periodic compensation in the second stage compensation will be 8 cycles, while the periodic compensation in the third stage compensation will be 15 cycles.

[0087] In steps S305 to S350, the UART controller calculates the timing errors of each bit time start bit, 8 data bits (bit 0 to bit 7) and a stop bit.

[0088] In step S355, the universal asynchronous transceiver controller accumulates the timing error as a cumulative error and determines whether it is the eighth cycle compensation. If not, in step S365, the universal asynchronous transceiver controller determines whether the cumulative error has been compensated. If so, in step S360, a T is added. 32k clock as compensation.

[0089] Return to step S365. When the universal asynchronous transceiver controller determines that the cumulative error has been compensated ("Yes" in step S365), this process ends. When the universal asynchronous transceiver controller determines that the cumulative error has not been compensated ("No" in step S365), in step S370, the universal asynchronous transceiver controller accumulates the cumulative error and determines whether it is the 15th cycle compensation.

[0090] When the universal asynchronous transceiver controller determines that it is not the 15th cycle compensation ("No" in step S370), in step S380, the cumulative error is continuously calculated and the number of cycle compensations is counted, and the process returns to S305. When the universal asynchronous transceiver controller determines that it is the 15th cycle compensation ("Yes" in step S370), in step S375, a T is added. 32k The clock is used as compensation, and the number of cycle compensations is counted, and the process returns to S305.

[0091] Second embodiment: With T 32k The clock is used to simulate 1×T 4800

[0092] According to the definition of UART transmission, it can be known that a "one-byte transfer" will include 10 bit-times (a start bit, 8 data bits (bit 0 to bit 7) and a stop bit. According to (5), if the clock calibration device uses 7×T 32k The clock is used to simulate 1×T 4800 cycle time, each bit time will generate -0.17334×T 32k timing error.

[0093] Therefore, in order to achieve the minimum cumulative error, when using 68×T 32k To simulate 10×T 4800 (ten bit times), the accumulated timing error is -0.266T 32k , which is the minimum cumulative error.

[0094] First stage compensation

[0095] In the first stage compensation, when using 68×T 32k To simulate 10×T 4800 bit time, will cause -0.266×T 32k (i.e., -4 / 15×T 32k ) is the cumulative timing error. It should be noted that this timing error is calculated using T 32k The minimum error of the simulated 4800 bit / sec baud rate frequency. Table 4 lists the symmetrical timing method using the first stage compensation method. In Table 4, the clock calibration device calculates a timing error for each bit time and accumulates each timing error as a cumulative error to illustrate the compensation result. For example, at bit time 0, using 7 T 32k Clock to simulate 1×T 4800 There will be a minimum timing error of 0.1734 (ie ). In another embodiment, the first stage compensation method can be applied to a finite state machine.

[0096] Table 4

[0097]

[0098]

[0099] Second stage compensation

[0100] In the second stage of compensation, the clock calibration device can calculate how many bits of data to transmit to minimize the cumulative error. In this embodiment, when 8 bits of data are transmitted continuously, the cumulative error will reach -1.066×T 32k [4×(-0.266)]. Since the cumulative error exceeds one T 32k , so the clock calibration device will add another T 32k In this embodiment, when transmitting 8-bit data continuously, we should add another T when the last compensation stage in the second stage compensation stops. 32k clock to minimize the cumulative error (-0.066T 32k ). In other words, it should be understood that the cumulative error of 8-bit group transmission is the smallest error.

[0101] Table 5 lists the symmetric timing method using the second stage compensation method. In Table 5, the clock calibration device calculates a timing error for each bit group transmission and accumulates each timing error as a cumulative error to illustrate the compensation result. In Table 2, the cumulative error is expressed as a fraction (e.g., -(4 / 15)). In one embodiment, the second stage compensation can be achieved using two flip-flops.

[0102] Table 5

[0103]

[0104]

[0105] Third stage compensation

[0106] Since in the second stage compensation, if the continuous transmission of UART data exceeds 4 bit groups, it can be known from Table 5 that the cumulative error will still gradually increase. Therefore, the third stage compensation is required to eliminate the cumulative error in the second stage compensation. In the third stage compensation, the clock calibration device can achieve zero cumulative error. The detailed calculation is shown in Table 6.

[0107] Table 6

[0108] Byte transfer Cumulative error Cycle compensation 1 -(1 / 15) 0 2 -(2 / 15) 0 3 -(3 / 15) 0 4 -(4 / 15) 0 5 -(5 / 15) 0 6 -(6 / 15) 0 7 -(7 / 15) 0 8 -(8 / 15) 0 9 -(9 / 15) 0 10 -(10 / 15) 0 11 -(11 / 15) 0 12 -(12 / 15) 0 13 -(13 / 15) 0 14 -(14 / 15) 0 15 0 <![CDATA[1(Add a T 32k )]]>

[0109] Table 6 shows that if 4-byte data is transmitted 15 times in succession, the cumulative error will be -1×T 32k Therefore, only one more T 32k The clock can compensate for this accumulated error to achieve "zero accumulated timing error". In fact, this multi-stage approximation correction method shows that if the data is continuously transmitted until 120ms and this multi-stage compensation method is followed, the accumulated timing error will be "zero". The following formula shows the detailed calculation information. In this embodiment, the third stage compensation can be achieved using four flip-flops.

[0110] 125ms = 600 bit-time = 4096 × T 32k ={[(68×4)+1]×15+1}×T 32k

[0111] From the above formula, we can know that 600×T 9800 =4096×T 32k .

[0112] It should be noted that in the second and third stage compensation, a T is added to compensate for the cumulative error. 32k The clock can be placed in the start bit and stop bit of the transmission data frame of the universal asynchronous transceiver transmitter. For example, a T 32k The clock can be placed in the start position, and the T added in the third stage compensation 32k The clock can be put into a stop position. Alternatively, a T is added in the second stage compensation 32k The clock can be put into the stop position, and the T added in the third stage compensation 32k The clock can be put into the start position.

[0113] Figure 4 FIG. 4 is a flow chart showing a method 400 for clock calibration according to a second embodiment of the present invention. The method may be performed as follows: Figure 2 The clock calibration apparatus 200 shown is implemented by the UART controller 210 to calibrate the Baud Rate of 4800 Bit / sec.

[0114] It should be noted that this process Figure 4 T 32k The clock is used to simulate 1×T 4800 In other words, the periodic compensation in the second stage compensation will be 4 cycles, while the periodic compensation in the third stage compensation will be 15 cycles.

[0115] In steps S405 to S450, the universal asynchronous transceiver controller calculates the timing errors of each bit time start bit, 8 data bits (bit 0 to bit 7) and a stop bit.

[0116] In step S455, the universal asynchronous transceiver controller accumulates the timing error as a cumulative error and determines whether it is the fourth cycle compensation. If not, in step S465, the universal asynchronous transceiver controller determines whether the cumulative error has been compensated. If so, in step S460, a T is added. 32k clock as compensation.

[0117] Return to step S465. When the universal asynchronous transceiver controller determines that the cumulative error has been compensated ("Yes" in step S465), this process ends. When the universal asynchronous transceiver controller determines that the cumulative error has not been compensated ("No" in step S465), in step S470, the universal asynchronous transceiver controller accumulates the cumulative error and determines whether it is the 15th cycle compensation.

[0118] When the universal asynchronous transceiver controller determines that it is not the 15th cycle compensation ("No" in step S470), in step S480, the cumulative error is continuously calculated and the number of cycle compensations is counted, and the process returns to S405. When the universal asynchronous transceiver controller determines that it is the 15th cycle compensation ("Yes" in step S470), in step S475, a T is added. 32k The clock is used as compensation, and the number of cycle compensations is counted, and the process returns to S405.

[0119] Figure 5 FIG. 5 is a flow chart showing a method 500 for clock calibration according to an embodiment of the present invention. The method may be performed as follows: Figure 2 The clock calibration is performed by the UART 210 in the apparatus 200 shown.

[0120] In step S505 , the UART controller obtains a corresponding relationship between a reference clock frequency and a baud rate frequency of a UART transmitter, wherein the reference clock frequency is generated by an internal oscillator in the clock calibration device.

[0121] In more detail, the above correspondence can be expressed as:

[0122]

[0123] Where T Baud Rate is a time unit of the above baud rate frequency, T 32K It is a time unit of the above-mentioned reference clock frequency.

[0124] Next, in step S510, the UART controller obtains a timing error of each bit time in a transmission period of the UART transmitter according to the corresponding relationship, and accumulates the timing error into a cumulative error, wherein the transmission period includes 10 bit times.

[0125] In step S515, the universal asynchronous transceiver controller compensates for the accumulated error to calibrate the baud rate frequency. In more detail, the step of compensating for the accumulated error includes:

[0126] (a) controlling the output time of one bit (8 bits) to minimize the error (with the ideal target baud rate) to obtain a first number of bit transmissions required for the cumulative error;

[0127] (b) determining whether the accumulated error can be compensated (greater than one cycle of 32.768 kHz) after accumulating the first amount after transmitting a number of bit groups;

[0128] (c) When the error cannot be compensated, the accumulated error is updated and steps (a) to (c) are repeated until the accumulated error can be compensated after the first amount is accumulated (greater than one cycle of 32.768 kHz).

[0129] In one embodiment, the step of compensating the accumulated error in step S515 is achieved by a second number n of triggers, where 2 to the power of n ≧ the first number.

[0130] As described above, in the clock calibration method and device of the present invention, the universal asynchronous transceiver controller chip can use a very low power circuit (7 or 6 triggers) and a reference clock frequency of 32.768kHz to simulate 9600bit / sec and 4800bit / sec UART transmissions and achieve "zero" cumulative timing error. (It is worth noting that although the present invention uses the correction of 9600bit / sec Baud rate and 4800bit / sec Baud rate UART transmission as an example, the present invention should not be limited to this, and those skilled in the art will understand that the present invention is also applicable to 2400bit / sec Baud rate, 1200bit / sec Baud rate and other high-frequency simulation of low-frequency asynchronous transmission). Since the present invention can be achieved by only a few triggers and combinational logic, this also means that the clock calibration method and device of the present invention can achieve zero-error baud rate frequency compensation with low power consumption and low cost.

[0131] For the embodiments of the present invention that have been described, the following describes an exemplary operating environment in which the embodiments of the present invention can be implemented. Figure 6 , Figure 6 600 is an exemplary operating environment for implementing embodiments of the present invention, which can generally be viewed as an electronic device 600. The electronic device 600 is only an example of a suitable computing environment and is not intended to suggest any limitation on the scope of use or functionality of the present invention. The electronic device 600 should not be interpreted as having any dependency or requirement related to any one or combination of components shown.

[0132] The present invention may be implemented in computer program code or machine-usable instructions, which may be computer executable instructions of a program module, which is executed by a computer or other machine, such as a personal digital assistant or other portable device. Generally speaking, a program module includes routines, programs, objects, devices, data structures, etc. A program module refers to a program code that performs a specific task or implements a specific abstract data type. The present invention can be implemented in a variety of system configurations, including portable devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The present invention can also be implemented in a distributed computing environment, processing devices connected by a communication network.

[0133] refer to Figure 6 Electronic device 600 includes bus 610 that directly or indirectly couples the following devices, memory 612, one or more universal asynchronous receiver and transmitter controllers 614, one or more display devices 616, input / output (I / O) interface 618, input / output (I / O) device 620, and illustrative power supply 622. Bus 610 represents a device that can be one or more buses (e.g., an address bus, a data bus, or a combination thereof). Although Figure 6The blocks are shown with lines for simplicity. Actually, the boundaries of the devices are not specific. For example, the presentation device of the display apparatus may be regarded as an I / O device; the universal asynchronous transceiver controller may have a memory.

[0134] The electronic device 600 generally includes various computer-readable media. Computer-readable media can be any available media that can be accessed by the electronic device 600, including both volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable media can include computer storage media and communication media. Computer-readable media also includes volatile and non-volatile media, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage device, magnetic disk, magnetic disk, magnetic disk storage device or other magnetic storage device, or any other media that can be used to store the desired information and can be accessed by the electronic device 600. Computer storage media itself does not include signals.

[0135] Communication media generally contain computer readable instructions, data structures, program modules or other data in the form of modular data signals such as carrier waves or other transmission mechanisms, and include any information delivery media. The term "modular data signal" refers to a signal that has one or more characteristics set or changed in a manner that encodes information in the signal. By way of example and not limitation, communication media include wired media such as a wired network or direct wired connection and wireless media such as audio, radio frequency, infrared and other wireless media. Combinations of the above media are included within the scope of computer readable media.

[0136] Memory 612 includes computer storage media in the form of volatile and non-volatile memory. Memory can be removable, non-removable, or a combination of the two. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. Electronic device 600 includes one or more universal asynchronous transceiver controllers that read data from entities such as memory 612 or I / O devices 620. Display device 616 displays data indications to a user or other device. Exemplary display devices include display devices, speakers, printing devices, vibration devices, etc.

[0137] The I / O interface 618 allows the electronic device 600 to be logically connected to other devices including the I / O device 620, some of which are built-in devices. Exemplary devices include microphones, joysticks, game consoles, satellite dish signal receivers, scanners, printers, wireless devices, etc. The I / O device 620 can provide a natural user interface for processing gestures, sounds, or other physiological inputs generated by the user. In some examples, these inputs can be transmitted to a suitable network device for further processing. The electronic device 600 can be equipped with a depth camera, such as a stereo camera system, an infrared camera system, an RGB camera system, and a combination of these systems to detect and identify objects. In addition, the electronic device 600 can be equipped with a sensor (e.g., radar, lidar) to periodically sense the surrounding environment within a sensing range, and generate sensor information indicating that it is associated with the surrounding environment. Furthermore, the electronic device 600 can be equipped with an accelerometer or gyroscope that detects motion. The output of the accelerometer or gyroscope can be provided to the electronic device 600 for display.

[0138] In addition, the UART 614 in the electronic device 600 may also execute the programs and instructions in the memory 612 to present the actions and steps described in the above embodiments, or other descriptions in the specification.

[0139] Any specific order or hierarchy of steps in the process disclosed herein is purely by way of example. Based on design preferences, it should be understood that any specific order or hierarchy of steps in the process may be rearranged within the scope of the invention disclosed herein. The accompanying method claims present means for various steps in an exemplary order and, therefore, should not be limited to the specific order or hierarchy presented.

[0140] The use of ordinal numbers such as "first", "second", "third", etc. to modify devices in the claims does not itself imply any priority, precedence, sequence between devices, or order of steps performed by the method, but is only used as an identifier to distinguish different devices with the same name (with different ordinal numbers).

[0141] Although the present invention has been described above with reference to the exemplary embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the claims.

Claims

1. A clock calibration device, characterized in that: include: A universal asynchronous transceiver controller; as well as an internal oscillator, coupled to the universal asynchronous receiver-transmitter controller, for generating a reference clock frequency for operating the universal asynchronous receiver-transmitter controller; The above-mentioned universal asynchronous transceiver controller performs the following steps: Obtaining a corresponding relationship between the reference clock frequency and a baud rate frequency of a universal asynchronous transceiver transmitter; According to the corresponding relationship, a timing error of each bit time in a transmission period of the universal asynchronous transceiver transmitter is obtained, and the timing errors are accumulated to form a cumulative error; and The accumulated error is compensated to calibrate the baud rate frequency.

2. The clock calibration device according to claim 1, characterized in that: The above correspondence is expressed as: Where T BaudRate is a time unit of the above baud rate frequency, T 32K It is a time unit of the above-mentioned reference clock frequency.

3. The clock calibration device according to claim 1, characterized in that: The above transmission period includes 10 bit times.

4. The clock calibration device according to claim 1, characterized in that: The steps for compensating the above-mentioned accumulated error include: Controlling the output time error of a bit group to be minimum, and obtaining a first number of bit group transmissions required for the cumulative error; determining whether the accumulated error can be compensated after accumulating the first amount after transmitting a plurality of bit groups; When the error cannot be compensated, the accumulated error is updated and the steps are repeated until the accumulated error can be compensated after the first amount is accumulated.

5. The clock calibration device according to claim 4, characterized in that: The step of compensating the accumulated error is achieved by a second number n of triggers, where 2 to the power of n is greater than or equal to the first number.

6. The clock calibration device according to claim 1, characterized in that: The reference clock frequency generates a frequency of 32768 Hz, wherein the baud rate frequency is 1200, 2400, 4800 or 9600 bit rate.

7. A clock calibration method, characterized in that: include: A corresponding relationship between a reference clock frequency generated by an internal oscillator and a baud rate frequency of a universal asynchronous receiver and transmitter is obtained by a universal asynchronous receiver and transmitter controller; According to the corresponding relationship, a timing error of each bit time in a transmission period of the universal asynchronous transceiver transmitter is obtained, and the timing errors are accumulated to form a cumulative error; and The accumulated error is compensated to calibrate the baud rate frequency.

8. The clock calibration method according to claim 7, characterized in that: The above correspondence is expressed as: Where T BaudRate is a time unit of the above baud rate frequency, T 32K It is a time unit of the above-mentioned reference clock frequency.

9. The clock calibration method according to claim 7, characterized in that: The steps for compensating the above-mentioned accumulated error include: Controlling the output time error of a bit group to be minimum, and obtaining a first number of bit group transmissions required for the cumulative error; determining whether the accumulated error can be compensated after accumulating the first amount after transmitting a plurality of bit groups; When the error cannot be compensated, the accumulated error is updated and the steps are repeated until the accumulated error can be compensated after the first amount is accumulated.

10. The clock calibration method according to claim 7, characterized in that: The reference clock frequency generates a frequency of 32768 Hz, wherein the baud rate frequency is 1200, 2400, 4800 or 9600 bit rate.

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