Method and apparatus for adjusting baud rate, electronic device, and storage medium

Abstract

The application discloses a baud rate adjustment method and device, electronic equipment and a storage medium. The method comprises the following steps: collecting the pulse width of adjacent edges in the synchronization byte field of an input signal through a general input and output interface; and adjusting the initial baud rate according to the collected pulse width to obtain a target baud rate. The baud rate adjustment method provided in the application can adaptively adjust the baud rate, thereby improving the reliability of communication using the LIN communication protocol.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a baud rate adjustment method and device, electronic equipment and storage medium. BACKGROUND

[0002] In the implementation of the LIN (Local Interconnect Network) communication protocol, it is generally required that the baud rate error between the receiving end and the sending end before communication meets the requirements to ensure that the communication of both parties can proceed normally. For this purpose, in the related art, the baud rates of the communication parties can be set in advance to be close to each other. However, if the baud rate of the receiving end is unknown to the sending end, the baud rate of the receiving end cannot be adjusted, which affects the normal communication between the receiving end and the sending end. SUMMARY

[0003] In view of the above problems, the present application provides a baud rate adjustment method and device, electronic equipment and storage medium, which can adaptively adjust the baud rate and improve the reliability of communication using the LIN communication protocol.

[0004] In a first aspect, the present application provides a baud rate adjustment method, comprising: sequentially collecting pulse widths of adjacent edges in a synchronization byte field of an input signal through a general input and output interface; and adjusting an initial baud rate according to the collected pulse widths to obtain a target baud rate.

[0005] In the technical scheme of the present application, the pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the general input and output interface, so that the initial baud rate can be adjusted according to the collected pulse widths to obtain the target baud rate. Thus, without adjusting or adding built-in digital circuits, the pulse widths of adjacent edges in the synchronization byte field of the input signal can be detected through the general input and output interface, and the detected pulse widths can be used to determine the baud rate used by the input signal at this time, and then the baud rate can be adaptively adjusted through the baud rate used by the input signal, thereby improving the reliability of communication using the LIN communication protocol. At the same time, the cost of implementing the adaptive baud rate adjustment can be reduced.

[0006] In some embodiments, the sequentially collecting the pulse widths of adjacent edges in the synchronization byte field of the input signal through the general input and output interface comprises: in response to an indication signal indicating that the synchronization interval field of the input signal is received, starting the general input and output interface, and sequentially collecting the pulse widths of adjacent edges in the synchronization byte field of the input signal through the general input and output interface. Thus, the situation that the edges of the synchronization interval field are misjudged as the edges of the synchronization byte field due to the reception of the synchronization interval field by the general input and output interface can be avoided, thereby improving the accuracy of subsequent baud rate adjustment.

[0007] In some embodiments, in response to an indication signal indicating receipt of a sync interval field of the input signal, enabling the universal input / output interface, and sequentially collecting pulse widths of adjacent edges in the sync byte field of the input signal through the universal input / output interface, includes: in response to receiving an indication signal indicating a target edge of the input signal, enabling the universal input / output interface, and sequentially collecting pulse widths of adjacent edges in the sync byte field of the input signal through the universal input / output interface; wherein the target edge is a rising edge of the input signal that is separated from a previous edge by a preset bit position. This improves the reliability of the pulse widths of adjacent edges in the sync byte field of the input signal subsequently collected through the universal input / output interface.

[0008] In some embodiments, it is determined that the number of collected pulse widths reaches a preset number, and the initial baud rate is adjusted based on each of the collected pulse widths to determine the target baud rate before completing the reception of the synchronization byte field; wherein the preset number is negatively correlated with the reception speed of the synchronization byte field, so that the baud rate adjustment can be completed before receiving the identifier field, so that subsequent data can be received normally.

[0009] In some embodiments, adjusting the initial baud rate based on the collected pulse widths includes: filtering out abnormal pulse widths from the collected pulse widths to obtain target pulse widths; and adjusting the initial baud rate based on the target pulse widths. This can reduce the likelihood of the adjusted baud rate mismatching the baud rate of the transmitter sending the input signal, improve the accuracy of the adjusted baud rate, and reduce the possibility of failure to properly receive the input signal.

[0010] In some embodiments, abnormal pulse widths are screened out from the collected pulse widths to obtain target pulse widths, including: obtaining target pulse widths other than the first pulse width from the collected pulse widths, thereby avoiding the influence of the pulse width corresponding to the start bit of the synchronization byte field on the baud rate calculation result, thereby improving the accuracy of the adjusted baud rate.

[0011] In some embodiments, the method further includes: in response to a prompt signal indicating completion of reception of the synchronization byte field, loading the target baud rate, thereby avoiding judging a certain edge in the synchronization byte field as the start bit of the next field, resulting in an inability to perform normal signal transmission, thereby enabling normal data reception after loading the target baud rate.

[0012] In some embodiments, the initial baud rate is greater than or equal to 20 kbps.

[0013] In the second aspect, the present application provides a baud rate adjustment device, including: a pulse width acquisition module, which is used to sequentially collect the pulse widths of adjacent edges in the synchronization byte field of the input signal through a general input and output interface; a baud rate adjustment module, which is used to adjust the initial baud rate according to the collected pulse widths to obtain the target baud rate.

[0014] In the technical solution of the embodiment of the present application, the pulse widths of adjacent edges in the synchronization byte field of the input signal are collected in sequence through a universal input / output interface, so that the initial baud rate is adjusted according to the collected pulse widths to obtain the target baud rate. Therefore, there is no need to adjust or add a built-in digital circuit. It is only necessary to detect the pulse widths of adjacent edges in the synchronization byte field of the input signal through the universal input / output interface. The detected pulse width can be used to determine the baud rate used by the input signal at this time, and then the baud rate is adaptively adjusted according to the baud rate used by the input signal, thereby improving the reliability of communication using the LIN communication protocol.

[0015] In a third aspect, the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the method in the implementation of the first aspect when executing the computer program.

[0016] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the method in the embodiment of the first aspect.

[0017] In a fifth aspect, the present application provides a computer program product, which, when running on a computer, enables the computer to execute the method in the first aspect or any optional implementation of the first aspect.

[0018] In a sixth aspect, the present application provides a battery management system, including the electronic device described in the third aspect.

[0019] In the seventh aspect, the application provides an electrical device comprising the battery management system described in the sixth aspect.

[0020] In the eighth aspect, the application provides an electrical device, including the battery management system described in the sixth aspect, or the electrical device described in the seventh aspect.

[0021] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0023] Figure 1 This is a first flow chart of a baud rate adjustment method according to some embodiments of the present application;

[0024] Figure 2 This is a schematic diagram of LIN communication in some embodiments of the present application;

[0025] Figure 3 This is a schematic diagram of a frame header of an input signal according to some embodiments of the present application;

[0026] Figure 4 A schematic diagram of a synchronization byte field in some embodiments of the present application;

[0027] Figure 5 A schematic diagram of a synchronization interval field in some embodiments of the present application;

[0028] Figure 6 A second flow chart of the baud rate adjustment method according to some embodiments of the present application;

[0029] Figure 7 This is a schematic structural diagram of a baud rate adjustment device according to some embodiments of the present application;

[0030] Figure 8 This is a schematic structural diagram of an electronic device according to some embodiments of the present application.

[0031] Some of the accompanying drawings in the specific implementation manner are as follows:

[0032] 200 - pulse width acquisition module; 201 - baud rate adjustment module; 300 - electronic device; 301 - processor; 302 - memory; 303 - communication bus. DETAILED DESCRIPTION

[0033] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0035] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0036] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0038] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0039] In the implementation of the LIN (Local Interconnect Network) communication protocol, it is generally required that the baud rate error between the receiver and transmitter meet certain requirements before communication begins to ensure normal communication between the two parties. For example, in LIN 2.0, the baud rate error between the receiver and transmitter must be between 1% and 14%. To achieve this, related technologies can pre-set baud rates for both communicating parties to ensure normal communication. However, if the transmitter has already set a corresponding baud rate, but the receiver is unaware of the baud rate set by the transmitter, the receiver's baud rate cannot be adjusted, affecting normal communication between the receiver and the transmitter.

[0040] To achieve this, the baud rate of the receiving end can be adaptively adjusted using the digital hardware circuitry built into the LIN transceiver chip on the receiving end. However, this approach requires built-in digital hardware circuitry. If this circuitry is not present, or if it is incompatible with the LIN communication protocol version, the baud rate of the receiving end cannot be adaptively adjusted, thus affecting normal communication between the receiving and transmitting ends.

[0041] In response to the above technical problems, an embodiment of the present application provides a baud rate adjustment method, which uses a universal input and output interface to sequentially collect the pulse widths of adjacent edges in the synchronization byte field of the input signal, and adjusts the initial baud rate according to the collected pulse widths to obtain the target baud rate. Therefore, there is no need to adjust or add a built-in digital circuit. It is only necessary to detect the pulse widths of adjacent edges in the synchronization byte field of the input signal through the universal input and output interface. The detected pulse width can be used to determine the baud rate used by the input signal at this time, and then the baud rate is adaptively adjusted according to the baud rate used by the input signal, thereby improving the reliability of communication using the LIN communication protocol.

[0042] The baud rate adjustment method, apparatus, electronic device, and storage medium disclosed in the embodiments of the present application can be applied to electronic devices to adjust the baud rate of the electronic devices. The electronic devices may include a LIN transceiver chip, which is an integrated circuit for a local interconnect network communication protocol and is used to transmit and receive data on a LIN bus.

[0043] According to some embodiments of the present application, a baud rate adjustment method is provided, which can be applied to the aforementioned electronic device to adjust the baud rate of the electronic device. Figure 1 As shown, the baud rate adjustment method includes:

[0044] S101, sequentially collecting pulse widths of adjacent edges in a synchronization byte field of an input signal through a general purpose input / output interface;

[0045] S102: adjusting the initial baud rate according to the collected pulse widths to obtain a target baud rate.

[0046] In some embodiments, the electronic device may be provided with a universal input / output interface capable of edge detection, which may be connected to a pin of a receiving end of the electronic device to collect a synchronization byte field of an input signal received by the receiving end of the electronic device.

[0047] For example, Figure 2As shown, the electronic device can be receiver A, communicating with transmitter B, which sends input signals, using the LIN transmission protocol. Since the LIN transmission protocol requires a signal level above 12V, which may not be directly connected to the receiver's pins, a LINPHY_CTRL converter can be used between receiver A and transmitter B to convert the 12V signal level to a 5V or 3.3V voltage that can be connected to receiver A's pins. After passing through the LINPHY_CTRL converter, the single LIN bus becomes two signal lines, connected to the output terminal TX and the receiver terminal RX of receiver A, respectively. This allows receiver A to send output signals to transmitter B via the output terminal TX and receive input signals from transmitter B via the receiver terminal RX. The general-purpose input / output port (GPIO) of receiver A is connected to the input terminal RX of receiver A, which is used to receive input signals, so that the input signal on the input terminal RX can be obtained.

[0048] Since the receiving end A and the transmitting end B use the LIN transmission protocol to communicate, the input signal received by the receiving end A from the transmitting end B includes a LIN protocol frame. For the LIN protocol frame, its frame header includes a synchronization interval field, a synchronization byte field, and an identifier field, such as Figure 3 As shown in the figure, the synchronous byte field in the input signal is usually a level signal of 0x55, which corresponds to 8 high and low levels with exactly the same pulse width, as shown in the figure. Figure 4 As shown, its pulse width may correspond to the baud rate set by the transmitter B. To this end, the edges of the synchronization byte field of the input signal may be detected sequentially through the general input / output interface to generate a capture of a timing value at each edge of the synchronization byte field, and the pulse widths of adjacent edges in the synchronization byte field may be determined based on the timing values ​​of the adjacent edges, thereby sequentially collecting the pulse widths of adjacent edges in the synchronization byte field.

[0049] For example, Figure 4 As shown, through the universal input / output interface, timing values ​​are captured starting from the start bit of the sync byte field. The first timing value is captured on the falling edge of the sync byte field's start bit, assuming it is buff1. The second timing value is captured on the rising edge of the sync byte field's end bit, assuming it is buff2. Based on buff2 and buff1, the first pulse width of the sync byte field can be captured. Similarly, the third timing value is captured on the next falling edge of the sync byte field, assuming it is buff3. Based on buff3 and buff2, the second pulse width of the sync byte field can be captured. Similarly, the pulse widths of adjacent edges in the sync byte field of the input signal can be captured sequentially.

[0050] After collecting multiple pulse widths, the initial baud rate of the receiving end A, i.e., the electronic device, can be adjusted based on each of the collected pulse widths, so that the adjusted initial baud rate is determined as the target baud rate of the electronic device. The initial baud rate refers to the baud rate loaded by the electronic device before receiving the current input signal.

[0051] For example, the target pulse width that appears the most times among all pulse widths can be obtained to adjust the initial baud rate to the baud rate calculated by the target pulse width, and the adjusted initial baud rate is the target baud rate; alternatively, the average pulse width of each pulse width can be calculated to adjust the initial baud rate to the baud rate calculated by the average pulse width, and the adjusted initial baud rate is the target baud rate.

[0052] To ensure that all baud rates complying with the LIN communication protocol, such as the LIN 2.0 communication protocol, can be detected, in some embodiments, the initial baud rate is greater than or equal to 20 kbps. Since the LIN 2.0 communication protocol requires that the operating baud rate range be between 1 and 20 kbps, the initial baud rate is set to be greater than or equal to 20 kbps so that the synchronization interval field formed by all baud rates below 20 kbps can always be detected, thereby enabling all baud rates complying with the LIN 2.0 communication protocol to be detected.

[0053] After obtaining the target baud rate, the target baud rate can be loaded and the data receiving function of the input terminal RX can be enabled, so that the input signal can be received and processed through the input terminal RX. At the same time, the universal input and output interface can be reset. After the signal frame reception of the current input signal is completed, the universal input and output interface can be reopened to collect the pulse width of the adjacent edges in the synchronization byte field of the new input signal to readjust the baud rate of the electronic device, thereby achieving adaptive adjustment of the baud rate.

[0054] The GPIO sequentially collects the pulse widths of adjacent edges in the synchronization byte field of the input signal. Based on the collected pulse widths, the initial baud rate is adjusted to obtain the target baud rate. This eliminates the need to adjust or add built-in digital circuits. Instead, the GPIO simply detects the pulse widths of adjacent edges in the synchronization byte field of the input signal. The detected pulse widths are then used to determine the baud rate used by the input signal. The baud rate is then adaptively adjusted based on the baud rate used by the input signal, improving the reliability of communication using the LIN communication protocol. This also reduces the cost of implementing adaptive baud rate adjustment.

[0055] In order to improve the accuracy of baud rate adjustment, in some embodiments, the pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through a universal input / output interface, including: in response to an indication signal indicating that the synchronization interval field of the input signal is received, the universal input / output interface is turned on, and the pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the universal input / output interface.

[0056] Because the pulse widths of adjacent edges in the sync interval field of an input signal cannot represent the baud rate of the transmitter B sending the input signal, to prevent the GPIO from receiving the sync interval field and misinterpreting the edges of the sync interval field as edges of the sync byte field, thereby affecting the accuracy of subsequent baud rate adjustment, in some embodiments, before receiving an input signal, the electronic device may first shut down the GPIO and enable the input terminal RX to detect whether the input signal has been received. Since the sync interval field is transmitted before the sync byte field, the sync interval field is detected first when the input signal is received. If the sync interval field is detected, it indicates that an input signal is being transmitted on the LIN bus. Upon confirming receipt of the sync interval field, an indication signal is generated indicating receipt of the sync interval field of the input signal. In response to this indication signal, the GPIO is enabled. The sync byte field of the input signal can then be received via the GPIO, and the pulse widths of adjacent edges in the sync byte field of the input signal can be sequentially collected via the GPIO. While the GPIO is enabled, the input terminal RX can be disabled.

[0057] By responding to an indication signal indicating that a synchronization interval field of an input signal has been received, the universal input / output interface is turned on, and the pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the universal input / output interface. This can avoid the situation where the edge of the synchronization interval field is misjudged as the edge of the synchronization byte field due to the synchronization interval field being received by the universal input / output interface, thereby improving the accuracy of subsequent baud rate adjustment.

[0058] To more accurately determine whether the synchronization interval field of the input signal is received, in some embodiments, in response to an indication signal indicating that the synchronization interval field of the input signal is received, the general purpose input / output interface is enabled, and pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the general purpose input / output interface, including:

[0059] In response to receiving an indication signal of a target edge of the input signal, turning on the general input / output interface, and sequentially collecting pulse widths of adjacent edges in a synchronization byte field of the input signal through the general input / output interface;

[0060] The target edge is a rising edge in the input signal that is separated from the previous edge by a preset bit position.

[0061] In some embodiments, the synchronization interval field includes a falling edge indicating a start bit and a rising edge indicating a stop bit. Based on the provisions of the LIN communication protocol, the low level in the synchronization interval field should be no less than a certain number of bits, that is, a certain number of bits must be separated between the falling edge and the rising edge of the synchronization interval field. Taking LIN2.0 as an example, the low level in the synchronization interval field should be no less than 13 bits, that is, there must be at least 13 bits between the falling edge indicating the start bit and the rising edge indicating the stop bit, such as Figure 5 shown.

[0062] Based on this, before receiving an input signal, the electronic device can first close the universal input / output interface (UIO) and open the input terminal RX to detect whether an input signal has been received. If an input signal is detected, it can be determined whether the interval between the current rising edge and the previous edge reaches a preset bit position. If the preset bit position is reached, it indicates that the received rising edge is the stop bit of the synchronization interval field. At this time, the rising edge can be determined as the target edge of the input signal, and an indication signal indicating the target edge of the input signal is generated. In response to this indication signal, the universal input / output interface is opened, and the synchronization byte field of the input signal can be received through the universal input / output interface. The pulse widths of adjacent edges in the synchronization byte field of the input signal are then sequentially collected through the universal input / output interface.

[0063] For example, using the LIN communication protocol LIN2.0 as an example, the preset bit number is 13 bits. Upon receiving an input signal, if a low level of at least 13 bits is detected, a rising edge is waited for to be received, thereby confirming receipt of the synchronization interval field. If the rising edge is received, the rising edge is determined as a target edge, and an indication signal indicating receipt of the target edge of the input signal is generated. In response to the indication signal, the general purpose input / output interface is enabled. In this way, the synchronization interval field of the received input signal can be accurately determined based on the target edge, thereby improving the reliability of the pulse widths of adjacent edges in the synchronization byte field of the input signal subsequently collected via the general purpose input / output interface.

[0064] After collecting each pulse width via the general-purpose input / output port, the initial baud rate of the electronic device can be adjusted based on each pulse width. However, considering that the identifier field of the input signal is received after the sync byte field, if the baud rate adjustment is not completed when the identifier field is received, it will affect the normal reception of subsequent data. To this end, in some embodiments, it is determined that the number of collected pulse widths has reached a preset number, and the initial baud rate is adjusted based on each of the collected pulse widths to determine the target baud rate before completing the reception of the sync byte field; wherein the preset number is inversely correlated with the speed of receiving the sync byte field.

[0065] In some embodiments, the preset number of pulse widths required to adjust the initial baud rate can be determined based on the reception speed of the sync byte field. For example, a test can be conducted in advance to determine the maximum number of pulse widths that can be used to adjust the initial baud rate at any sync byte field reception speed without affecting the normal reception of the subsequent identifier field. This maximum number of pulse widths can then be determined as the number of pulse widths corresponding to that reception speed. This allows for the number of pulse widths corresponding to different reception speeds. The faster the reception speed, the smaller the corresponding number of pulse widths, ensuring sufficient time to adjust the baud rate before receiving the identifier field.

[0066] After receiving the sync byte field of an input signal via a general purpose input / output interface, a number of pulse widths corresponding to the reception speed of the sync byte field is determined based on the reception speed of the sync byte field, serving as a preset number of pulse widths for adjusting the initial baud rate. Then, during the pulse width collection process, a detection is performed to determine whether the number of collected pulse widths reaches the preset number. If so, the initial baud rate is adjusted based on the collected pulse widths to determine the target baud rate before completing reception of the sync byte field, i.e., before receiving the stop bit of the sync byte field.

[0067] For example, taking the preset number of 5 pulse widths as an example, assuming that the synchronization byte field is as follows Figure 4As shown, when collecting the pulse width of the synchronization byte field, the timing value is captured starting from the start bit of the synchronization byte field through the general input and output interface. At this time, the first timing value will be captured at the falling edge starting from the start bit of the synchronization byte field, assuming it is buff1; the second timing value will be captured at the rising edge ending at the start bit of the synchronization byte field, assuming it is buff2. At this time, the first pulse width of the synchronization byte field can be collected based on buff2 and buff1, recorded as buff2; the third timing value will be captured at the next falling edge of the synchronization byte field, assuming it is buff3. At this time, the second pulse width of the synchronization byte field can be collected based on buff3 and buff2, recorded as buff3, that is, the third timing value is captured at the moment when the second pulse width ends. By analogy, when the 7th timing value is captured, the 5th pulse width {buff2, buff3, buff4, buff5, buff6} will be collected. At this time, it can be determined that the number of collected pulse widths reaches the preset number, triggering the baud rate adjustment to adjust the initial baud rate based on the first 5 pulse widths, so as to determine the target baud rate before the 10th timing value is captured, that is, before the timing value of the stop bit of the synchronization byte field is received.

[0068] By determining that the number of collected pulse widths reaches a preset number, the baud rate adjustment is triggered. The initial baud rate is adjusted according to the collected pulse widths to determine the target baud rate before completing the reception of the synchronization byte field, so that the baud rate adjustment can be completed before receiving the identifier field, so that subsequent data can be received normally.

[0069] In order to further improve the accuracy of the adjusted baud rate and reduce the possibility of not being able to normally receive the input signal, in some embodiments, the initial baud rate is adjusted according to the collected pulse widths, including: filtering out abnormal pulse widths of the collected pulse widths to obtain target pulse widths; and adjusting the initial baud rate according to the target pulse widths.

[0070] For example, after obtaining each pulse width, the standard deviation of each pulse width can be calculated to identify abnormal pulse widths from among the pulse widths based on the standard deviation of each pulse width. If the standard deviation of a pulse width reaches a threshold, it indicates that the pulse width is an abnormal pulse width. Alternatively, the variance of each pulse width can be calculated to identify abnormal pulse widths from among the pulse widths based on the variance of each pulse width. Alternatively, abnormal pulse widths can be screened out from among the pulse widths using an interquartile range or boxplot.

[0071] If any abnormal pulse widths exist among the pulse widths, they can be filtered out and the remaining pulse widths determined as target pulse widths. The initial baud rate can then be adjusted based on the target pulse widths. This reduces the likelihood of the adjusted baud rate mismatching the baud rate of the transmitter sending the input signal, improves the accuracy of the adjusted baud rate, and reduces the possibility of failure to properly receive the input signal.

[0072] Considering that in actual use, the sync byte field contains a start bit, which is followed by eight high and low pulses of substantially equal width. However, the start bit clock may be configured differently in different devices. Therefore, abnormal pulse widths typically only occur in the start bit of the sync byte field. Therefore, in some embodiments, the collected pulse widths are screened for abnormal pulse widths to obtain target pulse widths, including: obtaining target pulse widths other than the first pulse width from the collected pulse widths.

[0073] Since each pulse width is collected in the order of transmission, the pulse widths can be sorted according to the order in which they are received. In this case, the first pulse width is the pulse width between the falling edge and the rising edge corresponding to the start bit. However, in actual use, the start bit of the synchronization byte field does not belong to a certain bit in 0X55. It may be configured as 0.5 clocks, 1 clock, or 1.5 clocks in different devices. Therefore, there is an error between the pulse width corresponding to the start bit and the 8 pulse widths after the start bit. Based on this, the first pulse width, that is, the pulse width corresponding to the start bit, can be filtered out as an abnormal pulse width, and the remaining pulse widths can be determined as the target pulse widths. The initial baud rate can be adjusted according to each target pulse width.

[0074] For example, assuming that 5 pulse widths {buff2, buff3, buff4, buff5, buff6} are collected, and the first pulse width buff2 is the pulse width corresponding to the start bit, then buff2 can be screened out as an abnormal pulse width to obtain the remaining 4 target pulse widths {buff3, buff4, buff5, buff6}. The initial baud rate can be adjusted by these 4 target pulse widths, such as calculating the average pulse width by accumulating buff3, buff4, buff5, and buff6 and shifting them right by two places. The initial baud rate can be adjusted by the average pulse width.

[0075] By obtaining the target pulse widths except the first pulse width from the collected pulse widths, the initial baud rate is adjusted according to the target pulse widths, thereby avoiding the influence of the pulse width corresponding to the start bit of the synchronization byte field on the baud rate calculation result, thereby improving the accuracy of the adjusted baud rate.

[0076] After obtaining the target baud rate, the target baud rate can be loaded, and the data receiving function of the input terminal of the electronic device can be enabled, so that the input signal can be received and processed subsequently. In order to enable the electronic device to receive data normally after loading the target baud rate, in some embodiments, the method further includes: loading the target baud rate in response to a prompt signal indicating that the reception of the synchronization byte field is complete.

[0077] Consider that the internal clock at the input end of an electronic device only counts; once the count is complete, the next byte is considered to have begun. However, before baud rate adjustment, the initial baud rate may not match the baud rate of the transmitter sending the input signal. At this time, the internal clock of the electronic device and the transmitter may not match, meaning the bits between them may differ. Therefore, if the target baud rate is loaded immediately after it is determined, an edge in the synchronization byte field may be interpreted as the start bit of the next field, preventing normal signal transmission.

[0078] Based on this, in some embodiments, the completion of reception of the sync byte field, i.e., the reception of the stop bit of the sync byte field, can be detected by detecting an edge received by the general purpose input / output interface. If completion of reception of the sync byte field is detected, a prompt signal indicating completion of reception of the sync byte field is generated. In response to the prompt signal, the target baud rate is loaded. After the target baud rate is loaded, the input terminal RX is enabled for data reception.

[0079] For example, assuming that the LIN communication protocol is LIN2.0, the synchronization byte field in LIN2.0 is a level signal of 0x55, corresponding to a start bit, a stop bit, and 8 high and low levels with substantially equal pulse widths, such as Figure 4 As shown in the figure, the timing value is captured via the general-purpose input / output interface starting from the start bit of the sync byte field. The tenth timing value captured is the stop bit of the sync byte field. Therefore, upon detecting the tenth timing value captured via the general-purpose input / output interface, it can be determined that the sync byte field has been received. At this point, an alert signal can be generated, and in response to this alert signal, the target baud rate can be loaded.

[0080] By responding to the prompt signal indicating that the reception of the synchronization byte field is completed, the target baud rate is loaded, and then the target baud rate is loaded again after the reception of the synchronization byte field is completed, so as to avoid judging a certain edge in the synchronization byte field as the start bit of the next field, resulting in the inability to perform normal signal transmission, thereby enabling normal data reception after loading the target baud rate.

[0081] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be described clearly and completely below. In some embodiments, Figure 6 As shown, the bit rate adjustment method includes:

[0082] S201, in response to receiving an indication signal indicating a target edge of an input signal, enabling a general purpose input / output interface (GPIO) and sequentially collecting pulse widths of adjacent edges in a sync byte field of the input signal via the GPIO interface. The target edge is a rising edge of the input signal that is separated from a previous edge by a preset number of bits.

[0083] S202: Determine whether the number of pulse widths collected reaches a preset number, and if so, execute S203, wherein the preset number is negatively correlated with the receiving speed of the synchronization byte field.

[0084] S203: Acquire target pulse widths except the first pulse width from the collected pulse widths.

[0085] S204: Adjust the initial baud rate according to each target pulse width to determine the target baud rate before completing the reception of the synchronization byte field, wherein the initial baud rate is greater than or equal to 20 kbps.

[0086] S205 , in response to a prompt signal indicating that the synchronization byte field reception is completed, loading a target baud rate.

[0087] Figure 7 The present application provides a schematic diagram of the structure of a baud rate adjustment device. It should be understood that the device is Figure 1 The method embodiment executed in corresponds to the embodiment of the method, and the steps involved in the aforementioned method can be executed. The specific functions of the device can be found in the description above. To avoid repetition, the detailed description is appropriately omitted here. The device includes at least one software function module that can be stored in a memory in the form of software or firmware or fixed in the operating system (OS) of the device. Specifically, the device is used to adjust the baud rate of an electronic device. The device includes: a pulse width acquisition module 200, which is used to sequentially collect the pulse widths of adjacent edges in the synchronization byte field of the input signal through a general input and output interface; a baud rate adjustment module 201, which is used to adjust the initial baud rate according to each of the collected pulse widths to obtain a target baud rate.

[0088] In the technical solution of the embodiment of the present application, the pulse widths of adjacent edges in the synchronization byte field of the input signal are collected in sequence through a universal input / output interface, so that the initial baud rate is adjusted according to the collected pulse widths to obtain the target baud rate. Therefore, there is no need to adjust or add a built-in digital circuit. It is only necessary to detect the pulse widths of adjacent edges in the synchronization byte field of the input signal through the universal input / output interface. The detected pulse width can be used to determine the baud rate used by the input signal at this time, and then the baud rate is adaptively adjusted according to the baud rate used by the input signal, thereby improving the reliability of communication using the LIN communication protocol.

[0089] According to some embodiments of the present application, the pulse width acquisition module 200 is specifically used to: in response to an indication signal indicating that the synchronization interval field of the input signal is received, turn on the universal input and output interface, and sequentially collect the pulse widths of adjacent edges in the synchronization byte field of the input signal through the universal input and output interface.

[0090] According to some embodiments of the present application, the pulse width acquisition module 200 is specifically used to: in response to receiving an indication signal of a target edge of the input signal, turn on the general input / output interface, and sequentially collect the pulse widths of adjacent edges in the synchronization byte field of the input signal through the general input / output interface; wherein the target edge is a rising edge in the input signal that is separated from the previous edge by a preset bit position.

[0091] According to some embodiments of the present application, the baud rate adjustment module 201 is specifically used to: determine whether the number of collected pulse widths reaches a preset number, and adjust the initial baud rate based on each of the collected pulse widths to determine the target baud rate before completing the reception of the synchronization byte field; wherein the preset number is negatively correlated with the reception speed of the synchronization byte field.

[0092] According to some embodiments of the present application, the baud rate adjustment module 201 is specifically configured to: filter out abnormal pulse widths from the collected pulse widths to obtain target pulse widths; and adjust the initial baud rate according to the target pulse widths.

[0093] According to some embodiments of the present application, the baud rate adjustment module 201 is specifically configured to: obtain the target pulse widths except the first pulse width from the collected pulse widths.

[0094] According to some embodiments of the present application, the baud rate adjustment module 201 is further configured to: load the target baud rate in response to a prompt signal indicating completion of reception of the synchronization byte field.

[0095] According to some embodiments of the present application, the initial baud rate is greater than or equal to 20 kbps.

[0096] According to some embodiments of the present application, as shown in Figure 8 The present application provides an electronic device 300, comprising: a processor 301 and a memory 302, the processor 301 and the memory 302 are interconnected and communicate with each other through a communication bus 303 and / or other forms of connection mechanism (not marked), the memory 302 stores a computer program executable by the processor 301, when the computing device is running, the processor 301 executes the computer program to execute the method executed by the terminal in any optional implementation manner, for example: through a general input and output interface, sequentially collecting the pulse width of adjacent edges in the synchronization byte field of the input signal; according to the collected pulse width of each, adjust the initial baud rate to obtain the target baud rate.

[0097] The present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by the processor to execute the method in any optional implementation manner.

[0098] Wherein, the storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0099] The present application provides a computer program product, which when running on a computer, causes the computer to execute the method in any optional implementation manner.

[0100] The present application provides a battery management system, which comprises the electronic device in the above-mentioned embodiments.

[0101] The present application provides a battery device, which comprises the electronic device or the battery management system in the above-mentioned embodiments.

[0102] The present application provides an electric device, which may be an electric device such as a vehicle, a ship, or an aircraft, etc. The electric device includes a battery management system as described above, or a battery device as described above.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A baud rate adjustment method, characterized in that: include: The pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the general input and output interface; Adjusting the initial baud rate according to the collected pulse widths to obtain a target baud rate; Adjusting the initial baud rate according to the collected pulse widths to obtain the target baud rate includes: determining that the number of the collected pulse widths reaches a preset number, and adjusting the initial baud rate based on each of the currently collected pulse widths to determine the target baud rate before receiving a timing value of a stop bit of the synchronization byte field; Wherein, the preset number is negatively correlated with a receiving speed of the synchronization byte field; Adjusting the initial baud rate according to the collected pulse widths includes: Obtaining target pulse widths other than the first pulse width from the collected pulse widths; The initial baud rate is adjusted according to each of the target pulse widths.

2. The method according to claim 1, characterized in that Sequentially collecting the pulse widths of adjacent edges in the synchronization byte field of the input signal through a universal input / output interface, including: In response to an indication signal indicating that the synchronization interval field of the input signal is received, the universal input / output interface is enabled, and pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the universal input / output interface.

3. The method according to claim 2, characterized in that In response to an indication signal indicating that a synchronization interval field of the input signal is received, the universal input / output interface is enabled, and pulse widths of adjacent edges in the synchronization byte field of the input signal are sequentially collected through the universal input / output interface, including: In response to receiving an indication signal of a target edge of the input signal, turning on the general input / output interface, and sequentially collecting pulse widths of adjacent edges in a synchronization byte field of the input signal through the general input / output interface; The target edge is a rising edge in the input signal that is separated from the previous edge by a preset bit position.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The target baud rate is loaded in response to an indication signal indicating completion of reception of the sync byte field.

5. The method according to any one of claims 1 to 3, characterized in that: The initial baud rate is greater than or equal to 20 kbps.

6. A baud rate adjustment device, characterized in that: include: A pulse width acquisition module is used to sequentially acquire the pulse widths of adjacent edges in the synchronization byte field of the input signal through the general input and output interface; A baud rate adjustment module is used to adjust the initial baud rate according to the collected pulse widths to obtain a target baud rate; The baud rate adjustment module is specifically configured to determine that the number of collected pulse widths reaches a preset number, and adjust the initial baud rate according to each of the collected pulse widths to determine the target baud rate before receiving the stop bit of the synchronization byte field; Wherein, the preset number is negatively correlated with a receiving speed of the synchronization byte field; The baud rate adjustment module is specifically used for: Obtaining target pulse widths other than the first pulse width from the collected pulse widths; The initial baud rate is adjusted according to each of the target pulse widths.

7. An electronic device comprising a processor and a memory storing a computer program, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

9. A battery management system, characterized in that: Comprising the electronic device as claimed in claim 7.

10. A battery device, characterized in that: Comprising the battery management system as claimed in claim 9.

11. An electrical device, characterized in that: The battery management system comprises the battery management system according to claim 9, or the battery device according to claim 10.

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