Hardware detection method, device, equipment and medium for distributed power supply access unit

Abstract

The present invention relates to the field of power and communication technology, and in particular to a hardware detection method, device, equipment and medium for a distributed power access unit. The method comprises: receiving an externally input message test frame; parsing the message test frame to determine the hardware interface to be tested; sending an interface test frame to a hardware detection device based on the hardware interface to be tested; receiving the return data after the hardware detection device verifies the interface test frame; and generating a test result frame according to the return data. The present invention connects the hardware interface in the distributed power access unit with the hardware detection device, and sends a message test frame to the distributed power access unit, and performs signal interaction with the hardware detection device according to the message test frame to realize the detection of each hardware interface. Thus, the method can realize the production line automation test of the distributed power access unit, saving production cost and time.

Description

Technical Field

[0001] The present invention relates to the field of power and communication technology, and in particular to a hardware detection method, device, equipment and medium for a distributed power supply access unit. Background Art

[0002] In recent years, distributed photovoltaic power stations have been actively promoted, and because of the convenience, reliability, economy, and policy support of distributed photovoltaic control pilot projects, distributed photovoltaic power stations have been rapidly rolled out. Based on this, in order to improve the observability, measurability, adjustability, and controllability of low-voltage distributed photovoltaic power generation, related products such as distributed power access units have been developed.

[0003] However, for related products such as distributed power access units, if there are potential hidden dangers or damage in the distributed power access units but there is no corresponding test method to detect them, a large number of product functions will have problems after delivery, which not only greatly affects the efficiency of production and troubleshooting, but also indirectly affects the benefits and customer satisfaction with the product. Therefore, there is an urgent need for a method to perform spot inspection tests on the hardware functions and peripheral functions of the distributed power access unit product. Summary of the invention

[0004] In view of this, the present invention provides a hardware detection method, device, equipment and medium for a distributed power access unit to solve the problem in the prior art that there is a lack of a method for detecting the hardware and related functions of a distributed power access unit.

[0005] In the first aspect, the present invention provides a hardware detection method for a distributed power supply access unit, wherein the distributed power supply access unit includes multiple hardware interfaces and a main control chip, and the multiple hardware interfaces are connected to a hardware detection device. The method is applied to the main control chip, and the method includes: receiving an externally input message test frame; parsing the message test frame to determine a hardware interface to be tested; sending an interface test frame to a hardware detection device based on the hardware interface to be tested; receiving return data after the hardware detection device verifies the interface test frame; and generating a test result frame based on the return data.

[0006] In the present invention, by connecting the hardware interface and the hardware detection device in the distributed power access unit, and by sending a message test frame to the distributed power access unit, the distributed power access unit performs signal interaction with the hardware detection device according to the message test frame to realize the detection of each hardware interface. Therefore, based on this method, the production line automated testing of the distributed power access unit can be realized, saving production cost and time.

[0007] In an optional embodiment, when the hardware interface to be tested is the first CAN interface, the first 485 interface or the second 485 interface managed by the main control chip, an interface test frame is sent to the hardware detection device based on the hardware interface to be tested, including: controlling the hardware interface to be tested to open; obtaining the parameters of the opened hardware interface and setting the parameters; and sending the interface test frame to the hardware detection device through the hardware interface after the parameters are set.

[0008] In the present invention, when detecting the interface managed by the main control chip, the detection can be directly realized through the processes of opening the interface, obtaining interface parameters, setting parameters, and controlling the interaction between the interface and the hardware detection device, thereby realizing accurate detection of the relevant hardware interface.

[0009] In an optional embodiment, the distributed power supply access unit also includes a coprocessor. When the hardware interface to be tested is a second CAN interface managed by the coprocessor, an interface test frame is sent to the hardware detection device based on the hardware interface to be tested, including: sending a CAN protocol frame for opening the second CAN interface to the coprocessor, the CAN protocol frame is used to control the opening of the second CAN interface after being parsed by the coprocessor; receiving a first reporting frame sent by the coprocessor after controlling the second CAN interface to be opened; when the first reporting frame is an opening failure, stopping the test; when the first reporting frame is an opening success, sending a first parameter message frame to the coprocessor based on the first reporting frame; receiving the parameters of the second CAN interface reported by the coprocessor according to the first parameter message frame; and reporting to the coprocessor based on the parameters of the second CAN interface. The processor sends a first parameter setting frame, and the first parameter setting frame is used to perform parameter setting of the second CAN interface after being parsed by the coprocessor; the processor receives a first parameter result frame sent by the coprocessor after performing parameter setting of the second CAN interface; when the first parameter result frame indicates that the parameter setting fails, the test is stopped; when the first parameter result frame indicates that the parameter setting is successful, the processor sends a first test frame to the coprocessor based on the first parameter result frame, and the first test frame is used to send an interface test frame to the hardware detection device based on the second CAN interface after being parsed by the coprocessor; and receives return data after the hardware detection device verifies the interface test frame, including: receiving a first protocol result frame reported by the coprocessor, and the first protocol result frame is generated by the coprocessor according to the return data after the hardware detection device verifies the interface test frame.

[0010] In an optional embodiment, the distributed power supply access unit also includes a private protocol chip, the private protocol chip includes a coprocessor, a first expansion chip and a second expansion chip, the hardware interface to be tested also includes three groups of expansion interfaces, the three groups of expansion interfaces are respectively managed by the coprocessor, the first expansion chip and the second expansion chip, each group of expansion interfaces includes two 485 interfaces; based on the hardware interface to be tested, an interface test frame is sent to the hardware detection device, including: sending a 485 protocol frame for opening the 485 interface to the private protocol chip, the 485 protocol frame is used to control the opening of the 485 interface after being parsed by the private protocol chip; receiving a second reporting frame sent by the private protocol chip after controlling the opening of the 485 interface; when the second reporting frame is an opening failure, stopping the test; when the second reporting frame is an opening success, sending a second parameter message frame to the private protocol chip based on the second reporting frame; receiving the private protocol chip according to the second parameter message frame; The method comprises the following steps: reporting parameters of the 485 interface in two parameter message frames; sending a second parameter setting frame to the private protocol chip based on the parameters of the 485 interface, the second parameter setting frame being used for being parsed by the private protocol chip to perform parameter setting of the 485 interface; receiving a second parameter result frame sent by the private protocol chip after performing parameter setting of the 485 interface; stopping the test when the second parameter result frame indicates that the parameter setting fails; sending a second test frame to the private protocol chip based on the second parameter result frame when the parameter setting succeeds, the second test frame being used for being parsed by the private protocol chip to send an interface test frame to the hardware detection device based on the 485 interface; receiving return data after the hardware detection device verifies the interface test frame, including: receiving a second protocol result frame reported by the private protocol chip, the second protocol result frame being generated by the private protocol chip according to return data after the hardware detection device verifies the interface test frame.

[0011] In the present invention, for the detection of the second CAN interface and the extended interface managed by the coprocessor or the extended chip, the reliability of the detection implementation is guaranteed through the interaction between the main control chip and the coprocessor or the extended chip.

[0012] In an optional embodiment, the private protocol chip includes a test frame processing module, and the two interfaces in each group of extended interfaces include a forwarding 485 interface and a receiving 485 interface. The forwarding 485 interface is used to obtain preset data and send it to the receiving 485 interface through the distributed power supply access unit when applied; the test frame processing module is used to change the data transmission mode of the forwarding 485 interface after receiving the interface test frame, and control the forwarding 485 interface to send the interface test frame to the hardware detection device.

[0013] In the present invention, for the detection of the 485 interface which does not output data in actual application, a test frame processing module is set to change the data transmission mode in the detection process, thereby ensuring the reliable detection.

[0014] In an optional embodiment, the hardware interface to be tested also includes a telesignaling interface, and the telesignaling interface is connected to a relay in a hardware detection device. The method also includes: when the hardware interface to be tested is a telesignaling interface, obtaining a first telesignaling state of the telesignaling interface; when the first telesignaling state meets preset requirements, sending a relay control instruction to the hardware detection device based on the first 485 interface or the second 485 interface; within a preset time of sending the relay control instruction, obtaining a second telesignaling state of the telesignaling interface; and generating a telesignaling result frame according to the second telesignaling state.

[0015] In the present invention, the first telesignal state is obtained before the telesignal test to check whether the telesignal is in a normally open state before the uncoordinated device test, thereby avoiding the situation of continuous welding before the telesignal test.

[0016] In an optional embodiment, the hardware interface to be tested also includes multiple voltage interfaces, and the method also includes: sending a voltage interface test frame to the hardware detection device based on the first 485 interface or the second 485 interface, the voltage interface test frame is used to be parsed by the hardware detection device to determine the voltage interface to be tested, and collect the voltage of the voltage interface to be tested; based on the first 485 interface or the second 485 interface, receiving the voltage detection result generated by the hardware detection device according to the voltage.

[0017] In the second aspect, the present invention provides a hardware detection device for a distributed power supply access unit, the distributed power supply access unit includes multiple hardware interfaces and a main control chip, the multiple hardware interfaces are connected to the hardware detection device, the device is applied to the main control chip, and the device includes: a test frame receiving module, used to receive an external input message test frame; a test interface determination module, used to parse the message test frame and determine the hardware interface to be tested; a test frame sending module, used to send an interface test frame to the hardware detection device based on the hardware interface to be tested; a data receiving module, used to receive the return data after the hardware detection device verifies the interface test frame; a test result generation module, used to generate a test result frame according to the return data.

[0018] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the hardware detection method of the distributed power supply access unit of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0019] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the hardware detection method for a distributed power supply access unit of the first aspect or any corresponding embodiment thereof.

[0020] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the hardware detection method for a distributed power supply access unit of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a flow chart of a hardware detection method for a distributed power supply access unit according to an embodiment of the present invention;

[0023] Figure 2 is a structural block diagram of a distributed power supply access unit according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the connection relationship between a distributed power supply access unit and a hardware detection device according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of the structure of a message test frame according to an embodiment of the present invention;

[0026] Figure 5 is a flowchart of a hardware detection method for a distributed power supply access unit according to an embodiment of the present invention;

[0027] Figure 6 is a flow chart of another hardware detection method of a distributed power supply access unit according to an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of the internal structure and function of a distributed power supply access unit according to an embodiment of the present invention;

[0029] Figure 8 is a structural block diagram of a detection device for a distributed power supply access unit according to an embodiment of the present invention;

[0030] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0032] According to an embodiment of the present invention, an embodiment of a hardware detection method for a distributed power supply access unit is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] In this embodiment, a hardware detection method for a distributed power supply access unit is provided. Figure 1 is a flowchart of a hardware detection method for a distributed power supply access unit according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0034] Step S101, receiving an externally input message test frame.

[0035] Specifically, Figure 2 As shown, the distributed power access unit includes multiple hardware interfaces and a main control chip, wherein the multiple hardware interfaces include Figure 2 The two CAN interfaces, two 485 interfaces, one 12V interface and one remote signal interface are shown in the lower left corner. In addition, the hardware interface also includes an expansion interface with a 12V interface and a 485 interface. For these hardware interfaces, the main control chip is used Figure 2 The management of one CAN interface, two 485 interfaces, one 12V interface and one remote signal interface shown in the lower left corner. At the same time, in addition to the main control chip, the distributed power access unit also includes a coprocessor and an expansion slot chip (referred to as expansion chip) installed in two expansion slots. The coprocessor and expansion chip realize the management of other hardware interfaces except the main control chip management interface.

[0036] At the same time, in order to enable the distributed power access unit to have the monitoring function of the distributed photovoltaic power station, the distributed power access unit also includes a Bluetooth module, a carrier module, a metering module, a power management module and a storage module. In addition, the distributed power access unit can use the J-link tool to realize the burning of various functions in the chip.

[0037] In this embodiment, in order to detect multiple hardware interfaces in the distributed power access unit, a hardware detection device is provided. The hardware detection device includes an interface corresponding to the hardware interface and a processing chip. Figure 3 As shown, each CAN interface in the distributed power access unit includes signal lines H1, L1 or H2, L2. At the same time, each CAN interface is connected to the CAN interface in the hardware detection device through two signal lines for detection. For the two 485 interfaces managed by the main control chip in the hardware interface, each 485 interface includes two signal lines A1, B1 or A2, B2. The two 485 interfaces are connected to the 485 interface on the hardware detection device through signal lines for detection. The 12V interface and the remote signal interface in the hardware interface are also connected to the voltage interface and the remote signal interface in the hardware detection device to realize the detection of the corresponding interface.

[0038] In addition, there are three groups of expansion interfaces in the hardware interface, which are managed by a coprocessor and two expansion chips respectively. Each group of expansion interfaces includes one 12V interface and two 485 interfaces. The 12V interface is connected to the voltage interface in the hardware detection device for detection, and the 485 interface is connected to the 485 interface in the hardware detection device for detection.

[0039] In this embodiment, when the hardware interface is detected, the host computer can send a message test frame to the distributed power access unit, and the distributed power access unit performs signal interaction with the hardware detection device according to the message test frame. The format of the message test frame is as follows: Figure 4 As shown, it includes frame header, frame length, test frame command, frame sequence number, test object, frame check and frame tail. Since the hardware interface in the distributed power access unit includes multiple types, the hardware interface to be tested can be distinguished by the message test frame sent by the host computer, for example, it can be distinguished by the test object in the message test frame. In addition, the message test frame sent by the host computer can be received and processed by the main control chip in the distributed power access unit.

[0040] Step S102, parse the message test frame to determine the hardware interface to be tested. Specifically, after receiving the message test frame, the main control chip first parses the test frame to determine the specific test object. The test object is matched to the corresponding hardware interface for detection. In addition, if the test object obtained by parsing cannot be matched to the relevant hardware interface, the main control chip returns an error frame to the host computer, and the host computer displays the error frame to prompt the operator.

[0041] Step S103, based on the hardware interface to be tested, an interface test frame is sent to the hardware detection device. Specifically, after the specific hardware interface is determined by the message test frame received this time, an interface test frame is sent to the hardware detection device through the corresponding hardware interface. The interface test frame sent contains relevant parameters of the corresponding hardware interface.

[0042] Step S104, receiving the returned data after the hardware detection device verifies the interface test frame. Specifically, after receiving the interface test frame, the hardware detection device parses and processes it through its internal processing chip, and verifies the content and format of the parsed data, and then returns the data through the corresponding hardware interface after verification. Among them, if the main control chip does not receive the returned data after sending the interface test frame for a period of time, it returns an error frame to the upper computer and terminates the test.

[0043] Step S105, generating a test result frame according to the returned data. Specifically, after receiving the returned data, the main control chip needs to parse and verify the returned data, and generate a test result frame according to the verification result. The test result frame includes a qualified test or a failed test. Whether it is qualified or not is determined according to the parsing and verification result of the returned data. In addition, the generated test result frame can be sent to the host computer, and the host computer obtains the result and writes it back to the database of the local server to facilitate other personnel to view the test record of the table number. This achieves the traceability of the test results.

[0044] The hardware detection method for a distributed power access unit provided in an embodiment of the present invention connects the hardware interface and the hardware detection device in the distributed power access unit, and sends a message test frame to the distributed power access unit. The distributed power access unit performs signal interaction with the hardware detection device according to the message test frame to realize the detection of each hardware interface. Therefore, based on this method, automatic production line testing of the distributed power access unit can be realized, saving production cost and time.

[0045] In this embodiment, a hardware detection method for a distributed power access unit is provided. The distributed power access unit includes multiple hardware interfaces and a main control chip. The multiple hardware interfaces are connected to a hardware detection device. The method is applied to the main control chip. The method includes the following steps:

[0046] Step S201: Receive an externally input message test frame. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0047] Step S202: parse the message test frame to determine the hardware interface to be tested. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0048] Step S203: sending an interface test frame to the hardware detection device based on the hardware interface to be tested.

[0049] Specifically, when the hardware interface to be tested is the first CAN interface, the first 485 interface or the second 485 interface managed by the main control chip, the above step S203 includes:

[0050] Step S2031, controlling the hardware interface to be tested to open.

[0051] Step S2032, obtaining parameters of the opened hardware interface and setting the parameters.

[0052] Step S2033: Send an interface test frame to the hardware detection device through the hardware interface with parameter settings.

[0053] For multiple hardware interfaces in the distributed power access unit, the main control chip manages one CAN interface, two 485 interfaces, one 12V interface and one remote signaling interface. When the above step S202 is used to determine that the hardware interface to be tested is one CAN interface or any one 485 interface, the above step S203 can be used to implement the sending of the interface test frame.

[0054] Specifically, when the hardware interface to be tested is determined to be any one of the first CAN interface, the first 485 interface or the second 485 interface by parsing the message test frame, the corresponding interface is first controlled to be opened. If the opening fails, an error frame is returned to the upper computer. After the opening is successful, the parameters of the corresponding interface such as the baud rate are obtained, and an error frame is also returned if the acquisition fails. After the parameters are successfully obtained, the parameters are configured according to the obtained parameters, that is, the obtained parameters are adjusted to meet the test requirements. When setting the parameters, the corresponding connection interface in the hardware detection device can be set. For example, for the first CAN interface, its parameters are set to be consistent with the parameters of the CAN serial port in the hardware detection device.

[0055] After the parameter setting is completed, the interface test frame is sent through the corresponding hardware interface. For example, if the hardware interface to be tested is the first CAN interface, a specified interface test frame carrying the CANID is sent. When the hardware interface to be tested is a 485 interface, a fixed message can also be pre-set as an interface test frame. It should also be noted that under normal circumstances, the parameters during interface testing are different from the parameters during actual application. Therefore, after the test is completed, the parameters of the interface need to be adjusted back to the values ​​before the test based on the parameters obtained before the test.

[0056] In addition, the first 485 interface and the second 485 interface can be connected to one 485 interface of the hardware detection device, thereby reducing the processing of business logic. At the same time, the hardware detection device will not need to set up multiple processing chips due to too many 485 interfaces, thereby reducing the development workload and chip costs.

[0057] Step S204: Receive the returned data after the hardware detection device verifies the interface test frame. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0058] Step S205: Generate a test result frame based on the returned data. Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0059] In this embodiment, a hardware detection method for a distributed power access unit is provided. The distributed power access unit includes multiple hardware interfaces and a main control chip. The multiple hardware interfaces are connected to a hardware detection device. The method is applied to the main control chip. The method includes the following steps:

[0060] Step S301, receiving an external input message test frame; see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0061] Step S302: parse the message test frame to determine the hardware interface to be tested; see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0062] Step S303: sending an interface test frame to a hardware detection device based on the hardware interface to be tested.

[0063] Specifically, when the hardware interface to be tested is the second CAN interface managed by the coprocessor, the above step S303 includes:

[0064] Step S3031, sending a CAN protocol frame for opening the second CAN interface to the coprocessor, where the CAN protocol frame is used to control the opening of the second CAN interface after being parsed by the coprocessor.

[0065] Step S3032, receiving the first reporting frame sent after the coprocessor controls the second CAN interface to be opened.

[0066] Step S3033: When the first reporting frame fails to be opened, stop the test.

[0067] Step S3034: When the first reporting frame is opened successfully, a first parameter message frame is sent to the coprocessor based on the first reporting frame.

[0068] Step S3035, receiving the parameters of the second CAN interface reported by the coprocessor according to the first parameter message frame.

[0069] Step S3036: Send a first parameter setting frame to the coprocessor based on the parameters of the second CAN interface. The first parameter setting frame is used to perform parameter setting of the second CAN interface after being parsed by the coprocessor.

[0070] Step S3037, receiving a first parameter result frame sent by the coprocessor after performing parameter setting of the second CAN interface.

[0071] Step S3038: When the first parameter result frame indicates that parameter setting fails, the test is stopped.

[0072] Step S3039, when the first parameter result frame indicates that the parameter setting is successful, a first test frame is sent to the coprocessor based on the first parameter result frame, and the first test frame is used to be parsed by the coprocessor and then send an interface test frame to the hardware detection device based on the second CAN interface.

[0073] Specifically, the second CAN interface in the distributed power access unit is managed by the coprocessor, but the coprocessor cannot communicate with the host computer to obtain the message test frame, so the test of the second CAN interface is controlled by the main control chip to control the coprocessor to perform related actions. When the main control chip parses the message test frame to determine that the hardware interface to be tested is the second CAN interface, it sends a CAN protocol frame to the coprocessor based on a private protocol such as the TTL (Transistor-Transistor Logic) group. After receiving the CAN protocol frame, the coprocessor controls the corresponding second CAN interface to open. And according to the opening result, the first reporting frame is sent to the main control chip, and the first reporting frame includes the result of whether it is opened. When the first reporting frame received by the main control chip contains a first reporting frame that is not successfully opened or the coprocessor is not replied within the preset time, an error frame is returned to the host computer.

[0074] When the first reporting frame contains the result of successful opening, the main control chip continues to send the first parameter message frame to the coprocessor to obtain the second CAN interface. After receiving the first parameter message frame, the coprocessor obtains the parameters of the second CAN interface and reports it to the main control chip. The main control chip then sends the first parameter setting frame to the coprocessor based on the obtained parameters. After receiving the first parameter result frame, the coprocessor sets the parameters of the second CAN interface and sends the first parameter result frame to the main control chip after the setting is completed. After receiving the first parameter result frame, the main control chip further sends a test frame to the coprocessor. After receiving the test frame, the coprocessor controls the second CAN interface to send an interface test frame, i.e., a CAN test frame, to the hardware detection device. When setting the parameters, the parameters of the second CAN interface are set to be consistent with the parameters of the corresponding interface in the corresponding hardware detection device to ensure normal communication.

[0075] In an optional implementation, the distributed power access unit also includes a private protocol chip, which includes a coprocessor, a first expansion chip, and a second expansion chip. The hardware interface to be tested also includes three groups of expansion interfaces, which are respectively managed by the coprocessor, the first expansion chip, and the second expansion chip. Each group of expansion interfaces includes two 485 interfaces; wherein, the selection of the two expansion chips can be the same as that of the coprocessor. At the same time, since the coprocessor cannot communicate directly with the host computer, when testing the expansion interface, similar to the test of the second CAN interface, it also needs to be controlled by the main control chip. Specifically, the above step S303 also includes:

[0076] Step S30311, sending a 485 protocol frame for opening the 485 interface to the private protocol chip, the 485 protocol frame is used to control the opening of the 485 interface after being parsed by the private protocol chip.

[0077] Step S30312, receiving the second reporting frame sent after the private protocol chip controls the 485 interface to be opened.

[0078] Step S30313: When the second reporting frame fails to be opened, stop the test.

[0079] Step S30314: When the second reporting frame is opened successfully, a second parameter message frame is sent to the private protocol chip based on the second reporting frame.

[0080] Step S30315, receiving the parameters of the 485 interface reported by the private protocol chip according to the second parameter message frame.

[0081] Step S30316: Send a second parameter setting frame to the private protocol chip based on the parameters of the 485 interface. The second parameter setting frame is used to perform parameter setting of the 485 interface after being parsed by the private protocol chip.

[0082] Step S30317, receiving a second parameter result frame sent by the proprietary protocol chip after setting the parameters of the 485 interface.

[0083] Step S30318: When the second parameter result frame indicates that parameter setting fails, the test is stopped.

[0084] Step S30319, when the second parameter result frame indicates that the parameter setting is successful, a second test frame is sent to the private protocol chip based on the second parameter result frame, and the second test frame is used to be parsed by the private protocol chip and then send an interface test frame to the hardware detection device based on the 485 interface.

[0085] Based on the above steps, when testing the extended interface, its test process is similar to the test process of the second CAN interface, that is, it also includes the steps of opening the interface, obtaining parameters, setting parameters, and sending test frames. The specific processing process can refer to the test process of the second CAN interface, which will not be repeated here. When setting parameters, the parameters of the 485 interface are set to be consistent with the parameters of the corresponding interface in the corresponding hardware detection device to ensure normal communication.

[0086] In addition, in actual application scenarios, for the two 485 interfaces in each group of expansion interfaces, one 485 interface is connected to the inverter, and the other 485 interface is connected to the 4G stick. The 485 interface connected to the 4G stick obtains the relevant inverter data input from the outside through the 4G stick, and sends it to the 485 interface connected to the inverter inside the distributed power access unit, and then the 485 interface sends it to the inverter. Therefore, in actual applications, one 485 interface in the expansion interface only receives data and does not send data outward, that is, the two 485 interfaces in the expansion interface can be respectively called the forwarding 485 interface (connected to the 4G stick) and the receiving 485 interface. Among them, for the forwarding 485 interface, since it does not send data outward in actual applications, in order to realize the test of the forwarding 485 interface, a test frame processing module is set in the coprocessor or expansion chip in this embodiment. When the coprocessor or expansion chip receives the second test frame, the data transmission mode of the forwarding 485 interface is changed, that is, the forwarding 485 interface is not allowed to send the interface test frame to the receiving 485 interface through the distributed power supply access unit, but the interface test frame is sent to the hardware detection device, and the detection is realized through the cooperation of the hardware detection device.

[0087] It should be noted that the six 485 interfaces in the three groups of expansion interfaces can be connected to one 485 interface of the hardware detection device, thereby reducing the processing of business logic. At the same time, the hardware detection device will not need to set up multiple processing chips due to too many 485 interfaces, thereby reducing the development workload and chip costs.

[0088] Step S304, receiving the returned data after the hardware detection device verifies the interface test frame.

[0089] Specifically, when the hardware interface to be tested is the second CAN interface, the above step S304 includes:

[0090] Step S3041, receiving a first protocol result frame reported by the coprocessor, where the first protocol result frame is generated by the coprocessor according to return data after the hardware detection device verifies the interface test frame.

[0091] When the hardware interface to be tested is any 485 interface in the extended interface, the above step S304 includes:

[0092] Step S30411, receiving a second protocol result frame reported by the private protocol chip, where the second protocol result frame is generated by the private protocol chip according to return data after the hardware detection device verifies the interface test frame.

[0093] It should be noted that when testing the second CAN interface or the extended interface, it is necessary to forward the message test frame to the coprocessor or the expansion chip through the main control chip. Therefore, after the coprocessor or the expansion chip receives the return data after verification by the hardware detection device and generates a protocol result frame, it is necessary to return the protocol result frame to the main control chip first, and then the main control chip generates a test result frame and sends it to the host computer.

[0094] Step S305: Generate a test result frame based on the returned data. Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0095] In the present invention, since the distributed power supply access unit has many interfaces, one chip may not be able to carry many interfaces. Therefore, the dual-chip architecture of the main control chip and the coprocessor is adopted in this embodiment, so that more interfaces can be expanded. Secondly, the advantage of the dual-chip architecture can handle more business logics. The two do not interfere with each other, allowing the coprocessor to collaborate on some simple operations, and the main control chip has more resources to do more important things, which will also greatly improve the operating efficiency.

[0096] In this embodiment, a hardware detection method for a distributed power access unit is provided. The distributed power access unit includes multiple hardware interfaces and a main control chip. The multiple hardware interfaces are connected to a hardware detection device. The method is applied to the main control chip. The method includes the following steps:

[0097] Step S401: Receive an externally input message test frame. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0098] Step S402: parse the message test frame to determine the hardware interface to be tested; see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0099] Step S403: Send an interface test frame to the hardware detection device based on the hardware interface to be tested; see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0100] Step S404: Receive the returned data after the hardware detection device verifies the interface test frame; see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0101] Step S405: Generate a test result frame based on the returned data. Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0102] Step S406, when the hardware interface to be tested is a telesignaling interface, obtain the first telesignaling state of the telesignaling interface; when the first telesignaling state meets the preset requirements, send a relay control instruction to the hardware detection device based on the first 485 interface or the second 485 interface; within the preset time of sending the relay control instruction, obtain the second telesignaling state of the telesignaling interface; generate a telesignaling result frame according to the second telesignaling state.

[0103] Specifically, when testing the telesignaling interface, first obtain the first telesignaling state of the current telesignaling interface, and determine whether the first telesignaling state meets the preset requirements, that is, determine whether the telesignaling interface is in a normally open state before the test, so as to avoid continuous welding before testing the telesignaling. When the first telesignaling state meets the preset requirements, the main control chip sends a control instruction to the relay in the hardware detection device through any one of the two 485 interfaces it manages, such as sending a closing instruction. Since the telesignaling interface and the relay are connected, the second telesignaling state of the telesignaling interface is obtained again within a preset time after sending the instruction. If the relay is closed according to the closing instruction and the telesignaling interface is normal, the second telesignaling state will change compared to the first telesignaling state, and a telesignaling result frame can be generated accordingly. After receiving the telesignaling result frame, the main control chip can report it to the host computer.

[0104] Step S407, based on the first 485 interface or the second 485 interface, a voltage interface test frame is sent to the hardware detection device, the voltage interface test frame is used to be parsed by the hardware detection device to determine the voltage interface to be tested, and collect the voltage of the voltage interface to be tested; based on the first 485 interface or the second 485 interface, the voltage detection result generated by the hardware detection device according to the voltage is received.

[0105] Specifically, the hardware interface of the distributed power access unit includes multiple voltage interfaces, such as the 12V voltage interface managed by the main control chip and the 12V voltage interface included in each group of extended interfaces. When the voltage interface is detected, the main control chip can send a voltage interface test frame to the hardware detection device through the first 485 interface or the second 485 interface. The voltage interface test frame contains the voltage interface to be tested. After the hardware detection device receives the voltage interface test frame, it determines the voltage interface to be tested, collects the voltage of the corresponding voltage interface, and generates a voltage detection result based on the collected voltage value, such as whether the collected voltage value of the 12V voltage interface is around 12V, and returns the voltage detection result to the main control chip through the first 485 interface or the second 485 interface. After receiving the voltage detection result, the main control chip returns to the host computer.

[0106] As a specific application example of the embodiment of the present invention, the hardware detection method of the distributed power supply access unit can be implemented by the following process:

[0107] like Figure 5 As shown in the figure, when the distributed power access unit is powered on, the main control chip is initialized and runs, and the relevant test objects are allocated in the memory and the corresponding test program is generated. During the test, the message test frame is sent on the PC host computer, and the main control chip recognizes the message test frame sent by the serial port, and performs parsing and judgment. If the relevant test item object is not found in the memory table, an error frame is returned to the host computer, and the host computer displays the return frame to the operator to inform whether the test is successful or not. If the table lookup is successful, jump to the corresponding test program according to the specific test object to process different functional test logics. For example, 12V test, remote signal test, CAN test, 485 test, etc. are performed by cooperating with the hardware detection device. Specific functional tests to detect the quality of hardware functions will also package different frames and report them to the host computer through the serial port for display.

[0108] In specific tests, such as Figure 6 As shown, the host computer sends a message test frame to the main control chip. After receiving and parsing, if the main control chip determines that it needs to manage the first CAN interface CAN1 or the two 485 interfaces, i.e., 485-1 or 485-2, the main control chip tests the interface through the test process such as opening the control interface, obtaining parameters, setting parameters, and sending interface test frames to the device through the control interface. For the test of the remote signal interface, the test result is obtained by sending instructions to the relay in the hardware detection device and the remote signal state of the remote signal interface. For the test of the 12V voltage interface, the voltage interface is tested by collecting the voltage through the hardware detection device.

[0109] When the main control chip receives and analyzes the information and determines that the interface managed by the coprocessor or expansion chip is to be tested, the main control chip first converts the message test frame to generate a protocol frame of the private protocol and sends it to the coprocessor or expansion chip. After receiving the protocol frame, the coprocessor controls the relevant interface such as the second CAN interface CAN2 to perform the corresponding test. In the actual application scenario, for each group of expansion chips including two 485 interfaces managed by the coprocessor and the expansion chip, the two 485 interfaces are connected to the 4G stick and the inverter respectively. The 485 interface connected to the 4G stick obtains the relevant inverter data of the external input through the 4G stick, and sends it to the 485 interface connected to the inverter inside the distributed power access unit, and the 485 interface sends it to the inverter. That is, the 485 interface connected to the 4G stick does not send data outward in actual applications. In order to realize the test of the 485 interface, a test frame processing module is set in the coprocessor or expansion chip in this embodiment. When the coprocessor or expansion chip receives the protocol frame, the data transmission mode of the forwarding 485 interface is changed, that is, the forwarding 485 interface is not allowed to send the interface test frame to the 485 interface connected to the inverter through the distributed power supply access unit, but the interface test frame is sent to the hardware detection device, and the detection is realized through the cooperation of the hardware detection device.

[0110] Specifically, Figure 7 As shown, the distributed power access unit includes a main control module, a metering module and a conversion module (expansion chip). Among them, the main control module includes an application, an operating system and hardware peripherals. The application includes a main control chip and a coprocessor. The main control chip completes the exchange task (AC sampling task) through data acquisition, protocol processing, serial port processing and event reporting. At the same time, the main control chip can also realize parameter verification, light display, safety management, log tasks, event reporting, data storage and local control. Processing. Since the coprocessor cannot communicate directly with the host computer, the TTL group protocol is used to realize data interaction through the serial port between the main control chip and the coprocessor. In the operating system, it includes drivers, RTOS (Real Time Operate System, real-time operating system), task management, inter-task communication, BootLoader (boot loader), system components, memory management, interrupt service and clock management, etc. The drivers include IIC, CAN, SPI, UART, GPIO and Bluetooth. Hardware peripherals include 485, CAN, ESAM (Embedded Secure Access Module), EEPROM (Electrically Erasable Programmable Read Only Memory), FLASH, LED, ADC, watchdog, remote signal, Bluetooth, etc.

[0111] The metering module includes a management chip (i.e., a real-time clock chip (RTC)) and a metering chip. The management chip and the metering chip communicate with each other using SPI (Serial Peripheral Interface). The conversion module uses the same type of chip as the coprocessor. The conversion module also includes an application, an operating system, and hardware peripherals. Since the conversion module cannot communicate directly with the host computer, the TTL group protocol is also used to achieve data interaction through the serial port between the main control chip and the conversion module. The operating system in the conversion module includes UART driver and GPIO driver, and the hardware peripherals include two 485 serial ports.

[0112] Based on the structure of the above-mentioned distributed power access unit, the I2C pin and EEPROM can store the configured data such as device ID, address and communication protocol settings, so it is also necessary to detect the two. For the EEPROM test, the hardware abstraction layer can be called to write a value to the address and then compare the read value of the address to determine whether the function is complete. In addition, in order to ensure the information security of the distributed power unit, the SPI test can be implemented by judging and detecting the serial number obtained by ESAM. For the test of FLASH, operations such as reading and erasing blocks and writing can be used to verify whether the data acquisition is achieved normally. For the metering module in the distributed power access unit, the test can be performed in the following way: the main control chip is used to send the metering data frame such as voltage to the management chip, and the management chip retrieves the data in the metering chip and returns it. If it can be successfully acquired, it is judged as successful.

[0113] When the hardware detection method of the distributed power access unit of the present invention is adopted in practical applications, such as when operating the production line in a workshop, all the hardware interfaces can be fully contacted with the device by pressing, and then the device can be powered on. The workshop staff only needs to fill in the address of the corresponding product into the corresponding host computer, and select various programs to be tested by clicking the PC host computer with the mouse. The test of all items will start automatically. At this time, the assembly line operation cooperates with the device to perform functional detection. Finally, the results of all test items are printed on the interface, and the error items are uploaded to the server for management personnel and maintenance personnel to view. Therefore, employees do not need to pay attention to the internal implementation method, which greatly simplifies the process and improves efficiency.

[0114] In this embodiment, a hardware detection device for a distributed power access unit is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and will not be repeated hereafter. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0115] This embodiment provides a hardware detection device for a distributed power access unit. The distributed power access unit includes multiple hardware interfaces and a main control chip. The multiple hardware interfaces are connected to the hardware detection device. The device is applied to the main control chip, such as Figure 8 As shown, the device comprises:

[0116] The test frame receiving module 81 is used to receive a message test frame input from the outside.

[0117] The test interface determination module 82 is used to parse the message test frame and determine the hardware interface to be tested.

[0118] The test frame sending module 83 is used to send an interface test frame to the hardware detection device based on the hardware interface to be tested.

[0119] The data receiving module 84 is used to receive the returned data after the hardware detection device verifies the interface test frame.

[0120] The test result generating module 85 is used to generate a test result frame according to the returned data.

[0121] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0122] The embodiment of the present invention also provides a computer device having the above Figure 8 The hardware detection device of the distributed power supply access unit is shown.

[0123] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0124] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0125] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0126] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0127] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0128] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0129] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0130] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0131] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A hardware detection method for a distributed power supply access unit, characterized in that: The distributed power supply access unit includes multiple hardware interfaces and a main control chip, and the multiple hardware interfaces are connected to a hardware detection device. The method is applied to the main control chip, and the method includes: Receive external input message test frame; Parsing the message test frame to determine the hardware interface to be tested; Sending an interface test frame to a hardware detection device based on a hardware interface to be tested; Receiving the returned data after the hardware detection device verifies the interface test frame; Generate a test result frame according to the returned data; The distributed power supply access unit further includes a coprocessor. When the hardware interface to be tested is a second CAN interface managed by the coprocessor, an interface test frame is sent to the hardware detection device based on the hardware interface to be tested, including: Sending a CAN protocol frame for opening the second CAN interface to the coprocessor, wherein the CAN protocol frame is used to control the opening of the second CAN interface after being parsed by the coprocessor; Receiving a first reporting frame sent after the coprocessor controls the second CAN interface to be opened; When the first reporting frame fails to be opened, stopping the test; When the first reporting frame is opened successfully, sending a first parameter message frame to the coprocessor based on the first reporting frame; receiving parameters of the second CAN interface reported by the coprocessor according to the first parameter message frame; Sending a first parameter setting frame to the coprocessor based on the parameters of the second CAN interface, wherein the first parameter setting frame is used to perform parameter setting of the second CAN interface after being parsed by the coprocessor; Receiving a first parameter result frame sent by the coprocessor after performing parameter setting of the second CAN interface; When the first parameter result frame indicates that parameter setting fails, stopping the test; When the first parameter result frame indicates that the parameter setting is successful, a first test frame is sent to the coprocessor based on the first parameter result frame, wherein the first test frame is used to be parsed by the coprocessor and then send an interface test frame to the hardware detection device based on the second CAN interface; Receiving the returned data after the hardware detection device verifies the interface test frame, comprising: A first protocol result frame reported by the coprocessor is received, where the first protocol result frame is generated by the coprocessor according to return data after the hardware detection device verifies the interface test frame.

2. The method according to claim 1, characterized in that When the hardware interface to be tested is the first CAN interface, the first 485 interface or the second 485 interface managed by the main control chip, sending an interface test frame to the hardware detection device based on the hardware interface to be tested includes: Control the hardware interface to be tested to open; Obtaining parameters of the opened hardware interface and setting the parameters; Send an interface test frame to the hardware detection device through the hardware interface after parameter setting.

3. The method according to claim 1, characterized in that The distributed power access unit also includes a private protocol chip, which includes a coprocessor, a first expansion chip and a second expansion chip. The hardware interface to be tested also includes three groups of expansion interfaces, which are respectively managed by the coprocessor, the first expansion chip and the second expansion chip, and each group of expansion interfaces includes two 485 interfaces. Sending an interface test frame to a hardware detection device based on a hardware interface to be tested includes: Sending a 485 protocol frame for opening the 485 interface to the private protocol chip, wherein the 485 protocol frame is used to control the opening of the 485 interface after being parsed by the private protocol chip; Receiving a second reporting frame sent after the private protocol chip controls the 485 interface to be opened; When the second reporting frame fails to be opened, stop the test; When the second reporting frame is opened successfully, sending a second parameter message frame to the private protocol chip based on the second reporting frame; Receiving the parameters of the 485 interface reported by the private protocol chip according to the second parameter message frame; Sending a second parameter setting frame to the private protocol chip based on the parameters of the 485 interface, wherein the second parameter setting frame is used to perform parameter setting of the 485 interface after being parsed by the private protocol chip; Receiving a second parameter result frame sent by the private protocol chip after performing parameter setting of the 485 interface; When the second parameter result frame indicates that parameter setting fails, stopping the test; When the second parameter result frame indicates that the parameter setting is successful, a second test frame is sent to the private protocol chip based on the second parameter result frame, and the second test frame is used to be parsed by the private protocol chip and then send an interface test frame to the hardware detection device based on the 485 interface; Receiving the returned data after the hardware detection device verifies the interface test frame, comprising: A second protocol result frame reported by the private protocol chip is received, where the second protocol result frame is generated by the private protocol chip according to return data after the hardware detection device verifies the interface test frame.

4. The method according to claim 3, characterized in that The private protocol chip includes a test frame processing module, and the two interfaces in each group of extended interfaces include a forwarding 485 interface and a receiving 485 interface. The forwarding 485 interface is used to obtain preset data and send it to the receiving 485 interface through the distributed power supply access unit when applied; the test frame processing module is used to change the data transmission mode of the forwarding 485 interface after receiving the interface test frame, and control the forwarding 485 interface to send an interface test frame to the hardware detection device.

5. The method according to claim 2, characterized in that: The hardware interface to be tested also includes a remote signaling interface, and the remote signaling interface is connected to a relay in the hardware detection device. The method also includes: When the hardware interface to be tested is a remote signaling interface, obtaining a first remote signaling state of the remote signaling interface; When the first remote signaling state meets the preset requirements, a relay control instruction is sent to the hardware detection device based on the first 485 interface or the second 485 interface; Within the preset time of sending the relay control command, obtaining the second remote signaling state of the remote signaling interface; A telesignaling result frame is generated according to the second telesignaling state.

6. The method according to claim 2, characterized in that The hardware interface to be tested further includes a plurality of voltage interfaces, and the method further includes: Sending a voltage interface test frame to the hardware detection device based on the first 485 interface or the second 485 interface, wherein the voltage interface test frame is used to be parsed by the hardware detection device to determine the voltage interface to be tested, and to collect the voltage of the voltage interface to be tested; A voltage detection result generated by the hardware detection device according to the voltage is received based on the first 485 interface or the second 485 interface.

7. A hardware detection device for a distributed power supply access unit, characterized in that: The distributed power supply access unit includes multiple hardware interfaces and a main control chip, and the multiple hardware interfaces are connected to a hardware detection device, which is applied to the main control chip. The device includes: A test frame receiving module, used for receiving an externally input message test frame; A test interface determination module, used for parsing the message test frame to determine the hardware interface to be tested; A test frame sending module, used for sending an interface test frame to a hardware detection device based on a hardware interface to be tested; A data receiving module, used for receiving the returned data after the hardware detection device verifies the interface test frame; A test result generating module, used for generating a test result frame according to the returned data; The distributed power supply access unit further includes a coprocessor. When the hardware interface to be tested is a second CAN interface managed by the coprocessor, an interface test frame is sent to the hardware detection device based on the hardware interface to be tested, including: Sending a CAN protocol frame for opening the second CAN interface to the coprocessor, wherein the CAN protocol frame is used to control the opening of the second CAN interface after being parsed by the coprocessor; Receiving a first reporting frame sent after the coprocessor controls the second CAN interface to be opened; When the first reporting frame fails to be opened, stopping the test; When the first reporting frame is opened successfully, sending a first parameter message frame to the coprocessor based on the first reporting frame; receiving parameters of the second CAN interface reported by the coprocessor according to the first parameter message frame; Sending a first parameter setting frame to the coprocessor based on the parameters of the second CAN interface, wherein the first parameter setting frame is used to perform parameter setting of the second CAN interface after being parsed by the coprocessor; Receiving a first parameter result frame sent by the coprocessor after performing parameter setting of the second CAN interface; When the first parameter result frame indicates that parameter setting fails, stopping the test; When the first parameter result frame indicates that the parameter setting is successful, a first test frame is sent to the coprocessor based on the first parameter result frame, wherein the first test frame is used to be parsed by the coprocessor and then send an interface test frame to the hardware detection device based on the second CAN interface; Receiving the returned data after the hardware detection device verifies the interface test frame, comprising: A first protocol result frame reported by the coprocessor is received, where the first protocol result frame is generated by the coprocessor according to return data after the hardware detection device verifies the interface test frame.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the hardware detection method for a distributed power supply access unit according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the hardware detection method for a distributed power supply access unit according to any one of claims 1 to 6.

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