A raman spectrum acquisition transmission circuit and a transmission method

Abstract

The application relates to a Raman spectrum acquisition transmission circuit and a transmission method, which comprise a communication module, a spectrum acquisition module and a ZYNQ; the communication module is connected with the ZYNQ and is used for receiving data information and transmitting the data information to the ZYNQ and sending the data information to a remote data center; the ZYNQ is connected with the spectrum acquisition module and is used for processing the data information, driving the spectrum acquisition module to acquire, processing digital signals and transmitting the digital signals to the remote data center through the communication module; the spectrum acquisition module is connected with the ZYNQ and is used for receiving instructions and acquiring, and converting spectrum signals into digital signals and transmitting the digital signals to the ZYNQ. The circuit can synchronously acquire spectrum data, geographical and time information, send the information to a server, improve data security and traceability, can be used in a scene with extremely high data quality requirement, avoids the problem of unmatched communication protocols, and ensures the high speed and stability of data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Raman spectrum analysis, in particular to a Raman spectrum acquisition and transmission circuit and a transmission method. BACKGROUND

[0002] Raman spectrum is a technology that uses the scattering characteristics of molecules to identify different substances. When light shines on a substance, most of it undergoes Rayleigh scattering, with no change in wavelength; while a small part of the light undergoes Raman scattering, with a change in wavelength, forming a characteristic spectrum that can be used to identify the substance, so it is widely used in substance identification and chemical analysis.

[0003] The existing Raman spectrum acquisition and transmission circuit faces the challenge of remote data transmission, mainly due to the lack of direct sending capability, relying on serial communication and host computer transfer, which not only limits the transmission speed, but also may introduce data security risks, affecting the authenticity and traceability of data, especially in application scenarios that require high data integrity, such as environmental monitoring and legal evidence.

[0004] In addition, the existing circuit cannot realize remote control, limiting its use in industrial applications that require real-time monitoring and rapid response, such as oil refining and chemical production, which also prevents online monitoring of the production process. The existing Raman spectrometer realizes remote transmission by introducing a computer to transfer remote control commands, which increases system complexity and may cause control command transmission delay, reducing the reliability and real-time performance of the system.

[0005] In terms of hardware, the chip scheme of the existing circuit, whether single ARM, single FPGA or ARM+FPGA combination, has performance limitations. FPGA performs well in parallel computing and low-latency applications, but is not as good as ARM in general computing tasks. Conversely, ARM is simpler and more efficient in Ethernet communication, but cannot meet the high real-time scenarios such as driving high-performance CMOS and AD converters in Raman acquisition circuits. The communication protocol between FPGA and ARM in the existing scheme also cannot meet the demand of high-speed data transmission.

[0006] In terms of power supply, the existing circuit usually uses USB interface for power supply, lacks dedicated power supply circuit design, and cannot provide stable and high-quality power supply, which is crucial for the stable operation of key devices such as high-precision CMOS and AD converters. SUMMARY

[0007] To address one or more of the problems in the prior art, the first aspect of the present application provides a Raman spectrum acquisition and transmission circuit, comprising: a communication module, a spectrum acquisition module, and a ZYNQ; wherein:

[0008] The communication module is connected with the ZYNQ, and is used for receiving data information from a remote data center and transmitting the data information to the ZYNQ, and sending data information from the ZYNQ to the remote data center;

[0009] The ZYNQ is connected with the spectrum acquisition module, and is used for processing data information transmitted through the communication module, and driving the spectrum acquisition module to acquire, and processing digital signals from the spectrum acquisition module and transmitting the digital signals to the remote data center through the communication module;

[0010] The spectrum acquisition module is connected with the ZYNQ, and is used for receiving instructions from the ZYNQ and acquiring, and converting acquired spectrum signals into digital signals and transmitting the digital signals to the ZYNQ.

[0011] According to the Raman spectrum transmission circuit provided in the embodiment of the application, the ZYNQ includes a PS and a FPGA, the PS includes an Ethernet module, an ARM, a DDR control module, and the PS and the FPGA communicate through an AXI interface; wherein:

[0012] The Ethernet module is connected with the communication module and the ARM respectively, and is used for analyzing data information from a remote data center, and sending the analyzed data to the ARM, and sending data from the ARM to the remote data center through the communication module;

[0013] The ARM is connected with the FPGA and the DDR control module, and is used for processing data analyzed by the Ethernet module, and sending processed instructions to the FPGA through the AXI interface, and reading data in the DDR control module and packaging the data, and sending the packaged data to the Ethernet module;

[0014] The FPGA is used for receiving instructions from the ARM through the AXI interface, so as to drive the spectrum acquisition module to acquire and convert spectrum signals, and can write acquisition information data into the DDR control module through the AXI interface in a DMA mode.

[0015] According to the Raman spectrum transmission circuit provided in the embodiment of the application, the FPGA includes an instruction analysis module, a CMOS driving module, an AD driving module, a RAM and an AXI DMA module; wherein:

[0016] The instruction analysis module is connected with the ARM and the CMOS driving module, and is used for receiving instructions from the ARM, and analyzing the instructions, and transmitting analysis results to the CMOS driving module;

[0017] The CMOS driving module is connected with the spectrum acquisition module, and is configured to drive the spectrum acquisition module to perform acquisition when the instruction analysis result is an acquisition start signal, and is configured to save an integration time into a register of the CMOS driving module when the instruction analysis result is an integration time signal.

[0018] The AD driving module is connected with the spectrum acquisition module and the RAM, and is configured to generate a driving signal to drive the spectrum acquisition module to perform analog-digital conversion, and write the converted digital signal into the RAM.

[0019] The RAM is connected to the AXI DMA module, and the AXI DMA module is connected to the PS through an AXI interface, and is configured to write the digital signal stored in the RAM into the DDR control module in the PS through the AXI interface in a DMA manner.

[0020] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the spectrum acquisition module comprises a CMOS, a signal conditioning circuit and an AD conversion circuit; wherein:

[0021] The CMOS is connected with the CMOS driving module and the signal conditioning circuit, and is configured to perform spectrum acquisition work according to the driving signal of the CMOS driving module, and output the spectrum signal to the signal conditioning circuit after photoelectric signal conversion.

[0022] The signal conditioning circuit is connected with the AD conversion circuit, and is configured to filter and amplify the spectrum signal from the CMOS, and transmit the spectrum signal to the AD conversion circuit.

[0023] The AD conversion circuit is connected with the AD driving module, and is configured to convert the spectrum signal from the signal conditioning circuit from an analog signal to a digital signal after receiving the driving signal from the AD driving module, and send the digital signal to the AD driving module.

[0024] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the circuit further comprises a GPS module, and the FPGA further comprises a GPS control module, wherein:

[0025] The GPS control module is connected with the AD driving module, the GPS module and the RAM respectively, and is configured to receive the GPS acquisition start signal sent from the AD driving module, control the GPS module to capture the signal from the global positioning system satellite, read the data of the GNSS protocol in the GPS module, extract the longitude and latitude and time information from the data, and store the information in the RAM.

[0026] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the FPGA further comprises a FIFO and a serial communication module; wherein:

[0027] The FIFO is connected with the AD driving module, and is configured to write the converted digital signal into the FIFO for cross-clock domain processing.

[0028] The serial communication module is connected with the host computer, the instruction analysis module and the FIFO, configured to receive the instruction information sent by the host computer and send the instruction information to the instruction analysis module for analysis, and further configured to read the spectrum data from the FIFO and send the data to the host computer through the serial communication circuit for on-site display and processing of the Raman spectrum.

[0029] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the circuit further comprises an anti-backflow circuit and a CH340; wherein:

[0030] The CH340 is a USB-to-serial chip, connected with the serial communication module and the anti-backflow circuit, and configured to realize conversion between the serial communication protocol of the Raman spectrum acquisition and transmission control circuit and the USB protocol of the host computer (computer).

[0031] The anti-backflow circuit is connected with the host computer, and is configured to prevent the USB-to-serial chip from being burned out by backflow current.

[0032] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the circuit further comprises a DDR3, which is connected with the DDR control module, configured to store the data information transmitted from the DDR control module for reading by the DDR control module.

[0033] Preferably, the circuit further comprises an SD card circuit, configured to store a program and burn the program into the circuit system when the circuit system is powered on.

[0034] According to the Raman spectrum transmission circuit provided in the embodiment of the present application, the working process of the FPGA control program is as follows:

[0035] S1, the program starts running;

[0036] S2, the module outputs three signals, including a clock control signal scl, a write data signal sdata and a write enable signal sload, to complete configuration of an analog-to-digital converter AD9826 in the AD conversion circuit.

[0037] S3, it is determined whether there is a signal sent by the host computer, if not, S3 is repeated, and if yes, the next step is performed.

[0038] S4, the instruction analysis module analyzes the data.

[0039] S5, judging the instruction type, if it is the integration time signal, saving the integration time into the register in the CMOS driving module, then returning to S3 and proceeding downwards; if it is the acquisition start signal, then proceeding to the next step;

[0040] S6, outputting the CMOS chip driving clock, pulling up the CMOS chip acquisition control signal ST, and simultaneously controlling the integration counter defined in the FPGA to start counting, and the program enters the integration state;

[0041] S7, judging whether the integration time is reached by the integration counter, if not, then returning to S6 and proceeding downwards; if yes, then proceeding to the next step;

[0042] S8, the program enters the transmission state, receiving the synchronization signal Trig sent by the CMOS, and defining a Trig signal counter in the FPGA to count the synchronization signal Trig;

[0043] S9, judging whether the Trig signal counter reaches 89, if not, then returning to S8 and proceeding downwards; if yes, then proceeding to the next step;

[0044] S10, outputting two driving clocks cdsclk2 and adcclk to the analog-digital converter AD9826, and driving the analog-digital converter AD9826 to start analog-digital conversion;

[0045] S11, using the clock with the same frequency as one of the AD9826 driving clocks adcclk as the write clock, and writing the signal from the analog-digital converter AD9826 into the FIFO and the RAM.

[0046] S12, judging whether the synchronization signal Trig counter reaches 2136, if not, then returning to S10 and proceeding downwards; if yes, then proceeding to the next step;

[0047] S13, using the GPS control module to read the GPS data and write it into the RAM, and after the RAM is full, the GPS control module sends an interrupt signal;

[0048] S14, using the clock with the same frequency as the sending baud rate as the read clock, and reading out the data from the FIFO, thereby completing the cross-clock domain processing;

[0049] S15, using the serial communication module to send the data read out from the FIFO;

[0050] S16, judging whether the FIFO is read empty signal empty is read from the FIFO, if not, then returning to S14 and proceeding downwards; if yes, then proceeding to the next step;

[0051] S17, if no, save the integration time to the register in the CMOS driving module, then return to S3 and proceed; if yes, proceed to the next step;

[0052] S18, the program ends.

[0053] Preferably, the working flow of the control program of the PS end is as follows:

[0054] S1, the program starts;

[0055] S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and tcp / ip protocol initialization;

[0056] S3, three-way handshake with the server end to establish TCP connection;

[0057] S4, wait for the GPS module interrupt signal, if the GPS module interrupt signal does not exist, proceed to S4 again, if the GPS module interrupt signal exists, proceed to the next step;

[0058] S5, start DMA data transmission;

[0059] S6, wait for the DMA completion interrupt signal, if the DMA completion interrupt signal does not exist, proceed to S6 again, if the DMA completion interrupt signal exists, proceed to the next step;

[0060] S7, read the Raman spectrum raw data, time and position information from the DDR and send them to the server end through Ethernet;

[0061] S8, determine whether the Ethernet transmission is completed, if no, proceed to S8 again; if yes, proceed to the next step;

[0062] S9, determine whether to stop, if no, return to S4 and proceed; if yes, proceed to the next step;

[0063] S10, four-way handshake with the server end to disconnect the TCP connection;

[0064] S11, the program ends.

[0065] The second aspect of the present application provides a Raman spectrum acquisition and transmission method, which is applied to the above-mentioned circuit, and the method comprises the following steps:

[0066] The communication module receives the data information of the remote data center and transmits it to the ZYNQ;

[0067] The ZYNQ processes the data information transmitted through the communication module and drives the spectrum acquisition module to acquire;

[0068] The spectrum acquisition module receives instructions from the ZYNQ and acquires them, and converts the acquired spectrum signals into digital signals and transmits them to the ZYNQ;

[0069] The ZYNQ processes the digital signals from the spectrum acquisition module and sends the data to a remote data center through the communication module.

[0070] The above one or more embodiments of the present application have at least the following beneficial effects:

[0071] Security and integrity of remote data transmission: The Raman spectrum acquisition and transmission circuit designed in the present application realizes the synchronous acquisition of data acquisition and geographic location, time information by integrating ZYNQ chip and GPS module, and directly sends to the server through Ethernet, eliminating the traditional step of transfer through host computer, thereby improving the security, authenticity and traceability of data. This innovation is suitable for application scenarios with extremely high data quality requirements, such as environmental monitoring and law enforcement evidence, while avoiding the problem of communication protocol mismatch, ensuring the high speed and stability of data transmission.

[0072] Efficiency of remote data reception and analysis execution: The circuit design of the present application has the function of remote data reception and analysis execution, through the high processing capacity of ZYNQ chip, realizes the rapid response and execution of remote instructions, significantly improves the real-time performance and reliability. Compared with the prior art, the present scheme reduces the delay and single point failure risk of computer as an intermediary, and provides a more stable and efficient remote control solution for online monitoring of petrochemical, polymer synthesis, food processing and other industries.

[0073] Optimized implementation of master chip scheme: The present application uses ZYNQ as the master chip, fully utilizes the advantages of integrated FPGA and ARM, optimizes the communication efficiency of existing single ARM, single FPGA or ARM+FPGA scheme through the high-speed data transmission capability of AXI bus, solves the problem that they cannot take into account both advantages and low communication efficiency. The PL part of ZYNQ is responsible for high-speed data acquisition and peripheral driving, and the PS part is responsible for data packaging and network transmission. This design fully utilizes their respective advantages and improves the overall performance of the system.

[0074] Stability design of special power supply circuit: The power supply system designed in the present application is composed of BUCK step-down circuit and LDO voltage stabilizing circuit, which can provide an input voltage of up to 12V / 2A, ensuring stable power supply for all devices in the system. The use of high-efficiency IC and high-quality inductance and capacitance components, combined with careful PCB layout, realizes high stability, low ripple and noise of power supply output, meets the strict requirements of high-precision devices for power supply voltage, and provides solid and reliable power supply guarantee for the entire Raman spectrum acquisition and transmission circuit. Attached Figure Description

[0075] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the embodiments of the present application to explain the application and do not constitute a limitation thereof. In the drawings:

[0076] Figure 1 This is a schematic diagram of the structure of the Raman spectroscopy acquisition and transmission circuit provided in the embodiments of this application;

[0077] Figure 2 This is a power supply topology diagram of the Raman spectroscopy acquisition and transmission circuit provided in the embodiments of this application;

[0078] Figure 3 This is a schematic diagram of the PL (FPGA) side program workflow of the Raman spectroscopy acquisition and transmission circuit provided in the embodiments of this application;

[0079] Figure 4 This is a schematic diagram of the PS (ARM) terminal program workflow of the Raman spectroscopy acquisition and transmission circuit provided in the embodiments of this application. Detailed Implementation

[0080] Embodiments of this application will now be described in detail, examples of which are illustrated in the accompanying drawings. The components of the embodiments of this application described and shown in the drawings herein can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application.

[0081] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0082] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0083] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected, it can be mechanical connection, or electrical connection, it can be direct connection, or indirect connection through intermediate medium, it can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0084] The technical solutions of the present application will be described below in combination with Figure 1 And Figure 4 The technical solutions of the present application will be described below in combination with

[0085] The technical solutions of the present application will be described below in combination with Figure 1 The first aspect of the present application provides a Raman spectrum acquisition and transmission circuit, comprising: a communication module, a spectrum acquisition module, a ZYNQ; wherein:

[0086] The communication module is connected with the ZYNQ, and the module is responsible for data exchange with the remote data center, it receives data information of the remote data center, and transmits the information to the ZYNQ for further processing. At the same time, it is also responsible for sending the spectrum data processed by the ZYNQ back to the remote data center, to ensure real-time transmission and reception of data.

[0087] Optionally, the communication module can be an Ethernet interface.

[0088] The ZYNQ is the control center of the whole circuit, and is connected with the spectrum acquisition module, it receives data information from the communication module, analyzes the data information, and drives the spectrum acquisition module to collect data according to the information. In addition, the ZYNQ is also responsible for processing digital signals from the spectrum acquisition module, and sending the processing results to the remote data center through the communication module.

[0089] The spectrum acquisition module is connected with the ZYNQ, used for receiving instructions from the ZYNQ and collecting, and converting the collected spectrum signals into digital signals and transmitting to the ZYNQ for further processing and transmission.

[0090] The working process of the whole circuit system is: the remote data center sends data information to the communication module, the communication module transmits the data information to the ZYNQ, the ZYNQ analyzes the instructions and drives the spectrum acquisition module to collect data. After processing the collected spectrum signals, the ZYNQ sends them back to the remote data center through the communication module, to complete the whole data acquisition and transmission process.

[0091] The Raman spectrum acquisition and transmission circuit designed in the application has a remote data transmission function, solves the problem that the existing Raman spectrum acquisition circuit cannot guarantee the authenticity, reliability and traceability of data, and solves the problem that the existing Raman spectrum acquisition circuit cannot meet the requirements of high speed, stability and timely remote data transmission.

[0092] Compared with the existing method of first transmitting data to the host computer (computer) through serial communication, and then using software to send remote data through Ethernet, the Raman spectrum acquisition and transmission circuit designed in the application reduces the step of transferring by computer, avoids the additional potential risk of data tampering introduced by computer as an intermediate link, and improves the security and reliability of data. Therefore, the Raman spectrum acquisition circuit designed in the application is suitable for use in scenes requiring high data authenticity, reliability and traceability, such as water pollution on-site rapid detection and contraband on-site evidence law enforcement.

[0093] In addition, the remote data transmission scheme proposed in the application removes the slow serial communication in the existing remote transmission scheme, improves the overall data transmission rate of the system, avoids the problem of mismatch between two communication protocols, and improves the rate and stability of remote transmission. It can meet the requirements of high speed, stability and timely remote data transmission.

[0094] Further, the ZYNQ includes a processing system (PS) and a programmable logic part (PL, specifically a programmable logic array FPGA), the PS part integrates an Ethernet module, an ARM and a DDR control module, and the FPGA is connected with the PS through an AXI interface; wherein:

[0095] The Ethernet module is not only connected with the external communication module to realize data exchange with the remote data center, but also connected with the ARM to ensure smooth data flow. The Ethernet module is responsible for receiving data sent by the remote data center, completing frame detection and synchronization, address identification, data error detection and other data link layer analysis work, and transmitting data to the ARM. The ARM is responsible for completing MAC layer, IP layer and TCP layer protocol analysis work, and obtaining user data through analysis. At the same time, the Ethernet module can also send the data processed by the ARM to the remote data center through the communication module to complete the data transmission task.

[0096] The ARM is connected with the Ethernet module, the FPGA and the DDR control module. The ARM is responsible for processing the data parsed by the Ethernet module, further completing the protocol parsing work of the MAC layer, the IP layer and the TCP layer, parsing the user data such as the acquisition start signal and the integration time configuration signal, and sending the acquisition start signal or the integration time configuration signal to the FPGA through the AXI interface, so as to start the acquisition work of the spectrum acquisition module. In addition, the ARM reads the data in the DDR memory, gradually encapsulates the MAC layer, the IP layer and the TCP layer protocols, and sends the data to the remote data center through the Ethernet module.

[0097] The FPGA is used for receiving the instructions from the ARM through the AXI interface, so as to drive the spectrum acquisition module to perform the acquisition work, and can also drive the spectrum acquisition module to perform the conversion and processing of the spectrum signal. The FPGA is also responsible for writing the collected information data into the DDR control module through the AXI bus, so as to prepare for the subsequent data storage and transmission.

[0098] The DDR control module is used for receiving the acquisition information data written by the FPGA, and safely storing the acquisition information data in the DDR memory. The data can be read by the ARM processor, and is used for further data processing and encapsulation, and is finally sent to the remote data center through the Ethernet module.

[0099] The ZYNQ not only realizes efficient data processing and storage, but also ensures the flexibility and expansibility of the system through the highly integrated architecture.

[0100] Compared with the existing remote control mode which needs a computer as a "transit station", the remote control scheme designed in the application can directly send the control command to the Raman spectrum acquisition and transmission circuit with remote communication function without the computer transit. This greatly simplifies the communication process and reduces the delay in transmission. At the same time, since the computer transit link is removed, the risk of single point failure is reduced. The failure, shutdown or maintenance of the computer will no longer affect the realization of remote control, thereby improving the reliability and stability of the whole system. With the increasing complexity of the process flow in the fields of petrochemical, polymer synthesis, food processing and the like, the real-time performance and reliability of the monitoring system are required more and more, and the remote control scheme and the matching software and hardware proposed in the application have obvious advantages in real-time performance and reliability, and have broad application prospects.

[0101] Further, the FPGA comprises an instruction parsing module, a CMOS driving module, an AD driving module, a RAM and an AXI DMA module; wherein:

[0102] The instruction analysis module is connected with the ARM and CMOS driving module through the AXI interface, and is used for receiving the instruction sent by the ARM and analyzing the instruction, and transmitting the analysis result to the CMOS driving module to guide the subsequent action.

[0103] Optionally, the ARM can send the acquisition start instruction or the integration time configuration instruction to the instruction analysis module through the AXI interface.

[0104] The CMOS driving module is connected with the spectrum acquisition module, and the CMOS driving module takes action according to the result of the instruction analysis module. When the CMOS driving module receives the acquisition start signal, the module activates the spectrum acquisition module to start the spectrum data acquisition process. If the integration time signal is received, the CMOS driving module saves the time parameter in the register of itself to control the integration time length in the acquisition process.

[0105] The AD driving module is connected with the spectrum acquisition module and the RAM, and in the spectrum acquisition process, the AD driving module generates a driving signal to trigger the spectrum acquisition module to perform analog-to-digital conversion to convert the analog signal into a digital signal. The converted digital signal is then sent to the RAM to prepare for the next data storage and processing.

[0106] The AXI DMA refers to a DMA module with an AXI interface, the RAM is connected to the AXI DMA module, and finally the AXI DMA module is connected with the PS through the AXI interface. The RAM is responsible for temporarily storing the digital signal written by the AD driving module. Subsequently, the data information in the RAM is written into the PS through the AXI interface in a high-efficient manner through DMA (Direct Memory Access), realizing fast storage and subsequent processing of data.

[0107] In the transmission circuit disclosed in the application, the FPGA can not only quickly respond to the instructions of the ARM, but also efficiently manage and process the data from the spectrum acquisition module. This efficient data processing flow ensures that the system can collect and store spectrum data in real time and accurately, providing a solid foundation for subsequent data analysis and application.

[0108] In addition, the flexibility and programmability of the FPGA enable the system to be customized and optimized according to different application requirements, further improving the adaptability and performance of the system. This design not only improves the efficiency and accuracy of spectrum data acquisition, but also ensures the stability and reliability of the circuit system through a highly integrated architecture.

[0109] Further, the spectrum acquisition module includes a CMOS, a signal conditioning circuit and an AD conversion circuit; wherein:

[0110] CMOS is used to capture the spectral information of incident light, which is connected with CMOS driving module and signal conditioning circuit. According to the driving signal provided by the CMOS driving module, the spectral acquisition task is performed. The CMOS sensor converts the received optical signal into an electrical signal, i.e. a spectral signal, and outputs it to the signal conditioning circuit.

[0111] The signal conditioning circuit is located between the CMOS sensor and the AD conversion circuit. The signal conditioning circuit can filter and amplify the spectral signal output by the CMOS sensor. This step is crucial because it can improve the quality of the signal and reduce noise, thereby ensuring the accuracy and reliability of the signal. After signal conditioning, the spectral signal is transmitted to the AD conversion circuit, preparing for analog-to-digital conversion.

[0112] The AD conversion circuit is connected with the AD driving module. The task of the AD conversion circuit is to convert the spectral signal processed by the signal conditioning circuit from an analog signal to a digital signal. This conversion process is the basis for data storage and further analysis. The AD conversion circuit receives the driving signal from the AD driving module, triggers the analog-to-digital conversion process, and sends the converted digital signal to the AD driving module.

[0113] Further, the circuit further comprises a GPS module, and the FPGA further comprises a GPS control module, wherein:

[0114] The GPS control module is connected with the AD driving module. When the AD control module controls the AD conversion circuit to complete the current spectral data acquisition and stores the data in the RAM, the AD driving module sends a GPS acquisition start signal to the GPS control module. The above synchronization measures make each spectral data have corresponding position coordinate data, ensuring the authenticity and traceability of the original spectral data.

[0115] The GPS module is connected with the GPS control module. After the GPS control module receives the GPS acquisition start signal from the AD driving module, it controls the GPS module to capture signals from the Global Positioning System satellite. The GPS module communicates with the satellite in the sky to receive key time and geographic location data.

[0116] The GPS control module is connected with the RAM, used to read and process the satellite signals received by the GPS module, convert these signals into Global Navigation Satellite System (GNSS) format data, and store them in the RAM. These data can be accessed by other parts of the circuit system for further analysis and processing.

[0117] Through this design, the transmission circuit system provided by the application not only can realize efficient spectrum data acquisition and processing, but also can provide accurate time and geographic location information, greatly expanding the application range and function of the circuit system. At the same time, the circuit system also sends the position, time information and the original spectrum data to the remote data center, which improves the data integrity and traceability.

[0118] Further, the circuit further comprises a DDR3, the DDR3 is connected with the DDR control module, and the main function of the DDR3 is to store data information from the DDR control module. These data can include information collected from devices such as CMOS, GPS module, and intermediate data and result data generated during system operation; the DDR3 allows the DDR control module to read the stored data on demand. This reading capability ensures that data can be accessed and analyzed by subsequent processing units in a timely manner.

[0119] Further, the FPGA further comprises a serial communication module and a FIFO (First In, First Out, First In, First Out queue); wherein:

[0120] The serial communication module is connected with the host computer, the instruction analysis module and the FIFO, and is used to receive instruction information sent by the host computer and send it to the instruction analysis module for analysis. After the instruction information received by the serial communication module is analyzed by the instruction analysis module, the corresponding operation in the FPGA can be triggered, such as starting or stopping data acquisition, configuring acquisition parameters, etc. The serial communication module is also used to read the stored spectrum data from the FIFO and send the data to the host computer through the serial communication circuit. The spectrum data received by the host computer can be displayed and preliminarily processed in real time on the spot, providing an intuitive data view and fast data analysis capability for the operator. This not only improves the interactivity of the system, but also makes the on-site decision and response more rapid and accurate.

[0121] The FIFO is connected with the AD driving module and can be used to temporarily store digital signals converted by the AD conversion circuit, ensuring the stability and integrity of the data during cross-clock domain transmission. The use of FIFO effectively avoids data loss or errors caused by different clock domains, improving the data processing capacity and reliability of the system. The introduction of FIFO allows the circuit system to process data at different clock frequencies, which is the key to realizing high-speed data acquisition and transmission. Through cross-clock domain processing, the system can smoothly process the high-speed data stream from the AD conversion circuit while maintaining the synchronization and accuracy of the data.

[0122] Further, the transmission circuit provided by the application further comprises an anti-backflow circuit and a CH340; wherein:

[0123] CH340 is a USB-to-serial chip connected with the serial communication module and the anti-backflow circuit, used to realize seamless conversion between the serial communication protocol of the Raman collection and transmission control circuit and the USB protocol of the host computer (computer). This conversion capability greatly enhances the compatibility of the system, allowing data communication using ordinary USB interfaces, simplifying the connection method of the system and the host computer.

[0124] To ensure the stable operation of CH340, an anti-backflow circuit is specially integrated in the system design. This circuit is connected with the host computer, and its main function is to form protection in the circuit to prevent the reverse flow of current due to abnormal conditions of the USB interface, thereby avoiding burning the USB-to-serial chip.

[0125] The combination of the anti-backflow circuit and the CH340 chip provides a safe and convenient data communication method for users. Users do not need to worry about the risk of circuit damage and can focus on data analysis and processing.

[0126] Further, the circuit also includes an SD card circuit for storing programs and burning the programs into the circuit system when the circuit system is powered on. When the circuit system is powered on, the SD card circuit automatically detects and reads the programs stored on the SD card, and then burns these programs into the memory or flash memory of the system, realizing fast startup and deployment.

[0127] Further, the Raman spectrum collection and transmission circuit provided by the present application also has a protection circuit, such as a power supply circuit, which is responsible for providing power for the entire system.

[0128] Figure 2 The power supply topology diagram of the Raman collection and transmission circuit designed by the present application is shown. The system uses a lithium battery as the power supply, and through the careful design of the power management circuit, it ensures that each component obtains stable and appropriate voltage supply.

[0129] The following is the detailed workflow of the power management and distribution of the circuit system:

[0130] The circuit system is powered by a lithium battery, which provides the necessary energy for the system to run stably for a long time;

[0131] The output voltage of the lithium battery is reduced by a BUCK step-down circuit to 5V to meet the operating voltage requirements of the main components such as ZYNQ, GPS module, operational amplifier in signal conditioning circuit, CMOS sensor, AD conversion chip, etc.

[0132] The 5V voltage is stabilized to -5V by an LDO (Low Dropout Regulator) voltage stabilizing circuit, providing the required negative power voltage for the operational amplifier in the signal conditioning circuit.

[0133] Another 5V voltage is reduced to 3.3V by an LDO voltage stabilizing circuit, which provides stable power supply for anti-backflow circuit, DDR3 memory, Ethernet interface, SD card circuit and other components;

[0134] The 5V voltage is also reduced to 1.8V by an LDO voltage stabilizing circuit, which provides another required power supply voltage for the SD card circuit, ensuring the stable operation of the SD card;

[0135] The 5V voltage output by the host computer USB is stabilized to 3.3V by an LDO, which provides power supply for the USB-to-serial chip CH340, ensuring the stable operation of the serial communication module;

[0136] The power supply circuit designed in the application adopts a high-efficiency and stable architecture, which is composed of a BUCK voltage reducing circuit and four LDO voltage stabilizing circuits, can accept an input voltage of up to 12V / 2A, ensure to meet the power requirements of various devices in the system, and has sufficient margin to maintain stable operation of the system.

[0137] BUCK voltage reducing circuit: high switching frequency, high efficiency, low static current IC is selected, combined with high saturation current, low internal resistance power inductance, and low equivalent series resistance value, high saturation voltage filter capacitor. The PCB layout and wiring of the circuit are optimized for the BUCK topology structure to realize high-efficiency power conversion.

[0138] LDO voltage stabilizing circuit: according to the specific power requirements of each device, IC with high load regulation performance, high linear regulation speed and high ripple suppression capability, and low equivalent series resistance value, high saturation voltage filter capacitor are selected. These selected components ensure that the power supply circuit can provide high stability, low ripple, low noise and high accuracy power supply voltage.

[0139] Power supply performance: comprehensive design ensures that the power supply system can adapt to load changes and provide the required power supply voltage for high-precision devices in the system, meeting their strict requirements for power quality.

[0140] Through this power supply system design, the application not only improves the stability and efficiency of the power supply, but also ensures the reliability of the entire circuit system and maximizes the performance of the devices.

[0141] Further, the application provides a control program of the PL (FPGA) end in the Raman spectrum acquisition and transmission circuit, as shown in Figure 3 The working process is as follows:

[0142] S1, the program starts running;

[0143] S2, the module outputs 3-way signal, including clock control signal scl, write data signal sdata, write enable signal sload to complete the configuration of AD conversion circuit analog-to-digital converter AD9826.

[0144] S3, determine whether there is a signal from the host computer, if not, repeat S3, if yes, then the next step;

[0145] S4, instruction analysis module for data analysis;

[0146] S5, determine the type of instruction, if the integral time signal, the integral time is saved to the CMOS drive module in the register, then return to S3 and down; If the acquisition start signal then the next step;

[0147] S6, output CMOS chip drive clock, pull high CMOS chip acquisition control signal ST, while controlling the integration of the internal FPGA self-defined counter starts counting, the program enters the integration state;

[0148] S7, through the integration of the counter to determine whether to reach the integration time, if not, return to S6 and down; If yes, then the next step;

[0149] S8, the program enters the transmission state, accept the CMOS sent synchronization signal Trig, in the FPGA inside a Trig signal counter to count the synchronization signal Trig;

[0150] S9, determine whether the custom Trig signal counter counting reaches 89, if not, return to S8 and down; If yes, then the next step;

[0151] S10, output two-way drive clock cdsclk2 and adcclk to analog-to-digital converter AD9826, drive analog-to-digital converter AD9826 to start analog-to-digital conversion;

[0152] S11, using the same frequency as the AD9826 drive clock adcclk clock as a write clock, the signal from the analog-to-digital converter AD9826 write into the FIFO and RAM.

[0153] S12, determine whether the custom synchronization signal Trig counter counting reaches 2136, if not, return to S10 and down; If yes, then the next step;

[0154] S13, using GPS control module to read GPS data and write to RAM in RAM full after the GPS control module sends an interrupt signal;

[0155] S14, reading data from the FIFO using a clock with the same frequency as the transmission baud rate as a reading clock, thereby completing the cross-clock domain processing;

[0156] S15, sending the data read from the FIFO using a serial communication module;

[0157] S16, determining whether the FIFO is read empty signal empty is read from the FIFO, if not, returning to S14 and proceeding downward; if yes, proceeding to the next step;

[0158] S17, determining whether to stop, if not, saving the integration time to the register in the CMOS driving module, and then returning to S3 and proceeding downward; if yes, proceeding to the next step;

[0159] S18, program end.

[0160] Further, the present application provides a control program of the PS (ARM) end in the Raman spectrum acquisition and transmission circuit, as shown in the following table, and the working process is as follows: Figure 3

[0161] S1, program start;

[0162] S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and tcp / ip protocol initialization;

[0163] S3, three-way handshake with the server end to establish TCP connection;

[0164] S4, waiting for the GPS module interrupt signal, if the GPS module interrupt signal does not exist, proceeding to S4 again, if the GPS module interrupt signal exists, proceeding to the next step;

[0165] S5, starting DMA data transmission;

[0166] S6, waiting for the DMA completion interrupt signal, if the DMA completion interrupt signal does not exist, proceeding to S6 again, if the DMA completion interrupt signal exists, proceeding to the next step;

[0167] S7, reading Raman spectrum raw data, time and position information from the DDR and sending to the server end through Ethernet;

[0168] S8, determining whether the Ethernet transmission is completed, if not, proceeding to S8 again; if yes, proceeding to the next step;

[0169] S9, determining whether to stop, if not, returning to S4 and proceeding downward; if yes, proceeding to the next step;

[0170] S10, four-way handshake with the server end to disconnect the TCP connection;​

[0171] S11, Program ends.

[0172] This application uses the ZYNQ chip as the main control chip for the Raman spectroscopy acquisition and transmission circuit and writes the corresponding control program. ZYNQ is a SOC chip integrating FPGA and ARM, combining the advantages of FPGA in handling high-speed parallel computing and ARM in handling general-purpose computing tasks. Furthermore, the FPGA and ARM communicate via the AXI bus integrated within the ZYNQ. The AXI bus protocol is an on-chip bus designed for high performance, high bandwidth, and low latency, ensuring high-speed data transmission between the FPGA and ARM.

[0173] This application utilizes the PL (FPGA) section of ZYNQ to control high-performance CMOS for photoelectric conversion, control high-speed AD conversion circuits for analog-to-digital conversion, and control the GPS module to receive satellite signals and extract location, time, and other information, leveraging the advantages of FPGA in parallel computing and driving high-performance peripherals. This application also utilizes the PS (ARM) section of ZYNQ to package data and perform Ethernet data transmission, leveraging the advantages of ARM in general-purpose computing and high integration. This patent uses the internal AXI bus of ZYNQ to complete communication between the FPGA and ARM, handling the transmission of large amounts of raw Raman spectroscopy data between the FPGA and ARM. The solution in this patent addresses the shortcomings of existing single-ARM, single-FPGA, or ARM+FPGA chip solutions, which cannot simultaneously leverage the advantages of both ARM and FPGA, and suffer from low communication efficiency between the two.

[0174] The working process of the Raman spectroscopy acquisition and transmission circuit provided in this application is as follows:

[0175] The remote data center sends data information to the Ethernet port of the circuit system via Ethernet;

[0176] After receiving data, the Ethernet communication module in the PS section of ZYNQ completes data link layer parsing tasks such as frame detection and synchronization, address identification, and data error detection, and then transmits the data to the ARM.

[0177] The ARM processor processes the data parsed by the Ethernet module and further completes the protocol parsing work of the MAC layer, IP layer, and TCP layer. It parses and obtains user data such as the acquisition start signal and the integration time configuration signal, and sends the acquisition start signal or integration time configuration signal to the instruction parsing module through the AXI interface.

[0178] If the instruction parsing module confirms that the received signal is the acquisition start signal, the CMOS driving module will output a driving signal to the CMOS to start the spectral acquisition process; if the integral time signal is received, the CMOS driving module will save the time parameter to its own register in order to control the integral time length in the acquisition process;

[0179] The spectral signal collected by the CMOS is filtered and amplified by the signal conditioning circuit to improve the signal quality;

[0180] The AD driving module in the PL part of the ZYNQ drives the AD conversion circuit to convert the conditioned analog spectral signal into a digital signal and write it into the RAM;

[0181] At the same time, the GPS control module reads the current time and geographic location data from the GPS module and stores these information in the RAM;

[0182] The time, geographic location and spectral data in the RAM are written into the DDR3 in the form of DMA through the AXI interface between the PL and the PS, and are managed by the DDR control module.

[0183] The ARM reads the data in the DDR3 through the DDR control module, performs necessary processing and packaging, and packages the data into a format suitable for network transmission, including MAC layer, IP layer and TCP layer packaging;

[0184] The packaged data is sent to the remote data center through the Ethernet module and the Ethernet network port, completing the remote transmission of the data;

[0185] After receiving the data, the remote data center can perform further analysis and processing, such as spectral analysis, data storage, report generation, etc.

[0186] According to the processing results of the remote data center, the system can receive feedback instructions for the next operation, such as adjusting the acquisition parameters, re-acquiring, etc.

[0187] The entire workflow reflects the high automation and intelligence of the circuit system, from the reception of remote instructions to the acquisition, processing, storage and remote transmission of data, the entire process is efficient and accurate, meeting the needs of modern spectral analysis for remote communication and data processing. Through this design, the circuit system not only improves the efficiency and accuracy of spectral data acquisition, but also greatly expands its application scenarios through remote communication capabilities, suitable for a variety of fields that require remote monitoring and real-time data analysis.

[0188] The Raman spectrum acquisition and transmission circuit provided in the application also retains a serial communication interface to realize on-site operation and debugging, and its working process is as follows:

[0189] The operator connects the host computer to the serial communication interface of the circuit system, and the host computer sends instruction information to the PL part of the ZYNQ through the serial communication circuit, which may include start of acquisition, integration time configuration, etc.

[0190] The serial communication module in the PL part of the ZYNQ receives the instruction information sent by the host computer and sends the information to the instruction analysis module for analysis.

[0191] If the instruction analysis module confirms that the received signal is the start of acquisition signal, the CMOS driving module will output the corresponding driving signal to start the CMOS for spectral acquisition; if the integration time signal is received, the CMOS driving module will save the time parameter to its own register to control the integration time during the acquisition process.

[0192] The spectral signals collected by the CMOS are transmitted to the signal conditioning circuit for necessary filtering and amplification processing to optimize the signal quality.

[0193] The analog spectral signals after conditioning are driven by the AD driving module to drive the AD conversion circuit for analog-to-digital conversion, converting the analog signals to digital signals.

[0194] The converted digital signals are written into the FIFO for cross-clock domain processing to ensure safe and accurate transmission between different rate clock domains.

[0195] The serial communication module reads the processed spectral data from the FIFO and sends the data to the host computer through the serial communication circuit.

[0196] The spectral data received by the host computer can be displayed to the operator in real time, and provides on-site data processing functions such as data visualization and preliminary analysis.

[0197] The operator can monitor the spectral acquisition process in real time according to the data and analysis results displayed by the host computer, and send adjustment instructions such as changing the integration time and triggering re-acquisition through the serial communication interface as needed.

[0198] This method of on-site operation through the host computer and the serial communication interface provides an intuitive and flexible spectral acquisition control scheme. It allows the operator to directly interact with the system locally, quickly respond to the on-site situation, and achieve accurate spectral data acquisition and real-time processing, suitable for application scenarios that require fast on-site response and accurate control.

[0199] The second aspect of the present application provides a Raman spectrum acquisition and transmission method, which can be applied in the above-mentioned circuit, the method comprising:

[0200] The communication module receives data information from the remote data center and transmits it to the ZYNQ.

[0201] The ZYNQ processes the data information transmitted by the communication module and drives the spectrum acquisition module to acquire;

[0202] The spectrum acquisition module receives the instruction from the ZYNQ and acquires, and converts the acquired spectrum signal into a digital signal and transmits to the ZYNQ;

[0203] The ZYNQ processes the digital signal from the spectrum acquisition module and transmits through the communication module.

[0204] It should be noted that the technical solutions in each of the embodiments of the present application can be combined with each other, but the basis for the combination is that it can be realized by a person of ordinary skill in the art; when the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, that is, it is not within the protection scope of the present application.

[0205] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A Raman spectrum acquisition and transmission circuit, characterized by, The application relates to a spectrum acquisition system, which comprises a communication module, a spectrum acquisition module and a ZYNQ; wherein: the communication module is connected with the ZYNQ and is used for receiving data information from a remote data center and transmitting the data information to the ZYNQ and sending data information from the ZYNQ to the remote data center; the ZYNQ is connected with the spectrum acquisition module and is used for processing data information transmitted through the communication module, driving the spectrum acquisition module to perform acquisition, processing digital signals from the spectrum acquisition module and transmitting the digital signals to the remote data center through the communication module; the spectrum acquisition module is connected with the ZYNQ and is used for receiving instructions from the ZYNQ and performing acquisition and converting acquired spectrum signals into digital signals and transmitting the digital signals to the ZYNQ; wherein the ZYNQ comprises a PS and a FPGA, the PS comprises an ARM and a DDR control module; wherein the FPGA comprises an instruction analysis module, a CMOS driving module, an AD driving module, a RAM and an AXI DMA module; wherein: the instruction analysis module is connected with the ARM and the CMOS driving module and is used for receiving instructions from the ARM, analyzing the instructions and transmitting analysis results to the CMOS driving module; the CMOS driving module is connected with the spectrum acquisition module and is used for driving the spectrum acquisition module to perform acquisition when the instruction analysis result is an acquisition start signal and saving an integration time into a register of the CMOS driving module when the instruction analysis result is an integration time signal; the AD driving module is connected with the spectrum acquisition module and the RAM and is used for generating a driving signal to drive the spectrum acquisition module to perform analog-digital conversion and writing converted data into the RAM; the RAM is connected to the AXI DMA module, the AXI DMA module is connected to the PS through an AXI interface and is used for writing digital signals stored in the RAM into the DDR control module in the PS through the AXI interface in a DMA mode; wherein the spectrum acquisition module comprises a CMOS, a signal conditioning circuit and an AD conversion circuit; wherein: the CMOS is connected with the CMOS driving module and the signal conditioning circuit and is used for performing spectrum acquisition work according to a driving signal of the CMOS driving module and outputting spectrum signals to the signal conditioning circuit after photoelectric signal conversion; the signal conditioning circuit is connected with the AD conversion circuit and is used for filtering and amplifying spectrum signals from the CMOS and transmitting the spectrum signals to the AD conversion circuit; the AD conversion circuit is connected with the AD driving module and is used for converting spectrum signals from the signal conditioning circuit from analog signals into digital signals after receiving a driving signal from the AD driving module and sending the digital signals to the AD driving module; wherein the circuit further comprises a GPS module and the FPGA further comprises a GPS control module; wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The GPS control module is connected with the AD driving module, the GPS module and the RAM respectively, and is used for receiving a GPS acquisition start signal sent by the AD driving module, controlling the GPS module to capture signals from global positioning system satellites, reading data of a GNSS protocol in the GPS module, extracting longitude and latitude and time information from the data, and storing the information in the RAM.

2. The circuit of claim 1, wherein, The PS includes an Ethernet module, and communicates with the FPGA through an AXI interface. The Ethernet module is connected with the communication module and the ARM respectively, and is used for analyzing data information from a remote data center, sending the analyzed data to the ARM, and sending data from the ARM to the remote data center through the communication module. The ARM is connected with the FPGA and the DDR control module, and is used for processing the data analyzed by the Ethernet module, sending processed instructions to the FPGA through the AXI interface, and packaging data read from the DDR control module and sending the packaged data to the Ethernet module. The FPGA is used for receiving instructions from the ARM through the AXI interface, driving the spectrum acquisition module to perform acquisition work and spectrum signal conversion work, and writing acquisition information data into the DDR control module in a DMA mode through the AXI interface.

3. The circuit of claim 2, wherein, The FPGA further includes a FIFO and a serial communication module. The FIFO is connected with the AD driving module, and is used for writing converted digital signals into the FIFO for cross-clock domain processing. The serial communication module is connected with a host computer, the instruction analysis module and the FIFO, and is used for receiving instruction information sent by the host computer and sending the instruction information to the instruction analysis module for analysis, and reading spectrum data from the FIFO and sending the spectrum data to the host computer through the serial communication circuit for on-site display and processing of the Raman spectrum.

4. The circuit of claim 3, wherein, The circuit further includes an anti-backflow circuit and a CH340. The CH340 is a USB-to-serial chip, and is connected with the serial communication module and the anti-backflow circuit, and is used for converting a serial communication protocol of the Raman acquisition transmission control circuit and a USB protocol of the host computer. The anti-backflow circuit is connected with the host computer, and is used for preventing the USB-to-serial chip from being burned by backflow current.

5. The circuit of claim 4, wherein, The circuit further includes a DDR3, which is connected with the DDR control module, and is used for storing data information transmitted from the DDR control module for reading by the DDR control module.

6. The circuit of claim 5, wherein, The circuit further includes an SD card circuit, which is used for storing a program and burning the program into the circuit system when the circuit system is powered on.

7. The circuit of claim 6, wherein, The working flow of the FPGA control program is as follows: S1, the program starts running; S2, the module outputs 3-way signals, including clock control signal scl, write data signal sdata and write enable signal sload to complete the configuration of the analog-to-digital converter AD9826 in the AD conversion circuit; S3, it is judged whether there is a signal from the upper computer, if not, then repeat S3, if yes, then the next step is performed; S4, the instruction analysis module analyzes the data; S5, the instruction type is judged, if it is an integral time signal, then the integral time is saved to the register in the CMOS driving module, then return to S3 and proceed downward, if it is a collection start signal, then the next step is performed; S6, the CMOS chip driving clock is output, the CMOS chip collection control signal ST is pulled high, and the integral counter defined in the FPGA is controlled to start counting, and the program enters the integral state; S7, whether the integral time is reached is judged by the integral counter, if not, then return to S6 and proceed downward, if yes, then the next step is performed; S8, the program enters the transmission state, accepts the synchronization signal Trig sent by the CMOS, and defines a Trig signal counter in the FPGA to count the synchronization signal Trig; S9, whether the Trig signal counter reaches 89 is judged, if not, then return to S8 and proceed downward, if yes, then the next step is performed; S10, two-way driving clocks cdsclk2 and adcclk are output to the analog-to-digital converter AD9826, and the analog-to-digital converter AD9826 starts to perform analog-to-digital conversion; S11, the clock with the same frequency as the AD9826 driving clock adcclk is used as the write clock, and the signal from the analog-to-digital converter AD9826 is written into the FIFO and the RAM; S12, whether the synchronization signal Trig counter reaches 2136 is judged, if not, then return to S10 and proceed downward, if yes, then the next step is performed; S13, the GPS data is read by using the GPS control module and written into the RAM, and after the RAM is full, the GPS control module sends an interrupt signal; S14, the clock with the same frequency as the sending baud rate is used as the read clock, and the data is read from the FIFO, thereby completing the cross-clock domain processing; S15, the data read from the FIFO is sent by using the serial communication module; S16, whether the FIFO is read empty signal empty is read from the FIFO is judged, if not, then return to S14 and proceed downward, if yes, then the next step is performed; S17, whether to stop is judged, if not, then the integral time is saved to the register in the CMOS driving module, then return to S3 and proceed downward, if yes, then the next step is performed; S18, the program ends.

8. The circuit of claim 7, wherein, The working process of the control program of the PS end is: S1, the program starts; S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and tcp / ip protocol initialization; S3, three-way handshake with the server end is performed to establish TCP connection; S4, waiting for GPS module interrupt signal, if the GPS module interrupt signal does not exist, then S4 is performed again, if the GPS module interrupt signal exists, then the next step is performed; S5, starting DMA data transmission; S6, waiting for DMA completion interrupt signal, if the DMA completion interrupt signal does not exist, then S6 is performed again, if the DMA completion interrupt signal exists, then the next step is performed; S7, reading Raman spectrum original data, time, position information from DDR and sending to server end through Ethernet; S8, judging whether Ethernet transmission is completed, if not, then S8 is performed again, if yes, then the next step is performed; S9, judging whether to stop, if not, then returning to S4 and proceeding, if yes, then the next step is performed; S10, performing four times of handshaking with the server end, disconnecting TCP connection; S11, program ending.

9. A Raman spectrum acquisition transmission method, characterized by, The method is applied to the circuit of any one of claims 1-8, and the method comprises: The communication module receives data information of the remote data center and transmits the data information to the ZYNQ; The ZYNQ processes the data information transmitted through the communication module and drives the spectrum acquisition module to acquire; The spectrum acquisition module receives the instruction from the ZYNQ and acquires, and converts the acquired spectrum signal into a digital signal and transmits the digital signal to the ZYNQ; The ZYNQ processes the digital signal from the spectrum acquisition module and sends the data to the remote data center through the communication module.

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