Method for manufacturing semiconductor device, semiconductor device, and memory system

Abstract

Embodiments of the present application provide a semiconductor device manufacturing method, a semiconductor device and a memory system. The method comprises: forming an initial stack structure comprising alternating dielectric layers and sacrificial layers; forming a plurality of first holes, at least one second hole and a plurality of third holes through the initial stack structure, wherein the plurality of first holes and the at least one second hole are arranged collinearly along a first direction, the plurality of third holes are arranged collinearly along the first direction, the plurality of first holes are located in an array region, the plurality of third holes are located in a connection region, and the first direction is perpendicular to a stacking direction of the initial stack structure; etching the initial stack structure using the plurality of first holes, the at least one second hole and the plurality of third holes, so that the plurality of first holes are communicated with each other to form a first gate line slit structure, the plurality of third holes are communicated with each other to form a second gate line slit structure, and the initial stack structure is reserved between the first gate line slit structure and the at least one second hole after etching; and forming an isolation structure using the at least one second hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and a memory system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, resulting in the storage density of planar memories approaching the upper limit.

[0003] To overcome the limitations of planar memory, the industry has developed memory with three-dimensional structures (e.g., 3D NAND flash memory), which increases storage density by arranging memory cells three-dimensionally on a substrate. Currently, optimizing the gate gap structure and its manufacturing method is one of the problems that needs to be solved. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: forming an initial stacked structure comprising alternating dielectric layers and sacrificial layers, the initial stacked structure having an array region and a connection region; forming a plurality of first vias, at least one second via, and a plurality of third vias penetrating the initial stacked structure, wherein the plurality of first vias and at least one second via are collinearly arranged along a first direction, the plurality of third vias are collinearly arranged along the first direction, the plurality of first vias are located in the array region, the plurality of third vias are located in the connection region, and the first direction is perpendicular to the stacking direction of the initial stacked structure; etching the initial stacked structure using the plurality of first vias, at least one second via, and the plurality of third vias, such that the plurality of first vias are interconnected to form a first gate line slot structure, and the plurality of third vias are interconnected to form a second gate line slot structure, wherein the initial stacked structure is retained between the first gate line slot structure and the etched at least one second via; and forming an isolation structure using the at least one second via.

[0006] In some embodiments, the manufacturing method further includes: using a first gate line slot structure to remove the sacrificial layer of the initial stack structure located in the array region, and using a second gate line slot structure to remove a portion of the sacrificial layer of the initial stack structure located in the connection region.

[0007] In some embodiments, forming an isolation structure using at least one second hole includes: replacing a portion of the sacrificial layer exposed to at least one second hole with a dielectric layer using the etched at least one second hole; and filling the at least one second hole with a dielectric material to form an isolation structure.

[0008] In some embodiments, the manufacturing method further includes forming a gate layer within the void formed after the sacrificial layer is removed to form a stacked structure.

[0009] In some embodiments, adjacent first gate line slot structures in the second direction form a storage block, the first gate line slot structures and the second gate line slot structures are arranged collinearly, and the second direction is perpendicular to the first direction and the stacking direction.

[0010] In some embodiments, adjacent first gate line slot structures in a second direction form a memory block, a second gate line slot structure is located within the memory block, and the second gate line slot structure has a spacing distance from the first gate line slot structure in the second direction, the second direction being perpendicular to the first direction and the stacking direction.

[0011] In some embodiments, an initial stacked structure is etched using a plurality of first holes, at least one second hole, and a plurality of third holes, such that the plurality of first holes are interconnected to form a first gate line slot structure, and the plurality of third holes are interconnected to form a second gate line slot structure. The initial stacked structure is retained between the first gate line slot structure and the etched at least one second hole, including: retaining the initial stacked structure between the second gate line slot structure and the etched at least one second hole.

[0012] In some embodiments, a plurality of first holes are arranged at a first interval distance, and a plurality of third holes are arranged at a second interval distance. The minimum interval distance between the first holes and the second holes is greater than the first interval distance and the second interval distance, and the minimum interval distance between the third holes and the second holes is greater than the first interval distance and the second interval distance.

[0013] In some embodiments, the manufacturing method further includes: forming a plurality of fourth holes in the array region that penetrate the initial stack structure and are collinearly arranged in a first direction, the plurality of fourth holes being located within the memory block, and having a spacing distance between the plurality of fourth holes and the first gate line slot structure in a second direction; and etching the initial stack structure using the plurality of fourth holes to make the plurality of fourth holes interconnected to form a third gate line slot structure.

[0014] In some embodiments, the plurality of fourth holes are divided into at least two groups; wherein, etching the initial stacked structure with the plurality of fourth holes to make the plurality of fourth holes interconnected to form a third gate line slot structure includes: etching the initial stacked structure with the plurality of fourth holes to make each group of fourth holes interconnected to form a sub-gate line slot structure, and retaining the initial stacked structure between adjacent sub-gate line slot structures.

[0015] In some embodiments, the method further includes forming a plurality of channel holes through the initial stacked structure in the array region; wherein the plurality of channel holes, a plurality of first holes, at least one second hole, a plurality of third holes, and a plurality of fourth holes are formed in the same process.

[0016] In some embodiments, the connection region has a conductive region and an insulating region. The portion of the stacked structure located in the array region and the conductive region includes alternately stacked dielectric layers and gate layers. The portion of the stacked structure located in the insulating region includes alternately stacked dielectric layers and sacrificial layers. The manufacturing method further includes forming a plurality of contact structures in the insulating region that penetrate the stacked structure to different depths, wherein the contact structures are connected to the gate layer of the same layer.

[0017] Secondly, embodiments of this application provide a semiconductor device. The semiconductor device includes: a stacked structure having an array region and a connection region; a first gate isolation structure penetrating the stacked structure and extending in the array region along a first direction, the first direction being perpendicular to the stacking direction of the stacked structure; a second gate isolation structure penetrating the stacked structure and extending in the connection region along the first direction; and an isolation structure penetrating the stacked structure and contacting the first gate isolation structure; wherein the sidewalls of the first and second gate isolation structures are irregularly shaped.

[0018] In some implementations, adjacent first gate isolation structures in the second direction form a memory block, the first gate isolation structure and the second gate isolation structure extend collinearly, and the second direction is perpendicular to the first direction and the stacking direction.

[0019] In some implementations, the isolation structure is in contact with the second gate isolation structure.

[0020] In some embodiments, adjacent first gate isolation structures in a second direction form a memory block, a second gate isolation structure is located within the memory block, and in the second direction, the second gate isolation structure and the first gate isolation structure have a spacing distance, and the second direction is perpendicular to the first direction and the stacking direction.

[0021] In some embodiments, the semiconductor device further includes a third gate isolation structure that extends through the stacked structure, extends along a first direction in the array region, and is located within the memory block. In a second direction, the third gate isolation structure is spaced apart from the first gate isolation structure, and the sidewalls of the third gate isolation structure are irregularly shaped.

[0022] In some embodiments, the third gate line isolation structure includes at least two sub-gate line isolation structures that extend along a first direction in the array region and have a spacing between adjacent sub-gate line isolation structures.

[0023] In some implementations, the connection region has a conductive region and an insulating region, the portion of the stacked structure located in the array region and the conductive region includes alternately stacked dielectric layers and gate layers, and the portion of the stacked structure located in the insulating region includes alternately stacked dielectric layers and sacrificial layers.

[0024] In some embodiments, the semiconductor device further includes multiple contact structures located in the insulating region and penetrating the stacked structure at different depths, with the contact structures connected to the gate layer of the same layer.

[0025] In some embodiments, the semiconductor device also includes multiple channel structures that run through the stacked structure in the array region.

[0026] Thirdly, embodiments of this application provide a memory system. The memory system includes: at least one three-dimensional memory, including semiconductor devices as mentioned in any of the embodiments described above; and a controller coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0027] According to at least one embodiment of this application, the semiconductor device manufacturing method, semiconductor device, and memory system provided by this application utilize a plurality of first holes formed in the array region and a plurality of third holes located in the connection region to form a first gate line slot structure and a second gate line slot structure, which can effectively solve the tilting problem, thereby improving structural stability and yield. On the other hand, by utilizing at least one second hole arranged collinearly with the plurality of first holes to form an isolation structure, etching isolation can be provided between the first gate line slot structure and the portion of the initial stacked structure located in the connection region, so as to meet the need to perform different "gate replacement" ranges in the array region and the connection region respectively using the first gate line slot structure and the second gate line slot structure. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0029] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application;

[0030] Figures 2A to 7B This is a schematic diagram of the semiconductor device according to the first embodiment of this application during the manufacturing process;

[0031] Figures 8 to 10 This is a top view schematic diagram of the semiconductor device according to the second embodiment of this application during the manufacturing process;

[0032] Figures 11 to 13 This is a top view schematic diagram of the semiconductor device according to the third embodiment of this application during the manufacturing process;

[0033] Figures 14 to 16 This is a top view schematic diagram of the semiconductor device according to the fourth embodiment of this application during the manufacturing process;

[0034] Figures 17A to 21BThis is a schematic diagram of the semiconductor device according to the fifth embodiment of this application during the manufacturing process;

[0035] Figure 22 This is a block diagram of a system having a memory system according to an exemplary embodiment of this application; and

[0036] Figure 23A and Figure 23B This is a schematic diagram of a memory system according to an exemplary embodiment of this application. Detailed Implementation

[0037] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first hole discussed herein may also be referred to as the second hole, and vice versa.

[0039] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0040] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0041] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0043] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] It should be noted that, in the following figures, the x, y, and z directions illustrate the spatial relationships of the components in the semiconductor device. For example, the z direction is the stacking direction of the initial stacked structure (or stacked structure), and the x and y directions are the first and second directions perpendicular to each other in a plane perpendicular to the stacking direction, respectively. The same concepts will be used throughout this application to describe the spatial relationships of the components in the semiconductor device.

[0045] As the number of stacked layers in 3D NAND memory increases, the gate line slot structure tilting problem worsens, leading to yield loss. On the other hand, since the range of "gate replacement" performed using the gate line slot structure differs between the array region and the interconnect region of the 3D memory, optimizing the gate line slot structure and its manufacturing method has become one of the key technical challenges of concern to those skilled in the art.

[0046] Therefore, embodiments of this application provide a method for manufacturing a semiconductor device. Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application. Figure 1 As shown, the semiconductor device manufacturing method 1000 (hereinafter referred to as manufacturing method 1000) includes steps S110 to S140.

[0047] S110, forming an initial stacked structure comprising alternating dielectric layers and sacrificial layers, the initial stacked structure having an array region and a connection region.

[0048] S120, forming a plurality of first holes, at least one second hole and a plurality of third holes through the initial stacked structure, wherein the plurality of first holes and at least one second hole are arranged collinearly along a first direction, the plurality of third holes are arranged collinearly along the first direction, the plurality of first holes are located in the array region, the plurality of third holes are located in the connection region, and the first direction is perpendicular to the stacking direction of the initial stacked structure.

[0049] S130, the initial stacked structure is etched using multiple first holes, at least one second hole, and multiple third holes, so that the multiple first holes are connected to each other to form a first gate line slot structure, and the multiple third holes are connected to each other to form a second gate line slot structure, and the initial stacked structure is retained between the first gate line slot structure and the etched at least one second hole.

[0050] S140, an isolation structure is formed using at least one second hole.

[0051] According to the semiconductor device manufacturing method provided in the embodiments of this application, a first gate line slot structure and a second gate line slot structure are formed by utilizing a plurality of first holes formed in the array region and a plurality of third holes located in the connection region, respectively. This effectively solves the tilting problem, thereby improving structural stability and yield. On the other hand, by utilizing at least one second hole arranged collinearly with the plurality of first holes to form an isolation structure, etching isolation can be provided between the first gate line slot structure and the portion of the initial stacked structure located in the connection region, so as to meet the need to perform different "gate replacement" ranges in the array region and the connection region using the first gate line slot structure and the second gate line slot structure, respectively.

[0052] Figures 2A to 7B This is a schematic diagram of the semiconductor device according to the first embodiment of this application during the manufacturing process. It should be noted that, in order to clearly show the spatial relationships of the components in the semiconductor device, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A as well as Figure 7A The dielectric layer 123, furthest from the substrate 121, is omitted. Hereinafter, the structure of the semiconductor device during manufacturing is referred to as an intermediate structure. For example, this semiconductor device may be a 3D NAND memory or a portion thereof.

[0053] Figure 2A This is a top view of the intermediate structure after the initial stacked structure is formed, and multiple first holes, one second hole, and multiple third holes are formed. Figure 2B It is along Figure 2A The diagram shows a cross-section taken by line I-I'.

[0054] In step S110, as Figure 2A and Figure 2BAs shown, the initial stacked structure 122 can be formed by alternating dielectric layers 123 and sacrificial layers 124 using thin film deposition processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any combination thereof. The dielectric layers 123 and sacrificial layers 124 can extend laterally in a plane perpendicular to the z-direction. For example, the dielectric layers 123 and sacrificial layers 124 can extend laterally in the array region 101 and the interconnect region 102. The more stacked layers of dielectric layers 123 and sacrificial layers 124, the higher the integration density of the memory cells, i.e., the greater the unit storage density. For example, the materials of the dielectric layers 123 and sacrificial layers 124 can be different from each other, thereby giving the dielectric layers 123 and sacrificial layers 124 different etch selectivity ratios relative to the same etchant. For example, the material of the dielectric layer 123 can be silicon oxide, and the material of the sacrificial layer 124 can be silicon nitride.

[0055] In some embodiments, the initial stacked structure 122 may be formed on one side of the substrate 121. For example, the material of the substrate 121 may include silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The substrate 121 may be used to support the components formed thereon (e.g., the initial stacked structure 122).

[0056] In step S120, continue to refer to Figure 2A and Figure 2B A plurality of first holes 131 (e.g., first holes 131_1 to 131_n), a second hole 132, and a plurality of third holes 133 (e.g., third holes 133_1 to 133_n) penetrating the initial stacked structure 122 can be formed using photolithography and etching (e.g., dry etching). The plurality of first holes 131 are formed in the array region 101, and the plurality of third holes 133 are formed in the connection region 102. The plurality of first holes 131, second holes 132, and third holes 133 are collinearly arranged along the x-direction. For example, the plurality of first holes 131, second holes 132, and third holes 133 can be arranged in the above manner by patterning the photomask.

[0057] In some embodiments, each of the plurality of first holes 131, the second hole 132, and the plurality of third holes 133 may have substantially the same shape and size. In some examples, each of the plurality of first holes 131, the second hole 132, and the third hole 133 may be an ellipse with its minor axis parallel to the x-direction in a plane perpendicular to the z-direction. In other examples, each of the plurality of first holes 131, the second hole 132, and the third hole 133 may be a perfect circle (not shown) or other suitable shape in a plane perpendicular to the z-direction. For example, each of the plurality of first holes 131, the second hole 132, and the third hole 133 may have the same size. It should be noted that this application does not specifically limit the number of the plurality of first holes 131 and the plurality of third holes 133. For example, the size and number of the plurality of first holes 131 and the plurality of third holes 133 may be determined based on the area dimensions of the array region 101 and the connection region 102.

[0058] In some embodiments, a plurality of first holes 131 are arranged at a first interval s1, and a plurality of third holes 133 are arranged at a second interval s2. The minimum interval d1 between the first hole 131_1 and the second hole 132 is greater than the first interval s1 and the second interval s2, and the minimum interval d2 between the third hole 133_1 and the second hole 132 is greater than the first interval s1 and the second interval s2. For example, the first interval s1 and the second interval s2 can be the same. Alternatively, the two minimum intervals d1 and d2 can be the same. The non-uniform arrangement of the plurality of first holes 131, second holes 132, and third holes 133 facilitates the implementation of step S130, which will be described in detail below.

[0059] In some embodiments, the manufacturing method 1000 may further include the step of forming a plurality of channel holes 161 penetrating the initial stacked structure 122 in the array region 101. In the step of forming the plurality of channel holes 161, the plurality of channel holes 161 may be formed using photolithography and etching (e.g., dry etching) processes. For example, the plurality of channel holes 161, the plurality of first holes 131, the second holes 132, and the plurality of third holes 133 can be formed in the same photolithography and etching process by patterning the mask, thereby improving manufacturing efficiency and saving manufacturing costs. Optionally, during the formation of the plurality of channel holes 161, the plurality of first holes 131, the second holes 132, and the plurality of third holes 133, a plurality of dummy channel holes 163 penetrating the initial stacked structure 122 may also be formed in the connection region 102. For example, the plurality of dummy channel holes 163 are formed on both sides of the plurality of third holes 133.

[0060] In some embodiments, multiple channel structures 162 can be formed using multiple channel holes 161 (see reference). Figure 4AFor example, a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) can be sequentially formed on the inner wall of the channel via 161 using a thin film deposition process such as PVD, CVD, ALD, or any combination thereof. For example, the materials of the charge blocking layer, charge trapping layer, tunneling layer, and channel layer can be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively. Multiple channel structures 162 can be used to provide a memory cell array. Optionally, the dummy channel via 163 can be filled with the same material as the channel via 161, or filled with at least one insulating material to form a dummy channel structure 164 (see reference). Figure 4A For example, multiple dummy channel structures 164 can be used to provide mechanical support and / or load balancing.

[0061] Figure 3A This is a top view of the intermediate structure after the formation of the first and second grid line slot structures. Figure 3B It is along Figure 3A The diagram shows a cross-section taken by line I-I'.

[0062] In step S130, as Figures 2A to 3B As shown, an initial stacked structure 122 can be etched using multiple first holes 131, second holes 132, and multiple third holes 133, such that the multiple first holes 131 are interconnected to form a first gate line slot structure 141, and the multiple third holes 133 are interconnected to form a second gate line slot structure 142. The initial stacked structure 122 is retained between the first gate line slot structure 141 and the etched second holes 132, and between the second gate line slot structure 142 and the etched second holes 132. Both the first gate line slot structure 141 and the second gate line slot structure 142 can be trenches extending along the x-direction and have sidewalls with an uneven structure. It should be noted that the first gate line slot structure 141 and the second gate line slot structure 142 are in an unfilled state.

[0063] In some embodiments, a wet etching process may be used to allow an etchant to enter a plurality of first holes 131, second holes 132 and a plurality of third holes 133, and to etch the initial stacked structure 122 (e.g., dielectric layer 123 and sacrificial layer 124) of the outer peripheral portion of each of the plurality of first holes 131, second holes 132 and a plurality of third holes 133. When multiple first holes 131, second holes 132, and multiple third holes 133 have the non-uniform arrangement described above and are of the same size, during wet etching, the size of each of the multiple first holes 131, the multiple second holes 132, and the multiple third holes 133 increases approximately uniformly in the radial direction. When the radial size of each of the multiple first holes 131 increases to the point that the multiple first holes 131 are connected to each other to form a first gate line slot structure 141, and the radial size of each of the multiple third holes 133 increases to the point that the multiple third holes 133 are connected to each other to form a second gate line slot structure 142, since the two minimum spacing distances d1 and d2 are both greater than the first spacing distance s1 and the second spacing distance s2, the etched second hole 132 (or the second hole 132 with increased radial size) will not be connected to the first gate line slot structure 141 and the second gate line slot structure 142, but will retain the initial stacked structure 122 between them. Alternatively, a plurality of first holes 133, second holes 132, and a plurality of third holes 133 are evenly arranged at equal intervals (not shown), and on a plane perpendicular to the z-direction, the size of the second holes 132 is smaller than the size of each of the plurality of first holes 131 and each of the plurality of third holes 133. During wet etching, since the radial dimension of the second holes 132 before etching is smaller than the radial dimension of each of the plurality of first holes 131 and each of the plurality of third holes 133, the etched second holes 132 (or the second holes 132 with enlarged radial dimensions) will not communicate with the first gate line slot structure 141 and the second gate line slot structure 142, but will retain the initial stacked structure 122 between them.

[0064] In some related technologies, the first gate line slot structure and the second gate line slot can be elongated grooves that extend continuously along the x-direction in the array region and the connection region. Compared with related technologies, in this embodiment, the first gate line slot structure 141 and the second gate line slot structure 142 are formed by using multiple first holes 131 and multiple third holes 133. This can solve the problem that the trench depth is too deep and easy to tip over due to the increase in the number of stacked layers, thereby improving the structural stability and yield.

[0065] Figure 4A This is a top view of the intermediate structure after the first and second grid line slot structures are filled with sacrificial material. Figure 5A This is a cross-sectional schematic diagram of the intermediate structure after the isolation structure has been formed. Figure 4B and Figure 5B They are along Figure 4A and Figure 5A The diagram shows a cross-section taken by line I-I'.

[0066] In step S140, as Figure 5A and Figure 5B As shown, the etched second hole 132 (see...) can be utilized Figure 3A An isolation structure 151 is formed by forming an isolation structure 151. The isolation structure 151 can be used to provide etch isolation between the first gate line slot structure 141 and the second gate line slot structure 142 located in the array region 102, thereby providing etch isolation from the portion of the initial stacked structure 122 located in the array region 102. For example, the material of the isolation structure 151 may be the same as the material of the dielectric layer 123 (e.g., silicon oxide). The isolation structure 151 and the dielectric layer 123 do not have a clear interface.

[0067] In some implementations, the isolation structure 151 can be formed in the manner described below. First, as... Figure 4A and Figure 4B As shown, sacrificial material 171 can be filled in the first gate gap structure 141 and the second gate gap structure 142. The sacrificial material 171 may be different from the materials of the dielectric layer 123 and the sacrificial layer 124. For example, the sacrificial material 171 may include, but is not limited to, polysilicon or carbon. Then, as... Figure 5A and Figure 5B As shown, the etched second hole 132 (reference) can be utilized Figure 4B The sacrificial layer 124 exposed to the second hole 132 (reference) Figure 4B A portion of the sacrificial layer 124 is removed, and a dielectric layer 152 is formed in the void created by removing this portion of the sacrificial layer 124. A dielectric material 153 is then filled into the second hole 132, thereby forming an isolation structure 151. Exemplarily, the material of the dielectric layer 152 can be the same as that of the dielectric material 153 (e.g., silicon oxide). The dielectric layer 152 and the dielectric material can be formed in the same thin-film deposition process. When the first gate gap structure 141 and the second gate gap structure 142 are filled with sacrificial material 171, the removal of a portion of the sacrificial layer 124 exposed in the second hole 132 can be stopped at the sacrificial material 171, thereby facilitating control over the morphology of the isolation structure 151. It should be noted that... Figure 5A The shape of the isolation structure 151 shown is merely an example, and this application does not specifically limit the shape of the isolation structure 151 in the plane perpendicular to the z direction.

[0068] In some embodiments, the manufacturing method 1000 may further include the step of forming a gate layer. Figure 6A and Figure 6B This is a top view of the intermediate structure after the gate layer is formed. Figure 6B It is along Figure 6AThe diagram shows a cross-section taken by line I-I'.

[0069] In the step of forming the gate layer, firstly, as Figure 5A and Figure 5B As shown, an etching process (e.g., wet etching) can be used to remove the sacrificial material 171 filling the first gate slot structure 141, leaving the first gate slot structure 141 in an unfilled state, while retaining the sacrificial material 171 filling the second gate slot structure 142. Next, a wet etching process can be used to remove the sacrificial layer 124 of the initial stacked structure 122 located in the array region 101 using the first gate slot structure 141. The isolation structure 151 can prevent the etchant from etching the sacrificial layer 124 of the initial stacked structure 122 located in the connection region 102. Then, an etching process (e.g., wet etching) can be used to remove the sacrificial material 171 filling the second gate slot structure 142, leaving the second gate slot structure 142 in an unfilled state. Next, a wet etching process can be used to remove a portion of the sacrificial layer 124 of the initial stacked structure 122 located in the connection region 102 using the second gate slot structure 142. For example, compared to the sacrificial layer 124 removed from array region 101, the sacrificial layer 124 removed from connection region 102 has a smaller size in the y direction.

[0070] Furthermore, such as Figure 6A and Figure 6B As shown, a thin-film deposition process, such as PVD, CVD, ALD, or any combination thereof, can be used to form a gate layer 125 in the voids formed by the sacrificial layer 124 after the array region 101 and the connection region 102 are removed. The material of the gate layer 125 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other suitable conductive material. Optionally, a gate barrier layer, an adhesive layer, and a metal layer (not shown) may be sequentially formed in the voids formed by the sacrificial layer 124 after the array region 101 and the connection region 102 are removed. Thus, the initial stacked structure 122 (see reference) can be formed. Figure 5A This is transformed into a stacked structure 126. In the stacked structure 126, the gate layer 125 extends laterally in the array region 101 and a portion of the connection region 102 (i.e., the conductive region 103), and the sacrificial layer 124 extends laterally in another portion of the connection region 102 (i.e., the two insulating regions 104). As described above, the process of replacing the sacrificial layer 124 in the initial stacked structure 122 with the gate layer 125 can be called "gate replacement".

[0071] Further reference Figure 6A and Figure 6BInsulating material can be filled into the first gate line gap structure 141 and the second gate line gap structure 142 using a thin film deposition process employing PVD, CVD, ALD, or any combination thereof to form the first gate line isolation structure 143 and the second gate line isolation structure 143. Exemplarily, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. Optionally, insulating material and polysilicon can be sequentially formed in the first gate line gap structure 141 and the second gate line gap structure 142 to balance stress and save manufacturing costs.

[0072] It should be noted that although the manufacturing method of first removing the sacrificial material 171 in the first gate line slot structure 141 and then removing the sacrificial material 171 in the second gate line slot structure 142 is described in detail above, this application does not specifically limit the order in which the sacrificial material 171 is removed from the first gate line slot structure 141 and the second gate line slot structure 142.

[0073] In some embodiments, the manufacturing method 1000 may also include the step of forming a plurality of contact structures. Figure 7A and Figure 7B This is a top view of a semiconductor device after multiple contact structures have been formed. Figure 7B It is along Figure 7A The diagram shows a cross-section taken by line II-II'.

[0074] In the steps of forming multiple contact structures, such as Figure 7A and Figure 7B As shown, multiple contact holes penetrating different depths of the stacked structure 126 can be formed in the insulating region 104 using photolithography and etching (e.g., dry etching) processes. For example, the bottom of the contact hole may remain at its corresponding sacrificial layer 124. Optionally, a protective layer (not shown) can be formed on the sidewall of the contact hole. Then, a portion of the sacrificial layer 124 exposed at its bottom is removed using the contact hole until the gate layer 125 of the same layer is exposed, forming an epitaxial void. Optionally, the protective layer can prevent the sacrificial layer 124 adjacent to the sidewall of the contact hole from being removed. Then, a first conductive portion 182 is formed in the epitaxial void, and a second conductive portion 183 is formed in the contact hole. The first conductive portion 182 and the second conductive portion 183 can be used to form a contact structure 181. The contact structure 181 can be connected to the gate layer 125 of the same layer (e.g., physical connection and electrical connection).

[0075] In the first embodiment, the isolation structure can provide etch isolation between the first gate line slot structure and the initial stacked structure located in the connection region portion, in order to meet the need to perform different ranges of "gate replacement" in the array region and the connection region using the first gate line slot structure and the second gate line slot structure respectively.

[0076] Figures 8 to 10This is a top view schematic diagram of the semiconductor device according to the second embodiment of this application during the manufacturing process. For the purpose of simplicity, the same content as in the first embodiment will not be repeated in the following embodiments.

[0077] Figure 8 This is a top view of the intermediate structure after multiple first holes, one second hole, multiple third holes, and multiple fourth holes have been formed. In step S120, as... Figure 8 As shown, a plurality of first holes 231 (e.g., first holes 231_1 to 231_n), a second hole 232, and a plurality of third holes 233 (e.g., third holes 233_1 to 233_n) penetrating the initial stacked structure 222 can be formed using photolithography and etching (e.g., dry etching) processes. The plurality of first holes 231, second holes 232, and the plurality of third holes 233 are collinearly arranged along the x-direction.

[0078] In some embodiments, the manufacturing method 1000 may further include the step of forming a plurality of fourth holes 234 (e.g., fourth holes 234_1 to 234_n) penetrating the initial stacked structure 222. The plurality of fourth holes 234 are collinearly arranged in the array region 201 along the x-direction. For example, the plurality of fourth holes 234 adjacent to each other may have approximately the same spacing in the x-direction. For example, by patterning the photomask, the plurality of fourth holes 234, the plurality of first holes 231, the second holes 232, and the plurality of third holes 233 can be formed in the same photolithography and etching process to improve manufacturing efficiency and save manufacturing costs.

[0079] Figure 9 This is a top view of the intermediate structure after the formation of the first grid line slot structure, the second grid line slot structure, and the third grid line slot structure. In step S130, as... Figure 8 and Figure 9 As shown, a wet etching process can be used to etch the initial stacked structure 222 using multiple first holes 231, second holes 232, and multiple third holes 233. This allows the multiple first holes 231 to connect to each other, forming a first gate line slot structure 241, and the multiple third holes 233 to connect to each other, forming a second gate line slot structure 242. The initial stacked structure 222 is preserved between the first gate line slot structure 241 and the etched second holes 232, and between the second gate line slot structure 242 and the etched second holes 232. Two adjacent first gate line slot structures 241 in the y-direction can form a memory block 205. For example, the memory block 205 can be the smallest erasable cell of a three-dimensional memory.

[0080] In some embodiments, during the wet etching process forming the first gate line slot structure 241 and the second gate line slot structure 242, a plurality of fourth holes 234 can be used to etch the initial stacked structure, making the plurality of fourth holes 234 interconnected to form a third gate line slot structure 245. For example, the third gate line slot structure 245 may be a trench extending in the x-direction and having sidewalls with an uneven structure. The third gate line slot structure 245 is located within the memory block 205 and is used to provide mechanical support for the memory block 205. For example, the third gate line slot structure 245 can divide the memory block 206 into two finger memory regions 206. It should be noted that, depending on the number of third gate line slot structures 245, the memory block 206 may be divided into more finger memory regions, and this application does not specifically limit this.

[0081] In some embodiments, during wet etching, an etchant enters a plurality of fourth holes 234 and etches the initial stacked structure 222 of the outer peripheral portion of each of the plurality of fourth holes 234, causing the size of each of the plurality of fourth holes 234 to expand substantially uniformly in the radial direction until they connect with each other to form a third gate line slot structure 245. Using a plurality of fourth holes 245 to form the third gate line slot structure 245 can address the problem of excessive trench depth and potential tipping caused by an increase in the number of stacked layers, thereby improving structural stability and yield.

[0082] Figure 10 This is a top view schematic diagram of the intermediate structure after the formation of the isolation structure, gate layer, first gate line isolation structure, second gate line isolation structure, and third gate line isolation structure. In step S140, as... Figure 9 and Figure 10 As shown, the etched second via 232 can be used to form the isolation structure 251. In some embodiments, during the steps of forming the gate layer 225, the first gate isolation structure 243, the second gate isolation structure 244, and the third gate isolation structure 246, the sacrificial layer 224 of the initial stacked structure 222 located in the array region 101 can first be removed using the first gate gap structure 241 and / or the third gate gap structure 245, and the sacrificial layer 224 of the initial stacked structure 222 located in the two conductive regions 204 in the connection region 102 can be removed using the second gate gap structure 242. Then, the gate layer 225 is formed in the gap formed after removing the sacrificial layer 224, thereby transforming the initial stacked structure 222 into the stacked structure 226. Exemplarily, the third gate isolation structure 246 can be formed, for example, using the same thin film deposition process during the formation of the first gate isolation structure 243 and the second gate isolation structure 244.

[0083] In the second embodiment, the isolation structure not only provides etch isolation between the first gate line gap structure and the initial stacked structure located in the connection area, but also forms an insulating boundary of the memory block together with the first gate line isolation structure and the second gate line isolation structure.

[0084] Figures 11 to 13 This is a top view schematic diagram of the semiconductor device according to the third embodiment of this application during the manufacturing process.

[0085] Figure 11 This is a top view of the intermediate structure after multiple first holes, two second holes, multiple third holes, and multiple fourth holes have been formed. In step S120, as... Figure 11 As shown, unlike the second embodiment, the number of second holes collinear with the plurality of first holes 331 and the plurality of third holes 333 is two, namely, second holes 332_1 and 332_2. In some embodiments, the plurality of first holes 331 are arranged at a first interval distance s1, and the plurality of third holes 333 are arranged at a second interval distance s2. The minimum interval distance d1 between the first hole 331_1 and the second hole 332_1 is greater than the first interval distance s1 and the second interval distance s2, and the minimum interval distance d2 between the third hole 333_1 and the second hole 332_2 is greater than the first interval distance s1 and the second interval distance s2. The two second holes 332_1 and 332_2 have a third interval distance s3 in the x-direction. For example, the first interval distance s1, the second interval distance s2, and the third interval distance s3 can be the same. Another example is that the two minimum interval distances d1 and d2 can be the same.

[0086] Figure 12 This is a top view of the intermediate structure after the formation of the first grid line slot structure, the second grid line slot structure, and the third grid line slot structure. In step S130, as... Figure 11 and Figure 12 As shown, unlike the second embodiment, in the process of etching the initial stacked structure 322 using multiple first holes 331, second holes 332_1 and 332_2, and multiple third holes 333, the multiple first holes 331 are interconnected to form a first gate line slot structure 341, and the multiple third holes 333 are interconnected to form a second gate line slot structure 342. Furthermore, during the process of preserving the initial stacked structure 322 between the first gate line slot structure 341 and the etched second holes (i.e., openings 332a), and between the second gate line slot structure 342 and the openings 332a, the two second holes 332_1 and 332_2 can be interconnected to form openings 332a after etching. Alternatively, the two etched second holes (not shown) can retain the initial stacked structure 322 in the x-direction. In other words, the dimensions of the two etched second holes are increased in the radial direction, but they are not interconnected.

[0087] Figure 13This is a top view schematic diagram of the intermediate structure after the formation of the isolation structure, gate layer, first gate line isolation structure, second gate line isolation structure, and third gate line isolation structure. In step S140, as... Figure 12 and Figure 13 As shown, when the two etched second holes 332_1 and 332_2 are interconnected openings 332a, the openings 332a can be used to form an isolation structure 351. For example, a portion of the sacrificial layer 324 exposed to the opening 332a can be replaced with a dielectric layer (not shown), and the opening 332a can be filled with a dielectric material (not shown). The dielectric layer and the dielectric material can together constitute the isolation structure 351. Alternatively, when the two etched second holes 332_1 and 332_2 are not interconnected, the two second holes with radially enlarged dimensions after etching can be used to form an isolation structure. For example, a portion of the sacrificial layer exposed to the two second holes can be replaced with a dielectric layer, and the two second holes can be filled with a dielectric material to form an isolation structure. For example, the replaced dielectric layer can extend continuously laterally, so that the isolation structure can be a single structure.

[0088] In some implementations, the gate layer 325, the first gate line isolation structure 343, the second gate line isolation structure 344, and the third gate line isolation structure 346 can be formed using the method described above.

[0089] It should be noted that the number of second holes is not limited to the two described in the third embodiment; there may be more second holes, and this application does not specifically limit this. For example, at least one second hole can be formed in the same photolithography and etching process as multiple first holes and multiple third holes through patterning design of the photomask.

[0090] In the third embodiment, the number of second holes can be adjusted according to actual design requirements, which helps to increase the flexibility of patterned design.

[0091] Figures 14 to 16 This is a top view schematic diagram of the semiconductor device according to the fourth embodiment of this application during the manufacturing process.

[0092] Figure 14 This is a top view of the intermediate structure after multiple first holes, one second hole, multiple third holes, and multiple fourth holes have been formed. In step S120, as... Figure 14 As shown, unlike the second embodiment, the plurality of fourth holes 434 are divided into three groups: a first group 4341, a second group 4342, and a third group 4343. For example, in the x-direction, the minimum spacing d3 between adjacent groups is greater than the fourth spacing s4 between adjacent fourth holes within a group.

[0093] Figure 15This is a top view schematic diagram of the intermediate structure after forming multiple first grid line slot structures, second grid line slot structures, and multiple sub-grid line slot structures. In step S130, as... Figure 14 and Figure 15 As shown, unlike the second embodiment, during the etching of the initial stacked structure 422 using multiple fourth holes 434 divided into three groups, the fourth holes corresponding to the first group 4341, the second group 4342, and the third group 4343 can be interconnected to form three sub-gate line slot structures 4451, 4452, and 4453. The initial stacked structure 422 is retained between adjacent sub-gate line slot structures (e.g., sub-gate line slot structures 4451 and 4452, and sub-gate line slot structures 4452 and 4453).

[0094] Figure 16 This is a top view schematic diagram of the intermediate structure after forming the isolation structure, gate layer, first gate line isolation structure, second gate line isolation structure, and multiple sub-gate line isolation structures. In step S140, as... Figure 15 and Figure 16 As shown, during the formation of the first gate line isolation structure 443 and the second gate line isolation structure 444, three sub-gate line isolation structures 4461, 4462, and 4463 can be formed, for example, using the same thin-film deposition process. In some embodiments, the isolation structure 451, the gate layer 425, the first gate line isolation structure 443, and the second gate line isolation structure 444 can be formed using the method described above.

[0095] It should be noted that this application does not specify the number of groups into which the multiple fourth holes are divided, nor the number of fourth holes in each group.

[0096] In the fourth embodiment, multiple sub-gate line slot structures are formed by using multiple grouped fourth holes, thereby forming a third gate line slot structure for dividing the memory area. This can further address the tipping problem and help to further improve structural stability and yield.

[0097] Figures 17A to 21B This is a schematic diagram of the semiconductor device according to the fifth embodiment of this application during the manufacturing process. It should be noted that, in order to clearly show the spatial relationships of the components in the semiconductor device, Figure 17A , Figure 18A , Figure 19A , Figure 20A as well as Figure 21A The dielectric layer 523, which is furthest from the substrate 521, is omitted.

[0098] Figure 17A This is a top view of the intermediate structure after the initial stacked structure is formed, and multiple first holes, two second holes, and multiple third holes are formed. Figure 17B It is along Figure 17AThe diagram shows a cross-sectional view taken by line III-III'. In step S120, as... Figure 17A and Figure 17B As shown, a plurality of first holes 531 (e.g., first holes 531_1 to 531_n), two second holes 532_1 and 532_2, and a plurality of third holes 533 (e.g., third holes 533_1 to 533_n) penetrating the initial stacked structure 522 can be formed using photolithography and etching (e.g., dry etching). The plurality of first holes 531 are formed in the array region 501, and the plurality of third holes 533 are formed in the connection region 502. The plurality of first holes 531, the two second holes 532_1 and 532_2, and the plurality of third holes 533 are arranged sequentially along the x-direction. The plurality of first holes 531 and the two second holes 532_1 and 532_2 are collinearly arranged, while the plurality of third holes 533 are not collinearly arranged with respect to the plurality of first holes 531 and the two second holes 532_1 and 532_2. For example, multiple first holes 531 and two second holes 532_1 and 532_2 are arranged collinearly along a first virtual straight line parallel to the x-direction, and multiple third holes 533 are arranged collinearly along a second virtual straight line parallel to the x-direction. The first virtual straight line and the second virtual straight line have a gap in the y-direction.

[0099] In some embodiments, a plurality of first holes 531 are arranged at a first interval s1, and a plurality of third holes 533 are arranged at a second interval s2, wherein the minimum interval d1 between the first hole 531_1 and the second hole 532_1 is greater than the first interval s1. For example, the first interval s1 and the second interval s2 may be the same.

[0100] In some embodiments, a plurality of fourth holes 534 (e.g., fourth holes 534_1 to 534_n) penetrating the initial stacked structure 522 may be formed in the same photolithography and etching process as a plurality of first holes 531, two second holes 532_1 and 532_2 and a plurality of third holes 533.

[0101] Figure 18A This is a top view of the intermediate structure after the formation of the first and second grid line slot structures. Figure 18B It is along Figure 18A The diagram shows a cross-sectional view taken by line III-III'. In step S130, as... Figures 17A to 18BAs shown, an initial stacked structure 522 can be etched using multiple first holes 531, two second holes 532_1 and 532_2, and multiple third holes 533. This allows the multiple first holes 531 to connect to each other, forming a first gate line slot structure 541, and the multiple third holes 533 to connect to each other, forming a second gate line slot structure 542. The initial stacked structure 522 is retained between the first gate line slot structure 541 and the etched second holes (i.e., openings 532a). Two adjacent first gate line slot structures 541 in the y-direction can form a memory block 505. The second gate line slot structure 542 can be located within the memory block 505.

[0102] In some embodiments, during the wet etching process of forming the first gate line slot structure 541 and the second gate line slot structure 542, the initial stacked structure 522 can be etched using a plurality of fourth holes 534 so that the plurality of fourth holes 534 are interconnected to form a third gate line slot structure 545.

[0103] Figure 19A This is a top view of the intermediate structure after the first and second grid line slot structures are filled with sacrificial material. Figure 20A This is a cross-sectional schematic diagram of the intermediate structure after the isolation structure has been formed. Figure 19B and Figure 20B They are along Figure 19A and Figure 20A The diagram shows a cross-sectional view taken by line III-III'. In step S140, as... Figure 20A and Figure 20B As shown, an isolation structure 551 can be formed using an opening 532a. The isolation structure 551 is located at the end of the first gate slot structure 541 near the connection region 502. For example, the isolation structure 551 spans the array region 501 and the connection region 502.

[0104] In some implementations, the isolation structure 551 can be formed by the method described below. First, as... Figure 19A and Figure 19B As shown, sacrificial material 571 can be filled in the first grid line slot structure 541 and the second grid line slot structure 542. Then, as... Figure 20A and Figure 20B As shown, a portion of the sacrificial layer 524 exposed to the opening 532a can be removed, and a dielectric layer 552 can be formed in the void formed by removing this portion of the sacrificial layer 524. The opening 532a is then filled with a dielectric material 553, thereby forming an isolation structure 551.

[0105] In some embodiments, the manufacturing method 1000 may further include the step of forming a gate layer. Figure 21A and Figure 21B This is a top view of the intermediate structure after the gate layer is formed. Figure 21B It is along Figure 21A The diagram shows a cross-section taken by line III-III'.

[0106] like Figures 20A to 21B As shown, firstly, a wet etching process can be used to remove the sacrificial material 571 filling the first gate line slot structure 541, leaving the first gate line slot structure 541 in an unfilled state, while retaining the sacrificial material 571 in the second gate line slot structure 542. Next, a wet etching process can be used, utilizing the first gate line slot structure 541, to remove the sacrificial layer 524 of the initial stacked structure 522 located in the array region 501. The isolation structure 551 can prevent the etchant from etching the portion of the initial stacked structure 522 located in the array region 502. Then, an etching process (e.g., wet etching) can be used to remove the sacrificial material 571 filling the second gate line slot structure 542, leaving the second gate line slot structure 542 in an unfilled state. Next, a wet etching process can be used, utilizing the second gate line slot structure 542, to remove a portion of the sacrificial layer 524 of the initial stacked structure 522 located in the connection region 502. For example, compared to the sacrificial layer 524 removed from the array region 501, the sacrificial layer 524 removed from the connection region 502 has a smaller size in the y direction.

[0107] Furthermore, a thin-film deposition process, such as PVD, CVD, ALD, or any combination thereof, can be used to form a gate layer 525 in the voids formed by the sacrificial layer 524 after the array region 501 and the connection region 502 are removed. This allows the initial stacked structure 522 (refer to...) to be... Figure 20B The structure is transformed into a stacked structure 526. In the stacked structure 526, the gate layer 525 can extend laterally in the array region 501 and a portion of the connection region 502 (i.e., the conductive region 503), and the sacrificial layer 524 can extend laterally in another portion of the connection region 502 (i.e., the two insulating regions 504).

[0108] In some embodiments, the first gate line isolation structure 543, the second gate line isolation structure 544, and the third gate line isolation structure 546 may be formed using the same thin film deposition process.

[0109] In the fifth embodiment, the isolation structure not only provides etch isolation between the first gate line gap structure and the initial stacked structure located in the connection area, but also forms an insulating boundary of the memory block together with the first gate line isolation structure.

[0110] This application also provides a semiconductor device. For example, the semiconductor device may be a 3D NAND memory or a part of a 3D NAND memory, such as... Figure 7A and Figure 7B As shown, the semiconductor device 100 includes a stacked structure 126, a first gate isolation structure 143, a second gate isolation structure 144, and an isolation structure 151.

[0111] The stacked structure 126 has an array region 101 and a connection region 102. For example, in a plane perpendicular to the z-direction, the stacked structure 126 is divided into an array region 101 and a connection region 102 along the x-direction. A first gate line isolation structure 143 penetrates the stacked structure 126 and extends along the x-direction in the array region 101. A second gate line isolation structure 144 penetrates the stacked structure 126 and extends along the x-direction in the connection region 102. For example, the first gate line isolation structure 143 and the second gate line isolation structure 144 may extend along the x-direction. The sidewalls of the first gate line isolation structure 143 and the second gate line isolation structure 144 have an uneven structure. An isolation structure 151 penetrates the stacked structure 126 and contacts the first gate line isolation structure 143. For example, in a plane perpendicular to the z-direction, the isolation structure 151 is located in the extension direction (i.e., the x-direction) of the first gate line isolation structure 143.

[0112] In this embodiment, the first and second gate line isolation structures with concave-convex sidewalls improve structural stability, reduce the risk of tipping over, and increase yield. The contact between the isolation structure and the first gate line isolation structure ensures that the gate layer in the stacked structure has different extension ranges in the array region and the connection region.

[0113] In some implementations, such as Figure 7A and Figure 7B As shown, the connection region 102 has a conductive region 103 and an insulating region 104. For example, within the connection region 102, the conductive regions 103 are located on both sides of the second gate isolation structure 144. The two regions of the conductive regions 103 away from the second gate isolation structure 144 are insulating regions 104. The portion of the stacked structure 126 located in the array region 101 and the conductive region 103 includes alternately stacked dielectric layers 123 and gate layers 125. The portion of the stacked structure 126 located in the insulating region 104 includes alternately stacked dielectric layers 123 and sacrificial layers 124.

[0114] In some implementations, such as Figure 7A and Figure 7B As shown, the semiconductor device 100 may further include a plurality of contact structures 181. The plurality of contact structures 181 are located within the insulating region 104 and penetrate the stacked structure 126 at different depths. The contact structures 181 are connected to the gate layer 125 of the same layer (e.g., physical and electrical connections). For example, the contact structure 181 may include a first conductive portion 182 and a second conductive portion 183. The first conductive portion 182 is disposed in the same layer as a sacrificial layer 124 in the stacked structure 126 and extends laterally in a plane perpendicular to the z-direction to contact the gate layer 125 of the same layer as the sacrificial layer 124. The second conductive portion 183 extends longitudinally along the z-direction to contact the first conductive portion 182.

[0115] In some implementations, such as Figure 7A and Figure 7B As shown, the semiconductor device 100 may further include a plurality of channel structures 162 extending through the array region 101 and the stacked structure 126. For example, the channel structure 162 may include a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) arranged sequentially from the outside to the inside. Optionally, the semiconductor device 100 may further include a plurality of dummy channel structures 164 extending through the connection region 102 and the stacked structure 126. For example, the dummy channel structures 164 are located within the conductive regions 103 on both sides of the second gate isolation structure 144.

[0116] In some implementations, such as Figure 10 As shown, adjacent first gate line isolation structures 243 in the y-direction form a memory block 205. For example, the memory block 205 may include an array region 201 and a connection region 202 arranged in the x-direction. The first gate line isolation structure 243 and the second gate line isolation structure 244 extend collinearly. In this case, the isolation structure 251 is in contact with the second gate line isolation structure 244. The isolation structure 251, the first gate line isolation structure 243, and the second gate line isolation structure 244 together constitute the insulating boundary of the memory block 205.

[0117] In some implementations, such as Figure 10 As shown, the semiconductor device may further include a third gate isolation structure 246. The third gate isolation structure 246 extends through the stacked structure 226 and extends along the x-direction within the array region 201. In the y-direction, the third gate isolation structure 246 is spaced from the first gate isolation structure 243. The third gate isolation structure 246 can be used to divide the memory block 205 into two memory regions 206. The sidewalls of the third gate isolation structure 246 may have an uneven structure, which helps improve structural stability, reduces the risk of tipping, and improves yield.

[0118] In some implementations, such as Figure 16 As shown, the third gate line isolation structure 446 may include at least two (e.g., three) sub-gate line isolation structures 4461 to 4463. Each sub-gate line isolation structure 4461 to 4463 extends along the x-direction in the array region 401, and there is a spacing between adjacent sub-gate line isolation structures (e.g., sub-gate line isolation structures 4461 and 4462, and sub-gate line isolation structures 4462 and 4463), which is beneficial to further improve the structural stability.

[0119] In some implementations, such as Figure 21A and Figure 21BAs shown, adjacent first gate line isolation structures 543 in the y-direction form a memory block 505. For example, the memory block 505 may include an array region 501 and a connection region 502 arranged in the x-direction. The first gate line isolation structure 543 and the second gate line isolation structure 544 extend non-collinearly. The second gate line isolation structure 544 is located within the memory block 505, and in the y-direction, the second gate line isolation structure 544 and the first gate line isolation structure 543 are spaced apart. In this case, the isolation structure 551 and the second gate line isolation structure 544 do not contact each other. The isolation structure 551 and the first gate line isolation structure 543 together constitute the insulating boundary of the memory block 505.

[0120] Since the content and structure described in the above description of preparation method 1000 are fully or partially applicable to the semiconductor device described herein, related or similar content will not be repeated.

[0121] Some embodiments of this application also provide a memory system. Figure 22 This is a block diagram of a system having a memory system according to an exemplary embodiment of this application.

[0122] like Figure 22 As shown, system 11 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 22 As shown, system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0123] The three-dimensional memory 14 may include the semiconductor devices described in any embodiment of this application, for example, Figure 7A and Figure 7BThe semiconductor device 100 is shown. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0124] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 23AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 22 The host 18) is coupled to the memory card connector 24. In such a way... Figure 23B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 22 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0125] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: An initial stacked structure is formed, comprising alternating dielectric layers and sacrificial layers, wherein the initial stacked structure has an array region and a connection region; A plurality of first holes, at least one second hole, and a plurality of third holes are formed through the initial stacked structure, wherein the plurality of first holes and the at least one second hole are collinearly arranged along a first direction, the plurality of third holes are collinearly arranged along the first direction, the plurality of first holes are located in the array region, the plurality of third holes are located in the connection region, and the first direction is perpendicular to the stacking direction of the initial stacked structure; The initial stacked structure is etched using the plurality of first holes, the at least one second hole, and the plurality of third holes, such that the plurality of first holes are interconnected to form a first gate line slot structure, and the plurality of third holes are interconnected to form a second gate line slot structure, wherein the initial stacked structure is retained between the first gate line slot structure and the etched at least one second hole; and An isolation structure is formed using the at least one second hole.

2. The manufacturing method according to claim 1, wherein, Also includes: The first gate line slot structure is used to remove the sacrificial layer of the initial stack structure located in the array region, and the second gate line slot structure is used to remove a portion of the sacrificial layer of the initial stack structure located in the connection region.

3. The manufacturing method according to claim 1, wherein, Forming an isolation structure using at least one second hole includes: Using the etched at least one second hole, a portion of the sacrificial layer exposed in the at least one second hole is replaced with a dielectric layer; and The at least one second hole is filled with a dielectric material to form the isolation structure.

4. The manufacturing method according to claim 2, wherein, Also includes: A gate layer is formed within the void created after the sacrificial layer is removed to form a stacked structure.

5. The manufacturing method according to claim 1, wherein, The first gate line slot structures adjacent to each other in the second direction form a storage block, the first gate line slot structures and the second gate line slot structures are arranged collinearly, and the second direction is perpendicular to the first direction and the stacking direction.

6. The manufacturing method according to claim 1, wherein, The first gate line slot structures adjacent to each other in the second direction form a memory block, the second gate line slot structure is located within the memory block, and in the second direction, the second gate line slot structure and the first gate line slot structure have a spacing distance, the second direction is perpendicular to the first direction and the stacking direction.

7. The manufacturing method according to claim 5, wherein, The initial stacked structure is etched using the plurality of first holes, the at least one second hole, and the plurality of third holes, such that the plurality of first holes are interconnected to form a first gate line slot structure, and the plurality of third holes are interconnected to form a second gate line slot structure. The initial stacked structure is retained between the first gate line slot structure and the etched at least one second hole. The initial stacked structure is retained between the second gate line slot structure and the at least one second hole after etching.

8. The manufacturing method according to claim 7, wherein, The plurality of first holes are arranged at a first interval, and the plurality of third holes are arranged at a second interval. The minimum interval between the first hole and the second hole is greater than the first interval and the second interval, and the minimum interval between the third hole and the second hole is greater than the first interval and the second interval.

9. The manufacturing method according to claim 5 or 6, wherein, Also includes: A plurality of fourth holes are formed in the array region, penetrating the initial stacking structure and collinearly arranged along the first direction. The plurality of fourth holes are located within the memory block, and in the second direction, the plurality of fourth holes are spaced apart from the first gate line slot structure. as well as The initial stacked structure is etched using the plurality of fourth holes, so that the plurality of fourth holes are connected to each other to form a third gate line slot structure.

10. The manufacturing method according to claim 9, wherein, The plurality of fourth holes are divided into at least two groups; Specifically, etching the initial stacked structure using the plurality of fourth holes to connect the plurality of fourth holes to form a third gate line gap structure includes: The initial stacked structure is etched using the plurality of fourth holes, so that each group of fourth holes is connected to each other to form a sub-gate line slot structure, and the initial stacked structure is retained between adjacent sub-gate line slot structures.

11. The manufacturing method according to claim 9, wherein, Also includes: Multiple channel holes are formed in the array region, penetrating the initial stacked structure; The plurality of channel holes, the plurality of first holes, the at least one second hole, the plurality of third holes, and the plurality of fourth holes are formed in the same process.

12. The manufacturing method according to claim 4, wherein, The connection region has a conductive region and an insulating region. The portion of the stacked structure located in the array region and the conductive region includes alternately stacked dielectric layers and gate layers. The portion of the stacked structure located in the insulating region includes alternately stacked dielectric layers and sacrificial layers. The method further includes: Multiple contact structures are formed in the insulating region at different depths through the stacked structure, wherein the contact structures are connected to the gate layer of the same layer.

13. A semiconductor device, characterized in that, include: A stacked structure with an array area and a connection area; A first gate isolation structure penetrates the stacked structure and extends in the array region along a first direction, the first direction being perpendicular to the stacking direction of the stacked structure; A second gate line isolation structure extends through the stacked structure and extends along the first direction in the connection area; as well as An isolation structure extends through the stacked structure and contacts the first gate isolation structure; The sidewalls of the first gate line isolation structure and the second gate line isolation structure are concave-convex structures.

14. The semiconductor device according to claim 13, wherein, The first gate isolation structures adjacent to each other in the second direction form a memory block, the first gate isolation structure and the second gate isolation structure extend collinearly, and the second direction is perpendicular to the first direction and the stacking direction.

15. The semiconductor device according to claim 14, wherein, The isolation structure is in contact with the second gate line isolation structure.

16. The semiconductor device according to claim 13, wherein, The first gate isolation structures adjacent to each other in the second direction form a memory block, the second gate isolation structure is located within the memory block, and in the second direction, the second gate isolation structure and the first gate isolation structure have a spacing distance, the second direction is perpendicular to the first direction and the stacking direction.

17. The semiconductor device according to claim 14 or 16, wherein, It also includes a third gate line isolation structure, which penetrates the stacked structure, extends along the first direction in the array region and is located within the memory block. In the second direction, the third gate line isolation structure has a gap distance from the first gate line isolation structure, and the sidewall of the third gate line isolation structure has an uneven structure.

18. The semiconductor device according to claim 17, wherein, The third gate line isolation structure includes at least two sub-gate line isolation structures, which extend along the first direction in the array region, and adjacent sub-gate line isolation structures are spaced apart.

19. The semiconductor device according to claim 13, wherein, The connection region has a conductive region and an insulating region. The portion of the stacked structure located in the array region and the conductive region includes alternately stacked dielectric layers and gate layers. The portion of the stacked structure located in the insulating region includes alternately stacked dielectric layers and sacrificial layers.

20. The semiconductor device according to claim 19, wherein, It also includes multiple contact structures located in the insulating region and penetrating the stacked structure at different depths, and the contact structures are connected to the gate layer of the same layer.

21. The semiconductor device according to claim 13, wherein, It also includes multiple channel structures that run through the stacked structure in the array region.

22. A memory system, characterized in that, include: A three-dimensional memory, the three-dimensional memory comprising a semiconductor device as described in any one of claims 13 to 21; as well as A controller is coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

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