A method for manufacturing high-voltage planar thyristor

Abstract

The application provides a manufacturing method of a high-voltage planar thyristor, which is surrounded by an extended junction at the edge of the four sides of a front P-type base region, the diameter of the extended circle is different, and gradually decreases away from the front P-type base region, so that the doping concentration continuously and linearly decreases along the front P-type base region to the edge direction, and the gradually reduced doping concentration also gradually reduces the junction depth, which can effectively improve the main junction electric field, thereby reducing the size of the terminal and reducing the chip area; and a composite passivation film is formed on the front of the silicon wafer, which has a shielding effect on the applied electric field, avoids surface breakdown, improves the reverse voltage resistance, and is not easy to crack, so that the performance of the thyristor product is more superior.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of microelectronics, and particularly relates to a manufacturing method of high-voltage planar silicon controlled rectifier. BACKGROUND

[0002] The silicon controlled rectifier is a P1N1P2N2 four-layer three-terminal structure element, has three PN junctions, has three electrodes, has the characteristics of small volume, simple structure, high efficiency and long service life, and can be used in the fields of controllable rectification, AC voltage regulation, protection, non-contact electronic switch, inversion and frequency conversion. At present, the high-voltage silicon controlled rectifier product needs to meet the high-quality requirements that the withstand voltage is more than 1200V and the leakage current is less than 1uA, so it is necessary to optimize the terminal design and optimize the surface passivation protection of the high-voltage silicon controlled rectifier product. At present, the terminal surface protection of the high-voltage silicon controlled rectifier product produced by the remaining manufacturers is basically carried out by using the mesa process, that is, a groove with a depth of more than 50um is corroded on the surface of the silicon wafer material, and the groove is filled with glass. However, the total thickness of the silicon wafer is generally not more than 260um, and the thermal expansion coefficient of the glass is inconsistent with that of the silicon. Therefore, the silicon wafer with the completed mesa glass protection is very easy to break, and the purity of the glass is difficult to control. If there is external pollution, the leakage current of the silicon controlled rectifier will increase significantly. Therefore, the terminal structure of the planar type with a conventional field plate voltage dividing ring is proposed. The space charge region of the top surface of the semiconductor can be widened by the potential ring. This structure is the most frequently used terminal structure of the planar silicon controlled rectifier product at present. The advantages include that the silicon wafer will not be bent during the process, the breakage rate of the silicon wafer during the process is low, the chip surface is flat, and the appearance is good. However, the disadvantage is that the area occupied by the PN junction terminal is relatively large, so the chip area required by the product of the same specification is larger. Therefore, the optimization of the product junction terminal and the surface passivation technology have always been the main problems of the high-voltage silicon controlled rectifier product. SUMMARY

[0003] In view of the above problems, the application provides a manufacturing method of high-voltage planar silicon controlled rectifier, which can greatly reduce the breakage rate, reduce the leakage current, and reduce the size of the terminal and improve the utilization rate.

[0004] The application adopts the following technical scheme, a manufacturing method of high-voltage planar silicon controlled rectifier, comprising the following steps:

[0005] S1, selecting N-type monocrystalline silicon material to process into a silicon wafer, and then generating an oxide layer on the surface of the silicon wafer by heat;

[0006] S2, etching positive and negative isolation patterns on the silicon wafer by a photoetching machine, and then removing the oxide layer on the region to be manufactured by hydrofluoric acid;

[0007] S3, coating the front and back surfaces of the silicon wafer with a boron source, and then performing high-temperature diffusion to expand the P-type layers on the front and back surfaces of the silicon wafer to form isolation islands;

[0008] S4, etching a P-type region pattern on the front and back surfaces of the silicon wafer, and then coating the surface of the P-type region pattern with a boron source and placing it in a high-temperature diffusion furnace for processing, so that the boron source diffuses into the silicon wafer located in the P-type region pattern to form a front P-type base region and a back P-type base region, thereby forming a main junction of the thyristor;

[0009] S5, performing photoetching on the front surface of the silicon wafer according to a pattern to form an expansion junction around the edges of the front P-type base region, the expansion junction being formed by a plurality of expansion circles uniformly distributed around the edges of the front P-type base region, the expansion circles being implanted with boron ions and then subjected to high-temperature annealing and diffusion treatment, wherein the diameters of the expansion circles gradually decrease away from the front P-type base region;

[0010] S6, etching N+ emitter regions on the surfaces of the front and back P-type base regions, and etching a gate N+ region on the surface of the front P-type base region;

[0011] S7, cleaning the oxide layer on the surface of the silicon wafer, and sequentially depositing a polysilicon film, a silicon dioxide film, a silicon oxide film, and a silicon nitride film on the front surface of the silicon wafer from bottom to top to form a composite passivation film;

[0012] S8, etching a metal contact region on the front surface of the silicon wafer and etching away the composite passivation film of the metal contact region, depositing an aluminum layer on the metal contact region and the back surface of the silicon wafer, using a photoetching machine to photoetch a reverse etching pattern on the metal contact region and etch away the aluminum layer outside the pattern, thereby forming a gate and a T1 electrode of the thyristor, and depositing an isolation oxide layer on the metal contact region between the gate and the T1 electrode;

[0013] S9, continuously depositing a titanium-nickel-silver alloy layer on the aluminum layer on the back surface of the silicon wafer, thereby forming a T2 electrode of the thyristor;

[0014] S10, performing low-temperature treatment on the aluminum layer to form a metallic ohmic contact between the aluminum layer and the silicon wafer, and finally forming a thyristor chip.

[0015] Further, the silicon wafer is made of N-type single-crystal silicon material with a resistivity of 50 ohm centimeters and a thickness of 225 um;

[0016] Further, in the step S5, the front P-type base region is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the expansion circles are circumferentially arranged around the edges of the front P-type base region, the diameters of the expansion circles close to the front P-type base region are larger than the diameters of the expansion circles away from the front P-type base region, and as the diameters of the expansion circles gradually decrease, the spacing between adjacent expansion circles in the same circumferential direction gradually increases.

[0017] Further, in the step S7, the following steps are further included:

[0018] S7.1, using LPCVD equipment, and setting the temperature at 650-680℃, under the pressure condition of 280mtoor, then introducing 150-300cc of silane and 50-100cc of laughing gas into the LPCVD equipment to react, so as to deposit a polysilicon film with a thickness of 600-700nm on the front side of the silicon wafer;

[0019] S7.2, depositing a silicon dioxide film with a thickness of 400-500nm on the polysilicon film, and performing annealing treatment after the deposition is completed;

[0020] S7.3, using PECVD equipment, and setting the temperature at 300-400℃, under the pressure condition of 180mtoor, then introducing 150-300cc of silane and 50-100cc of laughing gas into the PECVD equipment to react, so as to deposit a silicon oxide film with a thickness of 200-300nm on the silicon dioxide film;

[0021] S7.4, replacing the reaction gas in the PECVD equipment, i.e. introducing 100-150cc of silane and 50-100cc of ammonia into the PECVD equipment to react, so as to deposit a silicon nitride film with a thickness of 600-700nm on the silicon oxide film;

[0022] Further, in the step S8, the thickness of the aluminum layer on the metal contact area is 4-6um, and the thickness of the aluminum layer on the back side of the silicon wafer is 1-2um;

[0023] Further, in the titanium-nickel-silver alloy layer, the thickness of titanium is 100-200nm, the thickness of nickel is 300-400nm, and the thickness of silver is 1000-1200nm.

[0024] The beneficial effects of the present application are that the P-type base region on the front side is surrounded by an extended junction with an extended circle with different diameters, and gradually decreases away from the P-type base region, so that the doping concentration continuously and linearly decreases along the P-type base region towards the edge direction, and the gradually reduced doping concentration also gradually reduces the junction depth, which can effectively improve the main junction electric field, thereby reducing the size of the terminal and the chip area; and the composite passivation film is formed on the front side of the silicon wafer, which has a shielding effect on the applied electric field, avoids surface breakdown, improves the reverse voltage, and is not easy to crack, so that the performance of the silicon controlled product is more superior. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1is a chip profile structure diagram made by the present application;

[0026] Figure 2 is a structure diagram of the composite passivation film in the present application;

[0027] Figure 3 is a distribution diagram of the extended circle in the present application;

[0028] Figure 4 is a breakdown simulation curve diagram of the present application. DETAILED DESCRIPTION

[0029] The present application is described in detail below to make the advantages and features of the present application more easily understood by those skilled in the art, so as to make the protection scope of the present application more clear and definite.

[0030] The following gives a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all contemplated aspects, and is neither intended to identify key or critical elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is given later.

[0031] As shown in the drawings, Figures 1-3 The present application is a method for manufacturing a high-voltage planar thyristor, which comprises the following steps:

[0032] S1, select N-type monocrystalline silicon material to process into a silicon wafer, then heat-growth (i.e. through hydrogen-oxygen synthesis) an oxide layer with a thickness of 1.6um on the surface of the silicon wafer 1; wherein, according to the high-voltage 1200V voltage requirement, the silicon wafer 1 uses N-type monocrystalline silicon material with a resistivity of 50 ohm centimeters and a thickness of 225um;

[0033] S2, etch the front and back isolation patterns on the silicon wafer 1 through a photoetching machine, and then remove the oxide layer on the area to be manufactured by hydrofluoric acid;

[0034] S3, coat boron source on the front and back of the silicon wafer 1, then perform high-temperature diffusion through a high-temperature diffusion furnace to extend the P-type layer of the silicon wafer 1 on the front and back, so as to form an isolation island 2;

[0035] S4, etch the pattern of the P-type region on the front and back of the silicon wafer 1 respectively, then coat boron source on the surface of the P-type region pattern and put it into the high-temperature diffusion furnace for processing, so that the boron source diffuses into the silicon wafer 1 located in the P-type region pattern, to form a front P-type base region 3 and a back P-type base region 4, thereby forming the main junction of the thyristor;

[0036] S5. Photolithography is performed on the front side of the silicon wafer 1 according to the photolithography pattern to form an extended junction 5 around the edges of the front P-type base region 3, which can form a continuous decreasing distribution of impurities from the main junction to the edge; the front P-type base region 3 is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the extended junction 5 is formed by a number of extended circles 14 uniformly distributed around the edges of the front P-type base region 3, and the extended circles 14 surround the edges of the front P-type base region 3 in an annular direction. Boron ions are injected into the extended circles 14 and then subjected to high-temperature annealing and diffusion treatment, wherein the diameter of the extended circle gradually decreases as it moves away from the front P-type base region 3, that is, the diameter of the extended circle close to the front P-type base region 3 is larger than the diameter of the extended circle away from the front P-type base region 3, and as the diameter of the extended circle gradually decreases, the spacing between adjacent extended circles in the same annular direction gradually increases, that is, Figure 3 As shown, the spacing between adjacent expanded circles in each vertical column becomes larger;

[0037] Specifically, after boron ions are injected into the expansion circle and then a high-temperature annealing diffusion treatment is performed, a ring-shaped junction terminal extension structure surrounding the front P-type base region 3 can be formed. The doping concentration of the ring-shaped junction terminal extension structure continuously decreases along the front P-type base region 3 toward the edge, and then high-temperature diffusion is performed to achieve impurity redistribution; that is, through high-temperature diffusion, the ions in the expansion circle diffuse laterally so that the various expansion circle areas are interconnected, which is equivalent to different doping concentrations, achieving the effect of lateral variable doping, and then forming a junction terminal extension structure surrounding the edges of the front P-type base region 3. Because the diameter of the expansion circle and the spacing between the expansion circles have regular changes, the doping concentration continuously and linearly decreases along the front P-type base region 3 toward the edge, and the reduction in doping concentration causes the junction depth to gradually decrease.

[0038] In summary, the use of annular junction terminal expansion technology and lateral variable doping technology, that is, the use of an annular decreasing circle design structure, can greatly reduce the size of the terminal and improve the utilization of the terminal size compared to the existing planar thyristor with a floating potential ring structure as the terminal; and the lateral variable doping and boron ion doping injection of expansion circles of different diameters will result in different impurity concentrations and junction depths in the doped area after annealing. This phenomenon is used to form a P-type region with varying doping concentrations and junction depths in the lateral direction, which can effectively improve the main junction electric field, reduce the chip area, and increase the voltage resistance ratio of the terminal.

[0039] S6. Etching an N+ emitter region 6 on the surface of the front P-type base region 3 and the back P-type base region 4, and etching a gate N+ region 13 on the surface of the front P-type base region 3. The N+ emitter region 6 and the gate N+ region 13 on the surface of the front P-type base region 3 are adjacently spaced apart.

[0040] S7, clean the surface of the silicon wafer 1 to remove the oxide layer, and deposit a polysilicon film (SIPOS), a silicon dioxide film (LTO), a silicon oxide film (TEOS), and a silicon nitride film (SiN) on the front surface of the silicon wafer 1 in order from bottom to top to form a composite passivation film 12;

[0041] The polysilicon film (SIPOS) is a semi-insulating passivation film, and is equivalent to a film having the advantages of both an insulating film and a "conductive" film. The polysilicon film (SIPOS) itself is electrically neutral, and can eliminate the accumulation of charges caused by surface induction, has no ohmic current flowing therethrough, does not change the space charge of a junction, has no hot carrier storage effect, and has a low density of recombination centers between the polysilicon film (SIPOS) and a thyristor substrate, which is advantageous for reducing PN junction leakage.

[0042] Specifically, in step S7, the following steps are further included.

[0043] S7.1, an LPCVD device is used, and the temperature is set to 650-680°C, and 150-300 cc of silane and 50-100 cc of laughing gas are introduced into the LPCVD device to react under a pressure of 280 mtoor, so as to deposit a polysilicon film with a thickness of 600 nm on the front surface of the silicon wafer 1.

[0044] S7.2, a silicon dioxide film with a thickness of 400 nm is deposited on the polysilicon film, and annealing is performed after the deposition is completed, so as to eliminate the stress and densify the film.

[0045] S7.3, a PECVD device is used, and the temperature is set to 300-400°C, and 150-300 cc of silane and 50-100 cc of laughing gas are introduced into the PECVD device to react under a pressure of 180 mtoor, so as to deposit a silicon oxide film with a thickness of 200 nm on the silicon dioxide film.

[0046] S7.4, the reaction gas in the PECVD device is replaced, i.e., 100-150 cc of silane and 50-100 cc of ammonia are introduced into the PECVD device to react, so as to deposit a silicon nitride film with a thickness of 600 nm on the silicon oxide film.

[0047] According to the above, the multilayer composite passivation film of SIPOS+LTO+TEOS+SIN is finally formed on the front surface of the silicon wafer 1. According to the characteristics of the film layers, the polysilicon film (SIPOS) is in contact with the silicon material at the interface without high energy barrier, and there are high-density traps in the film. When the surface of the silicon wafer 1 is contaminated by ions, the traps in the polysilicon film (SIPOS) can capture the ions, forming a space charge region. The space charge region has a shielding effect on the applied electric field, and the hot carriers cannot stay in the polysilicon film (SIPOS) for a long time, so the carriers injected into the passivation film will not cause storage effect due to P-N junction avalanche breakdown. At the same time, the polysilicon film (SIPOS) is electrically neutral, and the surface will not form an electric field concentration, avoiding surface breakdown and improving the reverse voltage resistance.

[0048] The structure of the silicon nitride film (SiN) is dense, the pinhole density is small, the chemical stability is good, the dielectric constant is large, and the blocking ability to sodium ions and water vapor is very high. The contamination of the polysilicon film (SIPOS) by the outside can be reduced, and the stress of the silicon nitride film (SiN) can be reduced, so that the structure of the silicon nitride film (SiN) is more stable and not easy to crack. The corrosion resistance of the silicon nitride film (SiN) is improved, and the silicon nitride film (SiN) can stably operate in a more severe environment.

[0049] S8. Etching a metal contact area 7 on the front surface of the silicon wafer 1 and etching away the composite passivation film of the metal contact area 7, and depositing an aluminum layer on the front surface of the silicon wafer 1 and the metal contact area 7 respectively. The thickness of the aluminum layer on the metal contact area 7 is 4um, and the thickness of the aluminum layer on the front surface of the silicon wafer 1 is 1um. Using a photoetching machine to photoetch a reverse etching pattern on the metal contact area 7 and etch away the aluminum layer outside the pattern, thereby forming a gate 8 and a T1 electrode 9 of the thyristor, and depositing an isolation oxide layer 11 on the metal contact area 7 between the gate 8 and the T1 electrode 9.

[0050] S9. Continuously depositing a titanium-nickel-silver alloy layer on the aluminum layer on the back surface of the silicon wafer 1, thereby forming a T2 electrode 10 of the thyristor. In the titanium-nickel-silver alloy layer, the thickness of titanium is 100nm, the thickness of nickel is 300nm, and the thickness of silver is 1000nm.

[0051] S10. Low-temperature treatment is performed on the aluminum layer to form a metal ohmic contact between the aluminum layer and the silicon wafer 1, and finally a thyristor chip is formed.

[0052] Compared with the plane structure thyristor on the market, the plane thyristor produced by the application can reach the demand of high withstand voltage of 1200V or above, and the effective terminal length is only 220um; the design structure of the application reduces the size of the terminal, improves the utilization of the terminal size, reduces the cost, and at the same time, the passivation structure of the multi-layer composite passivation film reduces the leakage of the thyristor product, improves the withstand voltage of the product, and greatly improves the ability of the product to resist harmful impurities, effectively improving the reliability of the thyristor product.

[0053] After the optimization of the terminal design and the optimization of the surface passivation protection of the application, the breakdown voltage simulated can reach 1400V or above, as shown in the formula (1). Figure 4 The application can greatly reduce the chip area, improve the withstand voltage ratio of the terminal, and use the multi-layer composite passivation film to reduce the leakage of the thyristor product, improve the withstand voltage of the product, and improve the ability of the product to resist harmful impurities, effectively improving the reliability of the thyristor product.

[0054] As shown in Table 1, the thyristor device obtained according to the manufacturing steps of the application is tested, and the test parameters can conclude that the withstand voltage is more than 1200V and the leakage is less than 1uA.

[0055] Symbols Test Conditions Test Values Units Off-state repetitive peak voltage VDRM IDRM = 1 uA 1257 V Reverse repetitive peak voltage VRRM IRRM = 1 uA 1345 V Off-state repetitive peak current IDRM VDRM = 1200 V 89 n A Reverse repetitive peak current IRRM VRRM = 1200 V 193 n A

[0056] Table 1

[0057] It is obvious for those skilled in the art that the application is not limited to the details of the above exemplary embodiments, and the application can be realized in other specific forms without departing from the spirit or essential characteristics of the application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0058] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can be properly combined to form other embodiments that those skilled in the art can understand.

Claims

1. A method for manufacturing a high-voltage planar thyristor, characterized in that: The following steps are involved: S1. Select N-type single crystal silicon material and process it into silicon wafers, then thermally generate an oxide layer on the surface of the silicon wafers; S2, etching the front and back isolation patterns on the silicon wafer using a photolithography machine, and then removing the oxide layer on the area to be processed using hydrofluoric acid; S3, coating the front and back surfaces of the silicon wafer with a boron source, and then performing high-temperature diffusion to penetrate the P-type layer on the front and back surfaces of the silicon wafer to form an isolation island; S4. Etching P-type region patterns on the front and back surfaces of the silicon wafer in the areas to be fabricated, respectively. Then, applying a boron source on the surface of the P-type region patterns and placing the wafer in a high-temperature diffusion furnace for treatment, so that the boron source diffuses into the silicon wafer located in the P-type region patterns to form a front P-type base region and a back P-type base region, thereby forming a main junction of the thyristor. S5. Performing photolithography on the front side of the silicon wafer according to a pattern to form an extended junction around the edges of the front P-type base region. The extended junction is formed by a plurality of extended circles evenly distributed around the edges of the front P-type base region. Boron ions are implanted into the extended circles and then subjected to a high-temperature annealing and diffusion treatment. The diameter of the extended circle gradually decreases as it moves away from the front P-type base region. S6. Etching an N+ emitter region on the surface of the front P-type base region and the back P-type base region, and etching a gate N+ region on the surface of the front P-type base region; S7, rinsing the oxide layer on the surface of the silicon wafer, and depositing a polysilicon film, a silicon dioxide film, a silicon oxide film, and a silicon nitride film on the front side of the silicon wafer from bottom to top to form a composite passivation film; S8. Etching a metal contact area on the front side of the silicon wafer and etching away the composite passivation film in the metal contact area. Depositing an aluminum layer in the metal contact area and on the back side of the silicon wafer, respectively. Using a photolithography machine, photoetching a reverse pattern in the metal contact area and etching away the aluminum layer outside the pattern, thereby forming the gate and T1 pole of the thyristor. An isolation oxide layer is deposited on the metal contact area between the gate and T1 poles. S9, continuing to deposit a titanium-nickel-silver alloy layer on the aluminum layer on the reverse side of the silicon wafer, thereby forming a T2 pole of the thyristor; S10. Performing low-temperature treatment on the aluminum layer so that the aluminum layer forms a metal ohmic contact with the silicon wafer, thereby finally forming a thyristor chip.

2. The method for manufacturing a high-voltage planar thyristor according to claim 1, wherein: The silicon wafer is made of N-type single crystal silicon material with a resistivity of 50 ohm-cm and a thickness of 225um.

3. The method for manufacturing a high-voltage planar thyristor according to claim 1, wherein: In step S5, the front P-type base region is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the expansion circle surrounds the edges of the front P-type base region in an annular direction, and the diameter of the expansion circle close to the front P-type base region is larger than the diameter of the expansion circle away from the front P-type base region, and as the diameter of the expansion circle gradually decreases, the distance between adjacent expansion circles in the same annular direction gradually increases.

4. The method for manufacturing a high-voltage planar thyristor according to claim 1, wherein: In step S7, the following steps are also included: S7.

1. Using an LPCVD device set at a temperature of 650°C to 680°C and a pressure of 280 mTor, introduce 150 cc to 300 cc of silane and 50 cc to 100 cc of nitrous oxide into the LPCVD device to react and deposit a polycrystalline silicon film having a thickness of 600 nm to 700 nm on the front surface of the silicon wafer. S7.2, depositing a silicon dioxide film with a thickness of 400 nm to 500 nm on the polysilicon film, and performing an annealing treatment after the deposition is completed; S7.3, using a PECVD apparatus, setting the temperature at 300° C. to 400° C. and the pressure at 180 mTor, then introducing 150 cc to 300 cc of silane and 50 cc to 100 cc of nitrous oxide into the PECVD apparatus to react and deposit a silicon oxide film having a thickness of 200 nm to 300 nm on the silicon dioxide film; S7.

4. Replace the reaction gas in the PECVD equipment, that is, introduce 100cc to 150cc of silane and 50cc to 100cc of ammonia into the PECVD equipment to react so as to deposit a silicon nitride film with a thickness of 600nm to 700nm on the silicon oxide film.

5. The method for manufacturing a high-voltage planar thyristor according to claim 1, wherein: In step S8, the thickness of the aluminum layer on the metal contact area is 4um to 6um; the thickness of the aluminum layer on the back side of the silicon wafer is 1um to 2um.

6. The method for manufacturing a high-voltage planar thyristor according to claim 1, wherein: In the titanium-nickel-silver alloy layer, the thickness of titanium is 100 nm to 200 nm, the thickness of nickel is 300 nm to 400 nm, and the thickness of silver is 1000 nm to 1200 nm.

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