A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

The present application provides a semiconductor device, a manufacturing method thereof, and an electronic device. The method includes: providing a substrate in which a drift region is formed; forming a first field oxide layer on the surface of the substrate; etching away a part of the first field oxide layer to retain a part of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; while etching away the second field oxide layer located on the substrate, forming a third field oxide layer with a sloped sidewall on the drift region. By etching away a part of the first field oxide layer and retaining a part of the first field oxide layer on the drift region, continuously depositing the second field oxide layer, and removing the second field oxide layer on the substrate, a field plate with a sloped sidewall is formed. Only one mask is required to form the sloped field plate, which simplifies the process flow and reduces the process cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] In the field of semiconductor device technology, for power devices, in order to improve the breakdown voltage of the device, the design of the field plate is essential. The field plate is a commonly used terminal protection structure for improving the high-voltage breakdown resistance of semiconductor devices. By changing the surface potential distribution of the device and increasing the radius of curvature at the main junction, the PN junction electric field is no longer concentrated at the bend of the main junction, preventing the electric field at the main junction from being too concentrated, thereby increasing the breakdown voltage and improving the voltage withstand reliability of the device.

[0003] In the related art, in order to increase the breakdown voltage of the device and prevent the occurrence of peak electric fields, a sloped field plate is usually adopted. The sloped field plate can reduce the electric field at the PN main junction and avoid breakdown caused by overly concentrated electric fields. Although the related art can achieve a high breakdown voltage, in the current process of fabricating a sloped field plate, at least two masks are required to fabricate the sloped field plate, thus increasing the complexity of the process and the process cost. Summary of the Invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present application is not intended to attempt to define the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: providing a substrate in which a drift region is formed; forming a first field oxide layer on the surface of the substrate; etching away a part of the first field oxide layer to retain a part of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; while etching away the second field oxide layer located on the substrate, forming a third field oxide layer with a sloped sidewall on the drift region.

[0006] Exemplarily, it further includes the step of forming a gate dielectric layer and a gate material layer on the substrate and the third field oxide layer, and patterning the gate dielectric layer and the gate material layer to form a gate structure, where a part of the gate structure is located on the substrate and a part is located on the third field oxide layer.

[0007] Exemplarily, the region of the substrate located outside the drift region and under the gate structure constitutes a channel region.

[0008] Exemplarily, a wet etching process is adopted to remove the second field oxide layer located on the substrate.

[0009] Exemplarily, a body region is formed in the substrate, and the drift region is located within the body region.

[0010] Exemplarily, the first field oxide layer and the second field oxide layer are made of the same material.

[0011] Exemplarily, the gate material layer includes polysilicon, and the gate dielectric layer includes silicon oxide or silicon oxynitride.

[0012] Exemplarily, the semiconductor device includes a power device.

[0013] On the other hand, the present application provides a semiconductor device manufactured by the method described above.

[0014] On yet another aspect, the present application further provides an electronic device including the semiconductor device described above.

[0015] For the semiconductor device, its manufacturing method, and the electronic device provided by the present application, by etching to remove a part of the first field oxide layer, retaining a part of the first field oxide layer on the drift region, continuously depositing the second field oxide layer, and removing the second field oxide layer on the substrate, a field plate with a sloped sidewall is formed. Only one mask is required to form the sloped field plate, which simplifies the process flow and reduces the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present application are hereby incorporated as part of the present application for understanding the present application. The embodiments and descriptions thereof shown in the drawings are used to explain the principles of the present application. In the drawings:

[0017] Figure 1 A schematic flow chart showing a manufacturing method of a semiconductor device according to a specific embodiment of the present application;

[0018] Figures 2A to 2F A cross-sectional schematic view showing the semiconductor device obtained by successively implementing each step of the manufacturing method of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present invention, some well-known technical features are not described.

[0020] It should be understood that the present application can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion without departing from the teachings of the present invention.

[0022] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented as "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0024] To thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other implementation manners.

[0025] Currently, in the related art, to fabricate a sloped field plate, a process flow is as follows: First, grow a field oxide layer on a silicon wafer where a sloped field plate structure needs to be fabricated, perform the first photolithography to initially define the active region and the termination region, etch the field oxide layer wet for the first time, and remove the photoresist; Second, perform the second photolithography to finally define the active region and the termination region, etch the field oxide layer wet for the second time, and remove the photoresist; Finally, deposit polysilicon or aluminum, and form a sloped field plate structure composed of the field oxide layer and polysilicon or aluminum after the second wet etching through photolithography and etching methods. However, this method for fabricating a sloped field plate requires the use of two masks to fabricate the sloped field plate, increasing the process complexity and process cost.

[0026] Therefore, in view of the existence of the foregoing technical problems, an embodiment of the present application provides a method for fabricating a semiconductor device, as Figure 1 shown, which mainly includes the following steps:

[0027] In step S101, provide a substrate, and a drift region is formed in the substrate;

[0028] In step S102, form a first field oxide layer on the surface of the substrate;

[0029] In step S103, etch and remove a part of the first field oxide layer to retain a part of the first field oxide layer on the drift region;

[0030] In step S104, form a second field oxide layer on the substrate and the first field oxide layer;

[0031] In step S105, while etching and removing the second field oxide layer located on the substrate, form a third field oxide layer with a sloped sidewall on the drift region.

[0032] The manufacturing method of the semiconductor device according to the embodiment of the present application removes part of the first field oxide layer by etching, retains part of the first field oxide layer on the drift region, continues to deposit the second field oxide layer, and removes the second field oxide layer on the substrate, thereby forming a field plate with a sloped sidewall. Only one mask is required to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0033] Embodiment (I)

[0034] Next, with reference to Figure 1 and Figures 2A to 2F a detailed description will be given of the manufacturing method of the semiconductor device of the present application. Among them, Figure 1 FIG. shows a flowchart of the manufacturing method of the semiconductor device according to a specific embodiment of the present application, Figures 2A to 2F and FIG. shows a cross-sectional schematic diagram of the device obtained by successively implementing the manufacturing method of the semiconductor device according to a specific embodiment of the present application.

[0035] Exemplarily, the manufacturing method of the semiconductor device of the present application includes the following steps:

[0036] First, step S101 is executed to provide a substrate in which a drift region is formed.

[0037] In one example, as Figure 2A shown, the material of the substrate 200 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors, or is silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon germanium-on-insulator stacked silicon (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may also be a double-sided polished wafer (Double Side Polished Wafers, DSP), a ceramic substrate such as alumina, a quartz or glass substrate, etc. Although several examples of materials that can form the substrate are described herein, any material that can be used as the substrate falls within the spirit and scope of the present invention.

[0038] Exemplarily, the semiconductor substrate 200 can be a P-type substrate or an N-type substrate.

[0039] In one example, as Figure 2AAs shown, a drift region 201 is formed in the substrate 200. Exemplarily, a body region is formed in the substrate 200, and the drift region 201 is located within the body region. Exemplarily, the body region and the drift region 201 can be formed by an ion implantation process. Among them, the body region and the drift region 201 can have opposite conductivity types, and specific settings can be reasonably made according to the type of the actual device, and no specific limitation is made thereto. For example, for an N-type LDMOS device, the drift region 201 is an N-type drift region, and the body region is a P-type body region.

[0040] Generally speaking, the doping concentration of the drift region 201 is relatively low, which can improve the breakdown voltage and is beneficial to improving the frequency characteristics. Exemplarily, the drift region 201 can be an N-type drift region, such as a lightly doped N-type drift region, or the drift region 201 can also be a P-type drift region, such as a lightly doped P-type drift region, and specific settings can be reasonably made according to the type of the actual device. The main doping ions of the N-type drift region can include phosphorus ions, arsenic ions, antimony ions, etc., and the main doping ions of the P-type drift region can include boron ions, gallium ions, indium ions, etc. For example, for an N-type LDMOS device, the drift region 201 can be an N-type drift region doped with arsenic ions.

[0041] The depth of ion implantation can be controlled by controlling the energy of ion implantation. After ion implantation, an annealing treatment step can also be performed to activate the doping ions in the drift region. The annealing process uses rapid thermal annealing (RTA) or other suitable annealing methods.

[0042] In one example, as Figure 2A shown, the region of the substrate 200 located outside the drift region 201 and under the gate structure constitutes the channel region 202. Specifically, the channel region can be a part of the above-mentioned body region, or the channel region 202 can be formed by an ion implantation process. Exemplarily, the channel region 202 can be an N-type channel region, or the channel region 202 can also be a P-type channel region, and specific settings can be reasonably made according to the type of the actual device. The main doping ions of the N-type channel region can include phosphorus ions, arsenic ions, antimony ions, etc., and the main doping ions of the P-type channel region can include boron ions, gallium ions, indium ions, etc.

[0043] Next, step S102 is executed to form a first field oxide layer on the surface of the substrate.

[0044] In one example, as Figure 2AAs shown, a first field oxide layer 203 is formed on the surface of the substrate 200. Exemplarily, any suitable method well-known to those skilled in the art can be used to form the first field oxide layer 203. For example, but not limited to, deposition processes such as Chemical Vapor Deposition (CVD) can be used to form the first field oxide layer 203. Specifically, Low Pressure Chemical Vapor Deposition (LPVCD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) can be used. Alternatively, the first field oxide layer 203 can also be formed by a high-temperature furnace tube thermal oxidation process. Preferably, the first field oxide layer 203 is formed by low pressure chemical vapor deposition, so that a relatively dense first field oxide layer 203 can be formed.

[0045] In this example, the material of the first field oxide layer 203 can be silicon dioxide (SiO2), or the material of the first field oxide layer 203 can also be other suitable materials, such as silicon oxynitride (SiON), and no specific limitation is made thereto.

[0046] Next, step S103 is performed to etch and remove part of the first field oxide layer to retain part of the first field oxide layer on the drift region.

[0047] In one example, as Figure 2BAs shown, a part of the first field oxide layer 203 is etched away, and a part of the first field oxide layer 203 on the drift region 201 is retained. Exemplarily, a patterned mask layer is formed on the first field oxide layer 203. Specifically, the patterned mask layer includes a photoresist layer. Exemplarily, the step of etching away a part of the first field oxide layer 203 may include the following steps: forming a photoresist layer on the upper surface of the first field oxide layer 203 by a coating process, performing exposure and development using a photomask, and patterning the photoresist layer through the exposure and development process; etching the first field oxide layer 203 using the photoresist layer as a mask to remove a part of the first field oxide layer 203 and retain a part of the first field oxide layer 203 on the drift region 201; and finally removing the patterned photoresist layer, whereby a part of the first field oxide layer 203 on the drift region 201 can be retained. Exemplarily, dry etching such as reactive ion etching (RIE), ion beam etching, plasma etching and other conventional etching processes can be used to etch the first field oxide layer 203, and dry etching or ashing process etc. can be used to remove the patterned photoresist layer. Of course, a hard mask layer can also be formed on the surface of the first field oxide layer 203 first, and then the pattern is transferred to the hard mask layer using the above-mentioned photoresist layer as a mask, and then the hard mask layer is used to etch away a part of the first field oxide layer 203 and retain a part of the first field oxide layer 203 on the drift region 201, and finally the hard mask layer is removed. The above-described method of etching away the field oxide layer is a common method in the art and will not be described or limited in detail here. In short, any method that can etch away the field oxide layer is within the protection scope of this application.

[0048] After that, step S104 is executed to form a second field oxide layer on the substrate and the first field oxide layer.

[0049] In one example, as Figure 2C shown, a second field oxide layer 204 is formed on the substrate 200 and the first field oxide layer 203. Exemplarily, any suitable method well-known to those skilled in the art can be used to form the second field oxide layer 204. For example, the second field oxide layer 204 can be formed by a deposition process such as, but not limited to, chemical vapor deposition. Specifically, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used, or the second field oxide layer 204 can also be formed by a high-temperature furnace tube thermal oxidation process. Preferably, the second field oxide layer 204 is formed by low-pressure chemical vapor deposition, so that a relatively dense second field oxide layer 204 can be formed.

[0050] In one example, the material of the second field oxide layer 204 may be the same as that of the first field oxide layer 203. Specifically, the material of the second field oxide layer 204 may be silicon dioxide, and the material of the second field oxide layer 204 may also be other suitable field oxide layer materials, such as silicon oxynitride, which is not specifically limited herein. In another example, the materials of the first field oxide layer 203 and the second field oxide layer 204 may also be different, which is not specifically limited herein.

[0051] Next, step S104 is performed. While etching and removing the second field oxide layer located on the substrate, a third field oxide layer with a sloped sidewall is formed on the drift region.

[0052] In one example, as Figure 2D shown, the second field oxide layer 204 located on the substrate 200 is etched and removed, and at the same time, a third field oxide layer 205 with a sloped sidewall is formed on the drift region 201. Exemplarily, the second field oxide layer 204 located on the substrate 200 can be etched and removed by using a wet etching process. Specifically, a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F) can be used to etch the second field oxide layer 204. Since wet etching is an isotropic etching process, a certain inclination angle will be formed, thereby forming a third field oxide layer 205 (i.e., a sloped field plate) with a sloped sidewall on the drift region 201. The sloped field plate can uniformly control the electric field in the surface area of the bottom semiconductor substrate 200, prevent the occurrence of peak electric fields, thereby eliminating the easily breakdown region, and can improve the overall breakdown voltage of the device. The above method of forming the third field oxide layer with a sloped sidewall by wet etching process in the present application does not require the use of a mask. Therefore, compared with the prior art, the use of a mask plate can be saved once, and the process cost can be effectively reduced.

[0053] In one example, as Figure 2E shown, a gate dielectric layer 206 and a gate material layer 207 are formed on the substrate 200 and the third field oxide layer 205. Exemplarily, any suitable method well-known to those skilled in the art can be used to form the gate dielectric layer 206. For example, the gate dielectric layer 206 can be formed by using, but not limited to, deposition processes such as chemical vapor deposition, or the gate dielectric layer 206 can also be formed by a high-temperature furnace tube thermal oxidation process. Exemplarily, the material of the gate dielectric layer 206 may include silicon dioxide or silicon oxynitride, and may also be other suitable materials, such as high dielectric constant materials, which is not specifically limited herein.

[0054] In this example, the formation of the gate material layer 207 can be achieved by various deposition methods commonly used in the art. For example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other methods. Exemplarily, the material of the gate material layer 207 can include suitable conductive materials such as polysilicon, tungsten silicide, and titanium, without specific limitation thereto.

[0055] In one example, as Figure 2F shown, the patterned gate dielectric layer 206 and the gate material layer 207 are patterned to form a gate structure. The gate structure is partially located on the substrate 200 and partially located on the third field oxide layer 205. Exemplarily, the method of forming the gate structure can include: patterning the gate material layer 207, and etching the gate dielectric layer 206 and the gate material layer 207 to form a gate structure, which includes the gate dielectric layer 206 and the gate material layer 207. Any existing technology well-known to those skilled in the art can be used in this etching step, preferably dry etching, which includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma etching, or any combination of these methods. The formed gate structure is partially located on the substrate 200 and partially located on the third field oxide layer 205.

[0056] In one example, the formed semiconductor device includes a power device. Exemplarily, the power device is, for example, an LDMOS device.

[0057] It is worth mentioning that the above steps are only examples, and the order of the above steps can be adjusted on the premise of no conflict.

[0058] So far, the process steps of the manufacturing method of the semiconductor device according to an embodiment of the present application have been completed. It can be understood that the manufacturing method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of the manufacturing method of this embodiment.

[0059] In summary, in the manufacturing method of the semiconductor device of the present application, by etching to remove part of the first field oxide layer, retaining part of the first field oxide layer on the drift region, continuously depositing the second field oxide layer, and removing the second field oxide layer on the substrate, a field plate with a sloped sidewall is formed. Only one mask is required to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0060] Embodiment (2)

[0061] The present invention also provides a semiconductor device, which can be obtained by the method in the foregoing Embodiment 1.

[0062] Next, referring to Figures 2A to 2FA detailed introduction and description of the semiconductor device in the embodiments of the present application is provided. It is worth mentioning that, to avoid repetition, only a brief description is given for the components and structures that are the same as those in the first embodiment described above. For specific explanations and descriptions, reference can be made to the description in the first embodiment.

[0063] Specifically, Figures 2A to 2F , the semiconductor device of the embodiment of the present application includes: a substrate 200, in which a drift region 201 is formed; a channel region 202, which is composed of the region of the substrate 200 located outside the drift region 201 and under the gate structure; a third field oxide layer 205 located on the drift region 201; a gate structure, which includes a gate dielectric layer 206 and a gate material layer 207. The gate structure is partially located on the substrate 200 and partially located on the third field oxide layer 205.

[0064] Thus, the introduction of the structure of the semiconductor device of the present application is completed. For a complete device, there may be other component structures, which will not be elaborated one by one here.

[0065] For the semiconductor device provided by the present application, by etching to remove part of the first field oxide layer, retaining part of the first field oxide layer on the drift region, continuously depositing the second field oxide layer, and removing the second field oxide layer on the substrate, a field plate with a sloped sidewall is formed. Only one mask is required to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0066] Embodiment (Three)

[0067] In another embodiment of the present application, an electronic device is further provided, which includes the aforementioned semiconductor device, and the semiconductor device is prepared according to the aforementioned method.

[0068] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or can also be any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0069] The present invention has been illustrated by the above embodiments. However, it should be understood that the above embodiments are only for the purpose of exemplification and illustration, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate having a drift region formed therein; forming a first field oxide layer on a surface of the substrate; etching and removing a portion of the first field oxide layer to retain a portion of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; A wet etching process is adopted to etch away a portion of the second field oxide layer located on the substrate, and at the same time, a third field oxide layer with a sloped sidewall is formed on the drift region.

2. The manufacturing method according to claim 1, characterized in that The method also includes forming a gate dielectric layer and a gate material layer on the substrate and the third field oxide layer, and patterning the gate dielectric layer and the gate material layer to form a gate structure, wherein the gate structure is partially located on the substrate and partially located on the third field oxide layer.

3. The manufacturing method according to claim 2, characterized in that: The area of ​​the substrate located outside the drift region and under the gate structure constitutes a channel region.

4. The manufacturing method according to claim 1, characterized in that: A body region is formed in the substrate, and the drift region is located in the body region.

5. The manufacturing method according to claim 1, characterized in that: The first field oxide layer and the second field oxide layer are made of the same material.

6. The manufacturing method according to claim 2, characterized in that: The gate material layer includes polysilicon, and the gate dielectric layer includes silicon oxide or silicon oxynitride.

7. The manufacturing method according to claim 1, characterized in that: The semiconductor device includes a power device.

8. A semiconductor device, characterized in that: The method is produced by the production method described in any one of claims 1 to 7.

9. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 8.

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