A graphene field-effect transistor based on spin-coated insulating dielectric and its fabrication method

Abstract

This invention provides a graphene field-effect transistor based on spin-coated insulating medium and its fabrication method. The transistor includes a substrate, a gate electrode, a gate dielectric layer, a first insulating layer, a second insulating layer, a source electrode, a drain electrode, and a graphene channel layer. By spin-coating the insulating medium, a gate dielectric layer with the same height as the gate electrode is formed at both ends of the gate in the buried gate structure, ensuring the flatness of subsequent processing. By spin-coating the insulating medium and etching to form an insulating dielectric layer with the same height as the source and drain electrodes, the stress on the graphene film when transferred to the processed substrate is greatly reduced, thereby reducing the damage to the graphene film. The nanoscale grooves on the insulating layer reduce the contact area between the graphene and the substrate, thereby reducing the influence of substrate scattering, improving the carrier mobility of graphene, and thus improving device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor electronic device technology, and in particular to a graphene field-effect transistor based on spin-coated insulating medium and its fabrication method. Background Technology

[0002] Graphene is a zero-bandgap semiconductor, with its conduction band and valence band intersecting at the Dirac point. Therefore, graphene-based field-effect devices exhibit both electron and hole transport characteristics. The type and concentration of charge carriers vary with different gate voltages, thus graphene possesses field-control effects, which can be utilized to fabricate field-effect transistors (FETs). Currently, graphene-based FETs mainly include top-gate graphene FETs, back-gate graphene FETs, and dual-gate graphene FETs.

[0003] Top-gate graphene field-effect transistors (FETs) allow for independent control of the graphene channel by the transistor's gate electrode. The channel is covered by a gate dielectric layer, minimizing the graphene's susceptibility to external influences. However, the graphene in the channel is more susceptible to the effects of the gate dielectric layer, thus reducing carrier mobility. Back-gate graphene FETs have two structures: full back-gate and buried gate. While the full back-gate structure is simpler to fabricate and easier to implement, all FETs on a single wafer use a single back gate electrode, making individual control of individual graphene FETs difficult. Therefore, buried gate structures are typically used for graphene FETs requiring higher performance and controllability. Buried gate structures facilitate individual transistor control, and because the gate dielectric is grown first before the graphene is transferred, the growth process of the gate dielectric has no impact on the graphene. However, the buried-gate graphene field-effect transistor (FET) process involves first forming the back gate electrode and then growing the dielectric layer. Common dielectric layer fabrication methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) inevitably result in inconsistencies in the height of the dielectric layer above the electrode compared to other areas. Furthermore, local protrusions may appear at the junction of the electrode and the dielectric layer. This undoubtedly affects the performance of the subsequently transferred graphene, potentially causing graphene breakage or damage at the step locations, or reducing graphene carrier mobility. Therefore, a buried-gate FET and its fabrication method are needed that can maintain a consistent dielectric layer height and prevent local protrusions in the dielectric layer above the gate electrode, thereby improving device yield, carrier mobility, and the overall performance of graphene FETs. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a graphene field-effect transistor based on spin-coated insulating medium and its fabrication method. Because spin-coated insulating medium possesses excellent leveling and local planarization capabilities, it can easily penetrate into minute gaps, effectively solving the gate oxide layer flatness problem present in existing buried gate technologies. It eliminates the height difference of the dielectric layer in the buried gate structure, improves the flatness of the contact area between the electrode and the gate dielectric, reduces graphene breakage and damage, and minimizes the influence of the substrate on carrier scattering in the graphene. Furthermore, spin-coating the insulating medium does not require excessively high temperatures, reducing thermal strain during processing and thus improving the overall performance of the buried gate device.

[0005] This invention proposes a graphene field-effect transistor based on spin-coated insulating dielectric, comprising:

[0006] Base;

[0007] A gate electrode is disposed on the substrate, and a portion of the gate electrode is not covered by the second insulating layer;

[0008] A gate dielectric layer is disposed above the gate electrode and the first insulating layer;

[0009] A first insulating layer and a second insulating layer. The first insulating layer is disposed on the substrate at both ends of the gate electrode and has the same height as the gate electrode. The second insulating layer is disposed on the gate dielectric layer and has multiple nano-sized grooves.

[0010] The source and drain are disposed on the gate dielectric layer and located at both ends of the second insulating layer;

[0011] The graphene channel layer is disposed on part of the source and drain regions and on the second insulating layer.

[0012] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, or Ti / Au.

[0013] Furthermore, the gate dielectric layer is made of a dielectric material, including TiO2. 2、 Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, LaAlO, with a gate dielectric layer thickness of 100nm-300nm.

[0014] Furthermore, the second insulating layer is located in a portion of the area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain regions.

[0015] Furthermore, the insulating dielectric material is one or more of SiO2, barium strontium titanate (BST), and lead zirconate titanate (PZT).

[0016] Furthermore, the graphene channel layer is a large-area graphene film with uniform synthesis performance, and it is also covered with a boron nitride protective layer.

[0017] This invention also proposes a method for fabricating the above-mentioned graphene field-effect transistor based on spin-coating insulating dielectric technology, the method comprising:

[0018] A substrate is provided on which a gate electrode is formed;

[0019] An insulating layer is formed on the substrate and the gate electrode. By etching away the insulating layer that is higher than the gate electrode, a first insulating layer is formed on both ends of the gate electrode, and the height of the insulating layer is consistent with that of the gate electrode.

[0020] A gate dielectric layer is formed on the first insulating layer and the gate electrode;

[0021] The source and drain are formed on the gate dielectric layer;

[0022] A second insulating layer is formed on the gate dielectric layer and between the source / drain and the gate. After forming, the portion higher than the height of the source and drain is etched away so that the height of the second insulating layer is consistent with the source and drain regions. Multiple nanoscale grooves are etched on the second insulating layer.

[0023] Graphene films are grown by chemical vapor deposition, then transferred onto the source / drain electrodes and the second insulating layer. Boron nitride is then applied over the graphene, and the film is patterned by laser direct writing etching to form a graphene channel layer.

[0024] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, or Ti / Au, and is achieved by electron beam evaporation; the gate dielectric layer is achieved by atomic layer deposition (ALD) or chemical vapor deposition (PECVD), and is made of TiO2. 2、 The gate dielectric layer is one of Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, and LaAlO, with a thickness of 100nm-300nm.

[0025] Furthermore, the formation of the source and drain electrodes includes: spin-coating a high-precision photoresist layer on the gate dielectric layer, then precisely patterning the photoresist layer to expose the area where the electrode needs to be deposited, and performing electron beam evaporation on the area.

[0026] Furthermore, the first insulating layer and the second insulating layer are prepared by surface treatment, spin coating, low-temperature baking and high-temperature annealing after the preparation of the precursor solution. Nanoscale grooves are formed on the second insulating layer by focused ion beam or etching.

[0027] Compared with the prior art, the present invention has the following beneficial technical effects:

[0028] (1) The present invention utilizes the fluidity of spin-coated insulating medium to ensure that the height of the insulating medium layer on the gate electrode of the buried gate structure transistor is consistent with that of the two ends during processing, and there will be no protrusion of the insulating medium layer on the gate electrode, which ensures the flatness of subsequent processing. By spin-coating insulating medium and etching to form a second insulating layer with the same height as the source and drain electrodes, the height of the second insulating layer is also consistent with that of the source and drain regions, thus achieving the planarization of the dielectric layer. There will be no curling, wrinkles or other phenomena that would affect the graphene. The stress on the graphene film when it is transferred to the processed substrate will be greatly reduced, thereby reducing the damage to the graphene film. At the same time, the setting of nano-sized grooves on the insulating layer reduces the contact area between the graphene and the substrate, thereby reducing the influence of substrate scattering, improving the carrier mobility of graphene, and thus improving the device performance.

[0029] (2) In the method for preparing graphene field-effect transistors based on spin-coated insulating dielectric proposed in this invention, the insulating dielectric layer is processed by spin-coating, low-temperature baking and high-temperature annealing, which has a fast generation rate and low preparation temperature, which greatly helps to reduce the thermal stress during device processing and also achieves the planarization of the dielectric layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic cross-sectional view of a graphene field-effect transistor based on spin-coated insulating dielectric (SOD) technology provided in an embodiment of the present invention, wherein: 1-substrate, 2-gate electrode, 31-first insulating layer, 32-second insulating layer, 41-source, 42-drain, 5-gate dielectric layer, 6-groove, 7-graphene channel layer.

[0032] Figure 2 This is a schematic diagram of the top structure of a graphene field-effect transistor based on spin-coated insulating dielectric (SOD) technology provided in an embodiment of the present invention, wherein: 2-gate electrode, 32-second insulating layer, 41-source electrode, 42-drain electrode, 7-graphene channel layer;

[0033] Figure 3This is a schematic flowchart of the fabrication method of graphene field-effect transistor based on spin-coated insulating dielectric (SOD) technology according to an embodiment of the present invention, wherein: 1-substrate, 2-gate electrode, 31-first insulating layer, 32-second insulating layer, 41-source, 42-drain, 5-gate dielectric layer, 6-groove, 7-graphene channel layer. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] On one hand, the present invention provides a graphene field-effect transistor based on spin-coated insulating dielectric, the cross-sectional structure of which is shown in the figure below. Figure 1 As shown, the graphene field-effect transistor includes:

[0036] Base;

[0037] A gate electrode is disposed on the substrate, and a portion of the gate electrode is not covered by the second insulating layer to provide a gate voltage;

[0038] A gate dielectric layer is disposed above the gate electrode and the first insulating layer;

[0039] A first insulating layer and a second insulating layer. The first insulating layer is disposed on the substrate at both ends of the gate electrode and has the same height as the gate electrode. The second insulating layer is disposed on the gate dielectric layer and has multiple nano-sized grooves.

[0040] The source and drain are disposed on the gate dielectric layer and located at both ends of the second insulating layer;

[0041] The graphene channel layer is disposed on part of the source and drain regions and on the second insulating layer.

[0042] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, or Ti / Au.

[0043] Furthermore, the gate dielectric layer is made of a dielectric material, including TiO2. 2、 Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, LaAlO, with a gate dielectric layer thickness of 100nm-300nm.

[0044] Furthermore, the second insulating layer is located in a portion of the area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain regions.

[0045] Furthermore, the insulating dielectric material is one or more of SiO2, barium strontium titanate (BST), and lead zirconate titanate (PZT).

[0046] Furthermore, the graphene channel layer is a large-area graphene film with uniform synthesis performance, and it is also covered with a boron nitride protective layer.

[0047] Figure 2 A schematic diagram of the top structure of a graphene field-effect transistor based on spin-coated insulating medium is shown. As shown in the figure, there are two regions on both sides of the gate electrode. One part is not covered by the second insulating layer and the gate dielectric layer, and the other part is exposed by etching to provide the gate voltage. The source, drain and the second insulating layer have the same height. The graphene film covers part of the source, drain and the second insulating layer.

[0048] On the other hand, the present invention also provides a method for fabricating the above-mentioned graphene field-effect transistor based on spin-coating insulating dielectric technology, such as... Figure 3 As shown, the method includes:

[0049] A substrate is provided, on which a gate electrode is formed, and a portion of the gate electrode is exposed by etching to provide a gate voltage;

[0050] An insulating layer is formed on the substrate and the gate electrode. By etching away the insulating layer that is higher than the gate electrode, a first insulating layer is formed on both ends of the gate electrode, and the height of the insulating layer is consistent with that of the gate electrode.

[0051] A gate dielectric layer is formed on the first insulating layer and the gate electrode;

[0052] The source and drain are formed on the gate dielectric layer;

[0053] A second insulating layer is formed on the gate dielectric layer and between the source / drain and the gate. After forming, the portion higher than the height of the source and drain is etched away so that the height of the second insulating layer is consistent with the source and drain regions. Multiple nanoscale grooves are etched on the second insulating layer.

[0054] Graphene films are grown by chemical vapor deposition, then transferred onto the source / drain electrodes and the second insulating layer. Boron nitride is then applied over the graphene, and the film is patterned by laser direct writing etching to form a graphene channel layer.

[0055] Furthermore, the areas on the substrate where gate electrodes do not need to be formed are covered using processes such as ultraviolet lithography and development. The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, or Ti / Au, and is achieved by electron beam evaporation. The gate dielectric layer is achieved by atomic layer deposition (ALD) or chemical vapor deposition (PECVD), and is made of TiO2. 2、 The gate dielectric layer is one of Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, and LaAlO, with a thickness of 100nm-300nm.

[0056] Furthermore, the formation of the source and drain electrodes includes: spin-coating a high-precision photoresist layer on the gate dielectric layer, then precisely patterning the photoresist layer to expose the area where the electrode needs to be deposited, and performing electron beam evaporation on the area.

[0057] Furthermore, the first insulating layer and the second insulating layer are prepared by surface treatment, spin coating, low-temperature baking and high-temperature annealing after the preparation of the precursor solution. Nanoscale grooves are formed on the second insulating layer by focused ion beam or etching.

[0058] The following specific examples illustrate the fabrication process of graphene field-effect transistors based on spin-coating insulating dielectric technology.

[0059] Example 1

[0060] Step 1: Forming the gate electrode. The area on the substrate where the gate electrode does not need to be formed is covered by ultraviolet lithography. Then, 10nm of Ti and 40nm of Au are deposited sequentially in the above area by electron beam evaporation to form the gate electrode. Then, the photoresist and the metal on top are stripped with acetone.

[0061] Step 2: Form the first insulating dielectric layer of the graphene field-effect transistor based on spin-coated insulating dielectric (SOD) technology. The first insulating layer is formed by spin coating, low-temperature baking and high-temperature annealing. The insulating dielectric covering the gate electrode is etched away to keep the first insulating layer and the gate electrode at the same height. The material of the first insulating dielectric layer is SiO2.

[0062] Step 3: Form a gate dielectric layer. A 100 nm thick gate dielectric layer is formed by chemical vapor deposition. The gate dielectric layer uses TiO2.

[0063] Step 4: Generate source and drain electrodes on the gate dielectric layer. Spin-coat photoresist on the substrate with the deposited gate dielectric layer. After patterning by ultraviolet lithography, expose the area where the electrodes need to be deposited. Then, deposit 10nm Ti and 40nm Au in the source and drain areas by electron beam evaporation to form source and drain electrodes.

[0064] Step 5: Form the second insulating layer. On the substrate where the source and drain electrodes have been deposited, the insulating medium is cured by processes such as spin coating, low temperature baking and high temperature annealing to form the second insulating layer. Similarly, the insulating medium covering the source and drain electrodes is etched away to keep the second insulating layer and the source and drain electrodes at the same height. The material of the second insulating medium layer is SiO2.

[0065] Step 6: Form multiple nanoscale grooves on the second insulating layer by focusing an ion beam.

[0066] Step 7: Transfer a graphene boron nitride film grown on another substrate by chemical vapor deposition onto the substrate that has been filled with the second insulating layer, then pattern the graphene boron nitride film, and then remove the graphene boron nitride in the channel region and outside the source and drain electrodes to form a graphene channel layer; Optionally, the patterned graphene boron nitride film is patterned using laser direct writing technology to avoid other substances from contacting the film and thus affecting the properties of the film.

[0067] Example 2

[0068] Step 1: Forming the gate electrode. The area on the substrate where the gate electrode does not need to be formed is covered by ultraviolet lithography. Then, 10nm Ni and 40nm Au are deposited sequentially in the above area by electron beam evaporation to form the gate electrode. Then, the photoresist and the metal on top are stripped with acetone.

[0069] Step 2: Form the first insulating dielectric layer of the graphene field-effect transistor based on spin-coated insulating dielectric (SOD) technology. The first insulating layer is formed by spin coating, low-temperature baking and high-temperature annealing. The insulating dielectric covering the gate electrode is etched away to keep the first insulating layer and the gate electrode at the same height. The material of the first insulating dielectric layer is lead zirconate titanate (PZT).

[0070] Step 3: Form a gate dielectric layer. A 300 nm thick gate dielectric layer is formed by chemical vapor deposition. The gate dielectric layer is made of Al2O3.

[0071] Step 4: Generate source and drain electrodes on the gate dielectric layer. Spin-coat photoresist on the substrate with the deposited gate dielectric layer. After patterning by ultraviolet lithography, expose the area where the electrodes need to be deposited. Then, deposit 10nm Ni and 40nm Au in the source and drain areas by electron beam evaporation to form source and drain electrodes.

[0072] Step 5: Form the second insulating layer. On the substrate where the source and drain electrodes have been deposited, the insulating medium is cured by spin coating, low-temperature baking and high-temperature annealing to form the second insulating layer. Similarly, the insulating medium covering the source and drain electrodes is etched away to keep the second insulating layer and the source and drain electrodes at the same height. The material of the second insulating medium layer is lead zirconate titanate (PZT).

[0073] Step 6: Form multiple nanoscale grooves by etching on the second insulating layer.

[0074] Step 7: Transfer a graphene boron nitride film grown on another substrate by chemical vapor deposition onto the substrate that has been filled with the second insulating layer, then pattern the graphene boron nitride film, and then remove the graphene boron nitride in the channel region and outside the source and drain electrodes to form a graphene channel layer; Optionally, the patterned graphene boron nitride film is patterned using laser direct writing technology to avoid other substances from contacting the film and thus affecting the properties of the film.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a graphene field-effect transistor based on spin-coating insulating dielectric technology, characterized in that, The method includes: A substrate is provided on which a gate electrode is formed; An insulating layer is formed on the substrate and the gate electrode. By etching away the insulating layer that is higher than the gate electrode, a first insulating layer is formed on both ends of the gate electrode, and the height of the insulating layer is consistent with that of the gate electrode. A gate dielectric layer is formed on the first insulating layer and the gate electrode; The source and drain are formed on the gate dielectric layer; A second insulating layer is formed on the gate dielectric layer and between the source / drain and the gate. After forming, the portion higher than the height of the source and drain is etched away so that the height of the second insulating layer is consistent with the source and drain regions. Multiple nanoscale grooves are etched on the second insulating layer. Graphene films are grown by chemical vapor deposition, then transferred onto the source / drain electrodes and the second insulating layer. Boron nitride is then applied over the graphene, and the film is patterned by laser direct writing etching to form a graphene channel layer. The first and second insulating layers are formed by preparing a precursor solution and then using surface treatment, spin coating, low-temperature baking and high-temperature annealing processes. Nanoscale grooves are formed on the second insulating layer by focusing ion beam or etching.

2. The preparation method according to claim 1, characterized in that, The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au, and is achieved by electron beam evaporation. The gate dielectric layer is achieved by atomic layer deposition (ALD) or chemical vapor deposition (PECVD), and is one of TiO2, Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, and LaAlO, with a thickness of 100nm-300nm.

3. The preparation method according to claim 1, characterized in that, The formation of source and drain electrodes includes: spin-coating a high-precision photoresist layer on the gate dielectric layer, then precisely patterning the photoresist layer to expose the area where the electrode needs to be deposited, and performing electron beam evaporation on the area.

4. A graphene field-effect transistor based on spin-coating insulating dielectric technology, prepared by the method for preparing a graphene field-effect transistor based on spin-coating insulating dielectric technology according to any one of claims 1-3, characterized in that, The graphene field-effect transistor includes: Base; A gate electrode is disposed on the substrate, and a portion of the gate electrode is not covered by the second insulating layer; A gate dielectric layer is disposed above the gate electrode and the first insulating layer; A first insulating layer and a second insulating layer. The first insulating layer is disposed on the substrate at both ends of the gate electrode and has the same height as the gate electrode. The second insulating layer is disposed on the gate dielectric layer and has multiple nano-sized grooves. The source and drain are disposed on the gate dielectric layer and located at both ends of the second insulating layer; The graphene channel layer is disposed on part of the source and drain regions and on the second insulating layer.

5. The graphene field-effect transistor based on spin-coated insulating dielectric technology according to claim 4, characterized in that, The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, or Ti / Au.

6. The graphene field-effect transistor based on spin-coated insulating dielectric technology according to claim 4, characterized in that, The gate dielectric layer uses a dielectric material, which is one of TiO2, Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, and LaAlO. The thickness of the gate dielectric layer is 100nm-300nm.

7. The graphene field-effect transistor based on spin-coated insulating dielectric technology according to claim 4, characterized in that, The second insulating layer is located in a portion of the area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain regions.

8. The graphene field-effect transistor based on spin-coated insulating dielectric technology according to claim 4, characterized in that, The insulating dielectric material is one or more of SiO2, barium strontium titanate (BST), and lead zirconate titanate (PZT).

9. The graphene field-effect transistor based on spin-coated insulating dielectric technology according to claim 4, characterized in that, The graphene channel layer is a large-area graphene film with uniform synthesis performance, and it is also covered with a boron nitride protective layer.

Images