An adjustable SCR device for ESD protection and connection method thereof

Abstract

The present invention proposes an adjustable SCR device for ESD protection and a connection method thereof, which belongs to the field of electronic science and technology. The device includes: a P-type substrate, an insulating layer, a first polysilicon gate region, a second polysilicon gate region, an N-type well region, a P-type well region, a first N+ region, a first P+ region, a second N+ region, a second P+ region, a first N-type channel region, a P-type channel region, and a second N-type channel region. In the above structure, the first N+ region and the first P+ region are interconnected by wires to form the anode of the device, and the second N+ region and the second P+ region are interconnected by wires to form the cathode of the device. The present invention introduces an NPN superjunction channel and a polysilicon side gate by improving the structure of a traditional SCR device without increasing the device area, and increases the NPN-type conforming channel region of the superjunction structure, thereby realizing adjustable current distribution and parameter characteristics of the SCR device.

Description

Technical Field

[0001] The invention belongs to the field of electronic science and technology, and in particular relates to an adjustable SCR device for ESD protection and a connection method thereof. Background Art

[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. However, such common electrical phenomena are a fatal threat to precision integrated circuits. Surge / transient voltage refers to the high voltage or current that suddenly appears in the circuit and exceeds the normal state. It is characterized by a short occurrence time and very large instantaneous energy. Surge is very destructive to electronic components and integrated circuits. It can induce malfunction of logic circuits at the least, and cause serious thermal effects such as secondary breakdown of transistors and latch effect of complementary metal oxide semiconductors (CMOS) to make devices or integrated circuits fail. Surge usually has two random sources. The first is the instability of the power grid, such as sudden switching, sudden startup of capacitive or inductive loads, hot plugging of related equipment, and unstable operation of related power supplies. The second is sudden interference from the outside, such as lightning and electrostatic discharge.

[0003] With the improvement of integrated circuit manufacturing technology, its minimum line width has dropped to the sub-micron or even nanometer level. While improving chip performance, its ability to resist ESD strikes has also been greatly reduced, so electrostatic damage is more serious. Most of the ESD can cause non-fatal damage to integrated circuits, thereby reducing the life and reliability of integrated circuits, and further causing degradation of system functions, which is a great obstacle to achieving large-scale high-reliability integration.

[0004] ESD devices are important semiconductor protection devices. When turned on, they have extremely low resistance values ​​and can absorb transient pulse power of up to several kilowatts. They clamp the voltage of the port at a relatively safe preset value, thereby protecting the corresponding circuit from damage or even irreversible damage caused by transient voltage pulses or current surges. ESD devices have the characteristics of fast response speed, low leakage, high transient power, and small size. They are currently widely used in overvoltage protection in various fields such as electromechanical systems, power supply equipment, electromagnetic interference suppression, input and output interfaces, communication equipment, and relays.

[0005] There are some problems with SCR devices in ESD protection. First, its trigger voltage is too high, which means that when ESD occurs, a higher voltage may be required to turn on the SCR and start discharging current. If the internal circuit is damaged by ESD before the SCR turns on, it will not be able to play an effective protective role. Secondly, the holding voltage after the SCR hysteresis is very low (can be lower than 2V). The too low holding voltage does not meet the lower limit of the ESD design window voltage requirement and is prone to cause the latch effect of the circuit. In addition, the SCR turns on slowly because after its avalanche breakdown, it takes a long time for the npn and pnp transistors to turn on and form positive feedback. Summary of the invention

[0006] The present invention aims to provide an adjustable SCR device for ESD protection and a connection method thereof, so as to solve the technical problem in the prior art that the SCR device cannot play an effective protective role in ESD protection.

[0007] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0008] An adjustable SCR device for ESD protection includes: a P-type substrate, an insulating layer, a first polysilicon gate region, a second polysilicon gate region, an N-type well region, a P-type well region, a first N+ region, a first P+ region, a second N+ region, a second P+ region, a first N-type channel region, a P-type channel region, and a second N-type channel region.

[0009] In the above structure, the first N+ region and the first P+ region are interconnected by wires to form an anode of the device, and the second N+ region and the second P+ region are interconnected by wires to form a cathode of the device.

[0010] Furthermore, the insulating layer is located inside the P-type substrate, the lower edge of the insulating layer is higher than the lower edge of the P-type substrate, and the upper edge of the insulating layer is lower than the upper edge of the P-type substrate.

[0011] The N-type well region and the P-type well region are located inside the P-type substrate and above the insulating layer. The lower edge of the N-type well region and the lower edge of the P-type well region are tangent to the upper edge of the insulating layer respectively, and the upper edge of the N-type well region and the upper edge of the P-type well region are tangent to the upper edge of the P-type substrate respectively; wherein, the relative position of the N-type well region is on the left side of the P-type well region, and the right edge of the N-type well region is 10um to 50um away from the left edge of the P-type well region.

[0012] The first N+ region and the first P+ region are located inside the N-type well region, the upper edge of the first N+ region and the upper edge of the first P+ region are both tangent to the upper edge of the N-type well region, and the lower edge of the first N+ region and the lower edge of the first P+ region are both higher than the lower edge of the N-type well region; wherein the relative position of the first N+ region is on the left side of the first P+ region, and the right edge of the first N+ region is 2um to 5um away from the left edge of the first P+ region.

[0013] The second N+ region and the second P+ region are located inside the P-type well region, the upper edge of the second N+ region and the upper edge of the second P+ region are both tangent to the upper edge of the P-type well region, and the lower edge of the second N+ region and the lower edge of the second P+ region are both higher than the lower edge of the P-type well region; wherein the relative position of the second N+ region is on the left side of the second P+ region, and the right edge of the second N+ region is 2um to 5um away from the left edge of the second P+ region.

[0014] The first polysilicon gate region and the second polysilicon gate region are located inside the P-type substrate and between the N-type well region and the P-type well region. The left edge of the first polysilicon gate region and the left edge of the second polysilicon gate region are tangent to the right edge of the N-type well region respectively. The right edge of the first polysilicon gate region and the right edge of the second polysilicon gate region are both tangent to the left edge of the P-type well region. The upper edge of the first polysilicon gate region and the upper edge of the second polysilicon gate region are both tangent to the upper edge of the P-type substrate. The lower edge of the first polysilicon gate region and the lower edge of the second polysilicon gate region are both tangent to the upper edge of the insulating layer. The relative position of the first polysilicon gate region is in front of the second polysilicon gate region, and the distance between the two is 5um to 30um.

[0015] The first N-type channel region, the P-type channel region and the second N-type channel region are inside the P-type substrate and are located between the first polysilicon gate region and the second polysilicon gate region. The relative positions of the first N-type channel region, the P-type channel region and the second N-type channel region from front to back are the first N-type channel region, the P-type channel region and the second N-type channel region. The left edge of the first N-type channel region, the left edge of the P-type channel region and the left edge of the second N-type channel region are tangent to the right edge of the N-type well region respectively, the right edge of the first N-type channel region, the right edge of the P-type channel region and the right edge of the second N-type channel region are all tangent to the left edge of the P-type well region, the upper edge of the first N-type channel region, the upper edge of the P-type channel region and the upper edge of the second N-type channel region are all tangent to the upper edge of the P-type substrate, and the lower edge of the first N-type channel region, the lower edge of the P-type channel region and the lower edge of the second N-type channel region are tangent to the upper edge of the insulating layer.

[0016] The first polysilicon gate region and the second polysilicon gate region are gates of the device; the first polysilicon gate region is Gate1, and the second polysilicon gate region is Gate2.

[0017] The present invention also provides a connection method for an adjustable SCR device for ESD protection. The connection method uses the adjustable SCR device structure as a basic unit to integrate multiple devices together; a second adjustable SCR device is added to the rear side of Gate 2 of the first adjustable SCR device, and Gate 2 is used as a common gate of the two device cells, that is, Gate 2 is also Gate 1 of the second adjustable SCR device, to achieve integration of two adjustable SCR devices. In this way, any number of adjustable SCR devices can be continuously integrated to achieve integration of multiple devices.

[0018] Furthermore, when different voltages are applied to different gates, the current distribution can be adjusted by controlling the width of the depletion layer. When the same voltage is applied to different gates, a uniform distribution of current in the channel region can be achieved;

[0019] The equivalent circuit is: the first P+ region, N-type well region, and P-type channel region constitute the parasitic PNP tube inside the device, and its emitter and the parasitic resistance R in the N-type well region n The first N-type channel region and the second N-type channel region, the P-type well region, and the second N+ region constitute a parasitic NPN tube inside the device, and its emitter and the parasitic resistance R in the P-type well region p The first N-type channel region, the P-type channel region and the second N-type channel region of different adjustable SCR device units respectively constitute the parasitic JFET tube inside the device, which is connected to the parasitic PNP tube and the parasitic resistor R n And parasitic NPN tube, parasitic resistance R p The parasitic JFET tubes are connected in parallel and jointly control the current distribution of the entire device according to the working environment and connection mode of the chip.

[0020] Compared with the prior art, the present invention has the following beneficial technical effects: Based on the traditional SCR device structure, the present invention combines SOI technology, super junction structure and trenching process to propose an SCR device structure with flexible design, reliable performance and adjustable device performance parameters. The present invention introduces an NPN super junction channel and polysilicon side gates by improving the traditional SCR device structure without increasing the device area, thereby increasing the NPN type conforming channel area of ​​the super junction structure, thereby achieving adjustable current distribution and parameter characteristics of the SCR device. Compared with the traditional SCR device structure, this structure can adjust the channel current size and current distribution when different bias voltages are applied to different side gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0022] Figure 1 This is a schematic diagram of the structure of an adjustable SCR device for ESD protection proposed by the present invention;

[0023] Figure 2 The equivalent circuit diagram of the adjustable SCR device for ESD protection proposed by the present invention;

[0024] Figure 3 A schematic diagram of a connection application method of an adjustable SCR device;

[0025] Figure 4 The figure is an equivalent circuit diagram of a connection application method of an adjustable SCR device.

[0026] Explanation of the markings in the figure: 101 - P-type substrate, 102 - insulating layer, 103 - first polysilicon gate region, 104 - second polysilicon gate region, 105 - N-type well region, 106 - P-type well region, 107 - first N+ region, 108 - first P+ region, 109 - second N+ region, 110 - first P+ region, 111 - first N-type channel region, 112 - P-type channel region, 113 - second N-type channel region. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Embodiment 1:

[0029] like Figure 1 As shown, this embodiment provides an adjustable SCR device structure for ESD protection, the device comprising: a P-type substrate 101, an insulating layer 102, a first polysilicon gate region 103, a second polysilicon gate region 104, an N-type well region 105, a P-type well region 106, a first N+ region 107, a first P+ region 108, a second N+ region 109, a second P+ region 110, a first N-type channel region 111, a P-type channel region 112, and a second N-type channel region 113.

[0030] Specific:

[0031] The insulating layer 102 is located inside the P-type substrate 101 , the lower edge of the insulating layer 102 is higher than the lower edge of the P-type substrate 101 , and the upper edge of the insulating layer 102 is lower than the upper edge of the P-type substrate 101 .

[0032] The N-type well region 105 and the P-type well region 106 are located inside the P-type substrate 101 and above the insulating layer 102. The lower edge of the N-type well region 105 and the lower edge of the P-type well region 106 are respectively tangent to the upper edge of the insulating layer 102, and the upper edge of the N-type well region 105 and the upper edge of the P-type well region 106 are respectively tangent to the upper edge of the P-type substrate 101; wherein, the relative position of the N-type well region 105 is on the left side of the P-type well region 106, and the right edge of the N-type well region 105 is 10um to 50um away from the left edge of the P-type well region 106.

[0033] The first N+ region 107 and the first P+ region 108 are located inside the N-type well region 105, and the upper edge of the first N+ region 107 and the upper edge of the first P+ region 108 are both tangent to the upper edge of the N-type well region 105, and the lower edge of the first N+ region 107 and the lower edge of the first P+ region 108 are both higher than the lower edge of the N-type well region 105; wherein, the relative position of the first N+ region 107 is on the left side of the first P+ region 108, and the right edge of the first N+ region 107 is 2um to 5um away from the left edge of the first P+ region 108.

[0034] The second N+ region 109 and the second P+ region 110 are located inside the P-type well region 106, the upper edge of the second N+ region 109 and the upper edge of the second P+ region 110 are both tangent to the upper edge of the P-type well region 106, and the lower edge of the second N+ region 109 and the lower edge of the second P+ region 110 are higher than the lower edge of the P-type well region 106; wherein, the relative position of the second N+ region 109 is on the left side of the second P+ region 110, and the right edge of the second N+ region 109 is 2um to 5um away from the left edge of the second P+ region 110.

[0035] The first polysilicon gate region 103 and the second polysilicon gate region 104 are located inside the P-type substrate 101 and between the N-type well region 105 and the P-type well region 106. The left edge of the first polysilicon gate region 103 and the left edge of the second polysilicon gate region 104 are tangent to the right edge of the N-type well region 105, respectively. The right edge of the first polysilicon gate region 103 and the right edge of the second polysilicon gate region 104 are both tangent to the left edge of the P-type well region 106. The upper edge of the first polysilicon gate region 103 and the upper edge of the second polysilicon gate region 104 are both tangent to the upper edge of the P-type substrate 101. The lower edge of the first polysilicon gate region 103 and the lower edge of the second polysilicon gate region 104 are both tangent to the upper edge of the insulating layer 102. The relative position of the first polysilicon gate region 103 is in front of the second polysilicon gate region 104, and the distance between the two is 5um to 30um.

[0036] The first N-type channel region 111, the P-type channel region 112 and the second N-type channel region 113 are inside the P-type substrate 101 and are located between the first polysilicon gate region 103 and the second polysilicon gate region 104. The first N-type channel region 111, the P-type channel region 112 and the second N-type channel region 113 are located in the first N-type channel region 111, the P-type channel region 112 and the second N-type channel region 113 from front to back. The left edge of the first N-type channel region 111, the left edge of the P-type channel region 112, and the left edge of the second N-type channel region 113 are respectively tangent to the right edge of the N-type well region 105, the right edge of the first N-type channel region 111, the right edge of the P-type channel region 112, and the right edge of the second N-type channel region 113 are all tangent to the left edge of the P-type well region 106, the upper edge of the first N-type channel region 111, the upper edge of the P-type channel region 112, and the upper edge of the second N-type channel region 113 are all tangent to the upper edge of the P-type substrate 101, and the lower edge of the first N-type channel region 111, the lower edge of the P-type channel region 112, and the lower edge of the second N-type channel region 113 are all tangent to the upper edge of the insulating layer 102.

[0037] The first N+ region 107 and the first P+ region 108 are interconnected by wires to form the anode of the device, and the second N+ region 109 and the second P+ region 110 are interconnected by wires to form the cathode of the device. The first polysilicon gate region 103 and the second polysilicon gate region 104 are the gates of the device; the first polysilicon gate region 103 is Gate1, and the second polysilicon gate region 104 is Gate2.

[0038] The equivalent circuit of the adjustable SCR device structure is as follows: Figure 2 As shown, the first P+ region 108, the N-type well region 105, and the P-type channel region 112 constitute a parasitic PNP transistor inside the device. The emitter of the parasitic PNP transistor and the parasitic resistance R in the N-type well region 105 are connected. n The first N-type channel region 111 and the second N-type channel region 113, the P-type well region 106, and the second N+ region 109 constitute a parasitic NPN transistor inside the device. The emitter of the parasitic NPN transistor and the parasitic resistor R in the P-type well region 106 p The first N-type channel region 111, the P-type channel region 112 and the second N-type channel region 113 constitute a parasitic JFET tube inside the device connected to the parasitic PNP tube and the parasitic resistor R n And parasitic NPN tube, parasitic resistance R p That is, Gate 1 and Gate 2 in the equivalent circuit diagram.

[0039] When the device is working, two PN junctions are formed in the NPN channel region of the superjunction structure between the N-type well region 105 and the P-type well region 106. The magnitude and distribution of the current passing through the channel region can be controlled by applying different bias voltages to the gate, thereby achieving regulation and control of the SCR device.

[0040] Embodiment 2:

[0041] This embodiment provides a connection application method for an adjustable SCR device. Figure 3 As shown, this embodiment is Figure 1 The adjustable SCR device structure shown is a basic unit that integrates multiple devices together. The specific implementation is as follows: On the rear side of Gate 2 of the first adjustable SCR device, a second adjustable SCR device is added, and Gate 2 is used as the common gate of the two device cells (that is, Gate 2 of the first adjustable SCR device is also Gate 1 of the second adjustable SCR device) to achieve the integration of two adjustable SCR devices. In this way, any number of adjustable SCR devices can be integrated to achieve the integration of multiple devices.

[0042] When different voltages are applied to different gates, the current distribution is adjusted by controlling the width of the depletion layer. When the same voltage is applied to different gates, a uniform distribution of current in the channel region can be achieved. Figure 3 The integration of two basic units is demonstrated, and any number of adjustable SCR devices can be integrated as basic units according to actual application scenarios and application requirements.

[0043] like Figure 4 As shown in FIG. 1 , it is an equivalent circuit diagram of the connection application mode. The first P+ region 108, the N-type well region 105, and the P-type channel region 112 constitute a parasitic PNP tube inside the device. The emitter of the parasitic PNP tube and the parasitic resistance R in the N-type well region 105 are n The first N-type channel region 111 and the second N-type channel region 113, the P-type well region 106, and the second N+ region 109 constitute a parasitic NPN transistor inside the device. The emitter of the parasitic NPN transistor and the parasitic resistor R in the P-type well region 106 p The first N-type channel region 111, the P-type channel region 112 and the second N-type channel region 113 of the different adjustable SCR device units respectively constitute the parasitic JFET tube inside the device connected to the parasitic PNP tube and the parasitic resistor R n And parasitic NPN tube, parasitic resistance R p These parasitic JFETs are connected in parallel and control the overall current distribution of the device according to the working environment and connection method of the chip.

[0044] Working principle:

[0045] The adjustable SCR device structure for ESD protection proposed in the present invention combines SOI technology, super junction structure and trenching process, introduces an NPN super junction channel and polysilicon side gate between the N-type well region and the P-type well region of the traditional SCR device, and realizes adjustable current distribution and parameter characteristics of the SCR device without increasing the area occupied by the device.

[0046] When an ESD event occurs at the anode, the SCR device structure will quickly open to form a large current discharge path, achieve conductivity modulation, and protect the working circuit from the threat of ESD events. Unlike traditional SCR devices, when the adjustable SCR device is working, two PN junctions are formed in the NPN superjunction channel region. When different bias voltages are applied to different side gates, the depletion layer widths of the two PN junctions will change accordingly, causing the current path width of the device channel to change, thereby achieving the adjustment of the channel current. If the same bias voltage is applied to different side gates, the current can be evenly distributed in the device channel region.

[0047] The device structure and the drawings proposed in the present invention are only a display and description of the adjustable SCR device structure for ESD protection. In addition to the structure in the drawings, anyone familiar with this technology can modify or change the above structure without violating the spirit and scope of the present invention, such as changing the SCR structure described above to a PNP structure, an NPN structure, a diode structure, a MOS structure, etc., and these structures should obviously be within the scope of protection of the present invention.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An adjustable SCR device for ESD protection, characterized in that: The device comprises: a P-type substrate (101), an insulating layer (102), a first polysilicon gate region (103), a second polysilicon gate region (104), an N-type well region (105), a P-type well region (106), a first N+ region (107), a first P+ region (108), a second N+ region (109), a second P+ region (110), a first N-type channel region (111), a P-type channel region (112), and a second N-type channel region (113); The first N+ region (107) and the first P+ region (108) are interconnected by wires to form an anode of the device, and the second N+ region (109) and the second P+ region (110) are interconnected by wires to form a cathode of the device; The insulating layer (102) is located inside the P-type substrate (101), the lower edge of the insulating layer (102) is higher than the lower edge of the P-type substrate (101), and the upper edge of the insulating layer (102) is lower than the upper edge of the P-type substrate (101); The N-type well region (105) and the P-type well region (106) are located inside the P-type substrate (101) and above the insulating layer (102); the lower edge of the N-type well region (105) and the lower edge of the P-type well region (106) are respectively tangent to the upper edge of the insulating layer (102); the upper edge of the N-type well region (105) and the upper edge of the P-type well region (106) are respectively tangent to the upper edge of the P-type substrate (101); wherein the relative position of the N-type well region (105) is on the left side of the P-type well region (106); and the right edge of the N-type well region (105) and the left edge of the P-type well region (106) are 10 um to 50 um apart; The first N+ region (107) and the first P+ region (108) are located inside the N-type well region (105); the upper edge of the first N+ region (107) and the upper edge of the first P+ region (108) are both tangent to the upper edge of the N-type well region (105); the lower edge of the first N+ region (107) and the lower edge of the first P+ region (108) are both higher than the lower edge of the N-type well region (105); wherein the relative position of the first N+ region (107) is on the left side of the first P+ region (108); and the right edge of the first N+ region (107) and the left edge of the first P+ region (108) are spaced 2um to 5um apart; The second N+ region (109) and the second P+ region (110) are located inside the P-type well region (106); the upper edge of the second N+ region (109) and the upper edge of the second P+ region (110) are both tangent to the upper edge of the P-type well region (106); the lower edge of the second N+ region (109) and the lower edge of the second P+ region (110) are both higher than the lower edge of the P-type well region (106); wherein the relative position of the second N+ region (109) is on the left side of the second P+ region (110); and the right edge of the second N+ region (109) and the left edge of the second P+ region (110) are spaced 2 um to 5 um apart; The first polysilicon gate region (103) and the second polysilicon gate region (104) are located inside the P-type substrate (101) and between the N-type well region (105) and the P-type well region (106); the left edge of the first polysilicon gate region (103) and the left edge of the second polysilicon gate region (104) are tangent to the right edge of the N-type well region (105), respectively; the right edge of the first polysilicon gate region (103) and the right edge of the second polysilicon gate region (104) are both tangent to the P-type well region (106). ), the upper edge of the first polysilicon gate region (103) and the upper edge of the second polysilicon gate region (104) are both tangent to the upper edge of the P-type substrate (101), and the lower edge of the first polysilicon gate region (103) and the lower edge of the second polysilicon gate region (104) are both tangent to the upper edge of the insulating layer (102); the relative position of the first polysilicon gate region (103) is in front of the second polysilicon gate region (104), and the distance between the two is 5um to 30um; The first N-type channel region (111), the P-type channel region (112) and the second N-type channel region (113) are inside the P-type substrate (101) and are located between the first polysilicon gate region (103) and the second polysilicon gate region (104); the relative positions of the first N-type channel region (111), the P-type channel region (112) and the second N-type channel region (113) from front to back are the first N-type channel region (111), the P-type channel region (112) and the second N-type channel region (113); the left edge of the first N-type channel region (111), the left edge of the P-type channel region (112) and the left edge of the second N-type channel region (113) The right edges of the first N-type channel region (111), the P-type channel region (112) and the second N-type channel region (113) are tangent to the left edge of the P-type well region (106); the upper edge of the first N-type channel region (111), the upper edge of the P-type channel region (112) and the upper edge of the second N-type channel region (113) are tangent to the upper edge of the P-type substrate (101); and the lower edge of the first N-type channel region (111), the lower edge of the P-type channel region (112) and the lower edge of the second N-type channel region (113) are tangent to the upper edge of the insulating layer (102); The first polysilicon gate region (103) and the second polysilicon gate region (104) are gates of the device; the first polysilicon gate region (103) is Gate1, and the second polysilicon gate region (104) is Gate2.

2. The adjustable SCR device for ESD protection according to claim 1, characterized in that: The equivalent circuit is as follows: the first P+ region (108), the N-type well region (105), and the P-type channel region (112) constitute a parasitic PNP tube inside the device, and the emitter of the parasitic PNP tube and the parasitic resistor Rn in the N-type well region (105) are connected to the anode of the device; the first N-type channel region (111), the second N-type channel region (113), the P-type well region (106), and the second N+ region (109) constitute a parasitic NPN tube inside the device, and the emitter of the parasitic NPN tube and the parasitic resistor Rp in the P-type well region (106) are connected to the cathode of the device; the first N-type channel region (111), the P-type channel region (112), and the second N-type channel region (113) constitute a parasitic JFET tube inside the device, and the parasitic JFET tube is connected between the parasitic PNP tube, the parasitic resistor Rn, and the parasitic NPN tube, the parasitic resistor Rp.

3. A connection method for an adjustable SCR device for ESD protection, characterized in that: The connection method uses the adjustable SCR device described in claim 1 as a basic unit to integrate multiple devices together; a second adjustable SCR device is added to the rear side of Gate 2 of the first adjustable SCR device, and Gate 2 is used as a common gate of the two device cells, that is, Gate 2 of the first adjustable SCR device is also Gate 1 of the second adjustable SCR device, thereby realizing the integration of two adjustable SCR devices; any number of adjustable SCR devices are continuously integrated in this way to realize the integration of multiple devices.

4. The connection method of the adjustable SCR device for ESD protection according to claim 3, characterized in that: When different voltages are applied to different gates, the current distribution is adjusted by controlling the width of the depletion layer; when the same voltage is applied to different gates, the current is evenly distributed in the channel region. The equivalent circuit is as follows: the first P+ region (108), the N-type well region (105), and the P-type channel region (112) constitute a parasitic PNP tube inside the device, and the emitter of the parasitic PNP tube and the parasitic resistance R in the N-type well region (105) n The first N-type channel region (111), the second N-type channel region (113), the P-type well region (106), and the second N+ region (109) constitute a parasitic NPN tube inside the device, and the emitter of the parasitic NPN tube is connected to the parasitic resistance R in the P-type well region (106). p The first N-type channel region (111), the P-type channel region (112) and the second N-type channel region (113) of the different adjustable SCR device units respectively constitute a parasitic JFET tube inside the device, and the parasitic JFET tube is connected to the parasitic PNP tube, the parasitic resistor R n And parasitic NPN tube, parasitic resistance R p These parasitic JFET tubes are connected in parallel and jointly control the overall current distribution of the device according to the working environment and connection method of the chip.

Images