Mixed stacked super compound eye chip capable of realizing wide-spectrum wide-angle detection and preparation method thereof

Abstract

The invention discloses a mixed stacked super compound eye chip capable of wide-spectrum wide-angle detection and a preparation method, the chip combines a 2.5 D out-of-plane architecture super bionic compound eye metasurface, a continuous domain bound state effect and a chip mixed stacked read-out integrated module, and has a large-area 2.5 D out-of-plane metasurface architecture. The structure integrates a single layer of Gr to simulate compound eyes of insects. Wide-angle detection equivalent to a curved surface is realized in the whole plane-level detection area on the chip, and meanwhile, absorption of a 1550 nm communication frequency band is improved to be close to 100% (300-1600 nm) through a continuous domain bound state effect. The invention also integrates a TSV (Through Silicon Via) technology for wafer-level manufacturing, designs a readout integrated circuit, and realizes a super-bionic compound eye chip based on stack integration. According to the invention, wide-angle detection in a planar chip is realized, and the detection range of a silicon-based chip is widened.

Description

Technical Field

[0001] The present invention belongs to the technical field of photoelectric detection, and in particular relates to a hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection and a preparation method thereof. Background Art

[0002] With the continuous development of optoelectronic technology, the demand for photoelectric detectors with wide spectrum, wide angle and other specific detection capabilities in the fields of optical communication, remote sensing and security monitoring is increasing day by day. Especially in the 1550 nm communication band, its wide spectrum and wide angle detection performance plays a key role in achieving accurate target recognition and signal acquisition.

[0003] However, traditional photoelectric detection technologies mostly use non-silicon-based broadband materials (such as InGaAs and Ge). Although their spectral response is broad, the material cost is high and the preparation is complex. In addition, existing wide-angle detection methods mostly rely on curved or spherical structures. Due to the complex manufacturing process and the limitation of the detection unit size, the complexity of the integration process is increased, and it is difficult to be compatible with conventional CMOS processes, which limits its applicability in modern electronic devices.

[0004] A Chinese patent application with publication number CN102250377B discloses a wide-spectrum and wide-angle anti-reflective polymer nano-bionic structural material and a preparation method thereof. The patent mentions that a wide-spectrum and wide-angle anti-reflective performance is achieved by forming a three-dimensional nano-gradient array structure on the surface of a polymer substrate. The anti-reflection performance is relatively high in the 360-1000nm spectral band with an incident angle of 0-60°. However, the polymer array structure cannot achieve effective absorption of incident light (absorption = total incident light - reflected light - transmitted light). The incident light is lost by transmission after passing through, and cannot be applied to the field of photoelectric detection. In addition, the working wavelength range is narrow, and the range of incident angles that can be targeted is limited, and it is impossible to operate in communication bands such as 1550nm.

[0005] The Chinese patent application with publication number CN115440828A discloses a photoelectric detection chip based on a metamaterial microstructure and its preparation method and device. The patent mentions that the recognition ability and detection accuracy of the photoelectric detection chip are improved by using a metamaterial microstructure located on the surface of the optoelectronic semiconductor device and using the RLC circuit model theory. However, due to the limitations of the preparation method of the metamaterial microstructure, the photoelectric detection chip can only prepare a 2D structure, and cannot achieve a 2.5D continuous domain bound state structure that breaks the out-of-plane symmetry, and cannot achieve a wide angle. In addition, the effective value of the detection of the photoelectric detection chip in the spectral range has not been explained, and there is a lack of effective circuit integrated readout and solution of the signal.

[0006] The structure of insect compound eyes can focus light within a larger viewing angle and maintain high detection efficiency under weak light conditions by arranging the crystal cones of the eyelet units into a hexagonal honeycomb structure. This design provides a natural advantage in broadening the field of view and weak light detection performance. In addition, insect compound eyes are environmentally tolerant, and even if some of the eyelet units fail, it does not affect the overall detection performance, providing a reference for the robustness of photoelectric detection devices. Bionic design can draw on the wide viewing angle and optical efficiency of insect compound eyes, and achieve ultra-wide-angle detection through bionic compound eye structures, which can effectively solve the bottlenecks of traditional photoelectric detectors in terms of viewing angle range and detection efficiency. For example, Yu Zhou et al. combined a 3D-printed honeycomb optical structure with a hemispherical, all-solid-state, high-density perovskite nanowire photodetector array to realize a pinhole compound eye detector (“An ultrawidefield-of-view pinhole compound eye using hemispherical nanowire array for robot vision”, Science Robotics, 9, eadi8666, 2024). However, the detector has a complex manufacturing process and a large area, and cannot be effectively integrated with the CMOS process. In addition, the detection range is narrow and can only detect visible light. The wide-angle detection range is only 140°, and the practical application value is low. Therefore, in the prior art, there are no reported solutions for wide-spectrum photoelectric detection and wide-angle photoelectric integration, which has become a major gap in current technology. Therefore, it is particularly important to develop a photoelectric detection chip that has both high-performance wide-spectrum and wide-angle detection capabilities and good CMOS compatibility. Summary of the invention

[0007] The purpose of the present invention is to solve the technical problems of low integration, redundant and bulky structure, narrow detection range and inability to achieve both wide-spectrum detection and wide-angle detection in existing photoelectric detectors and their components, and to provide a hybrid stacked super-compound eye chip and a preparation method capable of wide-spectrum and wide-angle detection.

[0008] The object of the present invention is achieved through the following technical solution: a hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection, the chip comprising: 2.5D out-of-plane architecture super-bionic compound eye metasurface, including a high-silicon metasurface and a low-silicon metasurface arranged in an array with a uniform interval of height difference and radius difference, and a metal metasurface arranged above the high-silicon metasurface and the low-silicon metasurface; graphene is provided above the metal metasurface; The top chip is based on silicon with array-arranged through-holes, the outer surface of the silicon body is provided with an insulating layer, and the insulating layer is provided with array-arranged through-hole grooves; the through-holes are provided with silicon-through-hole metal connecting columns, and the through-hole grooves are provided with 2.5D out-of-plane architecture super-bionic compound eye supersurfaces, forming the pixel array of the top chip; The bottom chip has an indium tin alloy on its upper surface, which is connected to the silicon and silicon through-hole metal connection columns of the top chip to make ohmic contact, thereby realizing vertical interconnection and stacking between chips, forming a chip hybrid stacking readout integrated module, which is connected to the readout integrated circuit module in the bottom chip.

[0009] The electrode is arranged above the insulating layer centered on the perforated groove and connected to the through-silicon via metal connecting column, and the top of the electrode is in contact with the graphene of the 2.5D out-of-plane architecture super-bionic compound eye supersurface.

[0010] Furthermore, the in-plane C2 symmetry is broken by changing the diameter of the metal / silicon supersurface in the 2.5D out-of-plane architecture super-bionic compound eye supersurface, and the out-of-plane C2 symmetry is broken by adjusting its height difference, thereby optimizing the entire chip; the loss of symmetry protection causes the BIC to couple with the radiation mode to form a quasi-q-BIC, achieving the wide-angle detection capability of a plane equivalent to a curved surface.

[0011] Furthermore, the 2.5D out-of-plane architecture super-bionic compound eye supersurface, wherein the graphene corresponds to the cornea in the insect compound eye structure, the metal supersurface corresponds to the crystal cones and pigment cells in the insect compound eye structure, the high / low silicon supersurface corresponds to the photoreceptors and pigment cells in the insect compound eye structure, and the nanocavity formed inside the structure of the metal supersurface, high silicon supersurface and low silicon supersurface corresponds to the sensory rod bundle in the insect compound eye structure.

[0012] Furthermore, the architecture of the readout integrated circuit module includes a pixel selector module, a digital control module, a phase-locked loop PLL, an analog front end AFE, an analog-to-digital converter ADC, a digital-to-analog converter DAC, a bandgap reference source BGR and a decoupling capacitor. The analog front end integrates a tunable capacitor to enable the readout integrated circuit module to accommodate current signals from nA to mA by adjusting the main frequency.

[0013] Furthermore, the chip hybrid stacking readout integrated module is formed by stacking a top chip and a bottom chip, and the stacking form of the top chip and the bottom chip is any one of pyramid stacking, cantilever stacking, side-by-side stacking or through silicon via TSV stacking.

[0014] Furthermore, the 2.5D out-of-plane architecture super-bionic compound eye super-surface pixel array on the top chip is in an n×n or n×m arrangement.

[0015] Furthermore, the preparation process of the insulating layer is any one of thermal oxidation growth, PECVD furnace growth, atomic layer deposition ALD or electron beam evaporation deposition of silicon oxide; the metal deposition process of the metal supersurface and the electrode is any one of thermal evaporation, electron beam evaporation or magnetron sputtering; the bottom chip CMOS tape-out preparation process node is any one of 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 14nm, 7nm, 5nm or 3nm.

[0016] Furthermore, the indium tin alloy used as the ohmic contact can be replaced by any one of metal silicide, gallium indium alloy or metal aluminum; the insulating layer on the upper surface of the silicon is provided with array-arranged perforated grooves, which are either polygonal grooves or circular grooves.

[0017] Furthermore, the graphene can be replaced by any one of single-element silicene, germanene, stanene, borene, black phosphorus, transition metal chalcogenides or main-group metal chalcogenides, wherein the number of layers is any one of a single layer or multiple layers.

[0018] In a second aspect, the present invention provides a method for preparing a hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection, the method comprising the following steps: (1) Preparation of the silicon substrate for the top chip: Cut the silicon wafer into the required size, clean the surface, and ultrasonically clean it in acetone, isopropanol, and deionized water solution in turn, then take it out and blow dry it with nitrogen; (2) Preparation of silicon via arrays on the top chip: Create the required silicon vias by performing an array deep silicon etching process on the silicon wafer, perform a thermal oxidation operation on the silicon wafer to form a surface insulation layer including the silicon vias, then deposit a metal seed layer in the silicon vias, electroplate and chemically polish the metal in the vias to obtain a top chip with silicon via metal connection columns; (3) Patterning of the silicon window of the top chip array: Spin-coat and pre-bake the cleaned silicon wafer with photoresist, then use a photolithography machine to photolithography the silicon wafer after photoresist coating. After the photolithography is completed, develop the wafer to completely solidify the photoresist. Then, etch the oxide layer of the window area not protected by the photoresist in a buffered oxide etching solution, and then perform a stripping process to complete the patterning of the silicon window of the array. (4) Patterning of the top chip array electrode: Continue to repeat the steps of coating-pre-baking-photolithography-development in step (3), then perform metal deposition operation, and then use acetone solution to peel off the remaining metal except the electrode pattern, and then use isopropyl alcohol to clean the acetone to obtain a complete electrode pattern; (5) Preparation of the supersurface in the 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip: First, a nickel film with periodic nanopillars is used to imprint an electropolished aluminum foil to form a nano-pit array with a certain spacing on the surface of the aluminum foil; then, the imprinted aluminum foil is anodized to form a nanopore array, recorded as A hole; then the A hole is enlarged by treating it in a phosphoric acid solution; after that, a thin layer of titanium dioxide is deposited in the A hole using atomic layer deposition (ALD); then, the top surface of the binary pore anodized aluminum oxide (AAO) template is milled using an ion beam etching system, a layer of polymethyl methacrylate (PMMA) solution is coated on the surface of the AAO template, and the unoxidized aluminum is removed; the PMMA layer is dissolved in acetone; finally, the AAO template is immersed in a NaOH solution at room temperature, the pore size is adjusted by controlling the immersion time, and a group of B holes are formed at the quadruple connection of the A hole; then the AAO The template is placed on a silicon substrate, and the first etching step is performed using inductively coupled plasma ICP etching to create a pore structure in the silicon; the barrier layer of the A hole is then milled away using IBE, and then Cr / Au is subjected to physical vapor deposition PVD. The Cr / Au layer serves as a protective cover for the AB holes; after removing the AAO template, a second etching step is performed, wherein the high silicon supersurface and the low silicon supersurface are obtained by using a metal supersurface as a mask, and then using ICP to etch silicon to obtain a composite supersurface containing metal supersurfaces, high silicon supersurfaces, and low silicon supersurfaces of different heights, i.e., the 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip; (6) Design and preparation of the readout integrated circuit module of the bottom chip: The architecture of the readout integrated circuit module includes a pixel selector module, an analog front end AFE, an analog-to-digital converter ADC, a digital control module, a digital-to-analog converter DAC, a bandgap reference source BGR, and a phase-locked loop PLL. The design integrates a decoupling capacitor in the analog front end and uses a CMOS 0.18-micron process node for wafer fabrication. (7) Preparation of a chip hybrid stacked readout integrated module: The wiring terminals on the upper surface of the readout integrated circuit module of the bottom chip are coated with indium tin alloy, and the bottom of the silicon of the top chip and the bottom of the through-silicon via metal connection column are respectively connected to the indium tin alloy stack on the bottom chip by flip-chip bonding to form a chip hybrid stacked readout integrated module; (8) Array patterning of top-layer chip graphene: Graphene grown by thermal chemical vapor deposition is transferred by PMMA-assisted method, and PMMA is spin-coated on the graphene as a supporting layer and placed in copper etching solution. The PMMA-supported graphene floating in the etching solution is scooped out and washed in deionized water so that the graphene area covers the above-mentioned composite supersurface and electrode area. The PMMA on the graphene is then removed with dichloromethane, and then a third photolithography is performed. The steps of photoresist-pre-bake-photolithography-development in step (3) are repeated to define the graphene-covered array area. The photoresist protects the electrode and window area covered by the graphene. The graphene area outside the electrode is then etched, and finally the photoresist is removed to achieve graphene array patterning.

[0019] Beneficial effects of the present invention: The present invention adopts a manufacturing process involving a binary hole anodized aluminum oxide (AAO) template on the surface, and integrates graphene to simulate the compound eye, thereby enhancing the detection capability in the ultraviolet and visible light range. It adopts a 2.5D out-of-plane architecture to achieve a wide-angle detection effect equivalent to a curved surface (170°), while increasing the absorption of the 1550 nm communication band to nearly 100% through the continuous domain bound state effect. In addition, through-silicon via (TSV) technology is integrated for wafer-level manufacturing, and a CMOS 0.18 μm integrated readout circuit is developed to realize a super-bionic compound eye chip based on hybrid stacking integration. The present invention not only realizes wide-angle detection in a planar chip, but also integrates the characteristics of a traditional curved surface structure, while expanding the detection spectrum of a silicon-based chip, and is suitable for wafer-level production. It not only reduces costs, but also significantly improves compatibility with existing CMOS processes, paving the way for cutting-edge chips that integrate broadband and wide-angle detection technologies, especially for various applications that often require complex and large optoelectronic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a schematic diagram of the structure of the present invention.

[0022] Figure 2 This is a real scanning electron microscope image of the 2.5D out-of-plane architecture super-bionic compound eye metasurface.

[0023] Figure 3Transmission electron microscope image of the super-surface structural unit of the 2.5D out-of-plane architecture super-bionic compound eye.

[0024] Figure 4 It is a physical picture and a partial enlarged picture of the present invention.

[0025] Figure 5 The present invention is a process flow chart of the preparation process.

[0026] Figure 6 It is a detailed bionic diagram of the present invention.

[0027] Figure 7 This is a diagram of the mechanism for realizing wide-angle detection in the present invention.

[0028] Figure 8 This is a schematic diagram of the readout circuit architecture of the present invention.

[0029] Fig. 9 This is a diagram of the test system and photoelectric imaging results of the present invention.

[0030] in: 1.2.5D out-of-plane architecture super-bionic compound eye metasurface; 2. Chip hybrid stacking readout integrated module; 3. Top chip; 4. Bottom chip; 5. Graphene; 6. Metal metasurface; 7. High silicon metasurface; 8. Low silicon metasurface; 9. Readout integrated circuit module; 10. Indium tin alloy; 11. Through silicon via metal connecting column; 12. Silicon; 13. Electrode; 14. Insulating layer. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific implementation examples described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] Continuum bound states (BIC) originate from the coherent decomposition of fluctuations, which can greatly suppress the radiation loss of micro-nano photonic devices, limit electromagnetic waves and enhance the interaction between light and matter, providing a new idea for solving light confinement in artificial micro-nano structures. Therefore, if the 2.5D out-of-plane architecture super-bionic compound eye metasurface, the continuous domain bound state effect and the chip hybrid stacking readout integrated module are combined, it is expected to completely change the design of future hybrid integrated advanced photoelectric detection chips. The present invention proposes a hybrid stacked super-compound eye chip and a preparation method capable of wide-spectrum and wide-angle detection, which has a large-area 2.5D out-of-plane metasurface architecture. This structure integrates a single layer of Gr to simulate the compound eye of insects. The entire plane-level detection area on the chip achieves wide-angle detection equivalent to a curved surface (170°), while the absorption of the 1550 nm communication band is increased to nearly 100% (300-1600 nm) through the continuous domain bound state effect. In addition, TSV technology is integrated for wafer-level manufacturing, and a CMOS 0.18 micron readout integrated circuit (ROIC) is developed to realize a super-bionic compound eye chip based on stacked integration. It achieves structural bionics and functional transcendence, not only realizing wide-angle detection in planar chips, but also broadening the detection range of silicon-based chips. This invention combines bionic design with the principles of quantum mechanics and represents a cutting-edge solution for various high-performance optical sensing applications.

[0033] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the present invention provides a hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection, comprising a 2.5D out-of-plane architecture super bionic compound eye metasurface 1, a chip hybrid stacked readout integrated module 2, a top chip 3, a bottom chip 4, graphene 5, a metal metasurface 6, a high silicon metasurface 7, a low silicon metasurface 8, a readout integrated circuit module 9, an indium tin alloy 10, a through silicon via metal connecting column 11, silicon 12, an electrode 13, and an insulating layer 14; The top chip 3 and the bottom chip 4 are vertically interconnected and stacked by the through silicon via (TSV) technology using the through silicon via metal connecting column 11 and the indium tin alloy 10, and together constitute the main body of the hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection of the present invention. The vertical interconnection reduces the interconnection length and signal delay of the top chip 3 and the bottom chip 4, reduces the capacitance and inductance, realizes low power consumption and high-speed communication between chips, increases bandwidth and realizes small integration; The 2.5D out-of-plane architecture super-bionic compound eye supersurface 1, the through silicon via metal connecting column 11, the silicon 12, the electrode 13, and the insulating layer 14 together constitute the main body of the top chip 3; the silicon 9 is used as the substrate of the top chip 3, and the silicon 9 is provided with array-arranged through-holes through a deep silicon etching process; the insulating layer 14 is arranged on the outer surface of the silicon 9, including the upper and lower surfaces of the silicon 9 and the inner surface of its through-holes; the through silicon via metal connecting columns 11 are evenly distributed in an array in the through-holes of the silicon 9, and the two are connected by the insulating layer 14; the insulating layer 10 located on the upper surface of the silicon 9 is provided with array-arranged perforated grooves, and the position arrangement of the grooves is consistent with the position of the through silicon via metal connecting columns 11; The 2.5D out-of-plane architecture super-bionic compound eye supersurface 1 is arranged in the perforated groove of the insulating layer 14 and contacts the silicon 9. The graphene 5, the metal supersurface 6, the high-silicon supersurface 7 and the low-silicon supersurface 8 together constitute the 2.5D out-of-plane architecture super-bionic compound eye supersurface 1; the high-silicon supersurface 7 and the low-silicon supersurface 8 are arranged in an array in a uniformly spaced manner with a certain height difference and radius difference, and the high-silicon supersurface 7 is surrounded by the low-silicon supersurface 8 on the top, bottom, left and right sides, and the low-silicon supersurface 8 is surrounded by the high-silicon supersurface 7 on the top, bottom, left and right sides. A metal supersurface 6 is disposed above the high silicon supersurface 7 and the low silicon supersurface 8, and its arrangement is consistent with that of the high silicon supersurface 7 and the low silicon supersurface 8; the graphene 5 is disposed above the electrode 13 and the metal supersurface 6, and is in contact with the electrode 13 and the metal supersurface 6 at the same time; the material of the metal supersurface can be any one of gold (Au), platinum (Pt), palladium (Pd), silver (Ag), copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni) or aluminum (Al). The graphene can be graphene, single element silicene, germanene, stanene, boronene, black phosphorus, transition metal chalcogenide (such as MoS 2 ,WSe 2 、ReS 2 , PtSe 2 、NbSe 2 ) or main group metal chalcogenides (such as GaS, InSe, SnS, SnS 2 ), wherein the number of layers can be any one of a single layer or a multilayer, and the graphene described in the present invention is one of the examples cited.

[0034] The pixel array form of the 2.5D out-of-plane architecture super-bionic compound eye supersurface on the top chip can be any arrangement form of 2×2, 4×4, 8×8, 16×16···n×n or n×m, where n and m are positive integers. The preparation process of the insulating layer can be any one of thermal oxidation growth, PECVD furnace growth, atomic layer deposition (ALD) or electron beam evaporation deposition of silicon oxide. The metal deposition process of the metal supersurface and electrode can be any one of thermal evaporation, electron beam evaporation or magnetron sputtering. The bottom chip CMOS tape-out preparation process node can be any one of 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 14nm, 7nm, 5nm or 3nm.

[0035] The electrodes 13 are uniformly distributed above the insulating layer 14 provided on the upper surface of the silicon 9 with the array-arranged perforated grooves of the insulating layer 14 as the center, and are in contact with and connected to the through-silicon via metal connecting pillars 11 uniformly distributed in the through-holes of the silicon 9; the array arrangement of the 2.5D out-of-plane architecture super-bionic compound eye supersurface 1 constitutes the pixel array of the top chip 3; The indium tin alloy 10 is disposed on the upper surface of the bottom chip 4, and the readout integrated circuit module 9 is disposed in the bottom chip 4 and connected to the indium tin alloy 10; the readout integrated circuit module 9 is composed of a digital control module and an analog module, and the analog module is composed of a phase-locked loop (PLL), an analog front end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR) and a decoupling capacitor; The bottom of the silicon 9 of the top chip 3 and the lower surface of the through silicon via metal connecting column 11 are connected to the indium tin alloy 10 on the bottom chip 4 for ohmic contact, forming the chip hybrid stacking readout integrated module 2; the indium tin alloy used as ohmic contact can be indium tin alloy, metal silicide (NiSi, TiSi 2 or CoSi 2), gallium-indium alloy or metal aluminum, and the indium-tin alloy described in the present invention is one of the examples. The insulating layer on the upper surface of the silicon is provided with an array of perforated grooves, which may be any of polygonal grooves such as L-shaped grooves, rectangular grooves, triangular grooves, or circular grooves. The overall chip architecture is composed of the 2.5D out-of-plane architecture super-bionic compound eye super-surface pixel array provided on the top chip 3, the chip hybrid stacking readout integrated module 2 and the readout integrated circuit module 9 of the bottom chip 4. The chip hybrid stacking readout integrated module 2 is formed by stacking the top chip and the bottom chip, and the stacking form of the top chip and the bottom chip can be any of pyramid stacking, cantilever stacking, side-by-side stacking or silicon through-hole TSV (Through-Silicon-Via) stacking. The ultra-compact architecture design abandons the bulky optical design and structural redundancy of the photosensitive module and the readout module in the traditional photoelectric detection chip / device assembly. The low energy consumption is due to the fact that the present invention can generate open-circuit voltage and short-circuit current by light itself without external power supply. Light itself can make the chip work, and the present invention can detect the near-infrared band at room temperature, without the need for additional liquid nitrogen refrigeration like traditional near-infrared detectors. This is a major breakthrough for near-infrared detectors.

[0036] According to the second aspect of this specification, a method for preparing a hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection is provided. The method is mainly divided into three process systems: the preparation of the top chip, the preparation of the bottom chip, and the stacking and bonding of the top chip and the bottom chip. Figure 5 As shown, the preparation process of the hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection includes the following steps: (1) Preparation of the top chip silicon substrate: Take N-type lightly doped silicon wafer (silicon wafer thickness 100-500 um, resistivity 1-10 Ω·cm) as an example, cut it to the required size, clean its surface, put it into acetone, isopropanol, and deionized water solution for ultrasonic cleaning, and take it out and blow dry it with nitrogen; (2) Preparation of silicon via arrays on the top chip: The required silicon vias are created by performing an array deep silicon etching process on the silicon wafer, and a thermal oxidation operation is performed on the silicon wafer to form a surface insulation layer including the silicon vias. A metal seed layer is then deposited in the silicon vias, and the metal in the vias is electroplated and chemically polished to obtain a top chip with silicon via metal connection columns.

[0037] (3) Patterning of silicon windows of the top chip array: Spin-coat the cleaned silicon wafer with photoresist so that the photoresist evenly covers the surface of the silicon wafer, pre-bake at 105°C for 5 minutes, and then use a photolithography machine to photolithography the silicon wafer after photolithography. After the photolithography is completed, mix the developer and water in a ratio of 1:7 to form a developing solution, perform the developing operation, and post-bake at 120°C for 20 minutes to completely solidify the photoresist, so as to protect the oxide layer under the photoresist in the next wet etching. Then, the oxide layer of the window area not protected by the photoresist is etched in a buffered oxide etch (BOE) solution. The ratio of the BOE solution is: NH 4 F: HF: H 2 O = 60 g: 30 ml: 100 ml. The etching rate of BOE solution with this ratio is 100 nm / min. 2 When the layer thickness is 100 nm, etching for 1 min is sufficient. After the device is removed from the BOE solution, it is washed in water and then debonded with acetone and isopropanol to complete the patterning of the array silicon window.

[0038] (4) Patterning of the top chip array electrode: Continue to repeat the above steps of coating-pre-baking-photolithography-development. Metal deposition can be performed using thermal evaporation, electron beam evaporation or magnetron sputtering. Use acetone solution to lift-off the remaining metal except the electrode pattern. Then clean the acetone with isopropyl alcohol to obtain a complete electrode pattern.

[0039] (5) Preparation of the 2.5D out-of-plane architecture super-bionic compound eye metasurface (without graphene at this time) of the top chip: First, a nickel (Ni) film with periodic nanopillars was used to imprint an electropolished aluminum foil at a pressure of 15 kN / cm² for 3 minutes, thereby forming a nanopit array with a spacing of 400 nm on the aluminum foil surface. Next, the imprinted aluminum foil was anodized in a 5 wt% phosphoric acid solution at 160 V at 30°C for 15 minutes to form a nanopore array (A hole). The A hole was then enlarged by treating it in a 5wt% phosphoric acid solution for 15 minutes. After this, a thin layer of titanium dioxide (TiO2) was deposited in the A hole using atomic layer deposition (ALD). 2) to protect the A pores from chemical etching. Subsequently, the top surface of the binary pore anodic aluminum oxide (AAO) template was milled using an ion beam etching (IBE) system to ensure that the B pores were fully open. A layer of polymethyl methacrylate (PMMA) solution was then coated on the surface of the AAO template, and a mixed solution of 1.5wt% copper chloride and 53.2 wt% hydrochloric acid was used to remove the unoxidized aluminum. The PMMA layer was dissolved in acetone. Finally, the AAO template was immersed in a 0.1 mol / L NaOH solution at room temperature, and the pore size was adjusted by controlling the immersion time to form a group of B pores at the quadruple junction of the A pores. The AAO template was then placed on a silicon substrate and the first etching step was performed using inductively coupled plasmon (ICP) etching (Ar: 10 sccm, CHF3: 2 sccm, SF6: 20 sccm) to create a pore structure in silicon. IBE is then used to mill off the barrier layer of hole A, and then Cr (2 nm) / Au (20 nm) is physically vapor deposited (PVD). The Cr / Au layer serves as a protective cover for the AB holes. After removing the AAO template, a second etching step is performed. The high-silicon supersurface and low-silicon supersurface use the metal supersurface as a mask, and then ICP (inductively coupled plasma dry etching system, using C4F8 and SF6 as reaction gases) is used to etch silicon to obtain a composite supersurface containing metal supersurfaces, high-silicon supersurfaces, and low-silicon supersurfaces with different heights, that is, the 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip (graphene is not included at this time).

[0040] (6) Design and preparation of the readout integrated circuit module of the bottom chip: The architecture of the readout integrated circuit includes a pixel selector module, an analog front end (AFE), an analog-to-digital converter (ADC), a digital control module, a digital-to-analog converter (DAC), a bandgap reference source (BGR), and a phase-locked loop (PLL). The design integrates a decoupling capacitor in the analog front end, allowing the readout module to accommodate current signals from nA to mA by adjusting the main frequency, thereby ensuring compatibility with various devices. The CMOS 0.18 micron process node is used for tape-out preparation, such as Figure 4 and Figure 8 shown.

[0041] (7) Preparation of chip hybrid stacking readout integrated module (top chip and bottom chip stacking): The upper surface terminal of the readout integrated circuit module of the bottom chip is coated with indium tin alloy using solder bump technology, and the bottom of the silicon of the top chip and the bottom of the through-silicon via metal connection column are respectively connected to the indium tin alloy stack on the bottom chip by flip-chip bonding to form a chip hybrid stack readout integrated module, such as Figure 1 shown.

[0042] (8) Array patterning of graphene on the top chip: high-quality graphene grown by thermal chemical vapor deposition is transferred by PMMA-assisted method, and PMMA is spin-coated on the graphene as a supporting layer and placed in copper etching solution. The PMMA-supported graphene floating in the etching solution is scooped out into deionized water for cleaning so that the graphene area covers the above-mentioned composite supersurface and electrode area. The PMMA on the graphene is then removed with dichloromethane, and then a third photolithography is performed. The steps of photoresist coating-pre-baking-photolithography-development are repeated to define the graphene-covered array area. The photoresist is protected in the graphene-covered electrode and window area. Then, the graphene area outside the electrode is etched with oxygen plasma etching equipment, and finally the resist is removed to realize the graphene array patterning. Finally, the 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip is obtained, such as Figure 1 , Figure 2 and Figure 3 shown.

[0043] The 2.5D out-of-plane architecture super bionic compound eye metasurface adopts a manufacturing process involving a binary hole anodized aluminum oxide (AAO) template, and may also adopt any one of a multi-step photolithography manufacturing process, a multi-step ion beam direct writing (DWL) manufacturing process, or an electron beam direct writing (EBL) manufacturing process. The metal metasurface, high silicon metasurface, and low silicon metasurface can achieve flexible control of the response wavelength by adjusting different sizes. The size of the 2.5D out-of-plane architecture super bionic compound eye metasurface in the present invention is one of the examples cited, and also includes a 2D planar metasurface (i.e., the height difference between the high silicon metasurface and the low silicon metasurface is consistent or the composite metasurface composed of the high silicon metasurface, the low silicon metasurface, and the metal metasurface is at the same plane height).

[0044] The structural units of the 2.5D out-of-plane architecture super-bionic compound eye metasurface of the present invention are compared with the structural units (ommatidia) of insect compound eyes, such as Figure 6As shown in (a), the constituent elements in the structural unit of the 2.5D out-of-plane architecture super-bionic compound eye metasurface correspond to the components of the cornea, cone cells and photoreceptor cells in the insect eye, respectively, wherein the graphene corresponds to the cornea in the insect compound eye structure, the metal metasurface corresponds to the cones and pigment cells in the insect compound eye structure, the high / low silicon metasurface corresponds to the photoreceptors and pigment cells in the insect compound eye structure, and the nanocavity formed inside the structure of the metal metasurface, high silicon metasurface and low silicon metasurface corresponds to the sensory rod bundle in the insect compound eye structure. According to actual tests, the structure of the 2.5D out-of-plane architecture super-bionic compound eye metasurface of the present invention achieves nearly 100% broadband absorption from 300 nm to 1600 nm in the ultraviolet-visible-near infrared band ( Figure 6 (b) in the figure), especially at the communication band of 1550 nm, the photoelectric detection capability of the present invention has been successfully realized by the mechanism of limiting electromagnetic waves by the bound state of the continuous domain (BIC) and enhancing the interaction between light and matter and greatly reducing the loss, thus surpassing the traditional silicon-based photodiode limit (<1100nm). Photoelectric detection chips involving the bound state of the continuous domain (BIC) mechanism have not been reported, and even related photoelectric detectors are rarely published. The uniform morphology of the structure of the 2.5D out-of-plane architecture super-bionic compound eye metasurface is shown in Figure 1. Figure 2 As shown. Thanks to the flexibility, unbreakable nature and wafer-level fabrication of graphene, good contact between graphene and metal supersurfaces, high-silicon supersurfaces and low-silicon supersurfaces is ensured, and effective cascade conduction between each photodetection unit is achieved ( Figure 2 and Figure 3 ).from Figure 3 The large intensity ratio of the 2D peak to the G peak (I2D / G>1) obtained in the Raman spectrum of graphene ( Figure 8 ) confirmed the high-quality properties of single-layer graphene.

[0045] The present invention can generate open-circuit voltage and short-circuit current through light without external power supply. Light itself can make the device work. In addition, the present invention can detect the near-infrared band at room temperature and does not require additional liquid nitrogen refrigeration like traditional near-infrared detectors. This is a major breakthrough for near-infrared detectors.

[0046] The in-plane C2 symmetry is broken by changing the diameter of the metal / silicon metasurface in the 2.5D out-of-plane architecture super bionic compound eye metasurface, and the out-of-plane C2 symmetry is broken by adjusting its height difference, thereby optimizing the entire system. The loss of symmetry protection leads to the coupling of BIC with the radiation mode to form a quasi-BIC (q-BIC) and produce nearly 100% absorption at 1550 nm. Figure 7(a) in the figure demonstrates the ultra-wide-angle detection capability of the 2.5D out-of-plane architecture super-bionic compound eye metasurface, achieving the wide-angle detection capability of a plane equivalent to that of a curved surface. The structure of the present invention bionics the structure of insect compound eyes, and its function surpasses that of compound eyes that require curved surfaces to achieve wide-angle detection, thus realizing the concept of super-bionics. Figure 7 (b) shows the ultra-wide angle detection of the structure, which is verified by experimental data of angular resolution. Figure 7 (c) shows that the standard 2D structure does not have this property. The inset depicts the relationship between responsivity and angle. The 2.5D structure achieves a uniform and strong response over a wide angle of 170°, while the 2D structure exhibits an inhomogeneous and limited response.

[0047] The metal metasurface film on the high-Si metasurface and low-Si metasurface induces surface plasmon resonance (SPR), which enhances the electromagnetic field. Hot carriers are located at the gold-Si Schottky junction, significantly shortening their initial distance and promoting electron transport across the barrier. SPR localizes and enhances the light field, stimulating hot electric carriers through non-radiative mechanisms such as Landau damping, transferring energy to the electronic system. The electric field enhancement widens the Schottky barrier and depletion region, improving the electron-hole pair collection efficiency within the junction depletion region for transmission to the external circuit. In the 2.5D out-of-plane architecture super-bionic compound eye metasurface, the strong electric field generated by the reverse bias voltage significantly improves the electron transfer efficiency by effectively collecting the excited charge carriers before recombination, scattering or phonon dissipation. Electron-hole pairs (EHP) are generated by photon absorption of metal metasurfaces, high-Si metasurfaces and low-Si metasurfaces coupled with graphene. The barrier height of 0.8 eV matches the 1550 nm excitation wavelength, preventing low-energy carrier transitions, effectively reducing dark current and accelerating the generation and separation of EHP. This improves the photoelectric conversion efficiency and responsivity at 1550 nm, while reducing thermal and electrical noise. For photons with a wavelength of ≤1.1 μm (ultraviolet and visible light), EHPs are directly excited and separated in the depletion region. Enhanced SPR and EHP spatial manipulation lead to external quantum efficiencies approaching 100% in these frequency bands. At 1550 nm, the strong absorption of the quasi-BIC (q-BIC) mechanism allows photoexcited electrons to directly pass through the barrier, further enhancing the photoresponse through the internal photoemission effect.

[0048] The structure of the readout integrated circuit module 9 of the present invention is as follows Figure 8As shown, it includes a pixel selector module, a digital control module, a phase-locked loop (PLL), an analog front end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR) and a decoupling capacitor. The design of the present invention integrates a tunable capacitor in the analog front end, so that the readout module can accommodate current signals from nA to mA by adjusting the main frequency, ensuring compatibility with various devices.

[0049] To verify the wide-spectrum and wide-angle imaging capability of the present invention, the Z, J and U templates were tested using incident light wavelengths of 375 nm, 532 nm and 1550 nm (deep ultraviolet-near infrared), respectively. Fig. 9 The present invention is connected to a field programmable gate array (FPGA) by wire bonding, and the FPGA is then connected to a computer. By writing a program and compiling it into the FPGA, the chip of the present invention implements multiple logic functions and computing acceleration assistance, which facilitates the chip readout integration in the present invention to automatically process electrical signals. The imaging test results in this embodiment show that the present invention can capture clear image results without any offset within a wide wavelength and wide field of view, as shown in FIG. Fig. 9 (e)- Fig. 9 As shown in (g) in the figure. Compared with the planar 2D metasurface of the prior art, the 2.5D out-of-plane architecture super-bionic compound eye metasurface of the present invention can capture clear imaging results without deviation as the incident light angle increases ( Fig. 9 (h) in the figure).

[0050] In summary, the embodiment of the present invention provides a hybrid stacked super compound eye chip and preparation method capable of wide-spectrum and wide-angle detection. The chip surface adopts a manufacturing process involving a binary hole anodized aluminum oxide (AAO) template, and integrates graphene to simulate the compound eye, thereby enhancing the detection capability in the ultraviolet and visible light range. It adopts a 2.5D out-of-plane architecture to achieve a wide-angle detection effect equivalent to a curved surface (170°), while increasing the absorption of the 1550 nm communication frequency band to nearly 100%. In addition, through-silicon via (TSV) technology is integrated for wafer-level manufacturing, and a CMOS 0.18 μm integrated readout circuit is developed to realize a super-bionic compound eye chip based on hybrid stacking integration. The present invention not only realizes wide-angle detection in a planar chip, but also integrates the characteristics of a traditional curved surface structure, while expanding the detection spectrum of a silicon-based chip, and is suitable for wafer-level production. Not only does it reduce costs, it also significantly improves compatibility with existing CMOS processes, paving the way for cutting-edge chips that integrate broadband and wide-angle detection technologies, which is crucial for a variety of applications that often require complex and large optoelectronic systems.

[0051] The above embodiments provide an exemplary description of the present invention. Obviously, the specific implementation of the present invention is not limited to the above methods. As long as various improvements are made using the method concept and technical solution of the present invention, or they are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection, characterized in that: The chip includes: 2.5D out-of-plane architecture super-bionic compound eye metasurface, including a high-silicon metasurface and a low-silicon metasurface arranged in an array with a uniform interval of height difference and radius difference, and a metal metasurface arranged above the high-silicon metasurface and the low-silicon metasurface; graphene is provided above the metal metasurface; The top chip is based on silicon with array-arranged through-holes, the outer surface of the silicon body is provided with an insulating layer, and the insulating layer is provided with array-arranged through-hole grooves; the through-holes are provided with silicon-through-hole metal connecting columns, and the through-hole grooves are provided with a 2.5D out-of-plane architecture super-bionic compound eye supersurface, forming a pixel array of the top chip; The bottom chip has an indium tin alloy on its upper surface, which is connected to the silicon and through-silicon via metal connection columns of the top chip to make ohmic contact, realize vertical interconnection stacking between chips, and form a chip hybrid stacking readout integrated module, which is connected to the readout integrated circuit module in the bottom chip; The electrode is arranged above the insulating layer centered on the perforated groove and connected to the through-silicon via metal connecting column, and the top of the electrode is in contact with the graphene of the 2.5D out-of-plane architecture super-bionic compound eye supersurface.

2. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The in-plane C2 symmetry is broken by changing the diameter of the metal / silicon supersurface in the 2.5D out-of-plane architecture super-bionic compound eye supersurface, and the out-of-plane C2 symmetry is broken by adjusting its height difference, thereby optimizing the entire chip; the loss of symmetry protection causes the BIC to couple with the radiation mode to form a quasi-q-BIC, achieving wide-angle detection capability that is equivalent to that of a curved surface.

3. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The 2.5D out-of-plane architecture super-bionic compound eye supersurface, wherein the graphene corresponds to the cornea in the insect compound eye structure, the metal supersurface corresponds to the crystal cones and pigment cells in the insect compound eye structure, the high / low silicon supersurface corresponds to the photoreceptors and pigment cells in the insect compound eye structure, and the nanocavity formed inside the structures of the metal supersurface, high silicon supersurface and low silicon supersurface corresponds to the sensory rod bundle in the insect compound eye structure.

4. The hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection according to claim 1, characterized in that: The architecture of the readout integrated circuit module includes a pixel selector module, a digital control module, a phase-locked loop PLL, an analog front end AFE, an analog-to-digital converter ADC, a digital-to-analog converter DAC, a bandgap reference source BGR and a decoupling capacitor. The analog front end integrates a tunable capacitor to enable the readout integrated circuit module to accommodate current signals from nA to mA by adjusting the main frequency.

5. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The chip hybrid stacking readout integrated module is formed by stacking a top chip and a bottom chip, and the stacking form of the top chip and the bottom chip is any one of pyramid stacking, cantilever stacking, side-by-side stacking or through silicon via TSV stacking.

6. The hybrid stacked super compound eye chip capable of wide spectrum and wide angle detection according to claim 1, characterized in that: The 2.5D out-of-plane architecture super-bionic compound eye super-surface pixel array on the top chip is arranged in an n×n or n×m form.

7. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The preparation process of the insulating layer is any one of thermal oxidation growth, PECVD furnace growth, atomic layer deposition ALD or electron beam evaporation deposition of silicon oxide; the metal deposition process of the metal super surface and the electrode is any one of thermal evaporation, electron beam evaporation or magnetron sputtering; the bottom chip CMOS tape-out preparation process node is any one of 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 14nm, 7nm, 5nm or 3nm.

8. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The indium tin alloy used as the ohmic contact can be replaced by any one of metal silicide, gallium indium alloy or metal aluminum; the insulating layer on the upper surface of the silicon is provided with array-arranged perforated grooves, which are either polygonal grooves or circular grooves.

9. The hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection according to claim 1, characterized in that: The graphene can be replaced by any one of single-element silicene, germanene, stanene, borene, black phosphorus, transition metal chalcogenides or main-group metal chalcogenides, wherein the number of layers is any one of a single layer or multiple layers.

10. A method for preparing a hybrid stacked super-compound eye chip capable of wide-spectrum and wide-angle detection based on any one of claims 1 to 9, characterized in that: The method comprises the following steps: (1) Preparation of the silicon substrate for the top chip: Cut the silicon wafer into the required size, clean the surface, and ultrasonically clean it in acetone, isopropanol, and deionized water solution in turn, then take it out and blow dry it with nitrogen; (2) Preparation of silicon via arrays on the top chip: Create the required silicon vias by performing an array deep silicon etching process on the silicon wafer, perform a thermal oxidation operation on the silicon wafer to form a surface insulation layer including the silicon vias, then deposit a metal seed layer in the silicon vias, electroplate and chemically polish the metal in the vias to obtain a top chip with silicon via metal connection columns; (3) Patterning of the silicon window of the top chip array: Spin-coat and pre-bake the cleaned silicon wafer with photoresist, then use a photolithography machine to photolithography the silicon wafer after photoresist coating. After the photolithography is completed, develop the wafer to completely solidify the photoresist. Then, etch the oxide layer of the window area not protected by the photoresist in a buffered oxide etching solution, and then perform a stripping process to complete the patterning of the silicon window of the array. (4) Patterning of the top chip array electrode: Continue to repeat the steps of coating-pre-baking-photolithography-development in step (3), then perform metal deposition operation, and then use acetone solution to peel off the remaining metal except the electrode pattern, and then use isopropyl alcohol to clean the acetone to obtain a complete electrode pattern; (5) Preparation of the supersurface in the 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip: First, a nickel film with periodic nanopillars is used to imprint an electropolished aluminum foil to form a nano-pit array with a spacing on the surface of the aluminum foil; then, the imprinted aluminum foil is anodized to form a nanopore array, recorded as A hole; then the A hole is enlarged by treating it in a phosphoric acid solution; after this, a thin layer of titanium dioxide is deposited in the A hole using atomic layer deposition (ALD); then, the top surface of the binary pore anodized aluminum oxide (AAO) template is milled using an ion beam etching system, a layer of polymethyl methacrylate (PMMA) solution is coated on the surface of the AAO template, and the unoxidized aluminum is removed; the PMMA layer is dissolved in acetone; finally, the AAO template is immersed in a NaOH solution at room temperature, and the pore size is adjusted by controlling the immersion time to form a group of B holes at the quadruple connection of the A hole; then the AAO The template is placed on a silicon substrate, and the first etching step is performed using inductively coupled plasmon (ICP) etching to create a pore structure in the silicon; the barrier layer of the A hole is then milled away using IBE, and then Cr / Au is subjected to physical vapor deposition (PVD); the Cr / Au layer serves as a protective cover for the AB holes; after removing the AAO template, a second etching step is performed, wherein the high silicon supersurface and the low silicon supersurface are obtained by using a metal supersurface as a mask, and then using ICP to etch silicon to obtain a composite supersurface comprising metal supersurfaces, high silicon supersurfaces, and low silicon supersurfaces of different heights, i.e., a 2.5D out-of-plane architecture super-bionic compound eye supersurface of the top chip; (6) Design and preparation of the readout integrated circuit module of the bottom chip: The architecture of the readout integrated circuit module includes a pixel selector module, an analog front end AFE, an analog-to-digital converter ADC, a digital control module, a digital-to-analog converter DAC, a bandgap reference source BGR, and a phase-locked loop PLL. The design integrates a decoupling capacitor in the analog front end and uses a CMOS 0.18-micron process node for wafer fabrication. (7) Preparation of a chip hybrid stacked readout integrated module: The wiring terminals on the upper surface of the readout integrated circuit module of the bottom chip are coated with indium tin alloy, and the bottom of the silicon of the top chip and the bottom of the through-silicon via metal connection column are respectively connected to the indium tin alloy stack on the bottom chip by flip-chip bonding to form a chip hybrid stacked readout integrated module; (8) Array patterning of top-layer chip graphene: Graphene grown by thermal chemical vapor deposition is transferred by PMMA-assisted method, and PMMA is spin-coated on the graphene as a supporting layer and placed in copper etching solution. The PMMA-supported graphene floating in the etching solution is scooped out and washed in deionized water so that the graphene area covers the above-mentioned composite supersurface and electrode area. The PMMA on the graphene is then removed with dichloromethane, and then a third photolithography is performed. The steps of photoresist-pre-bake-photolithography-development in step (3) are repeated to define the graphene-covered array area. The photoresist protects the electrode and window area covered by the graphene. The graphene area outside the electrode is then etched, and finally the photoresist is removed to achieve graphene array patterning.

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