Solar cell preparation method and solar cell
By preparing a passivation layer on the second side of the silicon substrate of the solar cell, the problem of poor carrier recombination effect in the front area is solved, and the conversion efficiency of the solar cell is improved.
Patent Information
- Application Number
- CN202411395031.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2025-01-14
AI Technical Summary
The effect of reducing carrier recombination in the front area of existing solar cells is poor, affecting the conversion efficiency of crystalline silicon solar cells.
A silicon oxide layer is prepared on the second side of the silicon substrate, a first passivation layer is prepared on the side where the polysilicon layer is away from the silicon substrate, and a second passivation layer is prepared on the side where the silicon oxide layer is away from the silicon substrate, A dense silicon oxide film is formed by thermal oxidation to prevent carrier recombination.
The carrier recombination on the second side of the silicon substrate is effectively reduced and the conversion efficiency of the solar cell is improved.
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Figure CN119317225A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of solar cells, and specifically provides a solar cell preparation method and a solar cell. Background Art
[0002] With the development of technology, the conversion efficiency of crystalline silicon solar cells has been continuously improved and has been widely used. The recombination of minority carriers in crystalline silicon solar cells affects its conversion efficiency. In related technologies, ultra-thin tunneling oxide layers and doped polysilicon layers are usually prepared on the back of the cell to reduce the carrier recombination in the back area, such as tunneling oxide layer passivation contact cells, and aluminum oxide layers are prepared on the front of the cell to reduce the carrier recombination in the front area. However, the effect of reducing carrier recombination in the front area is still poor. How to further effectively reduce the carrier recombination in the front area and improve the conversion efficiency of crystalline silicon solar cells has become an urgent problem to be solved. Summary of the invention
[0003] The present invention aims to solve the above technical problem, that is, to solve the problem that the effect of reducing carrier recombination in the front area of existing solar cells is still poor, and how to further effectively reduce the carrier recombination in the front area.
[0004] In a first aspect, the present invention provides a method for preparing a solar cell, comprising:
[0005] Sequentially prepare a tunneling layer and a polysilicon layer on a first surface of a silicon substrate;
[0006] preparing a silicon oxide layer on the second surface of the silicon substrate, the first surface and the second surface being arranged opposite to each other;
[0007] preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate; and,
[0008] A second passivation layer is prepared on a side of the silicon oxide layer away from the silicon substrate to obtain a solar cell.
[0009] In some embodiments, preparing a silicon oxide layer on the second surface of the silicon substrate comprises:
[0010] For the silicon substrate structure obtained after preparing the tunneling layer and the polysilicon layer, the first surface of the silicon substrate in the silicon substrate structure is placed opposite to the first surface of the silicon substrate in another silicon substrate structure, and the silicon substrate structure and the other silicon substrate structure are inserted into the card slot;
[0011] The card slot is placed in a furnace tube, and a silicon oxide layer is prepared on the second surface of the silicon substrate in the silicon substrate structure by a thermal oxidation method.
[0012] In some embodiments, before sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate, the method further includes: preparing a first type doping layer on the second surface of the silicon substrate.
[0013] In some embodiments, after preparing the first passivation layer on the side of the polysilicon layer away from the silicon substrate, the method further comprises: preparing a first electrode on the first surface of the silicon substrate;
[0014] and / or,
[0015] After preparing the second passivation layer on the side of the silicon oxide layer away from the silicon substrate, the method further comprises: preparing a second electrode on the second surface of the silicon substrate.
[0016] In some embodiments, the polysilicon layer includes a first doping type region and a second doping type region, and after preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate, the method further includes: preparing a first electrode connected to the first doping type region;
[0017] and / or,
[0018] After preparing the second passivation layer on the side of the silicon oxide layer away from the silicon substrate, the method further comprises: preparing a second electrode connected to the second doping type region.
[0019] In some embodiments, before sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate, the method further includes: cleaning and texturing the silicon substrate.
[0020] In some embodiments, before sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate, the method further comprises: performing alkali polishing on the first surface of the silicon substrate.
[0021] In some embodiments, preparing a second passivation layer on a side of the silicon oxide layer away from the silicon substrate comprises: sequentially preparing an aluminum oxide layer and an anti-reflection passivation layer on a side of the silicon oxide layer away from the silicon substrate.
[0022] In some embodiments, preparing the anti-reflection passivation layer includes: preparing at least one of a silicon oxynitride layer, a silicon nitride layer, and a silicon oxide layer.
[0023] In a second aspect, the present application provides a solar cell, which is prepared based on any of the methods described above.
[0024] In the case of adopting the above technical solution, the present invention can sequentially prepare a tunneling layer and a polysilicon layer on the first surface of a silicon substrate, prepare a silicon oxide layer on the second surface of the silicon substrate, prepare a first passivation layer on the side of the polysilicon layer away from the silicon substrate, and prepare a second passivation layer on the side of the silicon oxide layer away from the silicon substrate to obtain a solar cell. By preparing a silicon oxide layer on the second surface of the silicon substrate, the recombination of carriers on the second surface of the silicon substrate can be further effectively prevented, which plays a role in passivating the surface and is conducive to improving the conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings, in which:
[0026] Figure 1 It is a schematic diagram of a process for preparing a solar cell provided in an embodiment of the present application;
[0027] Figure 2 is a schematic diagram of the silicon substrate structure provided in an embodiment of the present application;
[0028] Figure 3 It is a schematic diagram of the structure of a silicon substrate inserted back-to-back into a card slot provided in an embodiment of the present application;
[0029] Figure 4 This is a schematic diagram of a method for preparing a TOPcon battery provided in an embodiment of the present application;
[0030] Figure 5 1 is a schematic diagram of the cross-sectional structure of a TOPcon battery provided in an embodiment of the present application;
[0031] Figure 6 It is a schematic flow chart of a method for preparing a TBC battery provided in an embodiment of the present application;
[0032] Figure 7 It is a schematic diagram of the cross-sectional structure of a TBC battery provided in an embodiment of the present application. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0035] See also Figure 1 As shown, Figure 1 1 is a schematic flow chart of a method for preparing a solar cell provided in an embodiment of the present application, which may include:
[0036] Step S11: sequentially preparing a tunneling layer and a polysilicon layer on a first surface of a silicon substrate;
[0037] Step S12: preparing a silicon oxide layer on the second surface of the silicon substrate, the first surface and the second surface are arranged opposite to each other;
[0038] Step S13: preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate; and,
[0039] Step S14: preparing a second passivation layer on the side of the silicon oxide layer away from the silicon substrate to obtain a solar cell.
[0040] By preparing a silicon oxide layer on the second surface of the silicon substrate, the recombination of carriers on the second surface of the silicon substrate can be further effectively prevented, which plays a role in passivating the surface and is beneficial to improving the conversion efficiency of solar cells.
[0041] In the embodiment of the present application, the first surface may be the backlight surface of the solar cell, and the second surface may be the light-receiving surface of the solar cell.
[0042] In some embodiments, in order to avoid the influence of the preparation of the silicon oxide layer on the backlight surface structure of the silicon substrate, step S12 may be specifically as follows:
[0043] For the silicon substrate structure obtained after preparing the tunneling layer and the polysilicon layer, the first surface of the silicon substrate in the silicon substrate structure is placed opposite to the first surface of the silicon substrate in another silicon substrate structure, and the silicon substrate structure and the other silicon substrate structure are inserted into the card slot;
[0044] The card slot is placed in a furnace tube, and a silicon oxide layer is prepared on the second surface of the silicon substrate in the silicon substrate structure by a thermal oxidation method.
[0045] See also Figure 2As shown, the silicon substrate structure is the structure obtained after step S11, which includes a silicon substrate 20, a tunneling layer 21 and a polysilicon layer 22 sequentially arranged on a first surface S1 of the silicon substrate 20, and a second surface S2 arranged opposite to the first surface S1. Figure 3 is a schematic diagram of the silicon substrate structure of the back-to-back insertion slot provided in the embodiment of the present application, such as Figure 3 As described above, by placing the first surfaces of the two silicon substrate structures opposite to each other and inserting the two silicon substrate structures into the slots, the influence on the structure on the first surface S1 of the silicon substrate 20 when the silicon oxide layer is subsequently prepared by thermal oxidation can be effectively avoided.
[0046] In addition, the silicon oxide layer is prepared on the second surface of the silicon substrate in the silicon substrate structure by a thermal oxidation method, which is conducive to forming a dense silicon oxide film, and the obtained silicon oxide layer has better quality.
[0047] The solar cell preparation method provided in this application can be applied to prepare a tunneling oxide layer passivation contact cell, namely a TOPcon cell. Figure 4 As shown, Figure 4 1 is a schematic flow chart of a method for preparing a TOPcon battery provided in an embodiment of the present application, which may include:
[0048] Step S41: cleaning and texturing the silicon substrate;
[0049] Step S42: preparing a first type doping layer on the second surface of the silicon substrate;
[0050] Step S43: performing alkali polishing on the first surface of the silicon substrate;
[0051] Step S44: sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate;
[0052] Step S45: preparing a silicon oxide layer on the second surface of the silicon substrate, the first surface and the second surface are arranged opposite to each other;
[0053] Step S46: preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate;
[0054] Step S47: preparing a second passivation layer on a side of the silicon oxide layer away from the silicon substrate;
[0055] Step S48: preparing a first electrode on the first surface of the silicon substrate;
[0056] Step S49: preparing a second electrode on the second surface of the silicon substrate.
[0057] Among them, step S45 can be executed in the same manner as step S12, and will not be described again for the sake of brevity.
[0058] In some embodiments, step 41 may specifically be to clean and texture the silicon substrate to obtain a clean silicon substrate and form a pyramid-like texture structure on the first and second surfaces of the silicon substrate to reduce the reflectivity of light, which is beneficial to subsequently improve the photoelectric conversion efficiency of the battery.
[0059] In an embodiment of the present application, the first type doped layer and the silicon substrate have different doping types. In some embodiments, the silicon substrate may be N-type doped, and the first type doped layer may be P-type doped to form a PN junction. In other embodiments, the silicon substrate may also be P-type doped, and the first type doped layer may be N-type doped.
[0060] When the first type doped layer is P-type doped, step S42 may specifically be to prepare the first type doped layer on the second surface of the silicon substrate by using a boron diffusion process.
[0061] Step S43 is helpful to optimize the surface quality of the first surface of the silicon substrate, and facilitates the subsequent preparation process. In some embodiments, the first surface of the silicon substrate can be polished with an organic base.
[0062] In some embodiments, step S44 may specifically include: using chemical vapor deposition to sequentially prepare a tunneling layer and a polysilicon layer on the first surface of the silicon substrate.
[0063] In some embodiments, the preparation of the polysilicon layer may specifically include first forming a single crystal silicon layer, and then obtaining a doped polysilicon layer by doping and high temperature annealing.
[0064] In some embodiments, the material of the tunneling layer can be any one of silicon oxide, aluminum oxide, tantalum oxide, zirconium oxide, and titanium dioxide. The doping type of the polysilicon layer is the same as the doping type of the silicon substrate.
[0065] In some embodiments, step S46 may specifically include: preparing a silicon nitride layer on a side of the silicon oxide layer away from the silicon substrate as a passivation layer.
[0066] In some embodiments, step S47 may specifically include: sequentially preparing an aluminum oxide layer and an anti-reflection passivation layer on the side of the silicon oxide layer away from the silicon substrate. Preparing the anti-reflection passivation layer is beneficial to reducing light reflection loss, improving light transmittance, and thus improving the photoelectric conversion efficiency of the battery.
[0067] In some embodiments, an aluminum oxide layer may be formed on a side of the silicon oxide layer away from the silicon substrate by using an atomic layer deposition process.
[0068] In some embodiments, preparing the anti-reflection passivation layer may be preparing at least one of a silicon oxynitride layer, a silicon nitride layer, and a silicon oxide layer.
[0069] In some embodiments, step S48 may specifically be to prepare a first electrode on the first surface of the silicon substrate by screen printing or coating process. The first electrode may penetrate the first passivation layer and form an ohmic contact with the polysilicon layer.
[0070] In some embodiments, step S49 may be specifically to prepare a second electrode on the second surface of the silicon substrate by screen printing or coating process. The second electrode may penetrate the second passivation layer and silicon oxide and form an ohmic contact with the first type doped layer on the second surface of the silicon substrate.
[0071] The coating process may include a chemical vapor deposition process or a physical vapor deposition process.
[0072] Based on the preparation method provided in the above embodiment, a TOPcon battery can be obtained accordingly, such as Figure 5 As shown, Figure 5 : is a schematic diagram of the cross-sectional structure of a TOPcon cell provided in an embodiment of the present application, which may include: a silicon substrate 50, a tunneling layer 51, a polysilicon layer 52, a first passivation layer 53 and a first electrode 54 sequentially arranged on the first surface S1 of the silicon substrate 50, and a silicon oxide layer 55, a second passivation layer 56 and a second electrode 57 sequentially arranged on the second surface S2 of the silicon substrate 50, wherein a first type doping layer 501 is arranged on the second surface S2 of the silicon substrate. By preparing a silicon oxide layer on the second surface of the silicon substrate, the recombination of carriers on the second surface of the silicon substrate can be further effectively prevented, which plays a role in passivating the surface and is conducive to improving the conversion efficiency of the cell.
[0073] The solar cell preparation method provided in this application can be applied to prepare TBC (TOPcon Back Contact) cells, see Figure 6 As shown, Figure 6 1 is a schematic flow chart of a method for preparing a TBC battery provided in an embodiment of the present application, which may include:
[0074] Step S61: cleaning and texturing the silicon substrate;
[0075] Step S62: performing alkali polishing on the first surface of the silicon substrate;
[0076] Step S63: sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate, wherein the polysilicon layer includes a first doping type region and a second doping type region;
[0077] Step S64: preparing a silicon oxide layer on the second surface of the silicon substrate, the first surface and the second surface are arranged opposite to each other;
[0078] Step S65: preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate;
[0079] Step S66: preparing a second passivation layer on a side of the silicon oxide layer away from the silicon substrate;
[0080] Step S67: preparing a first electrode connected to the first doping type region;
[0081] Step S68: preparing a second electrode connected to the second doping type region.
[0082] Among them, steps S61, S62, S64-S66 can be executed in the same manner as steps S41, S43, S45-S47, and will not be repeated here for the sake of brevity.
[0083] In some embodiments, step S63 may specifically be to use a low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition process to sequentially prepare a tunneling layer and an intrinsic polysilicon layer on the first surface of the silicon substrate, and perform doping on the intrinsic polysilicon layer to obtain a first doping type region and a second doping type region, wherein the first doping type region and the second doping type region are isolated from each other. As an example, the first doping type region may be an N-type doped region, and the second doping type region may be a P-type doped region.
[0084] In some embodiments, step S67 may specifically be forming a via hole in the first passivation layer corresponding to the first doping type region, and depositing a conductive material covering the via hole by screen printing or plating, thereby obtaining a first electrode connected to the first doping type region.
[0085] In some embodiments, step S68 may specifically be forming a via hole in the first passivation layer corresponding to the second doping type region, and depositing a conductive material covering the via hole by screen printing or plating to obtain a second electrode connected to the second doping type region.
[0086] It should be noted that steps S67 and S68 can also be implemented simultaneously. Specifically, vias can be formed in the first doping type region and the second doping type region, respectively, and a conductive material covering the vias can be deposited by screen printing or plating to obtain a first electrode connected to the first doping type region and a second electrode connected to the second doping type region.
[0087] Based on the preparation method provided in the above embodiment, a TBC battery can be obtained accordingly, such as Figure 7 As shown, Figure 7: is a schematic diagram of the cross-sectional structure of a TBC battery provided by an embodiment of the present application, which may include: a silicon substrate 70, a tunneling layer 71, a polysilicon layer 72, a first passivation layer 73, a first electrode 74 and a second electrode 75 sequentially arranged on the first surface S1 of the silicon substrate 70, and a silicon oxide layer 76 and a second passivation layer 77 sequentially arranged on the second surface S2 of the silicon substrate 70, wherein the polysilicon layer 72 includes a first doping type region 721 and a second doping type region 722 that are isolated and arranged. By preparing a silicon oxide layer on the second surface of the silicon substrate, the recombination of carriers on the second surface of the silicon substrate can be further effectively prevented, which plays a role in passivating the surface and is conducive to improving the conversion efficiency of the battery.
[0088] Another aspect of the present application also provides a solar cell, which can be based on the above Figure 1 , Figure 4 or Figure 6 The method provided in the corresponding embodiment is prepared and achieves the same beneficial effects as the above embodiment.
[0089] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A method for preparing a solar cell, characterized in that: include: A tunneling layer and a polysilicon layer v are sequentially prepared on the first surface of the silicon substrate preparing a silicon oxide layer on the second surface of the silicon substrate, the first surface and the second surface being arranged opposite to each other; preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate; and, A second passivation layer is prepared on a side of the silicon oxide layer away from the silicon substrate to obtain a solar cell.
2. The method according to claim 1, characterized in that The step of preparing a silicon oxide layer on the second surface of the silicon substrate comprises: For the silicon substrate structure obtained after preparing the tunneling layer and the polysilicon layer, the first surface of the silicon substrate in the silicon substrate structure is placed opposite to the first surface of the silicon substrate in another silicon substrate structure, and the silicon substrate structure and the other silicon substrate structure are inserted into the card slot; The card slot is placed in a furnace tube, and a silicon oxide layer is prepared on the second surface of the silicon substrate in the silicon substrate structure by a thermal oxidation method.
3. The method according to claim 1 or 2, characterized in that: Before sequentially preparing a tunneling layer and a polysilicon layer on the first surface of the silicon substrate, the method further comprises: preparing a first type doping layer on the second surface of the silicon substrate.
4. The method according to claim 3, characterized in that After the first passivation layer is formed on the side of the polysilicon layer away from the silicon substrate, the method further comprises: forming a first electrode on the first surface of the silicon substrate; and / or, After preparing the second passivation layer on the side of the silicon oxide layer away from the silicon substrate, the method further comprises: preparing a second electrode on the second surface of the silicon substrate.
5. The method according to claim 1 or 2, characterized in that: The polysilicon layer includes a first doping type region and a second doping type region. After preparing a first passivation layer on a side of the polysilicon layer away from the silicon substrate, the method further includes: preparing a first electrode connected to the first doping type region; and / or, After preparing the second passivation layer on the side of the silicon oxide layer away from the silicon substrate, the method further comprises: preparing a second electrode connected to the second doping type region.
6. The method according to claim 1 or 2, characterized in that: Before sequentially preparing the tunneling layer and the polysilicon layer on the first surface of the silicon substrate, the method further comprises: cleaning and texturing the silicon substrate.
7. The method according to claim 1 or 2, characterized in that: Before sequentially preparing the tunneling layer and the polysilicon layer on the first surface of the silicon substrate, the method further comprises: performing alkali polishing on the first surface of the silicon substrate.
8. The method according to claim 1 or 2, characterized in that: The step of preparing a second passivation layer on a side of the silicon oxide layer away from the silicon substrate comprises: sequentially preparing an aluminum oxide layer and an anti-reflection passivation layer on a side of the silicon oxide layer away from the silicon substrate.
9. The method according to claim 8, characterized in that The preparation of the anti-reflection passivation layer includes: preparing at least one of a silicon nitride oxide layer, a silicon nitride layer and a silicon oxide layer.
10. A solar cell, characterized in that: Prepared according to the method according to any one of claims 1 to 9.