Partial address translation invalidation request

Abstract

A partial address translation invalidation request causes a cache control circuit to identify whether a given cache entry of an address translation cache is a target cache entry to be invalidated, where the target cache entry includes a cache entry for which the cache entry is to be invalidated, the address translation data includes partial address translation data indicating an address of a next level page table specified by a table address of a target page table entry when the target page table entry is used as a branch page table entry; and triggering invalidation of the given cache entry when the given cache entry is identified as the target cache entry. Retaining the given cache entry is permitted when the given cache entry provides full address translation data indicating an address of a corresponding region of an address space corresponding to an output address specified by the target page table entry when the target page table entry is used as a leaf page table entry.

Description

Background Art

[0001] The present technology relates to the field of data processing.

[0002] In a data processing system, an input address can be converted to an output address using address conversion data of a page table entry that depends on a page table structure in a memory. The page table structure can be a multi-level page table structure, wherein each level of the table structure either specifies an output address for address conversion, or specifies the address of a next level page table in the multi-level page table structure. This allows address conversion data to be stored across multiple discrete regions of memory (e.g., there is no need to allocate a sufficiently large continuous memory block to hold a linear page table with enough entries to cover the entire address space). An address translation cache can also be provided to store a subset of address conversion data. Summary of the invention

[0003] From an example, the present technology provides a device, the device comprising:

[0004] An address translation cache comprising a plurality of cache entries, each cache entry being used to store address translation data depending on one or more page table entries of a multi-level page table structure in a memory, wherein each page table entry of the multi-level page table structure can be used as at least one of the following:

[0005] A branch page table entry, which specifies a table address of a next-level page table; and

[0006] a leaf page table entry that specifies an output address of an address translation map for a corresponding region of the address space; and

[0007] A cache control circuit, the cache control circuit being responsive to the partial address translation invalidation request to:

[0008] An invalidation lookup operation is performed to identify whether a given cache entry of an address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises a next page table entry specified by a table address of the target page table entry when the target page table entry is used as a branch page table entry.

[0009] Partial address translation data for addresses of the hierarchical page table; and

[0010] When a given cache entry is identified as a target cache entry, invalidation of the given cache entry is triggered,

[0011] The partial address translation invalidation request indicates permission to retain a given cache entry when the given cache entry provides full address translation data indicating an address of a corresponding region of an address space corresponding to an output address specified by the target page table entry when the target page table entry is used as a leaf page table entry.

[0012] From another example, the present technology provides a method, the method comprising:

[0013] storing, in each of a plurality of cache entries of the address translation cache, address translation data dependent on one or more page table entries of a multi-level page table structure in the memory, wherein each page table entry of the multi-level page table structure is usable as at least one of:

[0014] A branch page table entry, which specifies a table address of a next-level page table; and

[0015] a leaf page table entry that specifies an output address of an address translation map for a corresponding region of the address space; and

[0016] In response to a partial address translation invalidation request:

[0017] An invalidation lookup operation is performed to identify whether a given cache entry of an address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises a next page table entry specified by a table address of the target page table entry when the target page table entry is used as a branch page table entry.

[0018] Partial address translation data for addresses of the hierarchical page table; and

[0019] When a given cache entry is identified as a target cache entry, invalidation of the given cache entry is triggered,

[0020] The partial address translation invalidation request indicates permission to retain a given cache entry when the given cache entry provides full address translation data indicating an address of a corresponding region of an address space corresponding to an output address specified by the target page table entry when the target page table entry is used as a leaf page table entry.

[0021] Viewed from another example, the present technology provides a computer program comprising instructions that, when executed on a host data processing device, control the host data processing device to provide:

[0022] The address translation logic is configured to perform address translation based on a multi-level page table structure in a memory, the address translation logic being configured to maintain an address translation data structure comprising a plurality of data structure entries, each data structure entry being configured to store address translation data depending on one or more page table entries of the multi-level page table structure, wherein each page table entry of the multi-level page table structure is usable as at least one of the following:

[0023] A branch page table entry, which specifies a table address of a next-level page table entry;

[0024] and

[0025] a leaf page table entry that specifies an output address of an address translation map for a corresponding region of the address space; and

[0026] Control logic, the control logic being responsive to the partial address translation invalidation request to:

[0027] performing an invalidation lookup operation to identify whether a given data structure entry of an address translation data structure is a target data structure entry to be invalidated, wherein the target data structure entry comprises a data structure entry for which the address translation data comprises an indication of a next page table entry specified by a table address of the target page table entry when the target page table entry is used as a branch page table entry.

[0028] Partial address translation data for addresses of the hierarchical page table; and

[0029] When a given data structure entry is identified as a target data structure entry, invalidation of the given data structure entry is triggered,

[0030] The partial address translation invalidation request indicates permission to retain a given data structure entry when the given data structure entry provides full address translation data indicating an address of a corresponding region of an address space corresponding to an output address specified by the target page table entry when the target page table entry is used as a leaf page table entry.

[0031] From another example, the present technology provides a non-transitory computer-readable storage medium storing the above-mentioned computer program. In another alternative example, the computer-readable storage medium may be a transient computer-readable storage medium.

[0032] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 and Figure 2 shows a data processing system in which the present technology may be implemented;

[0034] Figure 3 shows how a multi-level table structure can be used to convert input addresses to output addresses;

[0035] Figure 4 shows the use of a page walker cache (PWC) when performing address translation;

[0036] Figures 5 to 7 shows how multiple page table hierarchies can be merged together;

[0037] Figure 8 shows a two-stage address translation using stage 1 (S1) and stage 2 (S2) page tables;

[0038] Fig. 9 is a flow chart illustrating how cache control circuitry may respond to a partial address translation invalidation request;

[0039] Fig.10 is a flow chart illustrating pre-fetching in response to a partial address translation invalidation request;

[0040] Fig.11 is a flow chart illustrating decoding and execution of a partial address translation invalidation instruction by a processing circuit;

[0041] Fig.12 is a flow chart showing how cache control circuitry may be triggered to perform a partial address translation invalidation process in response to detecting a partial address translation invalidation command in a command queue; and

[0042] Fig.13 It is shown how the hardware of the present technique can be emulated in simulator code. DETAILED DESCRIPTION

[0043] The following description of example implementations and associated advantages is provided before discussing example implementations with reference to the accompanying drawings.

[0044] According to an example configuration, there is provided an apparatus including an address translation cache, the address translation cache including a plurality of cache entries, each cache entry being used to store address translation data depending on one or more page table entries of a multi-level page table structure in a memory, wherein each page table entry of the multi-level page table structure is usable as at least one of the following:

[0045] A branch page table entry that specifies the table address of the next level page table; and

[0046] - A leaf page table entry that specifies an output address of an address translation map for the corresponding region of the address space.

[0047] The apparatus also includes cache control circuitry that is responsive to the partial address translation invalidation request to:

[0048] performing an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicating an address of a next-level page table specified by a table address of the target page table entry when the target page table entry is used as a branch page table entry; and

[0049] When a given cache entry is identified as a target cache entry, invalidation of the given cache entry is triggered.

[0050] The partial address translation invalidation request indicates permission to retain a given cache entry when the given cache entry provides full address translation data indicating an output address of a corresponding region of an address space corresponding to an address specified by the target page table entry when the target page table entry is used as a leaf page table entry.

[0051] As explained above, page table is used to define the address conversion data for converting input address into output address.For example, input address can be the address in the input address space, and output address can be the address in the output address space different from the input address space.But, it should be understood that the input address in an address space can also be converted into the output address in the same address space.Usually, a large amount of address conversion data need to be defined in page table, so that conversion is provided for all accessible pages in the memory.Therefore, it may be difficult to find sufficiently large continuous memory area to store all address conversion data in the address conversion data.

[0052] To solve this problem, address translation data can be defined in a nested set of page tables called a multi-level page table structure. In the multi-level page table structure, each page table entry can be interpreted as either specifying an output address of an address translation for a corresponding region of the address space (in this case, the page table entry is used as a leaf page table entry) or specifying a table address of a next-level page table (in this case, the page table entry is used as a branch page table entry).

[0053] It should be noted that, although in some examples, each page table entry in the multi-level page table structure includes either a branch page table entry or a leaf page table entry (not both), in some other examples, a given page table entry may be used as both a branch page table entry and a leaf page table entry. For example, in some specific implementations, one or more page table entries in a given page table of a multi-level page table structure may be defined by software as "self-referencing" so that they provide a pointer to the address corresponding to the given page table itself. This means that the same page table can be used at more than one lookup level of the multi-level page table structure. Therefore, if a self-referencing entry is present at the penultimate lookup level of the page table structure, the same page table entry may be used as both a branch page table entry (when referenced at the penultimate level) and a leaf page table entry (when referenced at the final lookup level). In another example, the self-referencing entry may be located at the first lookup level (e.g., this may be referred to as level 0 at L0). In this example, the address of the entry that is "dereferenced" may then be constructed. For example, consider a system with four lookup levels (e.g., L0, L1, L2, and L3). When the self-reference entry is dereferenced once, the level 2 (L2) page table entry containing the table address is ultimately treated as a level 3 (L3) page table containing the output address, and the original L3 entry is treated as a data page. The self-reference entry can be dereferenced multiple times to access other levels. For example, when the entry is dereferenced twice, the L2 table will be treated as a data page.

[0054] Whether a page table is self-referential depends on the specific value of a pointer defined by software in an entry of that page table. The hardware may not be able to know whether a table is self-referential - for example, an address translation cache may end up caching information from the same page table multiple times, corresponding to different levels of the page table lookup hierarchy.

[0055] Leaf page table entries can be considered the final level of the page table structure (although in practice, leaf page table entries may also be found at higher levels of the table in implementations that support early termination of page table traversal based on leaf entry indicators in higher level page table entries), and provide an output address corresponding to a particular input address to be translated. Branch page table entries, on the other hand, do not provide an output address, but rather point to an additional page table at a subsequent level of the multi-level table structure (e.g., provide a table address of the additional page table). The additional page table may itself contain leaf page table entries or branch page table entries.

[0056] The device of the present technology includes an address translation cache. The address translation cache is a storage circuit that stores address translation data corresponding to a subset of page table entries of a multi-level page table structure, thereby allowing subsequent conversions using the address translation data to be performed with reduced latency. The address translation cache can store full address translations (e.g., it can be a translation lookaside buffer (TLB)) to allow the input address to be converted into an output address without accessing the page table in the memory. Alternatively, the address translation cache can store partial address translation data (e.g., it can be a page traversal cache, PWC) to reduce the number of memory accesses required to convert a given input address (because the partial address translation data can allow skipping one or more levels of the multi-level page table structure). Therefore, the full address translation data specifies the output address (or information indicating the output address) specified by the leaf page table entry corresponding to the given input address. On the other hand, the partial address translation data specifies the table address (or information indicating the table address) specified by the branch page table entry corresponding to the given input address. In addition, some address translation caches store both full address translation data and partial address translation data. Other specific implementations can have separate address translation caches for caching full address translation data and partial address translation data, respectively. The address translation cache may take any form, for example it may be a fully associative, direct mapped or set associative cache and include a plurality of entries, each entry storing address translation data depending on one or more page table entries of a multi-level page table structure.

[0057] The present technology provides a partial address translation invalidation (PATI) request, which is a request for a cache control circuit to invalidate partial address translation data stored in an address translation cache without invalidating full address translation data. In particular, the cache control circuit performs an invalidation search in response to the PATI request to identify any target cache entry in the address translation cache that stores partial address translation data corresponding to one or more target page table entries used as branch page table entries, and triggers the invalidation of those target cache entries. For example, the target cache entry can be invalidated by clearing the "valid" bit (or setting the valid bit to a value indicating that the entry is invalid) so that the partial address translation data is no longer available for performing address translation. However, the PATI request also indicates that the cache control circuit is allowed to retain any entry (corresponding to one or more target page table entries used as leaf page table entries) that provides full address translation data, even if the entry is identified as a target cache entry in the invalidation search or can be identified as a target cache entry in other ways.

[0058] It may be considered that providing support for PATI requests that invalidate partial address translation data without invalidating full address translation data is unnecessary, because if address translation changes (e.g., if address mapping from input address to output address changes), this generally involves a change to the output address stored in the leaf page table entry. Therefore, it can be expected that full translation data will need to be invalidated, rather than just invalidating partial address translation data. However, the inventor of the present technology recognizes that there may be such a situation, wherein the partial address translation for a given address mapping may change while full address translation data (e.g., output address) remains unchanged. For example, this may be due to the rearrangement of a page table or the migration of a page table from one part of a memory to another part. In this case, the table address of each page table in the page table may have changed, while the output address has not changed. Therefore, in this case, even if the partial address translation data stored in the address translation cache is no longer the latest, any full address translation data stored in the address translation cache is still correct. In this case, the inventor recognizes that full address translation data need not be invalidated.

[0059] Therefore, PATI requests are provided that allow partial address translation data to be invalidated without invalidating the full address translation data. This allows any full translation data stored in the address translation cache to remain available for performing address translations, thereby reducing the latency associated with those translations (since the output address does not need to be fetched from memory each time). Therefore, supporting PATI requests helps improve performance compared to systems that do not support PATI requests.

[0060] In some examples, the partial address invalidation request specifies a table level identifier indicating a subset of page table levels of the multi-level page table structure, and the target page table entry includes a page table entry at one of the subsets of the page table levels specified by the table level identifier.

[0061] For a given address translation mapping (e.g., a translation of a given input address to a given output address), the partial address translation data stored in the address translation cache may indicate the table address of a page table at any level of the multi-level page table structure, although in practice it may not be necessary to cache the table address of the top-level page table (e.g., level 0) because the top-level page table address may already be accessed from the base address register. Thus, in some examples, the partial address translation data indicates the table address of a page table at any level other than the top level of the multi-level page table structure.

[0062] The inventors recognize that, in some cases, not all of the partial address translation data associated with a given address translation mapping need to be invalidated using a PATI request. For example, in some cases, only a subset of the branch page tables used to identify the address translation mapping is remapped (e.g., the structure of only some levels of a multi-level page table structure is changed). Therefore, the inventors recognize that it would be useful to be able to invalidate the partial address translation data corresponding to a subset of the levels of a multi-level page table structure without invalidating the partial address translation data associated with other levels. Therefore, in this example, a table level identifier may be specified by a PATI request, thereby indicating that only the partial address translation data corresponding to the page table level specified by the table level identifier should be invalidated (e.g., allowing the partial address translation data corresponding to levels other than those identified by the table level identifier to be retained).

[0063] Other examples may not support such table level identifiers and may provide for PATI requests that target a partial address translation associated with a target page table entry at any level.

[0064] In some examples, the apparatus includes processing circuitry to issue a partial address translation invalidation request in response to a partial address translation invalidation instruction.

[0065] Thus, in this example, an instruction may be defined in an instruction set architecture (ISA) to cause a PATI request to be issued to a cache control circuit of an address translation cache. For example, the instruction may be a dedicated PATI instruction, or it may be a more general address translation invalidation instruction that includes a parameter (e.g., in the instruction encoding or in a control register) that distinguishes whether the address translation instruction should act as a PATI instruction or another type of address translation instruction.

[0066] In this example, the processing circuitry may be configured to perform data processing in response to instructions decoded by an instruction decoder. The format of the instruction encoding and the functionality represented by each instruction may be defined in accordance with an instruction set architecture (ISA). An ISA represents a framework of agreements between hardware manufacturers that manufacture processing hardware for a given processor implementation and software developers that write code to execute on that hardware, so that code written in accordance with the ISA will function correctly on hardware that supports the ISA.

[0067] When designing ISA, there may be significant design challenges in determining the processing operation set to be supported in ISA and the encoding of the instructions representing those operations. In principle, there may be a variety of different types of processing operations that may be useful for supporting some program applications, but in the available encoding space, it is impossible to represent each possible data processing operation that may be useful for a specific programmer. There may be restrictions on the number of bits that can be used to encode each instruction, because whenever an instruction is stored anywhere in the processor or transmitted by a wired processing path between logic elements, increasing the instruction bit width will cause additional circuit area and power consumption. In order to limit hardware and power costs, the instruction bit width can be selected, and when considering the need to encode operand values ​​by register descriptors and / or immediate values, the operand space left by the instruction bit width is not enough to represent each possible data processing operation that may be expected. Therefore, it will be necessary to make a design decision about which operation subset is the most important to support, and any operation that cannot be supported in a single instruction will then have to be executed using multiple instruction sets with equivalent functionality when executed together.

[0068] Therefore, it may be considered that providing an instruction in the ISA that triggers the processing circuit to issue a PATI request - especially if the instruction is a dedicated PATI instruction - is a waste of encoding space that can be used to define other more useful instructions, and therefore it may be considered counterintuitive to provide dedicated PATI instructions. However, the inventors of the present technology recognize that in some cases, for example, where low latency in address translation is important, and where it is desired to frequently update the structure of a multi-level address translation table without updating the address translation map itself, the PATI instruction may be of sufficient value to justify the cost of implementing the instruction in the ISA.

[0069] In some examples, the partial address translation invalidation request includes a write request requesting that a partial address translation invalidation command be written to a memory region accessible to the cache control circuitry.

[0070] For example, a PATI request may request that a PATI command be written to a command queue in a memory, and a cache control circuit may monitor the command queue to identify any new commands issued, and may execute the PATI process described above in response to writing the PATI command to the command queue. According to this method, a PATI request may be implemented without necessarily defining a PATI instruction in the ISA, which avoids occupying coding space in the ISA (but it should be understood that a PATI instruction converted by a processing circuit to a write request may be defined). In addition, the method is particularly useful for invalidating a portion of the address translation cached in an address translation cache external to a processor core (e.g., an I / O MMU (input / output memory management unit) or an address translation cache accessible to a device MMU such as an MMU in a GPU (graphics processing unit)). An I / O MMU may also be referred to as a system MMU (SMMU).

[0071] In some examples, the cache control circuitry is configured to detect a partial address translation invalidation command issued on a memory system interconnect, wherein the partial address translation invalidation request includes the partial address translation invalidation command.

[0072] Another way in which a PATI command may be issued to the cache control circuitry is via a memory system interconnect (e.g., an interconnect that couples an address translation cache to memory, and which may also couple one or more request agents (such as processing elements) to each other and to memory). For example, while a PATI request may be issued via the interconnect as with a write request discussed above, the interconnect may support command encodings (different from encodings used for write requests) that indicate a PATI command (e.g., unlike a write option, a PATI command may be indicated by an encoding on a request channel of the interconnect, rather than by write data sent on a data channel associated with the write request). Likewise, a PATI command may be a command issued by processing circuitry in response to execution of a PATI instruction, but this is not necessarily the case.

[0073] In some examples, the apparatus includes a page table walk circuit that is responsive to an input address to locate a given page table entry in a multi-level page table structure based on a given table address and an index portion of the input address, the page table walk circuit being configured to determine a size of an index portion to be used for at least one level of the multi-level page table structure depending on whether a table merge indication is set.

[0074] The page table traversal circuit may be provided in the memory system of the device to locate and retrieve a given output address for the conversion of a given input address. For example, the page table traversal circuit may derive multiple index portions from the input address (or the address conversion circuit may derive the index portion and provide the index portions to the page table traversal circuit). Each index portion may be based on a subset of bits in the input address, for example. The page table traversal circuit then uses these index portions to "traverse" the multi-level page table structure until it reaches the leaf page table entry corresponding to the input address. For example, the traversal involves identifying the base address of a given page table (for example, for the first level page table, the base address can be obtained from the base address storage location, and for each subsequent page table level, the base address is the table address specified by the branch page table entry of the page table at the previous level), and using the corresponding index portion to identify a specific page table entry in a given page table. The page table entry (if it is a branch page table entry) is then used in conjunction with another index portion to identify the next level page table entry, and the process is repeated until the leaf page table entry corresponding to the input address is identified.

[0075] The size of each index portion depends on the size of the corresponding page table - a page table with more entries requires a larger index portion in order to allow the page table traversal circuit to identify the required page table entries in the page table. It can be expected that the index portion corresponding to each level of the multi-level page table structure remains constant, because it can be assumed that the size of the page table at each level will remain constant. However, the inventors recognize that in some cases, it may be useful to be able to merge page tables at two or more levels together. For example, if a sufficiently large continuous address space area becomes available for storing the merged L1 / L2 page table, it may be advantageous to move the L1 table and the L2 table to the continuous address space area and merge them together into a single table (e.g., with a shared base address). The entries in the merged L1 / L2 page table can then be identified based on the updated base address (obtained from the L0 page table, so it will need to be updated after the merge) and the larger index portion (e.g., this can be an index portion including the previous L1 and L2 portions). This can be advantageous because it reduces the number of accesses to memory required to obtain an address translation, since the table address obtained from the merged L1 / L2 page table can be used to identify the L3 page table, thus avoiding a separate lookup to the L2 table.

[0076] Thus, the page table traversal circuitry may use a table merge indication (which may be set to a predetermined value, for example, when merging two or more levels of a multi-level page table structure) to determine which bits of the input address should be used to determine each index portion to be used in the page table traversal.

[0077] The merging of multiple levels of multi-level page table structure is an example of the situation that partial address conversion data for multiple input addresses can be updated when full address conversion data is not updated.For example, in the example given above, the partial address conversion data indicating the base address of L2 table may be outdated, because the L1 / L2 table merged now is used, and the partial address conversion indicating the base address of L1 table may be outdated, because the L1 / L2 page table merged can be stored in different locations in the memory.However, although the structure of L1 / L2 table has changed, the output address defined for a given input address may not have changed.Therefore, this is a specific example of the situation that the PATI request of the present technology may be useful.Similarly, if the table previously merged is split to return from the merged L1 / L2 table to separate L1 table and L2 table, this may cause the partial address conversion data of cache to be outdated.

[0078] It should be understood that, although the examples given above consider the merging of L1 and L2 tables, other page table levels may also be merged, and more than two levels may be merged. In addition, although the merging of page tables has been described above as an example use case for a PATI request, it should be understood that there are other possible use cases for the request. For example, in some cases, the defragmentation of a memory may cause one or more page tables to need to be moved from one location in the memory to another. Therefore, even if no merging occurs, the base addresses of those tables that are moved (and therefore the corresponding partial address translation data) may be updated without updating the associated address translation mapping. Therefore, even in a system that does not support the merging of page table levels, a PATI request may also be useful.

[0079] The target cache entry to be invalidated may be identified in any of a variety of ways.

[0080] In some examples, the partial address translation invalidation request specifies target address information corresponding to a target page table entry.

[0081] Therefore, the target address information can be used to identify the target cache entry, such as by comparing the target address information with the address information associated with each cache entry in the cache entry in the address translation cache. This allows the partial address translation data associated with a specific address translation mapping to be specified and the partial address translation data to be invalidated in response to a PATI request, thereby avoiding the need to invalidate the partial address translations used for other address translation mappings when the partial address translation data may still be valid. This helps to improve performance, because the partial address translation data used for those other address translation mappings can remain available in the cache for use by the address translation circuit.

[0082] In some examples, where the PATI request specifies target address information, the cache control circuitry performs a pre-fetch operation in response to the partial address translation invalidation request to pre-fetch updated partial address translation data corresponding to the target address information.

[0083] Therefore, the partial address translation data that has been updated in the memory (causing the need to issue a PATI request) can be updated in the address translation cache, and the outdated partial address translation data can be invalidated. This reduces the waiting time for subsequent address translations based on the updated address translation data. The cache control circuitry can perform a pre-fetch operation after all partial address translation invalidation operations have been performed (e.g., after the partial address translation data in each target cache entry stored in the target cache entry has been invalidated), or the cache control circuitry can be capable of performing the pre-fetch operation and the PATI operation in parallel.

[0084] In some examples, the cache control circuitry is configured to limit prefetch operations to prefetching updated partial address translation data for addresses corresponding to invalidated cache entries that were invalidated in response to the partial address invalidation request.

[0085] In this way, the pre-fetch operation performed in response to a PATI request can be limited so that the cache eviction strategy applied by the cache control circuit (e.g., when trying to find an entry in the address translation cache for storing the pre-fetched updated address translation data) does not cause any valid address translation data to be evicted from the cache. The updated partial address translation data pre-fetched in response to a PATI request is therefore limited to data corresponding to the address for which the corresponding target cache entry is invalidated. This is helpful because the cache eviction strategy implemented by the address translation cache can be based on the recentness of access to the address associated with the cached conversion. The issuance of an invalidation request can only reflect that the supervisory process has reorganized the page table structure, rather than giving any clues about which addresses are most likely to be accessed again in the near future, so the pre-fetch performed in response to a PATI request is preferably not to disrupt the normal scheme for managing cache eviction. Therefore, on average, if the address translation data pre-fetched in response to a PATI request only replaces the invalidated address translation data, rather than causing the expulsion of other address translation data that has not been invalidated, performance can be improved.

[0086] In these examples, the target address information specified by the PATI request may be any address information that allows a particular cache entry to be identified as a target cache entry.

[0087] In some examples, the address translation mapping is between an input address in an input address space and an output address in an output address space, and the target address information includes the input address information.

[0088] This can be useful because many address translation caches are indexed and / or tagged based on the input address to be translated. Thus, identifying a target cache entry based on input address information (information indicating one or more input addresses) can utilize logic (e.g., comparison logic) that may already exist in the cache and / or cache control circuitry.

[0089] However, the target address information may also take different forms.

[0090] In some examples, the address translation mapping is between an input address in the input address space and an output address in the output address space, and the target address information includes an address in the output address space or an address in another address space translated from the output address space.

[0091] For example, the target page table entry may be a page table entry stored in a memory address region corresponding to the address specified by the PATI request (e.g., the target page table entry may be an entry of a page table stored at a memory address region corresponding to the address specified in the PATI request). In fact, in principle, any address indicating the target partial address translation data to be invalidated may be used as the target address information specified by the PATI request. For example, the invalidation may be performed by a physical address (PA), wherein if the partial address translation data corresponds to an entry in a page table having a base address corresponding to the specified PA, the partial address translation data is invalidated. In another example, the invalidation may be performed by an intermediate physical address (IPA), wherein if the partial address translation data corresponds to an entry in a page table having a base address corresponding to the specified IPA, the partial address translation data is invalidated. Moreover, the invalidation may be performed by a physical address (PA), wherein the target page table entry is an entry associated with a guest translation from a virtual address (VA) to an intermediate physical address (IPA), the intermediate physical address corresponding to a memory region corresponding to the specified physical address. This example may be useful when the PATI request is issued by a hypervisor responsible for stage 2 mapping from IPA to PA.

[0092] In some examples, the target address information includes a target address range that can span multiple pages.

[0093] Thus, rather than specifying an address indicating a single page (eg, a single output address defined in a single leaf page table entry, or a corresponding single input address), a range of target addresses may be specified.

[0094] While the above examples consider a PATI request that specifies target address information, this is not required and the PATI request may indicate the target cache entry in different manners.

[0095] For example, in some examples, the PATI request can be a global PATI request indicating that all partial address translation data in the address translation cache should be invalidated. In other examples, the PATI request can be a request to invalidate any partial address translation data corresponding to a specific level of a multi-level page table structure (e.g., identified by the table level indicator discussed above), independent of the address.

[0096] In some examples, the partial address translation invalidation request specifies a context identifier, and the cache control circuitry is configured to identify the target cache entry dependent on the context identifier.

[0097] Thus, in this example, the cache control circuitry is arranged to invalidate a portion of the address translation data corresponding to a particular context. For example, a PATI request may specify a context identifier (context ID) without specifying any target address information, or it may specify both the target address information and the context identifier, causing the cache control circuitry to identify any cache entry corresponding to both the target address information and the context identifier as the target cache entry.

[0098] Each of the cache entries in the address translation cache may be associated with a corresponding context identifier, in which case the target cache entry may be identified by the cache control circuitry by comparing a context identifier specified by the PATI request context identifier associated with the cache entry of the address translation cache.

[0099] In some examples, the context identifier indicates at least one of:

[0100] Virtual machine identifier;

[0101] an address space identifier; and

[0102] ·Safe status.

[0103] The context specified by a given context identifier may include any instruction execution context that the device is capable of supporting. For example, if the device is capable of supporting the execution of a virtual machine, the context identifier may include an indication of the specific virtual machine (e.g., a virtual machine identifier, VMID). If the device supports conversion of input addresses from multiple different address spaces, the context identifier may include an address space identifier (ASID) to identify a specific address space among the multiple address spaces. If the device is capable of operating in multiple security states (e.g., a secure state and a less secure state (sometimes also referred to as an unsecure state, although it should be understood that the "unsecure" state may still be supported by some security measures)), the context identifier may also identify a given security state.

[0104] The device can operate in an instruction execution context defined by multiple factors—for example, the device may be able to support any combination of multiple virtual machines, multiple address spaces, and multiple security states. Thus, the context identifier can be based on a combination of any two or more of VMID, ASID, and security state.

[0105] The context identifier may directly identify a variable or these variables (e.g., the context identifier may be a virtual machine identifier (VMID), an address space identifier (ASID), or an indication of a security state, or may be a cascade of multiple of these identifiers), or it may indirectly indicate one of these variables or a combination of these variables.

[0106] In some examples, the portion of the address translation data indicates one of:

[0107] The address of the next level of page table; and

[0108] Another address translated from the address in the next level page table.

[0109] For example, the address translation data may identify an address (e.g., it may be all or part of an address), or it may identify another address that is translated from the address. For example, in a device that supports translation from a virtual address to a physical address via an intermediate physical address (e.g., two-stage address translation), the partial address translation data may identify a physical table address (e.g., a table address that directly points to a next-level page table) or an intermediate physical table address (e.g., an address to be translated into a physical table address using a stage two translation table).

[0110] Full address translation data may similarly be represented in a variety of ways.

[0111] In some examples, the full address translation data indicates one of the following:

[0112] The output address; and

[0113] ·An additional address converted from the output address.

[0114] The techniques discussed above may be implemented in a hardware device having circuit hardware implementing the address translation cache and cache control circuitry described above (and optionally any of the additional features provided by some examples, such as address translation circuitry, processing circuitry, and page table traversal circuitry), the hardware device supporting PATI requests. For example, this may include support for PATI instructions as part of a native instruction set architecture supported by the decoding circuitry and processing circuitry.

[0115] However, in another example, the same technology can be implemented in a computer program (e.g., an architecture simulator or model), which can be provided to control a host data processing device to provide an instruction execution environment for executing instructions from a target code. The computer program includes an address conversion program logic for performing address conversion based on a multi-level page table structure in a memory (e.g., a memory accessible to a host data processing system), and the address conversion program logic maintains an address conversion data structure corresponding to the address conversion cache described above. When the computer program is executed by a host data processing circuit, the address conversion data structure can be implemented in (e.g.) a memory, but will be arranged to be stored in a subset of address conversion data defined in the multi-level page table structure (e.g., including partial address conversion data). The program also includes control logic for simulating the cache control circuit described above to support PATI requests. Therefore, the computer program controls the host data processing device when executed to provide an instruction execution environment corresponding to the device described above. Therefore, the computer program of the present technology can allow the host data processing system to provide all of the technical advantages discussed above.

[0116] Thus, such a simulator computer program can present an instruction execution environment for target code executed on the simulator computer program that is similar to the instruction environment provided by an actual hardware device capable of directly executing the target instruction set, even though any actual hardware providing these features may not be present in the host computer executing the simulator program.

[0117] This can be useful for executing code written for one instruction set architecture on a host platform that does not actually support that architecture. The simulator can also be useful during the development of software for a new version of an instruction set architecture, when software development is performed in parallel with the development of hardware devices that support the new architecture. This can allow software to be developed and tested on the simulator, allowing software development to begin before hardware devices that support the new architecture are available.

[0118] In some specific examples, the computer program may also include instruction decoding program logic for decoding instructions of the target code so as to control the host data processing device to perform data processing. Therefore, the instruction decoding program logic emulates the function of the instruction decoder of the hardware device as discussed above. The instruction decoding program logic may include support for the PATI instructions described in some of the above examples. However, even if a dedicated PATI instruction is not provided, a control program logic is provided to emulate the cache control logic discussed above so as to support PATI requests.

[0119] Furthermore, in some examples, the computer programs discussed above may be stored in a computer-readable storage medium, which may be a transient storage medium or a non-transitory storage medium.

[0120] Specific examples will now be described with reference to the accompanying drawings.

[0121] Figure 1 An example of a data processing system 102 is schematically shown, the data processing system having at least one processing element (PE) 104, which may be, for example, a CPU (central processing unit) or a GPU (graphics processing unit), having an instruction decoder 106 for decoding program instructions and processing circuitry 108 controlled to perform processing operations in response to instructions decoded by the instruction decoder 106. The PE 104 has a cache 110 for caching data from a memory for faster access by the PE, and has a memory management unit (MMU) 112, which functions as an address translation circuit to translate an input address (e.g., a virtual address specified by an instruction executed by the PE 104) into an output address (e.g., a physical address identifying a location within a memory system). The MMU may have at least one address translation cache 114 for storing address translation data (which may include one or both of partial address translation data and full address translation data) that depends on page table data from a page table structure stored in the memory system. The page table structure defines the address mapping between input addresses and output addresses, and may also define memory access permissions, which may define whether certain software processes executing on PE 104 are allowed to access certain addresses. MMU 112 may support 2-stage address translation, where the mapping of virtual addresses to physical addresses depends on stage 1 address translation data that maps a virtual address (VA) to an intermediate physical address (IPA) and stage 2 translation data that maps the IPA to a physical address (PA). Stage 1 address translation data may be set by an operating system or virtual machine. Stage 2 translation data may be set by a hypervisor. This is discussed in more detail below.

[0122] PE 104 is an example of a requester device capable of executing program instructions. Figure 1 Only one such requestor device is shown, but it should be understood that system 102 may have two or more such devices, which may include additional PEs, such as CPUs, GPUs, or other types of instruction execution devices.

[0123] In addition to PEs 104 or other devices that are capable of executing instructions and have their own internal MMUs 112, the system may also include requestor devices 120 (e.g., these devices may be I / O devices, hardware accelerators, etc. - for example, they may include devices that do not execute instructions themselves but can be configured by the PE to perform functions on behalf of the PE) that may not have an internal MMU and are therefore used to access memory and provide address translation functionality, such devices may communicate with the rest of the system via a system memory management unit (SMMU) 122, which includes address translation circuitry that controls address translation and memory permissions based on translation data defined in page table structures in memory. Likewise, the SMMU 122 may have one or more address translation caches 124 that have functionality similar to the address translation cache 114 within the MMU 112 of the PE 104. Devices 120 that access memory via the SMMU 122 may include cached devices that include an internal cache 126 and uncached devices that do not have any cache. For example, the device 120 may include a display controller for controlling the display of image frames on a display, a network controller for controlling the input or output of data via a network, a hardware accelerator for performing certain specialized processing functions in a more efficient manner than can be achieved using software executed on a general-purpose processor such as PE 104. Similar to the address translation cache 114 in the MMU 112, the SMMU address translation cache 124 can cache one or both of partial address translation data and full address translation data. It should be noted that although the PATI request discussed herein is a request to invalidate partial address translation data, the requester issuing the PATI request will not know the form of the address translation cache present at any recipient of the request - it simply issues the request. A recipient having only an address translation cache that caches full address translations can (for example) simply ignore the request completely, while a recipient having an address translation cache that caches partial address translations takes action on the request.

[0124] All of the requester devices 104, 120 communicate with each other via an interconnect 130 that is responsible for routing transactions between the requester devices and memory 132. The interconnect 130 may also be responsible for managing the coherency between data cached in the system's respective caches 110, 126. It should be understood that Figure 1 is a simplified diagram, and for the sake of brevity, the system 102 may have Figure 1 Many other components are shown.

[0125] Figure 2 Schematically showing a Figure 1 1. The data processing apparatus has a processing pipeline 108 (an example of processing circuitry, which may, for example, form part of a PE such as a CPU or GPU)—it should be noted that in this case, the instruction decoder 106 is considered to be part of the processing circuitry 108; whether the instruction decoder 106 is considered to be part of the processing circuitry is semantic. The processing circuitry 108 is used to execute instructions defined in an instruction set architecture (ISA) to perform the data processing operations represented by the instructions. The processing pipeline 108 includes a plurality of pipeline stages. In this example, the pipeline stages include: a fetch stage 205 for fetching instructions from an instruction cache 207; a decode stage (instruction decoder) 106 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; an issue stage 209 for checking whether the operands required for the micro-operation are available in the register file 215, and once the required operands for a given micro-operation are available, the micro-operation is issued for execution; an execution stage 216 for performing a data processing operation corresponding to the micro-operation by processing the operands read from the register file 215 to generate a result value; and a write-back stage 218 for writing the processed result back to the register file 215. It should be understood that this is only one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, a register renaming stage may be included for mapping an architectural register specified by a program instruction or micro-operation to a physical register descriptor identifying a physical register in the register file 215. In some examples, there may be a one-to-one relationship between program instructions defined in the ISA decoded by the decode stage 106 and corresponding micro-operations processed by the execute stage. It is also possible that there may be a one-to-many or many-to-one relationship between program instructions and micro-operations, such that, for example, a single program instruction may be split into two or more micro-operations, or two or more program instructions may be fused and processed as a single micro-operation.

[0126] The execution stage 216 includes a plurality of processing units for performing different categories of processing operations. For example, the execution units may include: a scalar arithmetic / logic unit (ALU) 240 for performing arithmetic or logic operations on scalar operands read from registers 215; a floating point unit 242 for performing operations on floating point values; a branch unit 244 for evaluating the results of branch operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 246 for performing load / store operations to access data in the memory system 207, 250, 252, 132.

[0127] As in Figure 1 , a memory management unit (MMU) 112 controls memory access permission checks and performs address translations between virtual addresses specified by a load / store unit 246 based on the operands of the data access instruction and the physical address identifying the storage location of the data in the memory system. Although the MMU 112 is shown as being associated with the load / store unit 246, the MMU 112 may also be consulted upon instruction fetches triggered by the fetch stage 205 (or a separate instruction-side MMU may be implemented to handle instruction fetches, separate from the data-side MMU used by the load / store unit 246 for data accesses—in which case both MMUs may cache information from the shared set of page tables in their address translation caches 114).

[0128] In this example, the memory system includes a level one data cache 250, a level one instruction cache 207, a shared level two cache 252, and the main system memory 132. The caches 207, 250, 252 are Figure 1 . It should be understood that this is only one example of a possible memory hierarchy and that other cache arrangements may also be provided. The specific type of processing units 240 to 246 shown in the execution stage 216 is only one example and other implementations may have different sets of processing units or may include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be handled in parallel. It should be understood that Figure 2 (as Figure 1 ) are only simplified representations of some components of a possible processor pipeline implementation, and the processor may include many other elements that are not shown for the sake of brevity.

[0129] Figure 3is a diagram schematically illustrating a page table walk operation performed by a page table walk circuit to identify an output address corresponding to an input address to be translated, assuming that there is a single stage address translation mechanism being used. In this example, it is assumed that the virtual address is 48 bits, and the virtual address 300 has a series of 9-bit portions associated with different levels of the page table walk process, and the 12 least significant bits representing the page offset.

[0130] At the beginning of the page table traversal process, the base address register is accessed to identify a base address 310 for identifying a page table 315. The 9 bits 305 associated with level 0 of the page table traversal process are used to identify an index into the page table 315, and therefore identify a branch page table entry storing an intermediate level descriptor 317. The intermediate level descriptor 317 provides a base address 320 (also referred to as a table address) for identifying an additional page table 330, wherein the level one virtual address bits 325 are used to identify an index into the table. This identifies an intermediate level descriptor 332, which provides an additional base address (table address) 335 to identify a page table 345. The level 2 virtual address bits 340 are then used to provide an index into the table 345 to identify the intermediate level descriptor 347, which then provides a base address (table address) 350 identifying a final page table 360. The level 3 virtual address bits 355 are then provided as an index into the table 360, thereby identifying a leaf page table entry that specifies a final level descriptor 362 (also referred to as a page descriptor or leaf descriptor). Using the information provided by the page descriptor, full address translation data may then be generated for storage in one of the entries in the address translation cache 114, thereby enabling the virtual page number 355 to be transformed into a physical page number 370, and thus allowing identification of the desired page in memory. This then enables the specific data (or instruction) item corresponding to the virtual address to be accessed by the kernel, thereby issuing the desired physical address to the memory system. An example of an address translation cache 114, 124 that stores full address translation data like this is a translation lookaside buffer (TLB).

[0131] In addition, partial address translation data corresponding to one or more of the base addresses 320, 335, 350 may also be stored in the address translation caches 114, 124. An example of an address translation cache 114, 124 storing partial address translation data is a page walker cache. In addition, an address translation cache 114, 124 storing both full address translation data and partial address translation data may also be provided.

[0132] It should be noted that in some embodiments, the final level descriptor (output address) may be specified at an earlier level in the page table traversal process. For example, descriptor 347 may have a block field that, when set, indicates that the descriptor is a block descriptor, which is a type of final level descriptor (e.g., an output address for an address translation map corresponding to a memory block), rather than an intermediate level descriptor (e.g., an indication table address). Therefore, the information within descriptor 347 may be used to generate full address translation data, and in such examples, the entry of page table 345 storing the block descriptor will be a leaf page table entry.

[0133] Therefore, it should be understood that the full address translation information returned to the address translation circuitry to enable the address translation data to be allocated to the address translation cache may be associated with a variety of different page sizes. For example, if the final level descriptor is descriptor 362, i.e., a leaf descriptor, the received translation information may be associated with a page of, for example, 4KB in size. In contrast, if the final level descriptor is a block descriptor, the associated page size may be significantly larger. For example, if Figure 3 The descriptor 347 in is this type of block descriptor, then in one embodiment it can be relevant to the 2MB page size. In addition, as will be discussed in more detail below, it is also possible that the partial address translation data is cached in the address translation cache of a base address in indication base address 320,335,350.

[0134] For example, Figure 4 Schematically, a page walker cache 400 (which is an example of an address translation cache 114, 124 and includes a plurality of cache entries 412) is used in an address translation circuit when translating from a virtual address (VA) as an input address to a physical address (PA) as an output address. The address translation circuit receives the virtual address and performs an initial lookup in the page walker cache 400. The lookup in the page walker cache 400 determines whether the virtual address, or a portion thereof, has been recently translated by the address translation circuit. If any sequentially most significant portion of the input address hits in the cache, then the lookup in the page walker cache 400 will result in that hit. Thus, if the most significant N-bit portion of the virtual address (e.g., Figure 3305) in the page walker cache 400, there will be a cache hit. This hit will also exist if the two most significant N-bit portions of the virtual address (e.g., the L0 and L1 index portions 305, 325) hit in the page walker cache 400. This hit will also exist if the three most significant N-bit portions of the virtual address (e.g., the L0, L1, and L2 index portions 305, 325, 340) hit in the page walker cache. If the page walker cache 400 is a shared structure that also caches full translations, this hit will also exist if the four most significant N-bit portions of the virtual address (e.g., the L0, L1, L2, and L3 index portions 305, 325, 340, 355) hit in the page walker cache. On the other hand, other implementations may cache full translations in a separate structure from partial translations, and in such cases, the page walker cache 400 may not detect any hits based on the combination of the L0, L1, L2, and L3 index portions 305, 325, 340, 355.

[0135] In this way, the page walker cache can determine multiple hits for a single virtual address. In the event that there are multiple hits in the page walker cache 400, the address translation circuitry is configured to use the most specific match, i.e., the hit that matches the most N-bit portion of the virtual address. Unless the match spans the full set of index portions 305, 325, 340, 355 (in which case the result of the lookup is full address translation data), the result of the lookup—regardless of how many most significant N-bit portions are matched—is partial address translation data, as it may allow address translation to be performed with reduced latency despite the unidentified output PA.

[0136] If the lookup in page walker cache 400 misses, the address translation circuitry then performs a maximum predetermined number of sequential lookups in the page table hierarchy (e.g., by instructing the page walker circuitry to perform a lookup such as Figure 3 In this case, the page walk circuit performs an L0 level lookup 402, an L1 level lookup 404, an L2 level lookup 406, and an L3 level lookup 408 to determine the physical address.

[0137] If the best hit in the page walker cache 400 matches only the most significant N-bit portion of the virtual address, the address translation circuitry does not need to perform an L0 lookup because the results of that lookup can be retrieved from the page walker cache. Therefore, the address translation circuitry performs an L1 lookup 404, an L2 lookup 406, and an L3 lookup 408 to determine the physical address.

[0138] If the best hit in the page walker cache 400 matches the two most significant N-bit portions of the virtual address, the address translation circuitry does not need to perform an L0 lookup or an L1 lookup because the results of those lookups can be retrieved from the page walker cache. Therefore, the address translation circuitry performs an L2 lookup 406 and an L3 lookup 408 to determine the physical address.

[0139] If the best hit in the page walker cache 400 matches the three most significant N-bit portions of the virtual address, the address translation circuitry does not need to perform an L0 lookup, an L1 lookup, or an L2 lookup because the results of those lookups can be retrieved from the page walker cache. Therefore, the address translation circuitry only performs an L3 lookup 408 to determine the physical address.

[0140] Figure 5 A specific use case of PATI request of this technique is demonstrated. In particular, Figure 5 Details of the address translation circuit 540 in some example configurations are schematically shown. The address translation circuit includes a partial translation storage circuit 550 for caching information related to previous address translations (for example, this can be a page walker cache (PWC) 400, or a general address translation cache 114 that stores full address translation data and partial address translation data). The address translation circuit 540 is also provided with at least one base address register 552 (for example, in some embodiments, there may be separate privileged and non-privileged base address registers). The base address register 552 includes the address of the sequential first (e.g., L0) page table level and optionally includes size information indicating the size of the sequential first page table level (for example, depending on whether merging of the L0 page table is supported - if only L1 / L2 page tables can be merged, then this size information may not need to be provided).

[0141] The address translation circuit 540 receives an input address 542 and performs a translation to output an output address 544. The address translation circuit 540 performs the translation by passing the input address and the base address or partial address translation data stored in the address translation cache 550 to a page table traversal circuit 549, which performs a page table traversal including multiple sequential searches in multiple page tables. The page table includes a conventional page table hierarchy 548 and a large (e.g., merged) page table hierarchy 546. Each search uses information from the previous search (or, in the case of an L0 search, the base address stored in the base address register) and information from the input address. The search includes an intermediate search that produces an address of the sequential next search in the sequential next page table hierarchy and page table hierarchy size information indicating the size of the sequential next page table hierarchy.

[0142] The address translation circuit also includes a cache control circuit 551 for controlling the address translation cache 550. The cache control circuit is configured to perform a PATI process in response to a partial address translation invalidation (PATI) request (e.g., a command written to a command queue and detected by the cache control circuit, or a command issued on the memory system interconnect 130). The PATI process involves identifying a target cache entry in the address translation cache (e.g., based on a target address and / or context ID specified by the PATI request), and if the target cache entry stores partial address translation data rather than full address translation data, the target cache entry is invalidated. For example, when multiple conventional page tables 548 are merged to form a large / merged page table 546, a PATI request may be issued. In this case, any partial address translation data corresponding to the merged page table may no longer be correct, even if the address translation itself is still correct. Therefore, in this case, it may be useful to be able to invalidate the partial address translation data without invalidating the full address translation data.

[0143] Figure 6 Schematically, details of address translation performed by address translation circuit 540 according to various configurations are shown. Address translation circuit 540 receives an input address. The input address includes 48 bits, which include a sequence of index portions (bit 47 down to bit 39; bit 38 down to bit 30; bit 29 down to bit 21; and bit 20 down to bit 12). Each index portion of the sequence of index portions corresponds to (is used for) a corresponding search level. In the illustrated configuration, four searches are shown, and the first address includes one index portion for each of the searches.

[0144] Bits 47 down to bit 39 of the input address are L0 index bits, which are used to index into the page table hierarchy accessed during the L0 lookup (the first intermediate lookup in sequence). The L0 lookup is performed in the page table hierarchy with a page table address (L0 base address) stored in a storage circuit (e.g., a base address register) of the address translation circuit. The storage circuit further includes size information indicating that the L0 lookup is a lookup in the conventional page table hierarchy. The lookup performed based on the L0 base address and the L0 index bits returns a base address to be used for the next lookup in sequence (L1 lookup) and size information indicating that the L1 lookup is a lookup in the conventional page table hierarchy.

[0145] Bits 38 through 30 of the input address are the L1 index bits, which are used to index into the page table hierarchy accessed during the L1 lookup (the sequential second intermediate lookup of the predetermined number of looks). The L1 lookup is performed in the page table hierarchy with the base address obtained during the L0 lookup (the L1 base address). The lookup performed based on the L1 base address and the L1 index bits returns the base address to be used for the next lookup in sequence (the L2 lookup) and size information indicating that the L2 lookup is a lookup in the regular page table hierarchy.

[0146] Bits 29 down to bit 21 of the input address are the L2 index bits, which are used to index into the page table hierarchy accessed during the L2 lookup (the sequential third intermediate lookup of the predetermined number of looks). The L2 lookup is performed in the page table hierarchy with the base address obtained during the L1 lookup (the L2 base address). The lookup performed based on the L2 base address and the L2 index bits returns the base address to be used for the next lookup in sequence (the L3 lookup) and size information indicating that the L3 lookup is a lookup in the regular page table hierarchy.

[0147] Bits 20 down to bit 12 of the input address are the L3 index bits, which are used to index into the page table hierarchy accessed during the L3 lookup (the final lookup of a predetermined number of looks). The L3 lookup is performed in the page table hierarchy with the base address (L3 base address) obtained during the L2 lookup. The lookup performed based on the L3 base address and the L3 index bits returns an address that is combined with the addressing portion of the input address (bits 11 down to bit 0) to obtain the output address.

[0148] Figure 7 Schematically shows the details of how an input address can be converted into an output address when the L1 table and the L2 table have been merged. Figure 6 As shown in , the address translation circuit 540 receives an input address. The input address is a 48-bit input address that includes a sequence of index portions (bit 47 down to bit 39; bit 38 down to bit 21; and bit 20 down to bit 12). Each index portion of the sequence of index portions corresponds to (is used for) a corresponding search level. However, the input address in this example is considered to include only three index portions. The second index portion (bit 38 down to bit 21) corresponds to a combination of using two sequential index portions (i.e., bit 38 down to bit 30 and bit 29 down to bit 21—more generally, if a conventional (unmerged) page table using N-bit indexing includes 2 N entries, and the large (merged) page table contains 2 N*M entries, then the index for the large lookup includes the M sequential N-bit index portions of the input address) indexed by the large lookup (of the large / merged page table). In order for the address translation circuit to correctly interpret the index portion of the input address, the corresponding page table level stores size information indicating when the next page table level is the large page table level. Figure 7 In the example of , size information is indicated in the L0 page table entry identified in the first lookup to indicate that the L1 table and the L2 table have been merged.

[0149] As in Figure 6 In the example shown in , bits 47 down to bit 39 of the input address are L0 index bits, which are used to index into the page table hierarchy accessed during the L0 lookup (the sequential first intermediate lookup in a predetermined number of looks). The L0 lookup is performed in the page table hierarchy with a table address (L0 base address) stored in a storage circuit (e.g., a base address register) of the address translation circuit. The storage circuit further includes size information indicating that the L0 lookup is a lookup in a conventional page table hierarchy. The lookup performed based on the L0 base address and the L0 index bits returns a base address to be used for the sequential next lookup (the merged L1 / L2 lookup) and size information indicating that the L1 / L2 lookup is a lookup in a large page table hierarchy.

[0150] and Figure 6 Unlike the example shown in , bits 38 down to bit 21 of the input address are L1 / L2 index bits, which are used to index into the L1 / L2 lookup (as a single lookup in a large page table and equivalent to Figure 6 The L1 / L2 lookup is performed in the large (merged) page table hierarchy with the base address obtained during the L0 lookup (the L1 / L2 base address). The lookup performed based on the L1 / L2 base address and the L1 / L2 index bits returns the base address to be used for the next lookup in sequence (the L3 lookup) and size information indicating that the L3 lookup is a lookup in the regular page table hierarchy.

[0151] As in Figure 6 In the example of , bits 20 down to bit 12 of the input address are L3 index bits used to index into the page table hierarchy accessed during an L3 lookup (a final lookup in a predetermined number of lookups). The L3 lookup is performed in the page table hierarchy with a base address (L3 base address) obtained during an L1 / L2 lookup. The lookup performed based on the L3 base address and the L3 index bits returns an address that is combined with the addressed portion of the first address (bits 11 down to bit 0) to obtain a second address.

[0152] In the illustrated configuration, L1 and L2 lookups are combined to form a single lookup in a large page table. It will be apparent to a skilled person that any sequential page table level lookups can be combined based on the techniques disclosed herein. In addition, the illustrated configuration shows the use of 9 bits for each of the N bit portions. However, in alternative configurations, different numbers of bits may be provided, and different lookup levels may be provided, each using a different number of bits.

[0153] As mentioned above, the present technology can also be implemented in a system that adopts two-stage address translation. For example, two-stage address translation can be implemented for memory accesses performed when the processing circuit is in a certain subset of execution states. Therefore, two sets of tables are used to convert virtual addresses from those execution states. These tables support virtualization and allow the hypervisor to virtualize the view of the physical memory seen by a given virtual machine (VM) (corresponding to the virtual machine of the client operating system and the application controlled by the client operating system). We refer to the conversion set controlled by the OS as stage 1 (S1). The stage 1 table converts the virtual address into an intermediate physical address (IPA-an example of the intermediate address mentioned earlier). In stage 1, the operating system behaves as if IPA is a physical address space. However, the hypervisor controls a second conversion set, which is referred to as stage 2 (S2). The second conversion set converts IPA into a physical address.

[0154] The stage 1 and stage 2 conversion tables are implemented as a hierarchical table structure that includes Figures 3 to 7 1 and 2 for a single translation stage (e.g., one of stage 1 and stage 2). In this example, both the stage 1 table and the stage 2 table may have four page table levels, namely level 0 (L0), level 1 (L1), level 2 (L2), and level 3 (L3). Although Figure 8 No table merges are shown for either stage 1 or stage 2, but they can be Figure 7 as shown in the examples are supported.

[0155] like Figure 8 As shown in , in practice, when performing a full translation table walk including both stage 1 and stage 2 translations, each stage 1 table base address obtained from the TTBR (Translation Table Base Register) and the table descriptors accessed in the stage 1 L0, L1, L2 translation tables will be intermediate addresses that themselves need to be translated using the stage 2 translation tables. Therefore, in the case where the translation table walk does not encounter any block descriptors, but proceeds all the way to L3 where a page descriptor is found, then in the absence of any table merging being applied, the full page table walk process may include accessing multiple page table hierarchies in the following sequence:

[0156] Stage 2 translation of the base address of the stage 1L0 page table to a physical address (the stage 1L0 base address is usually an intermediate physical address, since the stage 1 translation is configured by the operating system). The stage 2 translation consists of 4 lookups (stage 2L0; stage 2L1; stage 2L2; stage 2

[0157] L3).

[0158] Stage 1 L0 lookup of the entry at the address obtained based on the L0 index portion "a" of the target virtual address and the translated stage 1 L0 base address to obtain the stage 1 L1 base address (intermediate physical address)

[0159] - Stage 2 translation to make the stage 1 L1 base address a physical address (also includes 4 lookups).

[0160] Stage 1 L1 lookup of the entry at the address obtained based on the L1 index portion "b" of the target virtual address and the translated stage 1 L1 base address to obtain the stage 1 L2 base address (intermediate physical address)

[0161] Stage 2 translation to make the stage 1 L2 base address a physical address (also involves 4 lookups)

[0162] Stage 1 L2 lookup of the entry at the address obtained based on the L2 index portion "c" of the target virtual address and the translated stage 1 L2 base address to obtain the stage 1 L3 base address (intermediate physical address)

[0163] - Stage 2 translation to make the stage 1 L3 base address a physical address (also includes 4 lookups).

[0164] - A stage 1 L3 lookup of an entry at an address obtained based on the L3 index portion "d" of the target virtual address and the translated stage 1 L3 base address to identify a target intermediate physical address corresponding to the target virtual address.

[0165] - Stage 2 translation that makes the target intermediate physical address into the target physical address, which represents the location in memory to be accessed that corresponds to the original target virtual address (again involving 4 lookups).

[0166] Therefore, without any cache, and assuming that the starting level of stage 2 is L0, the translation will include a total of 24 lookups. If the starting level of stage 2 is L1, this can reduce the number of lookups to 19 (one less for each of the 5 stage 2 translations performed). However, as can be seen from the above sequence, performing the entire page table traversal process can be very slow, because for each stage in the stage of address translation, it may require a large number of accesses to the memory to step through each of the levels of the page table. This is why it is generally desirable to cache information derived from the translation table traversal in the address translation cache 114. The cached information can include full address translation data, which can be the final stage 1 address mapping from VA to IPA, the final stage 2 mapping from IPA to PA, or a combined stage 1 and stage 2 mapping from VA directly to PA (derived from previous lookups of the stage 1 and stage 2 structures). Alternatively (or in addition, if address translation cache 114 stores partial address translation data as well as full address translation data), the cached information may include partial address translation data that may be based on entries from higher level page tables from the stage 1 table and the stage 2 table. This may allow at least some steps of the full page table traversal to be bypassed even if the last level address mapping for a given target address is not currently in the address translation cache.

[0167] In the same manner that full address translation data may indicate a translation from VA to IPA, from IPA to PA, or from VA to PA, partial address translation data may also indicate a mapping from VA or IPA to IPA or PA. For example, the address translation cache may store partial address translation data that maps an input VA to a corresponding L2 base address, which may be expressed as an IPA 800 returned by the S1 L1 table or a PA 802 returned by the S2 L3 table after a lookup of the IPA returned by the S1 L1 table. Alternatively, the partial address translation data stored in the address translation cache may map an IPA to a PA, such as indicating, for a given IPA, the PA of the S2 L2 table corresponding to the IPA.

[0168] The address translation cache may cache both stage 1 address translation data and stage 2 address translation data (e.g., for converting VA to PA without expressing an intermediate IPA), or separate address translation caches may be provided for stage 1 translation and stage 2 translation. Thus, the output address identified by the full address translation data may be a physical address obtained from the stage 2 translation table, or an intermediate address obtained from the stage 1 address translation table. Similarly, each cache entry may be associated with all or part of an input address, which may be a virtual address or an intermediate physical address.

[0169] Fig. 9 is a flow chart illustrating an example of a method performed by the cache control circuit 551 in response to a PATI request.

[0170] The method includes a step 900 of determining whether a PATI request has been issued. When it is determined that a PATI request has been issued, the cache control circuit performs 902 an invalidation search in the address translation cache to identify the target cache entry. For example, the invalidation search can be based on a comparison of the index / tag associated with the cache entry with the information specified by the PATI request (such as the target address), or can be based on traversing the entire cache to check each entry to determine whether it is a hit. For situations where the PATI request is invalidated by an output address, a table level, or other parameters other than the input address, a traversal method can be useful (although it should be understood that this traversal method can also be used when the PATI request specifies the target input address information). For example, the invalidation search can depend on the information specified by the PATI address to determine whether a hit for a specific entry is detected. For example, the PATI address can specify one or more of the following:

[0171] an input address or input address range (e.g., this may be a virtual address (VA) or a VA range in a virtual address space or an intermediate physical address (IPA) or an IPA range in an intermediate physical address space), in which case a hit will not be detected unless the input address information associated with a given entry matches the input address information specified by the PATI request;

[0172] an output address or output address range in an output address space (e.g., this may be a physical address (PA) or PA range in a physical address space or an intermediate physical address (IPA) or IPA range in an intermediate physical address space), in which case a hit will not be detected unless the output address information associated with a given entry matches the output address information specified by the PATI request;

[0173] • Additional addresses or additional address ranges in additional address spaces translated from the output address space (eg, the PA may invalidate a PATI request when invalidating a stage 1 partial translation that provides table addresses for translating VA to IPA).

[0174] a table level indicator identifying one or more levels of a multi-level page table structure, in which case a hit will not be detected unless a given entry holds partial address translation data corresponding to the one or more levels identified as specified by the table level indicator in the PATI request; and

[0175] · A context identifier (e.g., based on one or more of a virtual machine identifier (VMID), an address space identifier (ASID), or a security state identifier), in which case a hit will not be detected unless the context identifier associated with a given entry in the cache matches the context identifier specified by the PATI request.

[0176] In addition, in some examples, the PATI request may be a global PATI request that triggers the invalidation of all partial address translation data in the address translation cache. In this case, a hit may be detected for any entry storing partial address translation data.

[0177] If 904 the lookup does not hit in the address translation cache (e.g., a no hit is detected), then the process ends and the control circuitry signals 906 completion (e.g., to the processing circuitry). On the other hand, if 904 at least one hit is detected (e.g., if a hit for N entries is detected), then the following set of steps are performed for each hit entry (after initializing 908 the index "i" to 0):

[0178] Determining 910 whether the i-th hit entry stores partial address translation data that is currently indicated as valid (eg, as opposed to storing full address translation data);

[0179] If yes, invalidate 912 the i-th hit entry, otherwise skip step 912 for the i-th hit entry (eg, do not invalidate it);

[0180] Determine 914 whether there is still at least one remaining entry to be processed (e.g., if i <N-1);

[0181] If yes, the process ends and completion is signaled 906 ; otherwise, the value of i is increased ( 916 ) by 1 (eg, i++ may also be written as i+=1 or i=i+1), and the process repeats from step 910 .

[0182] Steps 902 to 916 collectively constitute the PATI process 918 .

[0183] Thus, with this approach, the cache control circuitry responds to a PATI request by invalidating partial address translation data in any hit entry without invalidating the full address translation data, even if the full address translation data satisfies the filtering conditions specified by the PATI request (e.g., based on input / output addresses and / or context identifiers).

[0184] Fig.101000 is a flow chart illustrating a pre-fetch operation 1000 performed by cache control circuitry in response to a PATI request. This process may be performed in parallel with the PATI process 918 or after the PATI process is performed.

[0185] As in the PATI process, the cache control circuitry responds to the PATI request by performing a partial address translation invalidation (PATI) process 918 and, if the entry has been invalidated during the PATI process, pre-fetching 1002 the updated partial address translation data. Once the pre-fetch operation has been completed, the cache control circuitry signals 1004 completion.

[0186] Thus, the latest partial address translation data may be brought into the address translation cache without evicting any valid entries of the cache holding address translation data for other address translation mappings.

[0187] Fig.11 An example of a method performed by a processing circuit in response to receiving a decoded PATI instruction is shown. The method involves determining 1100 whether a PATI instruction has been decoded, and when it is determined that a PATI instruction has been decoded, triggering 1101 a partial address translation invalidation (PATI) process 918 to be executed in the MMU of the processing element itself, and also issuing 1102 a PATI command to the cache control circuit. A PATI command—an example of a PATI request—can be issued by writing the command to a command queue in a memory (e.g., a memory area accessible to the cache control circuit) or by issuing the command on a memory system interconnect 130.

[0188] Fig.12 1204. The cache control circuitry may monitor 1200 updates to the command queue to determine 1202 when a PATI command has been written to the command queue. When it is determined that a PATI command has been written to the command queue, the cache control circuitry performs a PATI process 918 and removes 1204 the PATI command from the command queue.

[0189] Fig.13A usable simulator is shown. Although the previously described embodiments implement the present invention in terms of the apparatus and method for operating the specific processing hardware supporting the technology involved, an instruction execution environment according to the embodiments described herein can also be provided, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, to a certain extent because such computer programs provide a software-based implementation of the hardware architecture. The types of simulator computer programs include emulators, virtual machines, models, and binary converters, which include dynamic binary converters. Typically, the simulator is specifically implemented and can be run on a host processor 1330 that supports the simulator program 1310, optionally running a host operating system 1320. In some arrangements, multiple simulation layers may exist between the hardware and the provided instruction execution environment and / or a plurality of different instruction execution environments provided on the same host processor. Historically, a powerful processor is required to provide a simulator that is executed at a reasonable speed, but this approach may be reasonable in certain circumstances, such as when it is desired to run another processor local code for compatibility or reuse reasons. For example, the simulator is specifically implemented to provide additional functionality that is not supported by the host processor hardware to the instruction execution environment, or to provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0190] Insofar as the embodiments have been described with reference to specific hardware structures or features, in the embodiments of simulation, equivalent functions may be provided by suitable software structures or features. For example, a specific circuit may be implemented as a computer program logic in the embodiments of simulation. For example, this may include a handler logic 1312 of a simulation processing circuit 108, an address translation program logic 1314 of a simulation address translation circuit 112, 540, and a table access program logic 1318 of a simulation page table traversal circuit. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the embodiments of simulation, and register simulation logic 1313 may be provided to control the simulation of registers. For example, address translation caches 114, 124, 550 may be implemented as software data structures. One or more of the hardware elements cited in the embodiments described previously are present in an arrangement on host hardware (e.g., host processor 1330), and some simulation embodiments may utilize host hardware where appropriate.

[0191] The simulator program 1310 may be stored on a computer-readable storage medium (which may be a transient or non-transitory medium) and provides a program interface (an instruction execution environment) to the target code 1300 (which may include an application, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture modeled by the simulator program 1310. Thus, the program instructions of the target code 1300 (which, in some embodiments, may include the PATI instructions described above) may be executed from within the instruction execution environment using the simulator program 1310, so that a host computer 1330 that does not actually have the hardware features of the device 1022 described above may emulate these features.

[0192] For example, a software maintained address translation cache may be provided to cache translation information in conjunction with performing a full page table walk (e.g., Figure 8 ), which gives faster access to partial / full conversions than the address conversion program logic 1314. The software-maintained cache is a data structure maintained by the address conversion program logic 1314 in the host memory through the simulator program to simulate the TLB to be provided in the hardware implementation scheme, so as to provide a reduced waiting time for address conversion by storing a subset of the address conversion data represented by the multi-level page table structure and by being a flat table. Then, according to an example of the present technology, when a PATI request (which can be in the form of a PATI instruction, or can be indirectly requested, for example, by requesting that a PATI command be written to a command queue), the cache control program logic (which can be considered as a part of the address conversion program logic 1314) invalidates the partial conversions from the software-maintained cache structure.

[0193] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0194] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device, comprising: An address translation cache comprising a plurality of cache entries, each cache entry being used to store address translation data depending on one or more page table entries of a multi-level page table structure in a memory, wherein each page table entry of the multi-level page table structure can be used as at least one of the following: A branch page table entry, wherein the branch page table entry specifies a table address of a next-level page table; and a leaf page table entry that specifies an output address of an address translation map for a corresponding region of the address space; and A cache control circuit, the cache control circuit being responsive to the partial address translation invalidation request to: performing an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicating an address of the next-level page table specified by the table address of the target page table entry when the target page table entry is used as the branch page table entry; as well as When the given cache entry is identified as the target cache entry, triggering invalidation of the given cache entry, The partial address translation invalidation request indicates that the given cache entry is allowed to be retained when the given cache entry provides full address translation data, and the full address translation data indicates the address of the corresponding area of ​​the address space corresponding to the output address specified by the target page table entry when the target page table entry is used as the leaf page table entry.

2. The device according to claim 1, wherein The partial address invalidation request specifies a table level identifier that indicates a subset of page table levels of the multi-level page table structure, and the target page table entry includes a page table entry at one of the subsets of page table levels specified by the table level identifier.

3. A device according to any preceding claim, comprising A processing circuit is provided to issue the partial address translation invalidation request in response to a partial address translation invalidation instruction.

4. A device according to any preceding claim, wherein The partial address translation invalidation request includes a write request requesting to write a partial address translation invalidation command to a memory area accessible to the cache control circuit.

5. A device according to any preceding claim, wherein The cache control circuitry is configured to detect a partial address translation invalidate command issued on a memory system interconnect, wherein the partial address translation invalidate request includes the partial address translation invalidate command.

6. A device according to any preceding claim, comprising page table traversal circuitry responsive to an input address for locating a given page table entry in the multi-level page table structure based on a given table address and an index portion of the input address, The page table traversal circuitry is configured to determine a size of the index portion to be used for at least one level of the multi-level page table structure depending on whether a table merge indication is set.

7. A device according to any preceding claim, wherein The partial address translation invalidation request specifies target address information corresponding to the target page table entry.

8. The device according to claim 7, wherein The cache control circuitry performs a pre-fetch operation to pre-fetch updated partial address translation data corresponding to the target address information in response to the partial address translation invalidation request.

9. The device according to claim 8, wherein The cache control circuitry is configured to limit the prefetch operation to prefetching updated partial address translation data for addresses corresponding to invalidated cache entries that were invalidated in response to the partial address invalidation request.

10. The device according to any one of claims 7 to 9, wherein: The address translation mapping is between an input address in an input address space and an output address in an output address space; and The target address information includes input address information.

11. The device according to any one of claims 7 to 9, wherein: The address translation mapping is between an input address in an input address space and an output address in an output address space; The target address information includes an address in the output address space or in another address space converted from the output address space.

12. The device according to any one of claims 7 to 11, wherein The target address information includes a target address range that can span multiple pages.

13. An apparatus according to any preceding claim, wherein: The partial address translation invalidation request specifies a context identifier; and the cache control circuitry is configured to identify the target cache entry dependent upon the context identifier.

14. The apparatus of claim 13, wherein the context identifier indicates at least one of: Virtual machine identifier; The address space identifier; and Security status.

15. An apparatus according to any preceding claim, wherein the partial address translation data indicates one of: The address of the next level page table; and Another address translated from the address of the next level page table.

16. An apparatus according to any preceding claim, wherein the full address translation data indicates one of: the output address; and A further address translated from the output address.

17. A method comprising: storing, in each of a plurality of cache entries of an address translation cache, address translation data dependent on one or more page table entries of a multi-level page table structure in a memory, wherein each page table entry of the multi-level page table structure is usable as one of: A branch page table entry, wherein the branch page table entry specifies a table address of a next-level page table; and a leaf page table entry that specifies an output address of an address translation map for a corresponding region of the address space; and In response to a partial address translation invalidation request: performing an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicating an address of the next-level page table specified by the table address of the target page table entry when the target page table entry is used as a branch page table entry; as well as When the given cache entry is identified as the target cache entry, triggering invalidation of the given cache entry, The partial address translation invalidation request indicates that the given cache entry is allowed to be retained when the given cache entry provides full address translation data, and the full address translation data indicates the address of the corresponding area of ​​the address space corresponding to the output address specified by the target page table entry when the target page table entry is used as the leaf page table entry.

18. A computer program comprising instructions which, when executed on a host data processing apparatus, control the host data processing apparatus to provide: The address translation program logic is configured to perform address translation based on a multi-level page table structure in a memory, the address translation logic being configured to maintain an address translation data structure comprising a plurality of data structure entries, each data structure entry being configured to store address translation data depending on one or more page table entries of the multi-level page table structure, wherein each page table entry of the multi-level page table structure is usable as at least one of the following: a branch page table entry, the branch page table entry specifying a table address of a next-level page table entry; and a leaf page table entry specifying an output address of an address translation map for a corresponding region of an address space; and A control program logic, the control program logic being responsive to the partial address translation invalidation request to: performing an invalidation lookup operation to identify whether a given data structure entry of the address translation data structure is a target data structure entry to be invalidated, wherein the target data structure entry comprises a data structure entry for which the address translation data comprises partial address translation data indicating an address of the next-level page table specified by the table address of the target page table entry when the target page table entry is used as the branch page table entry; as well as When the given data structure entry is identified as the target data structure entry, triggering invalidation of the given data structure entry, The partial address translation invalidation request indicates permission to retain the given data structure entry when the given data structure entry provides full address translation data, wherein the full address translation data indicates an address of the corresponding region of the address space corresponding to the output address specified by the target page table entry when the target page table entry is used as the leaf page table entry.

19. A computer-readable storage medium storing the computer program according to claim 18.

Images