Session-based recommendations using similarity maps

Abstract

A method for session-based recommendation may include generating a similarity graph comprising a plurality of nodes and one or more edges, each node corresponding to an individual session and an edge generated to connect two nodes in the similarity graph, wherein the similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and loading the similarity graph into a graph neural network (GNN) for session-based recommendation.

Description

Technical Field

[0001] The embodiments described herein generally relate to neural network technology, and more particularly to a method and apparatus for session-based recommendation (SBR) using similarity graphs. Background Art

[0002] In the overloaded information age and digital economy, recommender systems (RS) play an increasingly important role in informed consumption, services, and decision-making. In recent years, session-based recommender systems (SBRS) have emerged as a new RS paradigm. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following description and appended claims, and by referring to the following drawings, in which:

[0004] Figure 1 illustrates an example process for generating a similarity graph and training a graph neural network (GNN) for session-based recommendations according to some embodiments of the present disclosure;

[0005] Figure 2 illustrates an example representation of sessions in an example dataset for session-based recommendations according to some embodiments of the present disclosure;

[0006] Figure 3 illustrates an example process for utilizing a similarity graph in an existing or future session-based recommendation network according to some embodiments of the present disclosure;

[0007] Figure 4 illustrates a flow chart of an example process for session-based recommendations utilizing a similarity graph according to some embodiments of the present disclosure;

[0008] Figure 5 is a block diagram of an example processor platform that is configured to execute and / or instantiate machine-readable instructions and / or operations to implement example processes according to some embodiments of the present disclosure;

[0009] Figure 6 yes Figure 5 A block diagram of an example implementation of a processor circuit.

[0010] Figure 7 yes Figure 5 A block diagram of another example implementation of a processor circuit. DETAILED DESCRIPTION

[0011] The various aspects of the illustrative embodiments will be described using terms that are commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be appreciated by those skilled in the art that many alternative embodiments may also be implemented using some parts of the described aspects. For illustration, specific numbers, materials, and configurations are recorded to provide a thorough understanding of the illustrative embodiments. However, it will be clear to those skilled in the art that alternative embodiments may also be implemented without these specific details. In other cases, known features may be omitted or simplified to avoid blurring the illustrative embodiments.

[0012] In addition, various operations will be described as multiple discrete operations in turn in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be interpreted as meaning that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0013] In recent years, the emergence of SBRS has attracted increasing attention. Unlike traditional RS (e.g., content-based, collaborative filtering-based), SBRS learns user preferences from sessions associated and generated during the consumption process. Each session consists of multiple user-item interactions that occur together in a continuous time period, such as a basket of products purchased in a transaction visit, which usually lasts from a few minutes to a few hours. By taking each session as the basic input unit, SBRS is able to capture users' short-term preferences from their recent sessions, and is able to capture preference dynamics that reflect changes in users' preferences in different sessions, thereby providing more accurate and timely recommendations.

[0014] Currently, most solutions for session-based recommendations focus on capturing user preferences only from their own session sequences, with fewer attempts to leverage global context from other user sessions that may have similar preferences. The recently proposed Global Context Enhanced Graph Neural Network (GCE-GNN) incorporates global context by modeling paired item-transitions over all sessions, but fails to capture pairwise full-session (complete session sequence) similarities.

[0015] While consistent item-transitions across sessions can reveal item preferences or item similarities, they cannot capture the complete user session intent for the entire sequence. Take the fashion recommendation problem as an example to illustrate this: typical item-transitions will capture items that go well together, or similar items that a user might compare, but session-based similarity can capture the full session intent (e.g., the user is searching for a specific item category (i.e., pants or shoes)) or a full business outfit (e.g., suit, high heels, accessories, etc.).

[0016] In this disclosure, a novel solution for session-based recommendation is proposed to incorporate global context from all sessions, which relies on full session similarity instead of matched item-transitions. According to the proposed solution, the similarity between all pairs of sessions can be determined, and similar sessions can be utilized to generate more accurate next item predictions.

[0017] According to some embodiments of the present disclosure, a session-based recommendation scheme may include calculating pairwise session similarities and constructing a similarity graph to utilize similar sessions (eg, neighbor nodes in the similarity graph) to make next item recommendations.

[0018] Figure 1 An example process for generating a similarity graph and training a GNN for session-based recommendations according to some embodiments of the present disclosure is illustrated. The example process may include generating a representation for each session (step 1). For example, an individual session may be represented by an embedding list generated from a recommendation model pre-trained with the individual session. Figure 1 As shown, in the example process, you can The model SIHG4SR developed for RecSys Challenge 2022 is used as a pre-trained recommendation model for generating representations for individual sessions, but it can be understood that the representations for individual sessions can be generated by different models, which is not limited in this article.

[0019] The example process may then include generating a similarity graph (step 2). The graph consists of a set of nodes and a set of edges connecting pairs of nodes, the edges indicating relationships between the nodes. The nodes and edges may have associated features. According to some embodiments, the similarity graph may be defined to include multiple nodes and one or more edges. In the similarity graph, each node may correspond to an individual session, the features of each node may correspond to an embedding in the embedding list of the session generated in step 1, and when the similarity score of a pair of sessions corresponding to two nodes exceeds a preset similarity threshold, an edge may be generated to connect the two nodes.

[0020] In some embodiments, for each node, a multi-hot encoded session fingerprint can be generated that encodes the presence of item categories and values ​​associated with individual sessions, and then the similarity score of any pair of sessions can be calculated based on the similarity score between a pair of session fingerprints of the pair of sessions.

[0021] Figure 2 FIG. 4 illustrates an example representation of a session in an example dataset for session-based recommendations according to some embodiments of the present disclosure. Figure 2 As shown, an individual session can be represented by a fixed-size multi-hot encoded session fingerprint that encodes the presence of item categories and values ​​associated with the individual session.

[0022] Taking the RecSys Challenge 2022 dataset as an example, the content data of an item can be represented by a "category:value" taxonomy. An item may have more than one category, and for the same category, an item may have more than one associated value. Intuitively, items of different types (e.g., shoes and pants) may not share any categories, while items of the same type (e.g., evening gowns and business dresses) may share most categories.

[0023] Specifically, this dataset includes 74 categories and a total of 904 unique category-value pairs. Thus, a 904-dimensional array of item fingerprints can be defined using multi-hot encoding. For each item, the item fingerprint can include logical "1" for all category-value pairs in the content data of the item. Then, in order to generate a session fingerprint for a session, which reflects all items explored within the session, the item fingerprints of all items in the session can be aggregated by performing a logical OR operation on the item fingerprints of all items in the session. As a result, the session fingerprint is also a 904-dimensional array, such as Figure 2 shown.

[0024] Here, it should be noted that in practice, the session fingerprint can be generated by aggregating the project fingerprints of all or part of the projects in the session, such as through a logical or operation or different functions. In other words, the user can modify the way of generating the session fingerprint according to the specific application scenario. For example, in some scenarios, some projects may not be considered when generating the session fingerprint, such as very frequent projects or projects outside the directory. The user can select an appropriate operation to aggregate all project fingerprints or a subset of project fingerprints in order to generate a session fingerprint.

[0025] Next, for each pair of sessions in the data set, a similarity score of the pair of sessions may be calculated based on a similarity score between a pair of session fingerprints of the pair of sessions. For example, the similarity score between the pair of session fingerprints may include a Jaccard similarity score, a cosine similarity score, an Euclidean similarity score, a Hamming similarity score, a Tanimoto similarity score, or any other potential similarity score between the pair of session fingerprints.

[0026] It is noted that in order to solve different recommendation problems, domain-specific session fingerprints can be defined for datasets corresponding to different recommendation problems. In other words, session fingerprints are not limited to the fixed-size multi-hot encoded session fingerprints of this paper. Accordingly, specific fingerprint constructions and corresponding similarity metric selections can be customized for specific recommendation problems. The specific definition of the item fingerprint for an item in a session should be changed depending on the recommendation dataset to represent the presence or absence of substructures or features of the item.

[0027] With the similarity scores of all pairs of sessions calculated, a similarity threshold can be set so that when the similarity score of a pair of sessions corresponding to two nodes in the similarity graph exceeds the similarity threshold, an edge is generated to connect the two nodes. For example, the similarity threshold can be set to 0.98 based on experience, so that when the similarity score of a pair of sessions exceeds 0.98, an edge can be generated in the similarity graph to connect the two nodes corresponding to the pair of sessions. In this case, the resulting similarity graph can be a graph with about 1 million nodes and an average node degree of 8.2.

[0028] Continue to refer Figure 1 , the example process may also include training a GNN to exploit the global context from the neighbor sessions (step 3). For the above fashion recommendation problem proposed in RecSys Challenge 2022, the GNN can be composed of a two-layer Graph Attention Network (GAT), followed by two linear and Relu activations and an output linear layer to match the dimensions of the output features to the dimensions of the input embedding. Once the similarity graph is generated, the similarity graph can be loaded into the GNN, which can be trained with one or more similar neighbor sessions for each session. For example, the training of the GNN can be implemented by fitting the similarity graph into a pytorch trainer using the Pytorch Geometric (PyG) neighbor loader.

[0029] As described above, individual sessions can be represented by an embedding list generated from a recommendation model pre-trained with individual sessions. Training the recommendation model with individual sessions can be referred to as first-stage training, while training the GNN loaded with a similarity graph can be referred to as second-stage training, which is implemented based on similar neighbor sessions. Second-stage training can help calibrate first-stage individual session predictions (e.g., from a pre-trained recommendation model SIHG4SR) with the global context provided by similar neighbor sessions.

[0030] In addition, according to some embodiments of the present disclosure, the method of using the similarity graph to calibrate the representation of each session can be adapted to other models. For example, the similarity graph can be used as a plug-in for any mature or future pipeline.

[0031] Figure 3 An example process for utilizing a similarity graph in an existing or future session-based recommendation network according to some embodiments of the present disclosure is illustrated. For example, the similarity graph can be inserted into the base model SIHG4SR of RecSys Challenge 2022. Figure 3 As shown, session embeddings (i.e., node features in a similarity graph) can be generated based on the SIHG4SR model involved to generate a similarity graph, which can then be used to calibrate session representations for the SIHG4SR model. During training, the learning parameters in the SIHG4SR model can be fixed, and the graph similarity network can be trained with only similar neighbor sessions to obtain updated session embeddings, thereby enhancing the session representation of the SIHG4SR model. The enhanced session representation can then be applied to the SIHG4SR prediction network to obtain the final prediction.

[0032] It is noted that although the session-based recommendation scheme is described above for RecSysChallenge 2022 for fashion recommendation in some embodiments of the present disclosure, the scheme can be adapted to solve other recommendation problems for which domain-specific session fingerprints can be defined.

[0033] In order to better understand the overall idea of ​​the session-based recommendation solution proposed in this disclosure, reference will be made to Figure 4 The illustrated flowchart further describes an example process for session-based recommendations utilizing a similarity graph.

[0034] Figure 4 A flow chart of an example process for session-based recommendation utilizing a similarity graph according to some embodiments of the present disclosure is illustrated. The process may be implemented by a processor circuit and may include operations 410 and 420.

[0035] At operation 410, the processor circuit may generate a similarity graph including a plurality of nodes and one or more edges. In the similarity graph, each node may correspond to an individual session, and an edge may be generated to connect two nodes. A similarity score of a pair of sessions corresponding to two nodes in the similarity graph exceeds a preset similarity threshold.

[0036] At operation 420 , the processor circuit may load the similarity graph into a GNN for session-based recommendation.

[0037] According to some embodiments, individual conversations may be represented by a list of embeddings generated from a recommendation model pre-trained with the individual conversations.

[0038] According to some embodiments, the processor circuit may train the GNN with one or more similar neighbor sessions of an individual session.

[0039] According to some embodiments, the processor circuit may generate a similarity graph by: generating a multi-hot encoded session fingerprint for each node, the session fingerprint encoding the presence of item categories and values ​​associated with an individual session; and calculating a similarity score for a pair of sessions based on a similarity score between a pair of session fingerprints for the pair of sessions.

[0040] According to some embodiments, the similarity score between the pair of session fingerprints may include a Jaccard similarity score, a cosine similarity score, a Euclidean similarity score, a Hamming similarity score, a Tanimoto similarity score, or any other potential similarity score between the pair of session fingerprints.

[0041] According to some embodiments, the multi-hot encoded session fingerprint may be of fixed size.

[0042] According to some embodiments, a multi-hot encoded session fingerprint may be generated by aggregating the item fingerprints of all items or a portion of items in an individual session.

[0043] According to some embodiments, for each item in an individual session, an item fingerprint of the item may be defined relying on a recommendation dataset for session-based recommendation to indicate the presence or absence of a substructure or feature of the item.

[0044] According to some embodiments, the processor circuit may also load the similarity map into the session-based recommendation network to calibrate session representations in the session-based recommendation network based on the similarity map.

[0045] Figure 55 is a block diagram of an example processor platform 500 that is configured to execute and / or instantiate machine-readable instructions and / or operations to implement example processes according to some embodiments of the present disclosure. The processor platform 500 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smart phone, an iPad, etc.). TM ), an Internet appliance, a DVD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, headphones (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

[0046] The processor platform 500 of the illustrated example includes a processor circuit 512. The processor circuit 512 of the illustrated example is hardware. For example, the processor circuit 512 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processor circuit 512 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices.

[0047] The processor circuit 512 of the illustrated example includes a local memory 513 (e.g., cache, registers, etc.). The processor circuit 512 of the illustrated example communicates with a main memory including a volatile memory 514 and a non-volatile memory 516 via a bus 518. The volatile memory 514 may be a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory (DRAM) Dynamic Random AccessMemory, ) and / or any other type of RAM device. The non-volatile memory 516 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 514, 516 of the illustrated example is controlled by a memory controller 517.

[0048] The processor platform 500 of the illustrated example further includes an interface circuit 520. The interface circuit 520 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, near field communication (NFC) interface, PCI interface and / or PCIe interface.

[0049] In the illustrated example, one or more input devices 522 are connected to the interface circuit 520. The input device(s) 522 allow a user to enter data and / or commands into the processor circuit 512. The input device(s) 522 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0050] One or more output devices 524 are also connected to the interface circuit 520 of the illustrated example. The output device 524 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuit 520 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit, such as a GPU.

[0051] The interface circuitry 520 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate data exchange with external machines (e.g., any kind of computing device) over the network 526. Communications may be made through, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, direct-line wireless systems, cellular telephone systems, optical connections, and the like.

[0052] The processor platform 500 of the illustrated example also includes one or more mass storage devices 528 to store software and / or data. Examples of such mass storage devices 528 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid-state storage devices (such as flash memory devices), and DVD drives.

[0053] The machine-executable instructions 532 may be stored in the mass storage device 528, in the volatile memory 514, in the non-volatile memory 516, and / or on a removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0054] Figure 6 yes Figure 5 5. In this example, Figure 5 The processor circuit 512 is implemented by the microprocessor 600. For example, the microprocessor 600 can implement a multi-core hardware circuit, such as a CPU, a DSP, a GPU, an XPU, and the like. Although it may include any number of example cores 602 (e.g., 1 core), the microprocessor 600 of this example is a multi-core semiconductor device including N cores. The cores 602 of the microprocessor 600 can operate independently, or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 602, or may be executed by multiple cores in the core 602 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores in the core 602. The software program may correspond to part or all of the machine-readable instructions and / or operations discussed herein.

[0055] The core 602 can communicate via an example bus 604. In some examples, the bus 604 can implement a communication bus to implement communications associated with one (or more) of the cores 602. For example, the bus 604 can implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the bus 604 can implement any other type of computing or electrical bus. The core 602 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit 606. The core 602 can output data, instructions, and / or signals to one or more external devices via the interface circuit 606. Although the core 602 of this example includes an example local memory 620 (e.g., a level 1 (L1) cache that can be divided into an L1 data cache and an L1 instruction cache), the microprocessor 600 also includes an example shared memory 610 (e.g., a level 2 (L2 cache)) that can be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred (eg, shared) by writing to and / or reading from the shared memory 610. The local memory 620 of each core 602 and the shared memory 610 may be a plurality of levels of cache memory and main memory (eg, Figure 6 Cache memory is part of a hierarchy of storage devices (main memory 614, 616). Typically, higher level memories in the hierarchy exhibit lower access times and have smaller storage capacities than lower level memories. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by cache coherence policies.

[0056] Each core 602 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit. Each core 602 includes a control unit circuit 614, an arithmetic and logic (AL) circuit (sometimes referred to as an ALU) 616, a plurality of registers 618, an L1 cache 620, and an example bus 622. Other structures may also exist. For example, each core 602 may include a vector unit circuit, a single instruction multiple data (SIMD) unit circuit, a load / store unit (LSU) circuit, a branch / jump unit circuit, a floating-point unit (FPU) circuit, and the like. The control unit circuit 614 includes a semiconductor-based circuit that is configured to control (e.g., coordinate) data movement within the corresponding core 602. The AL circuit 616 includes a semiconductor-based circuit that is configured to perform one or more mathematical and / or logical operations on data within the corresponding core 602. Some examples of the AL circuit 616 perform integer-based operations. In other examples, the AL circuit 616 also performs floating-point operations. In other examples, the AL circuit 616 may include a first AL circuit that performs integer-based operations and a second AL circuit that performs floating-point operations. In some examples, the AL circuit 616 may be referred to as an Arithmetic Logic Unit (ALU). The register 618 is a semiconductor-based structure used to store data and / or instructions, such as the results of one or more operations performed by the AL circuit 616 of the corresponding core 602. For example, the register 618 may include (one or more) vector registers, (one or more) SIMD registers, (one or more) general registers, (one or more) flag registers, (one or more) fragment registers, (one or more) machine-specific registers, (one or more) instruction pointer registers, (one or more) control registers, (one or more) debug registers, (one or more) memory management registers, (one or more) machine check registers, and the like. The register 618 may be as follows: Figure 6 The registers 618 are shown arranged as bank groups. Alternatively, the registers 618 may be organized in any other arrangement, format, or structure, including being distributed throughout the core 602 to reduce access time. The bus 620 may implement at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0057] Each core 602 and / or more generally the microprocessor 600 may include additional and / or alternative structures as shown and described above. For example, there may be one or more clock circuits, one or more power supply sources, one or more power gates, one or more cache home agents (CHA), one or more converged / common mesh stops (CMS), one or more shifters (e.g., (one or more) barrel shifters) and / or other circuits. The microprocessor 600 is a semiconductor device that is manufactured to include many interconnected transistors so as to implement the above structure in one or more integrated circuits (ICs) contained in one or more packages. The processor circuit may include one or more accelerators and / or cooperate with one or more accelerators. In some examples, the accelerator is implemented by a logic circuit to perform certain tasks faster and / or more efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU or other programmable device may also be an accelerator. The accelerator may be on the board of the processor circuit, in the same chip package as the processor circuit, and / or in one or more packages separate from the processor circuit.

[0058] Figure 7 yes Figure 5 5. In this example, the processor circuit 600 is implemented by an FPGA circuit 700. For example, the FPGA circuit 700 can be used to perform operations that would otherwise be performed by Figure 6 The example microprocessor 600 of the embodiment of the present invention executes the operations performed by the corresponding machine-readable instructions. However, once configured, the FPGA circuit 700 instantiates the machine-readable instructions with hardware, thereby often performing the operations faster than the execution speed of a general-purpose microprocessor executing the corresponding software.

[0059] More specifically, Figure 6 Compared to the microprocessor 600 of FIG. 1 (which is a general-purpose device that can be programmed to perform some or all of the operations disclosed herein, but whose interconnections and logic circuits are fixed once manufactured), Figure 7The example FPGA circuit 700 includes interconnections and logic circuits, which can be configured and / or interconnected in different ways after manufacturing to instantiate. Specifically, FPGA 700 can be considered as an array of logic gates, interconnections and switches. The switches can be programmed to change the way the logic gates are interconnected by the interconnections, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit 700 is reprogrammed). The configured logic circuit enables the logic gates to cooperate in different ways to perform different operations on the data received by the input circuit. These operations can correspond to part or all of the software represented by the operations discussed herein. Therefore, FPGA circuit 700 can be constructed to effectively instantiate part or all of the machine-readable instructions representing the operations discussed herein as dedicated logic circuits to perform operations corresponding to these software instructions in a dedicated manner similar to ASIC. Therefore, the speed at which FPGA circuit 700 performs operations corresponding to part or all of the operations discussed herein can be faster than the speed at which a general-purpose microprocessor performs these operations.

[0060] exist Figure 7 In the example of , FPGA circuit 700 is constructed to be programmed (and / or reprogrammed one or more times) by an end user via a hardware description language (HDL) (eg, Verilog). Figure 7 FPGA circuit 700 includes example input / output (I / O) circuit 702 to obtain and / or output data to example configuration circuit 704 and / or external hardware (e.g., external hardware circuit) 706. For example, configuration circuit 704 can implement interface circuitry that can obtain machine-readable instructions to configure FPGA circuit 700, or (one or more) portions thereof. In some such examples, configuration circuit 704 can obtain machine-readable instructions from a user, a machine (e.g., a hardware circuit (e.g., a programmed or dedicated circuit) that can implement an Artificial Intelligence / Machine Learning (AI / ML) model to generate instructions), etc. In some examples, external hardware 706 can implement Figure 6 The microprocessor 600 of FPGA circuit 700 also includes an array of example logic gate circuits 708, a plurality of example configurable interconnects 710, and example storage circuits 712. The logic gate circuits 708 and the interconnects 710 may be configured to instantiate one or more operations discussed herein and / or other desired operations. Figure 7The logic gate circuit 708 shown is manufactured in groups or blocks. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. There is an electrically controllable switch (e.g., a transistor) in each logic gate circuit 708 so that the electrical structure and / or the logic gate can be configured to form a circuit to perform the desired operation. The logic gate circuit 708 may include other electrical structures, such as a look-up table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, and the like.

[0061] The interconnect 710 of the illustrated example is a conductive path, trace, via, or the like, which may include an electrically controllable switch (e.g., a transistor) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuits 708 to program the desired logic circuit.

[0062] The storage circuit 712 of the illustrated example is configured to store (one or more) results of one or more operations performed by the corresponding logic gates. The storage circuit 712 can be implemented by registers or the like. In the illustrated example, the storage circuit 712 is distributed between the logic gate circuits 708 to facilitate access and improve execution speed.

[0063] Figure 7 The example FPGA circuit 700 also includes an example dedicated operation circuit 714. In this example, the dedicated operation circuit 714 includes a dedicated circuit 716, which can be called to implement common functions to avoid the need to program these functions on site. Examples of such dedicated circuits 716 include memory (e.g., DRAM) controller circuits, PCIe controller circuits, clock circuits, transceiver circuits, memories, and multiplier-accumulator circuits. Other types of dedicated circuits may also exist. In some examples, the FPGA circuit 700 may also include an example general-purpose programmable circuit 718, such as an example CPU 720 and / or an example DSP 722. Other general-purpose programmable circuits 718 may exist additionally or alternatively, such as GPUs, XPUs, etc., which can be programmed to perform other operations.

[0064] Although Figure 6 and Figure 7 Picture shows Figure 5 These are two example implementations of the processor circuit 512, but many other approaches are also contemplated. For example, as described above, modern FPGA circuits may include an onboard CPU, such as Figure 7 One or more example CPUs 720. Therefore, Figure 5The processor circuit 512 may additionally be combined with Figure 6 An example microprocessor 600 and Figure 7 In some such hybrid examples, the first portion of the machine-readable instructions may be implemented by Figure 6 The one or more cores 602 are executed, and the second portion of the machine-readable instructions may be executed by Figure 7 The FPGA circuit 700 executes.

[0065] In some examples, Figure 5 The processor circuit 512 may be in one or more packages. For example, Figure 6 The processor circuit 600 and / or Figure 7 The FPGA circuit 700 can be in one or more packages. In some examples, the XPU can be composed of Figure 5 The XPU may be implemented in a processor circuit 512 that may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in another package, and an FPGA in another package.

[0066] In various embodiments, the operations discussed herein may be implemented as hardware (e.g., logic circuits), software, firmware, or a combination thereof, which may be provided as a computer program product, for example, including one or more tangible (e.g., non-transitory) machine-readable or computer-readable media having stored thereon instructions (or software processes) for programming a computer to perform the processes discussed herein. The machine-readable medium may include a storage device.

[0067] In addition, such computer-readable media may be downloaded as a computer program product, where the program may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a bus, a modem, or a network connection) by a data signal provided in a carrier wave or other propagation medium.

[0068] Although the embodiments are described in language specific to structural features and / or methodological acts, it is to be understood that the claimed subject matter may not be limited to the specific features or acts described. Rather, these specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

[0069] Additional notes and examples:

[0070] Example 1 includes an apparatus for session-based recommendations, the apparatus comprising: an interface circuit; and a processor circuit coupled to the interface circuit and configured to: generate a similarity graph comprising a plurality of nodes and one or more edges, each node corresponding to an individual session and an edge generated to connect two nodes in the similarity graph, wherein a similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and provide the similarity graph to the interface circuit for loading into a graph neural network (GNN) for the session-based recommendations.

[0071] Example 2 includes an apparatus as described in Example 1, wherein the individual conversations are represented by an embedding list, and the embedding list is generated from a recommendation model pre-trained with the individual conversations.

[0072] Example 3 includes an apparatus as described in Example 1 or 2, wherein the processor circuit is further configured to train the GNN with one or more similar neighbor sessions of the individual session.

[0073] Example 4 includes an apparatus as described in any one of Examples 1 to 3, wherein the processor circuit is configured to generate the similarity graph by: for each node, generating a multi-hot encoded session fingerprint that encodes the presence of item categories and values ​​associated with the individual session; and calculating a similarity score for the pair of sessions based on the similarity scores between a pair of session fingerprints of the pair of sessions.

[0074] Example 5 includes the apparatus of Example 4, wherein the similarity score between the pair of session fingerprints comprises at least one of a Jaccard similarity score, a cosine similarity score, a Euclidean similarity score, a Hamming similarity score, or a Tanimoto similarity score between the pair of session fingerprints.

[0075] Example 6 includes the apparatus of Example 4, wherein the multi-hot encoded session fingerprint is fixed size.

[0076] Example 7 includes the apparatus of Example 4, wherein the multi-hot encoded session fingerprint is generated by aggregating item fingerprints of all or a portion of the items in the individual sessions.

[0077] Example 8 includes an apparatus as described in Example 7, wherein, for each item in the individual session, an item fingerprint of the item is defined relying on a recommendation dataset used for the session-based recommendation to indicate the presence or absence of a substructure or feature of the item.

[0078] Example 9 includes an apparatus as described in any one of Examples 1 to 8, wherein the processor circuit is further configured to provide the similarity map to the interface circuit to be loaded into the session-based recommendation network to calibrate the session representation in the session-based recommendation network based on the similarity map.

[0079] Example 10 includes a method for session-based recommendations, the method comprising: generating a similarity graph comprising a plurality of nodes and one or more edges, each node corresponding to an individual session and an edge generated to connect two nodes in the similarity graph, wherein a similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and loading the similarity graph into a graph neural network (GNN) for the session-based recommendations.

[0080] Example 11 includes the method of Example 10, wherein the individual sessions are represented using a list of embeddings generated from a recommendation model pre-trained using the individual sessions.

[0081] Example 12 includes the method as described in Example 10 or 11, further comprising training the GNN with one or more similar neighbor sessions of the individual session.

[0082] Example 13 includes a method as described in any one of Examples 10 to 12, wherein generating the similarity graph includes: for each node, generating a multi-hot encoded session fingerprint that encodes the presence of item categories and values ​​associated with the individual session; and calculating a similarity score for the pair of sessions based on a similarity score between a pair of session fingerprints of the pair of sessions.

[0083] Example 14 includes the method of Example 13, wherein the similarity score between the pair of session fingerprints comprises at least one of a Jaccard similarity score, a cosine similarity score, a Euclidean similarity score, a Hamming similarity score, or a Tanimoto similarity score between the pair of session fingerprints.

[0084] Example 15 includes the method of Example 13, wherein the multi-hot encoded session fingerprint is a fixed size.

[0085] Example 16 includes the method of Example 13, wherein the multi-hot encoded session fingerprint is generated by aggregating item fingerprints of all items or a portion of items in the individual sessions.

[0086] Example 17 includes the method of Example 16, wherein, for each item in the individual session, an item fingerprint of the item is defined relying on a recommendation dataset used for the session-based recommendation to represent the presence or absence of a substructure or feature of the item.

[0087] Example 18 includes the method of any one of Examples 10 to 17, further comprising: loading the similarity graph into a session-based recommendation network to calibrate session representations in the session-based recommendation network based on the similarity graph.

[0088] Example 19 includes a computer-readable medium having instructions stored thereon, wherein the instructions, when executed by a processor circuit, cause the processor circuit to perform the method of any one of Examples 10 to 18.

[0089] Example 20 includes an apparatus comprising means for performing a method as described in any of Examples 10 to 18.

[0090] Various technologies or some aspects or parts thereof may take the form of program codes (i.e., instructions) embodied in tangible media, such as floppy disks, CD-ROMs, hard disk drives, non-transient computer-readable storage media, or any other machine-readable storage media, wherein when the program code is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for implementing various technologies. Non-transient computer-readable storage media may be computer-readable storage media that do not include signals. In the case of program code execution on a programmable computer, a computing system may include a processor, a storage medium (including volatile and non-volatile memory and / or storage elements) that can be read by the processor, at least one input device, and at least one output device. Volatile and non-volatile memory and / or storage elements may be RAM, EPROM, flash drives, optical drives, magnetic hard disk drives, solid-state drives, or other media for storing electronic data. One or more programs that may implement or utilize the various technologies described herein may use application programming interfaces (application programming interfaces, APIs), reusable controls, and the like. Such programs may be implemented in high-level procedural or object-oriented programming languages ​​to communicate with a computer system. However, if desired, the program(s) may be implemented in assembly or machine language. In any case, the language may be a compiled or interpreted language, and combined with a hardware implementation. Exemplary systems or devices may include, but are not limited to, laptop computers, tablet computers, desktop computers, smart phones, computer terminals and servers, storage databases, and other electronic devices utilizing circuits and programmable memory, such as household appliances, smart televisions, digital video disc (DVD) players, heating, ventilating, and air conditioning (HVAC) controllers, light switches, and the like.

[0091] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments that can be implemented. These embodiments are also referred to as "examples" in this article. Such examples may include additional elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) using any combination or arrangement of those elements shown or described, whether for a specific example (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein.

[0092] All publications, patents, and patent documents cited in this document are hereby incorporated by reference in their entirety, as if individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0093] In this document, the term "a" is used to include one or more than one, independent of any other instance or use of "at least one" or "one or more," as is common in patent documents. In this document, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "wherein" are used as the plain English equivalents of the respective terms "comprising" and "wherein." In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include other elements in addition to those listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0094] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by a person of ordinary skill in the art after viewing the above description. The abstract is intended to allow the reader to quickly determine the nature of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be interpreted as a desire to make the disclosed features that are not claimed necessary for any claim. More precisely, the subject matter of the invention may be present in less than all the features of a particular disclosed embodiment. Thus, the attached claims are incorporated herein into the "Specific Implementation" section, with each claim acting independently as a separate embodiment. The scope of the embodiment should be determined with reference to the attached claims and the full scope of equivalents to which such claims are entitled.

Claims

1. An apparatus for session-based recommendation, comprising: Interface circuit; and a processor circuit coupled to the interface circuit and configured to: generating a similarity graph including a plurality of nodes and one or more edges, each node corresponding to an individual session, and an edge being generated to connect two nodes in the similarity graph, wherein a similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and The similarity graph is provided to the interface circuit for loading into a graph neural network (GNN) for the session-based recommendation.

2. The device according to claim 1, wherein: The individual sessions are represented using a list of embeddings generated from a recommendation model pre-trained with the individual sessions.

3. The device according to claim 1, wherein: The processor circuit is also configured to train the GNN with one or more similar neighbor sessions of the individual session.

4. The apparatus according to any one of claims 1 to 3, wherein the processor circuit is configured to generate the similarity graph by: For each node, generating a multi-hot encoded session fingerprint that encodes the presence of item categories and values ​​associated with the individual session; and A similarity score for the pair of sessions is calculated based on a similarity score between a pair of session fingerprints for the pair of sessions.

5. The device according to claim 4, wherein: The similarity score between the pair of session fingerprints includes at least one of a Jaccard similarity score, a cosine similarity score, a Euclidean similarity score, a Hamming similarity score, or a Tanimoto similarity score between the pair of session fingerprints.

6. The device according to claim 4, wherein: The multi-hot encoded session fingerprint is of fixed size.

7. The device of claim 4, wherein: The multi-hot encoded session fingerprint is generated by aggregating the item fingerprints of all items or a portion of items in the individual session.

8. The device according to claim 7, wherein: For each item in the individual session, an item fingerprint of the item is defined relying on a recommendation dataset used for the session-based recommendation to indicate the presence or absence of a substructure or feature of the item.

9. The device of claim 1, wherein: The processor circuit is further configured to provide the similarity map to the interface circuit to be loaded into the session-based recommendation network to calibrate session representations in the session-based recommendation network based on the similarity map.

10. A method for session-based recommendation, comprising: generating a similarity graph including a plurality of nodes and one or more edges, each node corresponding to an individual session, and an edge being generated to connect two nodes in the similarity graph, wherein a similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and The similarity graph is loaded into a graph neural network (GNN) for the session-based recommendation.

11. The method of claim 10, wherein: The individual sessions are represented using a list of embeddings generated from a recommendation model pre-trained with the individual sessions.

12. The method of claim 10, further comprising training the GNN with one or more similar neighbor sessions of the individual session.

13. The method according to any one of claims 10 to 12, wherein: Generating the similarity graph includes: For each node, generating a multi-hot encoded session fingerprint that encodes the presence of item categories and values ​​associated with the individual session; and A similarity score for the pair of sessions is calculated based on a similarity score between a pair of session fingerprints for the pair of sessions.

14. The method of claim 13, wherein: The similarity score between the pair of session fingerprints includes at least one of a Jaccard similarity score, a cosine similarity score, a Euclidean similarity score, a Hamming similarity score, or a Tanimoto similarity score between the pair of session fingerprints.

15. The method of claim 13, wherein: The multi-hot encoded session fingerprint is of fixed size.

16. The method of claim 13, wherein: The multi-hot encoded session fingerprint is generated by aggregating the item fingerprints of all items or a portion of items in the individual session.

17. The method of claim 16, wherein: For each item in the individual session, an item fingerprint of the item is defined relying on a recommendation dataset used for the session-based recommendation to indicate the presence or absence of a substructure or feature of the item.

18. The method of claim 10, further comprising: The similarity map is loaded into a session-based recommendation network to calibrate session representations in the session-based recommendation network based on the similarity map.

19. A computer readable medium having instructions stored thereon, wherein: When the instructions are executed by a processor circuit, the processor circuit is caused to perform the method according to any one of claims 10 to 18.

20. An apparatus comprising means for performing the method of any one of claims 10 to 18.

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