Solid-state imaging device and imaging apparatus

Abstract

There is provided a light detection device including: a photoelectric conversion section that generates an electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator outputting a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit that counts the number of times the first signal is output by the comparator; and an amplification section that is connected to the first node and outputs a first analog signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Applications No. 2022-096866 and No. 2023-060904, filed on Jun. 15, 2022 and Apr. 4, 2023, respectively, which are hereby incorporated by reference herein in their entirety. Technical Field

[0002] The present disclosure relates to a solid-state imaging device and an imaging apparatus. Background Art

[0003] A method for extending the dynamic range of a solid-state imaging device is generally known, regardless of the accumulation capacitance for accumulating charges in the photoelectric conversion section. In this method for extending the dynamic range, the dynamic range is extended by counting the number of times the amount of charge obtained by photoelectric conversion exceeds a threshold value. However, charges that do not exceed the threshold value are not detected as signal charges, so the signal deteriorates as the illumination decreases. [Citation List] [Patent Document]

[0004] [Patent Document 1]: Japanese Patent Application Laid-Open JP 2021-114742A Summary of the invention [Technical issues to be solved]

[0005] Therefore, the present disclosure aims to provide a solid-state imaging device and an imaging apparatus which extend the dynamic range and are capable of converting a small amount of electric charge obtained by photoelectric conversion into an image signal. [Technical solution to the problem]

[0006] In order to solve the above problems, according to the present disclosure, a light detection device includes: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit configured to count the number of times the first signal is output by the comparator; and The amplifier is connected to the first node and outputs a first analog signal.

[0007] The light detection device may further include: an analog-to-digital conversion unit, which generates a digital signal based on the first analog signal; and A signal processing section generates an image signal based on: the number of times the first signal is output from the comparator; and the digital signal.

[0008] The light detection device may further include: A first transistor is connected between the first node and the photoelectric conversion unit.

[0009] After the amplifying unit outputs the first analog signal, the resetting unit may reset the first node. After the reset unit resets the first node, the amplifier unit may amplify the potential of the first node and output a second analog signal to the analog-to-digital converter unit, and The analog-to-digital conversion section may generate the digital signal based on the first analog signal and the second analog signal.

[0010] The amplification section may output the first analog signal after a sequence in which the first transistor is set to a conductive state and then set to a non-conductive state.

[0011] The light detection device may further include: a first charge holding portion connected to the photoelectric conversion portion via the first node; and A second charge holding portion is connected to the first node in parallel with the first charge holding portion.

[0012] The first charge holding portion may be connected to the first node via a second transistor, and The second transistor may be set to a conductive state during a first period, and may be set to a non-conductive state during a second period different from the first period.

[0013] The amplifier may output a third analog signal during the second period, and may output a fourth analog signal after the first transistor is set to an on state.

[0014] During the first period, the amplifier may output the first analog signal after the first transistor is set to an on state, and may output the second analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section may generate the digital signal based on the first analog signal, the second analog signal, the third analog signal, and the fourth analog signal.

[0015] The light detection device may further include: A third charge holding unit is connected to the first node via a third transistor.

[0016] The amplifier may output a fifth analog signal during a period in which the second transistor and the third transistor are set to an on state, and may output a sixth analog signal after the first transistor is set to an on state, and The analog-to-digital conversion section may generate the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

[0017] The amplifier may output a fifth analog signal while the second transistor and the third transistor are set to an on state, and may output a sixth analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section may generate the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

[0018] The reset unit may be composed of a fourth transistor connected between the first node and the power supply unit. A channel potential of the second transistor in a non-conducting state may be greater than a channel potential of the third transistor in a non-conducting state, and A channel potential of the fourth transistor in a non-conducting state may be greater than a channel potential of the second transistor in a non-conducting state.

[0019] The first accumulation capacitor may be formed of a metal-insulator-metal capacitor and connected to the first node.

[0020] The photoelectric conversion unit may be arranged in the first substrate, and The counting section may be arranged in a second substrate stacked with the first substrate.

[0021] The amplifying section may include a first amplifying transistor and a selecting transistor, The first amplifying transistor may be arranged in the first substrate, and The selection transistor may be disposed in the second substrate.

[0022] The comparator may include a second amplifying transistor and a current mirror, The second amplifying transistor may be arranged in the first substrate, and The current mirror may be arranged in the second substrate.

[0023] The photoelectric conversion unit may have a predetermined capacitance for accumulating charges, and The charge may overflow to the first node when exceeding the predetermined capacitance.

[0024] The reset unit may be formed of a fourth transistor connected between the first node and a power supply unit.

[0025] In order to solve the above problems, according to the present disclosure, a camera device is provided, comprising: The above-mentioned light detection device; and Optical system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 : is a block diagram showing a configuration example of the image pickup device 1 according to the first embodiment. Figure 2 : is a block diagram showing a configuration example of the solid-state imaging device 200 according to the first embodiment. Figure 3 is a diagram schematically showing the connection of a pixel circuit and a processing circuit. Figure 4 2 is a block diagram showing a configuration example of the pixel circuit 250 . Figure 5 2 is a diagram showing a circuit configuration example of the pixel circuit 250 . Figure 6 : is a block diagram showing a configuration example of the read circuit 260 according to the first embodiment of the present technology. Figure 7 is a sequence diagram of a processing example according to the first embodiment. Figure 8 is a timing chart of a processing example according to Modification 1 of the first embodiment. Fig. 9 It is a conceptual explanation Figure 8 Graph of the read potentials at the Vr level, Vs level, Vs level, and Vr level in . Fig.10 : is a block diagram showing a configuration example of a pixel circuit 250 according to the second embodiment. Fig.11 : is a diagram showing a circuit configuration example of a pixel circuit 250 according to the second embodiment. Fig.12 is a timing chart of an operation example according to the second embodiment. Fig.13 is a sequence diagram of a processing example according to a modification of the second embodiment. Fig.14 : is a block diagram showing a configuration example of a pixel circuit 250 according to the third embodiment. Fig.15: is a diagram showing a circuit configuration example of a pixel circuit 250 according to the third embodiment. Fig.16 is a timing chart of an operation example according to the third embodiment. Fig.17 : is a diagram showing a circuit configuration example of a pixel circuit 250 according to Modification 1 of the third embodiment. Fig.18 is a timing chart of an operation example according to Modification 1 of the third embodiment. Fig.19 : is a diagram showing a circuit configuration example of a pixel circuit 250 according to Modification 2 of the third embodiment. Fig. 20 : is a diagram showing a configuration example of a pixel circuit 250 according to Modification 3 of the first embodiment. Fig.21 is a diagram showing a configuration example of a first substrate and a second substrate. Fig. 22 It shows Fig.11 The illustrated pixel circuit 250 is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Fig.23 It shows Fig.15 The illustrated pixel circuit 250 is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Fig.24 It shows Fig.19 A diagram showing a configuration example of a pixel circuit 250 is shown. Fig.25 is a diagram showing a configuration example of a first substrate, a second substrate, and a third substrate. Fig.26 It shows Figure 4 The illustrated pixel circuit 250 is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Fig. 27 It shows Fig.10 The illustrated diagram is a configuration example in which the pixel circuit 250 is composed of three substrates. Fig.28 It shows Fig.14 The illustrated pixel circuit 250 is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Fig.29 It shows Fig.14 The illustrated pixel circuit 250 is a diagram of a configuration example in which the pixel circuit 250 is composed of three substrates. Fig.30 2 is a diagram schematically showing a part of the imaging device 200 . Fig.31 is a timing diagram of an operation example in calibration mode. Fig.32is a timing diagram of an operation example in calibration mode. Fig.33 is a block diagram showing a schematic configuration example of a vehicle control system. Fig.34 1 is an explanatory diagram showing an example of the layout positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0027] The embodiments of the solid-state imaging device and the imaging apparatus will be described below with reference to the accompanying drawings. Although the main components of the solid-state imaging device and the imaging apparatus will be mainly described below, the components and functions of the solid-state imaging device and the imaging apparatus may not be shown or described. The following description does not exclude the components and functions that are not shown or described.

[0028] [First embodiment] Figure 1 1 is a block diagram showing a configuration example of an image pickup device 1 according to a first embodiment of the present technology. The image pickup device 1 is a device for capturing image data, and includes an optical section 110, a solid-state image pickup device 200, and a DSP (Digital Signal Processing) circuit 120. The image pickup device 1 also includes a display section 130, an operation section 140, a bus 150, a frame memory 160, a storage section 170, and a power supply section 180. It is assumed that the image pickup device 1 is a camera installed in a smartphone, a car camera, or the like.

[0029] The optical section 110 collects light from the subject and guides the collected light to the solid-state imaging device 200. The solid-state imaging device 200 generates image data by photoelectric conversion. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209. For example, the optical section 110 is composed of a plurality of lenses and constitutes an optical system.

[0030] The DSP circuit 120 performs predetermined signal processing on the image data and outputs the processed image data to the frame memory 160 or the like via the bus 150 .

[0031] The display unit 130 displays image data. For example, a liquid crystal panel or an organic electroluminescence (EL: ElectroLuminescence) panel is assumed to be the display unit 130. The operation unit 140 generates an operation signal according to a user operation.

[0032] The bus 150 is a common path for the optical section 110 , the solid-state imaging device 200 , the DSP circuit 120 , the display section 130 , the operation section 140 , the frame memory 160 , the storage section 170 , and the power supply section 180 to exchange data with each other.

[0033] The frame memory 160 stores image data. The storage section 170 stores various types of data such as image data. The power supply section 180 supplies power to the solid-state imaging device 200 , the DSP circuit 120 , the display section 130 , and the like.

[0034] (Configuration Example of Solid-State Image Pickup Device) Figure 2 : is a block diagram showing a configuration example of the solid-state imaging device 200 according to the first embodiment. Figure 3 is a diagram schematically showing the connection between a pixel circuit and a processing circuit.

[0035] like Figure 2 and Figure 3 As shown, the solid-state imaging device 200 includes a vertical scanning circuit 210, a timing control unit 220, a digital to analog converter (DAC: Digital to Analog Converter) 230, a pixel array unit 240, a reading circuit 260, a horizontal scanning circuit 270, and a signal processing unit 280. In the pixel array unit 240, a plurality of pixel circuits 250 are arranged in a two-dimensional grid.

[0036] The vertical scanning circuit 210 sequentially selects and drives each row in the pixel array section 240. The timing control section 220 controls the operation timing of each of the vertical scanning circuit 210, the DAC 230, the reading circuit 260, and the horizontal scanning circuit 270 in synchronization with the vertical synchronization signal VSYNC.

[0037] The DAC 230 generates sawtooth-shaped ramp signals, and these ramp signals are supplied to the read circuit 260 as reference signals.

[0038] The pixel circuit 250 is a circuit that performs photoelectric conversion under the control of the vertical scanning circuit 210. The pixel circuit 250 counts the number of times the amount of charge obtained by the photoelectric conversion exceeds the threshold value, and outputs a digital signal including the counted number of times via the horizontal signal line Lsh to the signal processing section 280. In addition, the pixel 100 outputs an analog residual charge signal related to the residual charge as an analog signal to the reading circuit 260 via the vertical signal line Lsv.

[0039] ADC (Analog-to-Digital Converter) (See Figure 3 ) are arranged in the reading circuit 260 for each column of the pixel circuit 250. Each ADC converts the pixel signal of the corresponding column into a digital signal, which is output to the signal processing unit 280 under the control of the horizontal scanning circuit 270. The horizontal scanning circuit 270 controls the reading circuit 260 to output the digital signal in sequence. Note that in this embodiment, the reading circuit 260 can also be written as the readout circuit 260.

[0040] The signal processing section 280 generates image signals for the respective pixels 100 by using the counter values ​​from the pixels 100 in the pixel array section 240 and the residual signal values ​​of the pixels 100 supplied from the reading circuit 260. The signal processing section 280 outputs the image signal values ​​of the pixels 100 to the DSP circuit 120.

[0041] (Configuration Example of Pixel Circuit) Will refer to Figure 4 and Figure 5 A configuration example of the pixel circuit 250 according to the present embodiment will be described. Figure 4 2 is a block diagram showing a configuration example of the pixel circuit 250. The pixel circuit 250 includes a photoelectric conversion section 101, a first accumulation section 102, a determination section 103, a reset section 104, a count mechanism section 105, and an amplification section 106. Furthermore, the signal processing section 280 includes a memory 282 and a calculation section 284.

[0042] The photoelectric conversion section 101 generates electric charge according to received light. The photoelectric conversion section 101 has a predetermined capacitor. The first accumulation section 102 accumulates electric charge exceeding the capacitance of the predetermined capacitor of the photoelectric conversion section 101. Note that the first accumulation section 102 according to the present embodiment corresponds to a first charge holding section.

[0043] The determination section 103 determines whether the potential of the first accumulation section 102 has reached a predetermined value, and when the potential has reached the predetermined value, the determination section 103 outputs a first signal to the reset section 104 and the counting mechanism section 105. The reset section 104 resets the first accumulation section 102 according to the first signal, and discharges the accumulated charge in the first accumulation section 102.

[0044] The count mechanism section 105 counts the number of inputs of the first signal and outputs the obtained count to the memory 282 of the signal processing section 280. The memory 282 stores the counter number in a storage area corresponding to the coordinates of the pixel circuit 250. Note that the initial value of the count mechanism section 105 after reset is 0.

[0045] The amplifier section 106 outputs an analog residual charge signal to the read circuit 260 based on the residual charge remaining in the first accumulation section 102 which has not been reset.

[0046] Therefore, the charge generated by the photoelectric conversion unit 101 is accumulated in the first accumulation unit 102, and after the determination unit 103 determines that this is a predetermined potential, the reset operation of the first accumulation unit 102 is performed. The counting mechanism unit 105 counts this as one count. The first accumulation unit 102 starts accumulation again. This process is repeated during the accumulation period.

[0047] After the accumulation period ends, the amplifier 106 outputs an analog residual charge signal to the readout circuit 260 based on the residual charge accumulated in the first accumulation section 102. The readout circuit 260 outputs a digital signal Sa to the memory 282 of the signal processing section 280 based on the analog residual charge. The memory 282 stores the digital signal Sa in a storage area corresponding to the coordinates of each pixel circuit 250.

[0048] The potential accumulated in the first accumulation section 102 at the time of reset is previously associated with the accumulated charge amount. Therefore, the charge amount generated during the accumulation period is [(the accumulated charge amount in the first accumulation section)×(the number of resets)]. In addition, a pixel signal according to the residual charge at the first accumulation section during the reading period is also output to the reading circuit 260. Therefore, the charge amount finally generated is [(the accumulated charge amount in the first accumulation section)×(the number of resets)+(the residual charge amount)].

[0049] The calculation section 280b of the signal processing section 280 calculates the first image signal corresponding to [(accumulated charge amount in the first accumulation section)×(number of reset times)] as [K1×(number of reset times)], and calculates the second image signal corresponding to [(remaining charge amount)] as [K2×(value of the digital signal Sa)]. That is, the calculation section 280b of the signal processing section 280 calculates [K1×(number of reset times)+K2×(value of the digital signal Sa)] for the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. K1 and K2 are selected coefficients for matching dimensions. The coordinates (x, y) are the position coordinates of the pixel circuit 250 corresponding to the read row and read column of the pixel array section 240.

[0050] The memory 282 stores the image signal G(x,y) in a storage area corresponding to the coordinates (x,y) of each pixel circuit 250. Then, the memory 282 outputs the image signal G(x,y) corresponding to the coordinates of each pixel circuit 250 to the DSP circuit 120 as image data.

[0051] Figure 5 : is a diagram showing a circuit configuration example of the pixel circuit 250. The photoelectric conversion portion 101 is configured to include a photoelectric conversion element 101a, and, for example, the first accumulation portion 102 is composed of a capacitor. For example, the first accumulation portion 102 is a floating diffusion portion (FD: floating diffusion).

[0052] In addition, the determination section 103 is configured to include a comparator 103a, the reset section 104 is configured to include a reset transistor 104a, and the counting mechanism section 105 is configured to include a counter 105a. In addition, the amplifier section 106 has an amplifier transistor 106a and a selection transistor 106b. That is, as Figure 5 As shown, the pixel circuit 250 has a photoelectric conversion element 101a, a first accumulation section 102, a comparator 103a, a reset transistor 104a, a counter 105a, an amplification transistor 106a, a selection transistor 106b, a transfer transistor 107, and a counter reset circuit 108.

[0053] For example, the reset transistor 104a, the amplifying transistor 106a, the selecting transistor 106b and the transferring transistor 107 are composed of N-channel MOS transistors. Then, the driving signal TG, the driving signal RST and the driving signal SEL are respectively supplied to the gate electrodes of these MOS transistors. These driving signals are pulse signals that are in an active state (on state) when in a high level state, and in an inactive state (off state) when in a low level state.

[0054] like Figure 5 As shown, the photoelectric conversion element 101a is made of, for example, a PN junction photodiode, receives light from a subject, generates charge corresponding to the amount of light received from the subject by photoelectric conversion, and accumulates the charge.

[0055] The transfer transistor 107 is connected between the photoelectric conversion element 101a and the first accumulation section 102 via the node n10. The residual charge accumulated in the photoelectric conversion element 101a is transferred to the first accumulation section 102 according to the drive signal TG applied to the gate electrode of the transfer transistor 107. Note that in this embodiment, when accumulating the charge, the drive signal TG is driven in a low level state, and the accumulated charge is accumulated in the first accumulation section 102 as leak charge via the transfer transistor 107.

[0056] The input terminal of the comparator 103a is connected to the node n10, and the output terminal is connected to the gate terminal of the reset transistor 104a via the node n12. When the potential of the node n10 crosses the predetermined threshold potential Vth to the lower side, the comparator 103a outputs a first signal. The first signal is a high-level signal, but the first signal becomes a low-level signal when the first accumulator 102 is reset, thereby becoming a pulse signal.

[0057] The reset transistor 104a is a device for initializing (resetting) the first accumulator 102 as needed. The drain of the reset transistor 104a is connected to a power supply having a power supply potential VDD, and the source is connected to the first accumulator 102 via a node n10. The above-mentioned first signal is applied to the gate electrode of the reset transistor 104a as a drive signal RST. When the drive signal RST is applied, the reset transistor 104a is in a conducting state, and the potential of the node n10 is reset to the level of the power supply potential VDD.

[0058] The input terminal of the counter 105a is connected to the output terminal of the comparator 103a via the node n12, and the output terminal of the counter 105a is connected to the signal processing unit 280. The counter 105a increments the counter by 1 each time the first signal is input, and outputs the obtained count to the signal processing unit 280.

[0059] The gate electrode of the amplifier transistor 106a is connected to the first accumulation section 102 via the node n10, the drain of the amplifier transistor 106a is connected to a power supply having a power supply potential VDD, and the drain is an input portion of a source follower circuit for reading the residual charge of the first accumulation section 102 and the photoelectric conversion section 101. That is, by connecting the source of the amplifier transistor 106a to the vertical signal line Lsv via the selection transistor 106b, the amplifier transistor 106a constitutes a source follower circuit together with the constant current source 106c connected to one end of the vertical signal line Lsv.

[0060] The selection transistor 106b is connected between the source of the amplifier transistor 106a and the vertical signal line Lsv, and the drive signal SEL is supplied to the gate electrode of the selection transistor 106b as a selection signal. When the drive signal SEL is in an active state, the selection transistor 106b enters a conductive state, and the pixel equipped with the selection transistor 106b is in a selected state. When the pixel is in a selected state, the signal output from the amplifier transistor 106a is read out by the reading circuit 260 via the vertical signal line Lsv.

[0061] The counter reset circuit 108 provides an initialization signal SHT to the node n12. After the counter 105a receives the initialization signal SHT, the counter value is initialized to 0. In addition, at each of the pixel circuits 250, for example, a plurality of drive lines are laid for each pixel row. Using the plurality of drive lines acting as pixel drive lines, the drive signal TG, the drive signal RST, the drive signal SEL and the drive signal SHT are supplied to the pixel from the vertical scanning circuit 210. Note that although a structure in which a counter 105a and a reading circuit 260 are provided for each pixel circuit 250 is adopted in the present embodiment, this is not restrictive. For example, a plurality of photoelectric conversion units 101 can be connected in parallel to the node n10, and the counter 105a and the reading circuit 260 are provided for an increment shared by the pixel. In some embodiments, when the voltage applied to the terminal of the transistor exceeds the threshold voltage of the transistor, the transistor can be in an on state. For example, a MOS (metal-oxide-semiconductor) field effect transistor (FET) can be in a conducting state when the difference between the gate terminal and the source terminal exceeds a threshold value (e.g., a positive voltage threshold for an n-type channel transistor or a negative voltage threshold for a p-type channel transistor). In some embodiments, the transistor can be in a non-conducting state when the voltage applied to the terminals of the transistor does not exceed the threshold voltage of the transistor. However, it should be understood that a transistor in a non-conducting state may still conduct a parasitic amount of leakage current.

[0062] (Configuration Example of Column Signal Processing Section) Figure 6 2 is a block diagram showing a configuration example of a read circuit 260 according to a first embodiment of the present technology. The read circuit 260 has a comparator 300, a counter 261, and a latch 262 arranged for each column. When the number of columns is N (N is an integer), each of the comparator 300, the counter 261, and the latch 262 is arranged in N pieces. Note that a set of the comparator 300, the counter 261, and the latch 262 according to the present embodiment is equivalent to an ADC.

[0063] The comparator 300 compares the reference signal from the DAC 230 with the pixel signal from the corresponding column. The potential of the reference signal hereinafter is the reference potential V RMP , and the potential of the vertical signal line 259 for transmitting the pixel signal hereinafter is the input potential V VSL The comparator 300 supplies an output signal VCO indicating a comparison result to the counter 261 of the corresponding column.

[0064] In addition, for example, when the pixel circuit 250 is initialized, the level of the pixel signal (ie, the input potential V VSL ) will be referred to as the "Vr level"; and when the residual charge accumulated in the photoelectric conversion element 101a is transferred to the node n10, the level of the pixel signal will be referred to as the "Vs level". That is, in this embodiment, there is a case where the level serving as a comparison reference is referred to as the "Vr level" and the level serving as a comparison object is referred to as the "Vs level". Note that in this embodiment, there is a case where the first "Vr1 level" is used as a comparison reference and the second "Vr2 level" different from the Vr1 level is used as a comparison object. Similarly, there is a case where the first "Vs1 ​​level" is used as a comparison reference and the second "Vs2 level" different from the Vs1 level is used as a comparison object.

[0065] In addition, there are cases where the information related to the residual charge (which corresponds to the analog image signal) is included in both the level used as a comparison reference and the level used as a comparison object, which is called CDS (Correlated Double Sampling) driving. At the same time, there are driving examples of cases where the information related to the residual charge (which corresponds to the analog image signal) is not included in at least one of the level used as a comparison reference and the level used as a comparison object, which is called DDS (Double Data Sampling) driving. Generally, CDS driving tends to show a better signal-to-noise ratio (SN ratio) in the digital signal after digital conversion compared with DDS driving.

[0066] The counter 261 counts the count value during the period before the output signal VCO is inverted. For example, the counter 261 counts down during the period before the output signal VCO is inverted, which corresponds to the reset level; the counter 261 counts up during the period before the output signal VCO is inverted, which corresponds to the signal level. This realizes a process for finding the difference between the Vr level and the Vs level, for example.

[0067] Then, the counter 261 causes the latch 262 to hold the digital signal for representing the count value. The comparator 300 and the counter 261 implement the AD conversion process of converting the analog pixel signal into a digital signal. That is, the comparator 300 and the counter 261 are used as ADC. This ADC implemented by using a comparator and a counter is generally referred to as a single slope ADC. The latch 262 is used to hold the digital signal. The latch 262 outputs the held digital signal under the control of the horizontal scanning circuit 270.

[0068] Figure 7 is a sequence diagram of a processing example according to the present embodiment. Figure 7 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Figure 7 B in FIG. 1 is an example of a state in which the counter 105a does not count under low illumination. The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the drive signal TG, the accumulated charge L10 of the photoelectric conversion element 101a, and the potential L16 of the first accumulation section 102. Line L10 represents the charge in the capacitance of the photoelectric conversion element 101a. Line L12 represents the amount of generated charge of the photoelectric conversion element 101a, and line L14 represents the amount of charge obtained by subtracting the charge not accumulated in the first accumulation section 102 at the time of reset from line L12. The drive signal EXP represents the charge accumulation period when it is at a high level, and represents the reading period when it is at a low level.

[0069] like Figure 7 As shown in A in FIG. 1 , in the high illuminance state, the drive signal RST and the drive signal TG become high level at time t0, and the photoelectric conversion element 101a and the first accumulation section 102 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0070] Next, at time t1, the drive signal RST and the drive signal TG become low level, and the drive signal EXP becomes high level. Therefore, the charge generated by the photoelectric conversion element 101a exceeds the capacitance and is accumulated at the first accumulation section 102. Next, at time t1, the potential at the node n10 of the first accumulation section 102 begins to drop. Then, at time t2, the threshold potential Vth of the comparator 103a is reached for the first time. Therefore, the comparator 103a outputs the first signal, and the counter 105a increments the count value by 1. At the same time, the first signal as the drive signal RST is at a high level, so the reset transistor 104a enters the on state, and the potential of the node n10 of the first accumulation section 102 is reset to the power supply potential VDD.

[0071] The above-mentioned processing is repeated, and then at time t6, the drive signal EXP becomes a low level, and the reading period starts. Next, at time t7, the drive signal TG becomes a high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102, and the potential of the node n10 corresponds to the potential of the remaining charge. Then, at time t8, the drive signal RST becomes a high level, and the potential of the node n10 of the first accumulation section 102 is reset to the power supply potential VDD.

[0072] Furthermore, between time t7 and time t8, the analog signal potential corresponding to the residual charge is output as the Vs level to the reading circuit 260. In contrast, between time t8 and time t9, the analog signal potential corresponding to the dark current is output as the Vr level to the reading circuit 260. Therefore, the reading circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital signal Sa, and outputs it to the signal processing section 280.

[0073] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 2 times)+K2×(value of the digital signal Sa)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal G(x, y) in a storage area corresponding to the coordinates (x, y) of each pixel circuit 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates (x, y) of each pixel circuit 250 to the DSP circuit 120 as image data.

[0074] Compared with the above, Figure 7 As shown in B in FIG. 1 , in the low illumination state, the drive signal RST and the drive signal TG become high level at time t0, and the photoelectric conversion element 101a and the first accumulation section 102 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0075] Subsequently, at time t1, the drive signal RST and the drive signal TG become low level, and the drive signal EXP becomes high level. Therefore, charge is generated at the photoelectric conversion element 101a, and the charge amount L18 continues to increase, but the charge amount generated in the capacitance within the photoelectric conversion element 101a remains unchanged.

[0076] At time t6, the drive signal EXP becomes a low level, and the reading period starts. Subsequently, at time t7, the drive signal TG becomes a high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102, and the potential of the node n10 corresponds to the potential of the remaining charge. Then, at time t8, the drive signal RST becomes a high level, and the potential of the node n10 of the first accumulation section 102 is reset to the power supply potential VDD.

[0077] Furthermore, between time t7 and time t8, the analog signal potential corresponding to the residual charge is output as the Vs level to the reading circuit 260. Furthermore, between time t8 and time t9, the analog signal potential corresponding to the dark current is output as the Vr level to the reading circuit 260. Therefore, the reading circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital signal Sa, and outputs it to the signal processing section 280.

[0078] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 0 times)+K2×(value of the digital signal Sa)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal G(x, y) in a storage area corresponding to the coordinates (x, y) of each pixel circuit 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates (x, y) of each pixel circuit 250 to the DSP circuit 120 as image data.

[0079] As described above, according to the present embodiment, the charge generated at the photoelectric conversion element 101a is accumulated in the first accumulation section 102, and each time the comparator 103a reaches the predetermined threshold potential Vth, the first signal is output, the first accumulation section 102 is reset, and the counter 105a further increments the count value by 1. Therefore, even in the case where the charge generated at the photoelectric conversion element 101a exceeds the capacitor of the first accumulation section 102, the charge can continue to be accumulated in the first accumulation section 102, and the amount of charge generated at the photoelectric conversion element 101a can be calculated from the count value. In addition, the residual charge of the photoelectric conversion element 101a and the first accumulation section 102 is read out by the amplifier 106 to the reading circuit 260 as an analog potential and converted into a digital value. Therefore, even under high illumination, an image signal containing the residual charge can be generated without saturating the dynamic range.

[0080] Furthermore, even in the case of low illumination and the capacitance of the first accumulation section 102 is not exceeded even once, the residual charge of the photoelectric conversion element 101a and the first accumulation section 102 is read out as an analog potential by the amplification section 106 to the reading circuit 260 and converted into a digital value. Therefore, even in the case of low illumination in which the capacitance of the first accumulation section 102 is not exceeded even once, an image signal including the residual charge can be generated.

[0081] [Variation 1 of the first embodiment] The solid-state imaging device 200 according to Modification 1 of the first embodiment is different from the solid-state imaging device 200 according to the first embodiment in that CDS driving is further enabled. The differences of Modification 1 with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0082] Figure 8 is a timing chart of a processing example according to Modification 1 of the first embodiment. Figure 8 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Figure 8 B in FIG. 1 is an example of a state in which the illumination is low and therefore the counter 105 a does not count. This is different from the solid-state imaging device 200 according to the first embodiment in that the Vr level is read between time t6 and time t7, and the Vs level is read between time t7 and time t8.

[0083] Fig. 9 It is a conceptual explanation Figure 8 Graph showing the read potential at the Vr level, Vs level, Vs level, and Vr level in FIG. The vertical axis represents the absolute value of the difference in potential relative to the power supply potential VDD. Figure 8 As shown, the potential of the Vr level between time t6 and time t7 is the potential before the drive signal TG becomes high level. That is, this corresponds to the potential before the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102. The potential V10 is the potential of the first accumulation section 102, and the potential V12 is the noise component.

[0084] The potential of the Vs level between time t7 and time t8 corresponds to the potential after the drive signal TG becomes high and the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102. The difference between these potentials is a potential V14, which corresponds to the accumulated charge of the photoelectric conversion element 101a minus the potential V12 of the noise component. The capacitor of the photoelectric conversion element 101a and the capacitor of the first accumulation section 102 are known, and therefore, the potential V10 of the first accumulation section 102 can also be calculated based on the potential V14 corresponding to the accumulated charge of the photoelectric conversion element 101a. In addition, the potential of the Vr level after time t9 is the potential V16 of the noise component after the drive signal TG becomes high and the accumulated charge of the photoelectric conversion element 101a is reset.

[0085] Therefore, the calculation section 280b of the signal processing section 280 is able to calculate the digital signal Sb corresponding to the residual charge from the result of the AD conversion performed for the first time. That is, the signal value S of the digital signal Sa can be obtained by multiplying the signal value of the digital signal Sb in the AD conversion performed for the first time by the coefficient K3. Therefore, the calculation section 280b calculates [K1×(number of resets: 2 times)+K2×K3×(signal value of the digital signal Sb)] as the image signal G(x,y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal G(x,y) in a storage area corresponding to the coordinates (x,y) of each pixel circuit 250. Then, the memory 282 outputs the image signal G(x,y) corresponding to the coordinates (x,y) of each pixel circuit 250 to the DSP circuit 120 as image data.

[0086] As described above, according to the present embodiment, execution of CDS driving is further enabled, and a digital signal corresponding to the residual charge can be generated with noise suppressed.

[0087] [Variation 2 of the first embodiment] The solid-state imaging device 200 according to the modification 2 of the first embodiment is different from the solid-state imaging device 200 according to the first embodiment in that the first accumulation section 102 is constructed as a MIM (Metal-Insulator-Metal) capacitor. The differences of modification 2 relative to the solid-state imaging device 200 according to the first embodiment will be described below. Since the first accumulation section 102 is constructed as a MIM (Metal-Insulator-Metal) capacitor, it is possible to easily increase the capacitance value by changing the type of insulating film. It is possible to suppress the difference in the determination made by the determination section 103 as the first accumulation section 102 becomes larger. In addition, in combination with miniaturization, a high aspect ratio convex-concave structure, a cylindrical structure, or a simple stacked structure can be used for the first accumulation section 102 so as to obtain high capacitance with a small area.

[0088] [Second embodiment] The solid-state imaging device 200 according to the second embodiment is different from the solid-state imaging device 200 according to the first embodiment in further including a second accumulating section 109. The differences of the second embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0089] (Configuration Example of Pixel Circuit) Will refer to Fig.10 and Fig.11 A configuration example of the pixel circuit 250 according to the second embodiment will be described. Fig.102 is a block diagram showing a configuration example of a pixel circuit 250 according to the second embodiment. The pixel circuit 250 is different from the pixel circuit 250 according to the first embodiment in that a second accumulating section 109 is further included. The capacitor capacitance of the second accumulating section 109 is configured to be smaller than the capacitor capacitance of the first accumulating section 102.

[0090] The second accumulation section 109 is connected in parallel with the first accumulation section 102 when accumulating charges. Therefore, when accumulating charges, the capacitance of the capacitor for accumulating charges can be increased. Note that the second accumulation section 109 according to the present embodiment corresponds to a second charge holding section.

[0091] In contrast, when the residual charge is read out, the first accumulation section 102 and the second accumulation section 109 are not electrically connected, and the charge of the photoelectric conversion section 101 is transferred only to the second accumulation section 109. Therefore, an analog residual charge signal corresponding to the residual charge in the second accumulation section 109 is output to the readout circuit 260. At this time, the capacitor capacitance of the second accumulation section 109 is smaller than the capacitor capacitance of the first accumulation section 102, and it is known that the SN ratio of the analog residual charge signal corresponding to the second accumulation section 109 is better than the SN ratio of the analog residual charge signal corresponding to the first accumulation section 102.

[0092] Fig.11 2 is a diagram showing a circuit configuration example of a pixel circuit 250 according to the second embodiment. The second capacitor 109a is connected to the node n10. For example, the second capacitor 109a is a floating diffusion. The capacitance connection transistor 110 is connected between the node n10 and the node n16, and the first accumulation unit 102 is connected to the node n16.

[0093] For example, the capacitor connection transistor 110 is composed of an N-channel MOS transistor. A drive signal FDG is supplied to the gate electrode of the MOS transistor. The drive signal is a pulse signal that is in an active state (on state) when in a high level state, and in an inactive state (off state) when in a low level state.

[0094] When accumulating charges, the capacitance connection transistor 110 is supplied with a high-level driving signal FDG and assumes an active state (conductive state). Therefore, the first accumulation section 102 and the second capacitor 109a are in a state of being connected in parallel.

[0095] In contrast, when reading the residual charge, the low-level driving signal FDG is supplied and assumes an inactive state (off state). Therefore, the first accumulation section 102 and the second capacitor 109a are not electrically connected.

[0096] (Operation Example) Fig.12 is a timing chart of an operation example according to the second embodiment. Fig.12 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Fig.12 B in FIG. 1 is an example of a state where the illumination is low and therefore the counter 105 a does not count.

[0097] The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the drive signal TG, the drive signal FDG, the accumulated charges L10 and L18 of the photoelectric conversion element 101 a , the potentials L16 and L20 of the first accumulation section 102 , and the potentials L22 and L24 of the second accumulation section 109 .

[0098] like Fig.12 As shown in A in FIG. 1 , in the high illumination state, the drive signal RST, the drive signal TG, and the drive signal FDG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, and the second accumulator 109 are initialized. That is, the potential of the node n10 is the power supply potential VDD. At this time, the drive signal FDG is at a high level, and therefore, the first accumulator 102 and the second accumulator 109 are connected in parallel and are at the potential of the node n10.

[0099] Next, at time t1, the drive signal RST and the drive signal TG become low level, and the drive signal EXP becomes high level. Therefore, the charge generated by the photoelectric conversion element 101a is accumulated at the first accumulation section 102 and the second accumulation section 109, and the potential at the node n10 of the first accumulation section 102 and the second accumulation section 109 begins to decrease. Then, at time t2, the threshold potential Vth of the comparator 103a is reached for the first time. Therefore, the comparator 103a outputs the first signal, and the counter 105a increments the count value by 1. At the same time, the first signal as the drive signal RST is at a high level, and therefore, the reset transistor 104a enters the on state, and the potential of the node n10 of the first accumulation section 102 is reset to the power supply potential VDD.

[0100] Such processing as described above is repeated, and at time t6, the drive signal EXP becomes low level, and the reading period starts. Next, at time t7, the drive signal FDG becomes low level, and the first accumulating section 102 and the second accumulating section 109 are in a non-electrically connected state.

[0101] Subsequently, at time t8, the drive signal TG becomes a high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the second accumulation section 109, and the potential of the node n10 corresponds to the potential of the remaining charge. Then at time t9, the drive signal TG becomes a low level, and the photoelectric conversion element 101a and the second accumulation section 109 are in a non-electrically connected state.

[0102] Next, at time t10, the drive signal FDG and the drive signal TG become high level, and the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102 and the second accumulation section 109. Then, at time t11, the drive signal TG becomes low level, and the photoelectric conversion element 101a, the first accumulation section 102 and the second accumulation section 109 are in a non-electrically connected state with each other.

[0103] Next, at time t12, the drive signal RST becomes high level, and the first accumulating section 102 and the second accumulating section 109 are reset and become the power supply potential VDD. Then, at time t13, the drive signal RST becomes low level, and at time t14, the drive signal FDG becomes low level.

[0104] In addition, between time t7 and time t8, the analog residual charge signal of the second accumulation section 109 is output to the readout circuit 260 as the Vr level. In addition, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the accumulated charge of the photoelectric conversion element 101a has been added is output to the readout circuit 260 as the Vs level. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa1, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa1 is a signal corresponding to the residual charge of the photoelectric conversion element 101a. The capacitance of the photoelectric conversion element 101a and the capacitance of the first accumulation section 102 and the second accumulation section 109 are known, and therefore, a value corresponding to the total residual charge at the end of the accumulation period can be calculated from the digital residual charge signal Sa1.

[0105] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 2 times)+K4×(signal value of the digital residual charge signal Sa1)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal in a storage area corresponding to the coordinates of each of the pixel circuits 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates of each of the pixel circuits 250 as image data to the DSP circuit 120. K4 is a coefficient.

[0106] In addition, between time t11 and time t12, an analog residual charge signal corresponding to the total residual charge obtained by adding the residual charge of the photoelectric conversion element 101a to the residual charge of the first accumulation section 102 and the second accumulation section 109 is output as the Vs level to the readout circuit 260. In addition, between time t13 and time t14, an analog residual charge signal corresponding to the accumulated charge of the first accumulation section 102 and the second accumulation section 109 after reset is output as the Vr level to the readout circuit 260. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa2, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa2 is a signal corresponding to the total residual charge. The calculation section 280b of the signal processing section 280 can calculate [K1×(number of resets: 2 times)+K5×(signal value of the digital residual charge signal Sa2)] as the image signal G(x, y) of the pixel circuit 250. K5 is a coefficient. Note, however, that, as described above, the image signal G(x, y) calculated from the level signals of the first Vs level and the Vr level has a better SN ratio.

[0107] Compared with the above, Fig.12 As shown in B in FIG. 1 , in the low illumination state, the drive signal RST, the drive signal TG, and the drive signal FDG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, and the second accumulator 109 are initialized. That is, the potential of the node n10 is the power supply potential VDD. At this time, the drive signal FDG is at a high level, and therefore the first accumulator 102 and the second accumulator 109 are connected in parallel and are at the potential of the node n10.

[0108] Subsequently, at time t1, the drive signal RST and the drive signal TG become low level, and the drive signal EXP becomes high level. Therefore, a charge is generated at the photoelectric conversion element 101a, and the charge amount L18 continues to increase, but the charge amount generated in the capacitor in the photoelectric conversion element 101a remains unchanged. Therefore, the potentials L20 and L24 of the first accumulator 102 and the second accumulator 109 are both maintained at the initial potential VDD.

[0109] At time t6, the drive signal EXP changes to a low level, and a reading period starts. Subsequently, at time t7, the drive signal FDG changes to a low level, and the first accumulating section 102 and the second accumulating section 109 are in a non-electrically connected state.

[0110] Subsequently, at time t8, the drive signal TG changes to a high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the second accumulation section 109, and the potential of the node n10 corresponds to the potential of the remaining charge. Then at time t9, the drive signal TG changes to a low level, and the photoelectric conversion element 101a and the second accumulation section 109 are in a non-electrically connected state.

[0111] Next, at time t10, the drive signal FDG and the drive signal TG become high level, and the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102 and the second accumulation section 109. Then, at time t11, the drive signal TG becomes low level, and the photoelectric conversion element 101a, the first accumulation section 102 and the second accumulation section 109 are in a non-electrically connected state with each other.

[0112] Next, at time t12, the drive signal RST becomes high level, and the first accumulating section 102 and the second accumulating section 109 are reset and become the power supply potential VDD. Then at time t13, the drive signal RST becomes low level, and at time t14, the drive signal FDG becomes low level.

[0113] In addition, between time t7 and time t8, the analog residual charge signal of the second accumulation section 109 is output to the readout circuit 260 as the Vr level. In addition, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the accumulated charge of the photoelectric conversion element 101a has been added is output to the readout circuit 260 as the Vs level. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa1, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa1 is a signal corresponding to the residual charge of the photoelectric conversion element 101a. The capacitance of the photoelectric conversion element 101a and the capacitance of the first accumulation section 102 and the second accumulation section 109 are known, and therefore, a value corresponding to the total residual charge at the end of the accumulation period can be calculated from the digital residual charge signal Sa1.

[0114] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 0 times)+K4×(signal value of the digital residual charge signal Sa1)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal in a storage area corresponding to the coordinates of each of the pixel circuits 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates of each of the pixel circuits 250 as image data to the DSP circuit 120. K4 is a coefficient.

[0115] In addition, between time t11 and time t12, an analog residual charge signal corresponding to the total residual charge obtained by adding the residual charge of the photoelectric conversion element 101a to the residual charge of the first accumulation section 102 and the second accumulation section 109 is output as the Vs level to the readout circuit 260. In addition, between time t13 and time t14, an analog residual charge signal corresponding to the accumulated charge of the first accumulation section 102 and the second accumulation section 109 after reset is output as the Vr level to the readout circuit 260. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa2, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa2 is a signal corresponding to the total residual charge. The calculation section 280b of the signal processing section 280 is capable of calculating [K1×(number of resets: 0 times)+K5×(signal value of the digital residual charge signal Sa2)] as the image signal G(x, y) of the pixel circuit 250. K5 is a coefficient. Note, however, that, as described above, the image signal G(x, y) calculated from the level signals of the first Vs level and the Vr level has a better SN ratio.

[0116] As described above, according to the present embodiment, the charge generated at the photoelectric conversion element 101a is accumulated in the first accumulation section 102 and the second accumulation section 109, and each time the comparator 103a reaches the predetermined threshold potential Vth, the first signal is output, the first accumulation section 102 and the second accumulation section 109 are reset, and the counter 105a further increments the count value by 1. Therefore, even in the case where the charge generated at the photoelectric conversion element 101a exceeds the capacitance of the first accumulation section 102 and the second accumulation section 109, the charge can continue to be accumulated in the first accumulation section 102 and the second accumulation section 109, and the amount of charge generated at the photoelectric conversion element 101a can be calculated from the count value. In addition, the residual charge of the photoelectric conversion element 101a and the second accumulation section 109 is read out to the readout circuit 260 as an analog residual charge signal by the amplifier 106, and is converted into a digital value. In this case, the capacitance of the second accumulation section 109 is smaller than the capacitance of the first accumulation section 102, and thus the degradation of the SN ratio of the analog residual charge signal is suppressed. In contrast, during the charge accumulation period, the charges are accumulated in the first accumulation portion 102 and the second accumulation portion 109 , whereby the number of resets can be reduced, and the charge loss at the time of reset can be suppressed.

[0117] Furthermore, even in the case of low illumination and the capacitance of the first accumulation section 102 is not exceeded even once, the residual charge of the photoelectric conversion element 101a and the second accumulation section 109 is read out to the readout circuit 260 by the amplification section 106 as an analog residual charge signal, and is converted into a digital value. Therefore, even in the case of low illumination in which the capacitance of the first accumulation section 102 is not exceeded even once, an image signal containing residual charge can be generated. In this case, too, the capacitance of the second accumulation section 109 is smaller than the capacitance of the first accumulation section 102, and thus the degradation of the SN ratio of the analog residual charge signal is suppressed.

[0118] [Modification of the second embodiment] The solid-state imaging device 200 according to the modification of the second embodiment is different from the solid-state imaging device 200 according to the second embodiment in that the reading of the Vr level and the Vs level is added at different timings. The differences of this modification with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0119] Fig.13 is a sequence diagram of a processing example according to a modification of the second embodiment. Fig.13 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Fig.13 B in FIG. 1 is an example of a state in which the illumination is low and therefore the counter 105 a does not count. This is different from the solid-state imaging device 200 according to the first embodiment in that the Vr1 level is read between time t6 and time t7 and the Vs level is read between time t7 and time t8.

[0120] Since the driving signal FDG is at a high level, the readout potential at the Vr1 level for the first time corresponds to the residual charges of the first and second accumulation portions 102 and 109. Therefore, the potential corresponding to the residual charges of the first and second accumulation portions 102 and 109 can be read out.

[0121] Since the driving signal FDG is at a low level, the readout potential at the Vr2 level for the first time corresponds to the residual charge of the second accumulation portion 109. Therefore, the potential corresponding to the residual charge of the second accumulation portion 109 can be read out.

[0122] Since the readout potential at the Vs1 level for the first time after the drive signal TG becomes high level corresponds to the residual charge of the photoelectric conversion element 101a and the second accumulation portion 109, the potential corresponding to the residual charge of the photoelectric conversion element 101a and the second accumulation portion 109 can be read out.

[0123] Since the drive signal FDG is at a high level, and after the drive signal TG becomes high again, the readout potential at the Vs2 level for the second time corresponds to the residual charges of the photoelectric conversion element 101a, the first accumulation section 102, and the second accumulation section 109. Therefore, the potential corresponding to the residual charges of the photoelectric conversion element 101a, the first accumulation section 102, and the second accumulation section 109 can be read out.

[0124] Since the drive signal FDG is at a high level, and after the drive signal RST becomes a high level, the readout potential at the Vr3 level for the third time corresponds to the charges of the first accumulating section 102 and the second accumulating section 109 after reset. Therefore, the potential corresponding to the charges of the first accumulating section 102 and the second accumulating section 109 after reset can be read out.

[0125] Therefore, after entering the reading period, the Vr1 level determined by the residual charge of the first accumulation section 102 is sampled as the offset level. Next, when the capacitance connection transistor 110 is in a non-connected state (off), the offset level of the second accumulation section 109 (in a state where the capacitance is reduced) is sampled as the Vr2 level. Subsequently, when the transfer transistor 107 is in a connected state (on), the charge of the photoelectric conversion element 101a is transferred and read out as the Vs1 level by CDS driving. Subsequently, when the capacitance connection transistor 110 is in a connected state (on), the level is read out as the Vs2 level by CDS driving in a state where the capacitance increases and all the charges in the photoelectric conversion element 101a can be read out. Subsequently, when the reset transistor 104a is in a connected state (on), the first accumulation section 102 and the second accumulation section 109 are read out as the Vr3 level as the reset level by DDS driving.

[0126] As can be seen from these, by comparing the Vr1 level and the Vr2 level, comparing the Vr2 level and the Vs1 level, comparing the Vs1 level and the Vs2 level, and comparing the Vs2 level and the Vr3 level, it is possible to generate a digital signal corresponding to the residual charge in each of the photoelectric conversion element 101a, the first accumulation section 102, and the second accumulation section 109. Furthermore, in the solid-state imaging device 200 according to the modification of the second embodiment, the signal corresponding to the residual charge in all the photoelectric conversion elements 101a can be read out by CDS driving, and in particular, an image signal with lower noise and a higher SN ratio can be obtained under low illuminance and medium illuminance.

[0127] [Third embodiment] The solid-state imaging device 200 according to the third embodiment is different from the solid-state imaging device 200 according to the first embodiment in that a third accumulating section is further included. The differences of the third embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0128] (Configuration Example of Pixel Circuit) Will refer to Fig.14 and Fig.15 A configuration example of the pixel circuit 250 according to the present embodiment will be described. Fig.14 2 is a block diagram showing a configuration example of a pixel circuit 250 according to the third embodiment. This pixel circuit 250 is different from the pixel circuit 250 according to the first embodiment in that a third accumulation section 111 is further included.

[0129] The third accumulation unit 111 can be connected in parallel to the first accumulation unit 102 and the second accumulation unit 109 .

[0130] Fig.15 2 is a diagram showing a circuit configuration example of a pixel circuit 250 according to a third embodiment. The third accumulator 111 is connected to the node n10 via the second transfer transistor 112. For example, the third accumulator 111 is a floating diffusion. For example, the second transfer transistor 112 is composed of an N-channel MOS transistor. A drive signal TCG is supplied to the gate electrode of the MOS transistor. The drive signal TCG is a pulse signal that is in an active state (on state) when in a high level state, and in an inactive state (off state) when in a low level state.

[0131] An OR gate 114 is connected to the gate electrode of the second transfer transistor 112, and a NOT gate 113 is connected to the OR gate 114. The signal xEXP is a signal that becomes 0 during the accumulation period and becomes 1 during the reading period. Therefore, when the drive signal RST is at a high level during the accumulation period, the drive signal TCG is at a high level, and the drive signal TCG is always at a high level during the reading period.

[0132] The second capacitor connection transistor 115 is connected between the node n10 and the node n16. For example, the second capacitor connection transistor 115 is composed of an N-channel MOS transistor. The drive signal FCG is supplied to the gate electrode of the MOS transistor. The drive signal FCG is a pulse signal: when it is in a high level state, the pulse signal presents an active state (conduction state), and when it is in a low level state, the pulse signal presents an inactive state (off state).

[0133] (Operation Example) Fig.16 is a timing chart of an operation example according to the third embodiment. Fig.16 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Fig.16B in FIG. 1 is an example of a state where the illumination is low and therefore the counter 105 a does not count.

[0134] The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the drive signal TG, the drive signal FCG, the drive signal TCG, the accumulated charges L10 and L18 of the photoelectric conversion element 101a, the potentials L16 and L20 of the first accumulation section 102, the potentials L22 and L24 of the second accumulation section 109, and the potentials L26 and L28 of the third accumulation section 111. Line L10 represents the accumulated charge of the photoelectric conversion element 101a, and line L12 represents the amount of generated charge of the photoelectric conversion element 101a. The drive signal EXP represents the charge accumulation period when it is at a high level, and represents the reading period when it is at a low level. When it is in an inactive state (in an off state), the order of the channel potentials of the transistors is transistor 112 < transistor 115 < transistor 104a.

[0135] like Fig.16 As shown in A in FIG. 1 , in the high illumination state, the drive signal RST, the drive signal TG, the drive signal FCG, and the drive signal TCG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, the second accumulator 109, and the third accumulator 111 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0136] Next, at time t1, the drive signal RST, the drive signal TG, the drive signal FCG and the drive signal TCG become low levels, and the drive signal EXP becomes high level. Therefore, a charge is generated at the photoelectric conversion element 101a, and the charge exceeding the capacitance of the photoelectric conversion element 101a is accumulated at the second accumulation section 109, and the potential L22 at the node n10 of the second accumulation section 109 begins to decline. Then at time t2, the charge is accumulated to the upper limit of the capacitance of the second accumulation section 109. Therefore, the charge exceeding the capacitance of the second accumulation section 109 is accumulated in the first accumulation section 102, and the potential L16 of the first accumulation section 102 begins to decline.

[0137] Then, at time t3, the threshold potential Vth of the comparator 103a is reached for the first time. Therefore, the comparator 103a outputs the first signal, and the counter 105a increments the count value by 1. At the same time, the first signal as the drive signal RST is at a high level, and therefore, the reset transistor 104a enters a conductive state, and the potential of the node n10 of the first accumulating section 102 is reset to the power supply potential VDD.

[0138] In addition, the drive signal TCG becomes high level synchronously with the drive signal RST, and the second transfer transistor 112 is in an electrically conductive state. Therefore, the charge generated at the photoelectric conversion element 101a during the reset of the first accumulation section 102 is accumulated at the third accumulation section 111, and the potential L26 drops from the initial potential VDD.

[0139] Next, at time t4, the drive signal RST becomes low level, and the drive signal TCG also becomes low level, and the charge generated at the photoelectric conversion element 101a is accumulated again in the first accumulation section 102. Such processing as described above is repeated, and then at time t7, the drive signal EXP becomes low level and the reading period starts, and the drive signal TCG and the drive signal FCG become high level and the second transfer transistor 112 and the second capacitance connection transistor 115 are in the on state.

[0140] Subsequently, at time t8, the drive signal TG changes to a high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111, and the potential of the node n10 corresponds to the potential of the residual charge of the photoelectric conversion element 101a, the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111. Then, at time t9, the drive signal TG changes to a low level, and the photoelectric conversion element 101a, the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111 are in a non-electrically connected state with each other.

[0141] Next, at time t10, the drive signal RST becomes high level, and the first accumulator 102, the second accumulator 109, and the third accumulator 111 are reset to the initial potential VDD. Subsequently, at time t10, the drive signal RST becomes low level, and the drive signals FCG and TCG become low level.

[0142] Furthermore, between time t7 and time t8, the analog residual charge signal of the second accumulation section 109 is output as the Vr level to the readout circuit 260. Furthermore, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the accumulated charge of the photoelectric conversion element 101a has been added is output as the Vs level to the readout circuit 260.

[0143] Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa3, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa3 is a signal corresponding to the residual charge of the photoelectric conversion element 101a. The capacitance of the photoelectric conversion element 101a and the capacitances of the first accumulator 102, the second accumulator 109, and the third accumulator 111 are known, and therefore, a value corresponding to the total residual charge at the end of the accumulation period can be calculated from the digital residual charge signal Sa3.

[0144] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 2 times)+K6×(signal value of the digital residual charge signal Sa3)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal in a storage area corresponding to the coordinates of each of the pixel circuits 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates of each of the pixel circuits 250 as image data to the DSP circuit 120. K6 is a coefficient.

[0145] In addition, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the accumulated charge of the photoelectric conversion element 101a has been added is output to the readout circuit 260 as the Vs level. In addition, between time t11 and time t12, the analog residual charge signal corresponding to the accumulated charge of the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 after reset is output to the readout circuit 260 as the Vr level. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa4, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa4 is a signal corresponding to the entire residual charge. The calculation section 280b of the signal processing section 280 is capable of calculating [K1×(number of resets: 2 times)+K7×(signal value of the digital residual charge signal Sa4)] as the image signal G(x, y) of the pixel circuit 250. K7 is a coefficient. Note, however, that, as described above, the image signal G(x, y) calculated from the level signals of the first Vs level and the Vr level has a better SN ratio.

[0146] Compared with the above, Fig.16 As shown in B in FIG. 1 , in the low illumination state, the drive signal RST, the drive signal TG, the drive signal FCG, and the drive signal TCG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, the second accumulator 109, and the third accumulator 111 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0147] Subsequently, at time t1, drive signal RST, drive signal TG, drive signal FCG and drive signal TCG become low level, and drive signal EXP becomes high level. Therefore, charge is generated at photoelectric conversion element 101a, and the charge is accumulated in the capacitance of photoelectric conversion element 101a. The charge amount L18 continues to increase, but the charge amount generated in the capacitance in photoelectric conversion element 101a remains unchanged. Therefore, the potential L20, L24 and L28 of the first accumulator 102, the second accumulator 109 and the third accumulator 111 are all maintained at the initial potential VDD.

[0148] Next, at time t7, the drive signal EXP becomes low level and the reading period starts, and further, the drive signal TCG and the drive signal FCG become high level, and the second transfer transistor 112 and the second capacitance connection transistor 115 are in the on state. Subsequently, at time t8, the drive signal TG becomes high level, the accumulated charge of the photoelectric conversion element 101a is transferred to the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111, and the potential of the node n10 corresponds to the potential of the residual charge of the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111. Then, at time t9, the drive signal TG becomes low level, and the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 are in a non-electrically connected state with each other.

[0149] Next, at time t10, the drive signal RST becomes high level, and the first accumulator 102, the second accumulator 109, and the third accumulator 111 are reset to the initial potential VDD. Then, at time t10, the drive signal RST becomes low level, and the drive signals FCG and TCG become low level.

[0150] In addition, between time t7 and time t8, the analog residual charge signal of the second accumulation section 109 is output to the readout circuit 260 as the Vr level. In addition, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the accumulated charge of the photoelectric conversion element 101a has been added is output to the readout circuit 260 as the Vs level. Therefore, the readout circuit 260 converts the difference between the potential corresponding to the Vs level and the potential corresponding to the Vr level into a digital residual charge signal Sa3, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa3 is a signal corresponding to the residual charge of the photoelectric conversion element 101a. The capacitance of the photoelectric conversion element 101a and the capacitances of the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 are known, and therefore, a value corresponding to the total residual charge at the end of the accumulation period can be calculated from the digital residual charge signal Sa3.

[0151] Then, the calculation section 280b of the signal processing section 280 calculates [K1×(number of resets: 0 times)+K6×(signal value of the digital residual charge signal Sa3)] as the image signal G(x, y) of the pixel circuit 250, and outputs it to the memory 282. The memory 282 stores the image signal in a storage area corresponding to the coordinates of each of the pixel circuits 250. Then, the memory 282 outputs the image signal G(x, y) corresponding to the coordinates of each of the pixel circuits 250 as image data to the DSP circuit 120. K6 is a coefficient.

[0152] In addition, between time t9 and time t10, the analog residual charge signal of the second accumulation section 109 to which the residual charge of the photoelectric conversion element 101a has been added is output as the Vs level to the readout circuit 260. In addition, between time t11 and time t12, the analog residual charge signal corresponding to the accumulated charge of the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 after reset is output as the Vr level to the readout circuit 260. Therefore, the readout circuit 260 converts the difference between the Vs level and the Vr level into a digital residual charge signal Sa4, and outputs it to the signal processing section 280. That is, the digital residual charge signal Sa4 is a signal corresponding to the entire residual charge. The calculation section 280b of the signal processing section 280 is capable of calculating [K1×(number of resets: 0 times)+K7×(signal value of the digital residual charge signal Sa4)] as the image signal G(x, y) of the pixel circuit 250. K7 is a coefficient. Note, however, that, as described above, the image signal G(x, y) calculated from the level signals of the first Vs level and the Vr level has a better SN ratio.

[0153] As described above, according to the present embodiment, the charge generated at the photoelectric conversion element 101a is accumulated in the first accumulation section 102 and the second accumulation section 109, and each time the comparator 103a reaches the predetermined threshold potential Vth, the first signal is output, the first accumulation section 102 is reset, and the counter 105a further increments the count value by 1. Therefore, even in the case where the charge generated at the photoelectric conversion element 101a exceeds the capacitance of the first accumulation section 102, the charge can continue to be accumulated in the first accumulation section 102, and the amount of charge generated at the photoelectric conversion element 101a can be calculated from the count value. In addition, the charge of the first accumulation section 102 at the time of reset can be accumulated at the third accumulation section 111.

[0154] Therefore, the residual charge at the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 is read out by the amplifier section 106 to the readout circuit 260 as an analog residual charge signal, and is converted into a digital value. The residual charge also includes the charge generated at the photoelectric conversion element 101a during the reset of the first accumulation section 102, and therefore, all the charges generated at the photoelectric conversion element 101a can be generated as the image signal G (x, y). Therefore, even under high illumination, an image signal including the residual charge at the time of reset can be generated without saturating the dynamic range.

[0155] Furthermore, even in the case of low illumination and the capacitance of the first accumulation section 102 is not exceeded even once, the residual charges of the photoelectric conversion element 101a and the second accumulation section 109 are read out as analog residual charge signals by the amplification section 106 to the readout circuit 260 and converted into digital values. Therefore, even in the case of low illumination in which the capacitance of the first accumulation section 102 is not exceeded even once, an image signal containing residual charges can be generated.

[0156] [Variation 1 of the third embodiment] The solid-state imaging device 200 according to Modification 1 of the third embodiment is different from the solid-state imaging device 200 according to the third embodiment in further including a capacitance connection transistor 110. The differences of Modification 1 from the solid-state imaging device 200 according to the third embodiment will be described below.

[0157] (Configuration Example of Pixel Circuit) Fig.17 : is a diagram showing a circuit configuration example of a pixel circuit 250 according to Modification 1 of the third embodiment. A capacitance connecting transistor 110 is connected between a node n10 and a node n20.

[0158] (Operation Example) Fig.18is a timing chart of an operation example according to Modification 1 of the third embodiment. Fig.18 A in FIG. 1 is an example of a state where the illumination is high and therefore the counter 105 a counts more than once, and Fig.18 B in FIG. 1 is an example of a state where the illumination is low and therefore the counter 105 a does not count.

[0159] The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the drive signal TG, the drive signal FDG, the drive signal FCG, the drive signal TCG, the accumulated charges L10 and L18 of the photoelectric conversion element 101a, the potentials L16 and L20 of the first accumulation section 102, the potentials L22 and L24 of the second accumulation section 109, and the potentials L26 and L28 of the third accumulation section 111. Line L10 represents the accumulated charge of the photoelectric conversion element 101a, and line L12 represents the amount of generated charge of the photoelectric conversion element 101a. The drive signal EXP represents the charge accumulation period when it is at a high level, and represents the reading period when it is at a low level. When it is in an inactive state (in an off state), the order of the channel potentials of the transistors is transistor 112 < transistor 115 < transistor 104a.

[0160] like Fig.18 As shown in A in FIG. 1 , in the high illumination state, the drive signal RST, the drive signal TG, the drive signal FDG, the drive signal FCG, and the drive signal TCG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, the second accumulator 109, and the third accumulator 111 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0161] Next, at time t1, the drive signal RST, the drive signal TG, the drive signal FCG and the drive signal TCG become low levels, and the drive signal EXP becomes high level. Therefore, a charge is generated at the photoelectric conversion element 101a, and the charge exceeding the capacitance of the photoelectric conversion element 101a is accumulated at the second accumulation section 109, and the potential L22 at the node n10 of the second accumulation section 109 begins to decline. Then at time t2, the charge is accumulated to the upper limit of the capacitance of the second accumulation section 109. Therefore, the charge exceeding the capacitance of the second accumulation section 109 is accumulated in the first accumulation section 102, and the potential L16 of the first accumulation section 102 begins to decline.

[0162] Then, at time t3, the threshold potential Vth of the comparator 103a is reached for the first time. Therefore, the comparator 103a outputs the first signal, and the counter 105a increments the count value by 1. At the same time, the first signal as the drive signal RST is at a high level, and therefore, the reset transistor 104a enters a conducting state, and the potential of the node n10 of the first accumulating section 102 is reset to the power supply potential VDD.

[0163] In addition, the drive signal TCG becomes high level synchronously with the drive signal RST, and the second transfer transistor 112 is in an electrically conductive state. Therefore, the charge generated at the photoelectric conversion element 101a during the reset of the first accumulation section 102 is accumulated at the third accumulation section 111, and the potential L26 drops from the initial potential VDD.

[0164] Then, at time t4, the drive signal RST becomes low level, and the drive signal TCG also becomes low level, and the charge generated at the photoelectric conversion element 101a is accumulated again in the first accumulation section 102. Such processing as described above is repeated, and then at time t7, the drive signal EXP becomes low level and the reading period starts, and the drive signal TCG and the drive signal FCG become high level, and the second transfer transistor 112 and the second capacitance connection transistor 115 are in the on state.

[0165] Subsequently, at time t8, the drive signal FDG becomes a low level, and the second accumulator 109, the first accumulator 102, and the third accumulator 111 are in a non-electrically connected state. Subsequently, at time t9, the drive signal TG becomes a high level, and the accumulated charge of the photoelectric conversion element 101a is transferred to the second accumulator 109, and the potential of the node n10 corresponds to the potential of the residual charge of the photoelectric conversion element 101a and the second accumulator 109. Then, at time t10, the drive signal TG becomes a low level, and the photoelectric conversion element 101a and the second accumulator 109 are in a non-electrically connected state.

[0166] Subsequently, at time t11, the drive signal TG and the drive signal FDG become high levels, the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109 and the third accumulation section 111 are in a non-electrically connected state, and the potential of the node n10 corresponds to the potential of the residual charge of the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109 and the third accumulation section 111.

[0167] Subsequently, at time t12, the drive signal TG becomes a low level, and then at time t13, the drive signal RST becomes a high level, and the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111 are reset to the initial potential VDD. Subsequently, at time t14, the drive signal RST becomes a low level, and the drive signals FDG, FCG, and TCG become low levels.

[0168] Furthermore, between time t7 and time t8, the analog residual charge signal of the second accumulation section 109 is output as the Vr1 level to the readout circuit 260. The analog residual charge signal corresponding to the accumulated charges of the first accumulation section 102, the second accumulation section 109, and the third accumulation section 111 is output to the readout circuit 260.

[0169] Between time t8 and time t9, the analog residual charge signal corresponding to the accumulated charge of the second accumulation section 109 is output as the Vr2 level to the readout circuit 260. Furthermore, between time t10 and time t11, the analog residual charge signal corresponding to the accumulated charge of the second accumulation section 109 is output as the Vs1 level to the readout circuit 260. Furthermore, the analog residual charge signal corresponding to the accumulated charge obtained by adding the accumulated charge of the photoelectric conversion element 101a to the accumulated charge of the second accumulation section 109 is output to the readout circuit 260.

[0170] Furthermore, between time t12 and time t13, an analog residual charge signal corresponding to the accumulated charge obtained by adding the accumulated charge of the photoelectric conversion element 101a to the accumulated charges of the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111 is output twice as the Vs2 level to the readout circuit 260. Then, between time t14 and time t15, an analog residual charge signal corresponding to the reset charge of the first accumulating section 102, the second accumulating section 109, and the third accumulating section 111 is output as the Vr3 level to the readout circuit 260.

[0171] As can be understood from the above, a digital signal corresponding to the residual charge of each of the photoelectric conversion element 101 a , the first accumulation section 102 , the second accumulation section 109 , and the third accumulation section 111 can be generated by comparing the signal levels.

[0172] Compared with the above, Fig.18 As shown in B in FIG. 1 , in the low illumination state, the drive signal RST, the drive signal TG, the drive signal FDG, the drive signal FCG, and the drive signal TCG become high level at time t0, and the photoelectric conversion element 101a, the first accumulator 102, the second accumulator 109, and the third accumulator 111 are initialized. That is, the potential of the node n10 is the power supply potential VDD.

[0173] Subsequently, at time t1, drive signal RST, drive signal TG, drive signal FCG and drive signal TCG become low level, and drive signal EXP becomes high level. Therefore, charge is generated at photoelectric conversion element 101a, and the charge is accumulated in the capacitance of photoelectric conversion element 101a. The charge amount L18 continues to increase, but the charge amount generated in the capacitance in photoelectric conversion element 101a remains unchanged. Therefore, the potential L20, L24 and L28 of the first accumulator 102, the second accumulator 109 and the third accumulator 111 are all maintained at the initial potential VDD.

[0174] Reading is handled the same way as at high illumination levels.

[0175] As described above, according to the present variation 1, in addition to having the same processing effect as that of the third embodiment, a digital signal corresponding to the residual charge of each of the photoelectric conversion element 101a, the first accumulation section 102, the second accumulation section 109 and the third accumulation section 111 can be generated by comparing the signal levels.

[0176] [Variation 2 of the third embodiment] The solid-state imaging device 200 according to the modification 2 of the third embodiment is different from the solid-state imaging device 200 according to the modification 1 of the third embodiment in that the third accumulating section 111 is connected to the photoelectric conversion element 101a without connecting the transistor 110 through a capacitor. The difference of this modification 2 with respect to the solid-state imaging device 200 according to the modification 1 of the third embodiment will be described below.

[0177] (Configuration Example of Pixel Circuit) Fig.19 is a diagram showing an example of a circuit configuration of a pixel circuit 250 according to a modification 2 of the third embodiment. This is different from the solid-state imaging device 200 according to the modification 1 of the third embodiment in that one end of the second transfer transistor 112 is connected to the photoelectric conversion element 101a. In addition, according to this connection, the second capacitance connection transistor 115 is connected between one end of the third accumulation section 111 and the node n16. Therefore, the charge is transferred through one transistor instead of two transistors, and therefore, in addition to the effect of the modification 1 of the third embodiment, the effect of further improving the transfer efficiency can be obtained.

[0178] [Fourth embodiment] The solid-state imaging device 200 according to the fourth embodiment is different from the solid-state imaging device 200 according to the first to third embodiments in that the pixel circuit 250 is composed of two substrates. The differences of the fourth embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0179] Fig. 20 1 is a diagram showing a construction example of a pixel circuit 250 according to a modification example 3 of the first embodiment. Here, a construction is formed in which a first substrate and a second substrate are divided along line L190. It is known that the SN ratio during signal conversion increases as the capacitance of the first accumulator 102 becomes a low capacitance. In addition, a connection is made so that a diffusion layer connected to the amplifier transistor (AMP) in the comparator 103a is located on the first substrate. Similarly, a connection is made so that a polysilicon (POLY) gate of a MOS transistor connected to the amplifier transistor (AMP) in the comparator 103a is also located on the first substrate. The comparator 103a has a current mirror including two transistors (PTR1, PTR2). The current mirror is arranged on the second substrate.

[0180] Fig.21 2 is a diagram showing a configuration example of a first substrate and a second substrate. For example, the first substrate 200a and the second substrate 200b may be connected by a Cu-Cu interconnect. The connection may be performed by connecting parts such as VIA (vertical interconnect via), bumps, etc. Fig. 22 It shows Fig.11 The pixel circuit 250 shown is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Here, a configuration is formed in which the first substrate 200a and the second substrate 200b are divided along the line L192. Fig.23 It shows Fig.15 The pixel circuit 250 shown is a diagram of a configuration example in which the pixel circuit 250 is composed of two substrates. Here, a configuration is formed in which the first substrate 200a and the second substrate 200b are divided along the line L194. Fig.24 It shows Fig.19 FIG. 2 is a diagram showing an example of a configuration of a pixel circuit 250. Here, a configuration is formed in which the first substrate 200a and the second substrate 200b are divided along the L196 line. With such a configuration, the size of the solid-state imaging device 200 can be further reduced.

[0181] [Fifth embodiment] The solid-state imaging device 200 according to the fifth embodiment is different from the solid-state imaging device 200 according to the first to third embodiments in that the pixel circuit 250 is composed of two substrates or three substrates. The differences of the fifth embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0182] Fig.25 200a, the second substrate 200b, and the third substrate 200c are connected to each other through a Cu-Cu interconnection.

[0183] Fig.26 It shows Figure 4 The pixel circuit 250 shown in the figure is a configuration example composed of two substrates. Here, a first substrate (see FIG. 1 ) is formed in which the pixel circuit 250 is divided into two substrates along the line L200. Fig.25 ) and a second substrate (see Fig.25 ) structure. Fig. 27 It shows Fig.10 The pixel circuit 250 shown in the figure is a configuration example composed of three substrates. Here, a first substrate (see FIG. 204 ) is formed in which the first substrate is divided along lines L202 and L204. Fig.25 ), the second substrate (see Fig.25 ) and the third substrate (see Fig.25 ) structure. Fig.28 It shows Fig.14 The pixel circuit 250 shown in the figure is a configuration example composed of two substrates. Here, a first substrate is formed in which the first substrate is divided along lines L206 and L208 (see Fig.25 ) and a second substrate (see Fig.25 ) structure. Fig.29 It shows Fig.14 The pixel circuit 250 shown in the figure is a configuration example composed of three substrates. Here, a first substrate (see FIG. 250 ) is formed in which the first substrate is divided along lines L210 and L220. Fig.25 ), the second substrate (see Fig.25 ) and the third substrate (see Fig.25 With such a configuration, the size of the solid-state imaging device 200 can be further reduced.

[0184] [Sixth embodiment] The solid-state imaging device 200 according to the sixth embodiment is different from the solid-state imaging device 200 according to the first embodiment in that a comparator 300, a counter 261, and a latch are arranged in the column signal processing section 160 for each pixel circuit 250. The differences of the sixth embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0185] Fig.30 2 is a diagram schematically showing a part of the imaging device 200. Fig.30As shown, a comparator 300, a counter 261 and a latch are arranged in the column signal processing unit 160 for each pixel circuit 250. In addition, the comparator 300 can be used as the comparator 103a (see Figure 5 This enables the circuit scale to be reduced, and area reduction can be achieved.

[0186] [Seventh Implementation Plan] The solid-state imaging device 200 according to the seventh embodiment is different from the solid-state imaging device 200 according to the first embodiment in having a normal shooting mode and a calibration mode. The differences of the seventh embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0187] Normal shooting mode (see Figure 7 ) has an accumulation period and a reading period, and is a mode in which normal shooting is performed. In contrast, the calibration mode is a mode for acquiring information for performing calibration on characteristic differences of individual pixel circuits before normal shooting.

[0188] Due to manufacturing differences of transistors in the determination unit 103, there are differences in the inversion threshold from one pixel to another, so in this embodiment, a calibration mode is used to find its threshold. Each mode is set according to an instruction input via the operation unit (140). In each mode, the drive signal supplied to each pixel circuit 250 via the vertical scanning circuit 210 is changed according to the mode.

[0189] (Operation example of calibration mode) Fig.31 1 is a timing chart of an operation example in the calibration mode according to the present embodiment. The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the potential L18 of the variable voltage power supply VRS, and the potential L20 of the first accumulating section 102. Note that in the solid-state imaging device 200 according to the seventh embodiment, the variable voltage power supply VRS is connected to the drain of the reset transistor 104a (see Figure 5 ). In normal shooting mode (see Figure 7 ), the variable voltage source VRS supplies a current to the drain of the reset transistor 104a (see Figure 5 ) supplies a fixed potential VDD, and in the calibration mode, supplies a fixed potential VDD to the drain of the reset transistor 104a (see Figure 5 ) supplies a potential L18 that changes in time series. Note that the potential of the variable voltage power supply VRS according to the present embodiment corresponds to a reset potential.

[0190] As mentioned above, at node n10 (see Figure 5) crosses the threshold potential Vth to the downward side, the comparator 103a outputs the first signal of low level, and the node n10 (see Figure 5 ) crosses the threshold potential Vth to the lower side, the comparator 103a outputs a high-level first signal. In addition, when the first signal is at a high level, the reset transistor 104a outputs a high-level signal. Note that the node n10 (see Figure 5 ) corresponds to the first accumulating section 102.

[0191] like Fig.31 As shown, at time t0, the potential L18 of the variable voltage source VRS starts to increase. At the beginning, the potential of the node n10 is in a state of crossing the threshold potential Vth to the lower side, and therefore the first signal is at a high level, and the drive signal RST is at a high level. Since the drive signal RST is at a high level, the reset transistor 104a maintains the on state.

[0192] As the potential L18 of the variable voltage power supply VRS further continues to increase, the potential of the node n10 at time t1 is in a state of crossing the threshold potential Vth to the upper side. Therefore, the first signal becomes a low level, and the drive signal RST becomes a low level. Therefore, the reset transistor 104a enters a non-conducting state. Thereafter, the potential L18 of the variable voltage power supply VRS continues to increase, but the reset transistor 104a is in a non-conducting state, and therefore, the potential of the node n10 is maintained at the threshold potential Vth.

[0193] Then, at time t2, the read period is reached. During the read period, the potential L18 of the variable voltage power supply VRS is maintained at the power supply potential VDD. Then, at time t3, due to the reset circuit 108 (see Figure 5 ) outputs the initialization signal SHT, the drive signal RST becomes a high level signal, and the node n10 (see Figure 5 ) is initialized to the power supply potential VDD.

[0194] At this time, the potential of the node n10 corresponding to the threshold potential Vth between the time t2 and the time t3 is read out to the reading circuit 260 as the Vs level. In contrast, the potential of the node n10 corresponding to the power supply potential VDD between the time t4 and the time t5 is read out to the reading circuit 260 as the Vr level. Therefore, the difference between the potential of the Vs level and the potential of the Vr level is generated as the threshold potential Vth of the pixel circuit 250. The memory 282 stores the threshold potential Vth for the coordinates (x, y) of each pixel circuit 250. The capacitance of the first accumulating section 102 is known, and therefore the residual charge amount corresponding to one count of the counter 105a can be accurately calculated from the information of the threshold potential Vth and the capacitance of the first accumulating section 102. Therefore, the coefficient K1 is calibrated and stored as K1 (x, y) for the coordinates (x, y) of each pixel circuit 250. That is, the image signal G(x, y) of the pixel circuit 250 can be more accurately calculated as [K1(x, y)×(number of resets)+K2×(value of the digital signal Sa)].

[0195] As described above, according to the present embodiment, in the calibration mode, the potential L18 of the variable voltage power supply VRS increases from the lower side of the threshold potential Vth. Therefore, by the continued increase of the potential L18 of the variable voltage power supply VRS, the potential of the node n10 reaches a state of crossing the threshold potential Vth to the upper side, the reset transistor 104a becomes a non-conducting state, and the potential of the node n10 is maintained at the state of the threshold potential Vth. Therefore, the information of the threshold potential Vth can be obtained for each pixel circuit 250, and the coefficient K1 can be calibrated and stored as K1(x, y) for the coordinates (x, y) of each pixel circuit 250. Therefore, the image signal G(x, y) of the pixel circuit 250 can be more accurately calculated as [K1(x, y)×(number of resets)+K2×(value of the digital signal Sa)].

[0196] [Eighth Implementation Plan] The solid-state imaging device 200 according to the eighth embodiment is different from the solid-state imaging device 200 according to the seventh embodiment in that the calibration mode is performed while the potential change slope of the variable voltage power supply VRS is changed a plurality of times. The differences of the eighth embodiment with respect to the solid-state imaging device 200 according to the first embodiment will be described below.

[0197] (Operation example of calibration mode) Fig.321 is a timing chart of an operation example of the calibration mode according to the present embodiment. The horizontal axis represents time, and the vertical axis represents the drive signal EXP, the drive signal RST, the potentials L22 and L24 of the variable voltage power supply VRS, and the potentials L26 and L28 of the first accumulating section 102. The potential L22 and the potential L26 show a state in which the potential change slope is greater than the potential change slope of the potential L24 and the potential L28.

[0198] There are cases where the determination threshold changes when the potential change slope of the first accumulating section 102 changes due to characteristics such as operation delay of the comparator 103a. For this reason, in the calibration data acquisition mode, calibration data is acquired multiple times while changing the sweep slope of the variable voltage power supply VRS.

[0199] In the case where the count value of the counter 105a is small, the illumination is low, and the potential change slope at the first accumulating section should be small, so a value with a small inclination can also be used as calibration data. In contrast, in the case where the count value is large, the illumination is high, so a value with a large inclination can be used as calibration data. Therefore, it is possible to follow the fluctuation of the determination threshold value caused by the change in the slope of the potential of the first accumulating section 102.

[0200] [4. Application examples] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, an unmanned aerial vehicle, a ship, a robot, a construction machine, an agricultural machine (tractor), etc.

[0201] Fig.33 7000 is a block diagram showing a schematic configuration example of a vehicle control system 7000 as an example of a mobile control system to which the technology of the present disclosure is applicable. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. Fig.33In the example shown, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. For example, the communication network 7010 that interconnects the above-mentioned plurality of control units may be an in-vehicle communication network that complies with an optional standard such as a controller area network (CAN), a local interconnect network (LIN), a local area network (LAN), FlexRay (registered trademark), or the like.

[0202] Each control unit includes: a microcomputer that performs calculations according to various programs; a storage unit that stores programs executed by the microcomputer and parameters used for various calculations; and a drive circuit that drives various devices that are controlled. Each control unit also includes: a network interface (I / F: interface) that is used to perform communication between the control unit and other control units via the communication network 7010; and a communication I / F that is used to perform communication between the control unit and devices or sensors inside and outside the vehicle using wired or wireless communication. Fig.33 76, as the functional structure of the integrated control unit 7600, a microcomputer 7610, a general communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, a sound / image output unit 7670, an in-vehicle network I / F 7680, and a storage unit 7690 are shown. Similarly, other control units also include a microcomputer, a communication I / F, a storage unit, and the like.

[0203] The drive system control unit 7100 controls the operation of devices related to the vehicle drive system according to various programs. For example, the drive system control unit 7100 functions as a control device for devices such as: a drive force generating device such as an internal combustion engine or a traction motor for generating a vehicle drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a vehicle braking force. The drive system control unit 7100 can also function as a control device for an antilock brake system (ABS) or an electronic stability control system (ESC).

[0204] The vehicle state detection unit 7110 is connected to the drive system control unit 7100. Examples of the vehicle state detection unit 7110 include at least one of the following: a gyro sensor for detecting the angular velocity of the axial rotational motion of the vehicle body; an acceleration sensor for detecting the acceleration of the vehicle; and a sensor for detecting the operation amount of the accelerator pedal, the operation amount of the brake pedal, the steering angle of the steering wheel, the engine speed, or the wheel speed, etc. The drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle state detection unit 7110, and controls the internal combustion engine, the traction motor, the electric steering device, the brake device, etc.

[0205] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for devices such as: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, taillights, brake lights, turn indicators, fog lights, etc. In this case, the body system control unit 7200 is capable of receiving input of radio waves emitted from a portable device that replaces the key or signals from various switches. The body system control unit 7200 receives input of these radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0206] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source of the traction motor, according to various programs. For example, information such as battery temperature, battery output potential, battery charge state, etc. is input to the battery control unit 7300 from a battery device including the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculation processing, and performs control such as temperature adjustment control of the secondary battery 7310 or control of a cooling device included in the battery device.

[0207] The vehicle exterior information detection unit 7400 detects external information of a vehicle equipped with the vehicle control system 7000. For example, the vehicle exterior information detection unit 7400 is connected to at least one of the camera unit 7410 and the vehicle exterior information detection unit 7420. The camera unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. For example, the vehicle exterior information detection unit 7420 includes at least one of the following: an environmental sensor for detecting current weather or atmospheric conditions; and a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0208] For example, the environmental sensor may be at least one of the following: a raindrop sensor for detecting rainy days; a fog sensor for detecting fog; a sunshine sensor for detecting the degree of sunshine; and a snow sensor for detecting snowfall. The surrounding information detection sensor may be at least one of the following: an ultrasonic sensor; a radar device; and a LIDAR device (such as a light detection and ranging device, or a laser imaging detection and ranging device). The camera unit 7410 and the vehicle exterior information detection unit 7420 may each be configured as an independent sensor or device, or may be configured as a device in which a plurality of sensors or a plurality of devices are integrated.

[0209] Now, Fig.34 An example of the installation position of the camera unit 7410 and the vehicle exterior information detection unit 7420 is shown. For example, the camera units 7910, 7912, 7914, 7916 and 7918 are respectively arranged at least one of the front nose, side mirrors, rear bumper, trunk door and the upper part of the windshield in the vehicle compartment of the vehicle 7900. The camera unit 7910 arranged at the front nose and the camera unit 7918 arranged at the upper part of the windshield in the vehicle compartment mainly obtain the image in front of the vehicle 7900. The camera units 7912 and 7914 arranged at the side mirrors mainly obtain the image of the side of the vehicle 7900. The camera unit 7916 arranged at the rear bumper or the trunk door mainly obtains the image of the rear of the vehicle 7900. The camera unit 7918 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect the front driving vehicle, pedestrians, obstacles, signal lights, traffic signs or lane demarcation lines, etc.

[0210] Notice, Fig.34 An example of the photographing range of each of the camera units 7910, 7912, 7914, and 7916 is shown. The photographing range a represents the photographing range of the camera unit 7910 disposed at the front nose. The photographing ranges b and c represent the photographing ranges of the camera units 7912 and 7914 disposed at the side mirrors, respectively. The photographing range d represents the photographing range of the camera unit 7916 disposed at the rear bumper or the trunk door. For example, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained by superimposing the image data captured by the camera units 7910, 7912, 7914, and 7916.

[0211] For example, the vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, and 7930 respectively disposed at the front, rear, side, corner, and upper portion of the windshield in the vehicle 7900 may be ultrasonic sensors or radar devices. For example, the vehicle exterior information detection units 7920, 7926, and 7930 disposed at the front nose of the vehicle 7900, at the rear bumper or trunk door of the vehicle 7900, and at the upper portion of the windshield in the vehicle 7900 may be LIDAR devices. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect vehicles, pedestrians, obstacles, etc. traveling ahead.

[0212] Return to Fig.33 The description continues. The vehicle exterior information detection unit 7400 causes the camera unit 7410 to capture an image of the outside of the vehicle and receive the captured image data. In addition, the vehicle exterior information detection unit 7400 receives the detected information from the vehicle exterior information detection unit 7420 connected thereto. In the case where the vehicle exterior information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the vehicle exterior information detection unit 7400 transmits ultrasonic waves or electromagnetic waves, etc., and receives information of the received reflected waves. Based on the received information, the vehicle exterior information detection unit 7400 can perform object detection processing or distance detection processing on objects such as pedestrians, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the vehicle exterior information detection unit 7400 can perform environmental recognition processing for identifying rainfall, fog, road conditions, etc. Based on the received information, the vehicle exterior information detection unit 7400 can calculate the distance to the object outside the vehicle.

[0213] In addition, based on the received image data, the vehicle exterior information detection unit 7400 can perform image recognition processing or distance detection processing for identifying pedestrians, vehicles, obstacles, signs or text on the road surface. The vehicle exterior information detection unit 7400 can perform processing such as distortion correction and position alignment on the received image data, and can synthesize the image data captured by different camera units 7410 to generate a bird's-eye view image or a panoramic image. The vehicle exterior information detection unit 7400 can use the image data captured by different camera units 7410 to perform viewpoint conversion processing.

[0214] The in-vehicle information detection unit 7500 detects information inside the vehicle. For example, the in-vehicle information detection unit 7500 is connected to a driver state detection unit 7510 for detecting the driver's state. The driver state detection unit 7510 may include a camera for photographing the driver, a biosensor for detecting the driver's biometric information, a microphone for performing sound collection of voices in the vehicle compartment, etc. For example, the biosensor is arranged on the surface of the seat, or in the steering wheel, etc., and is used to detect the biometric information of the occupant sitting in the seat or the biometric information of the driver holding the steering wheel. Based on the detection information input from the driver state detection unit 7510, the in-vehicle information detection unit 7500 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver has fallen asleep. The in-vehicle information detection unit 7500 can subject the collected voice signal to processing such as noise elimination processing.

[0215] The integrated control unit 7600 generally controls the operations within the vehicle control system 7000 according to various programs. The integrated control unit 7600 is connected to the input unit 7800. For example, the input unit 7800 is implemented by devices such as a touch panel, a button, a microphone, a switch, a joystick, etc. that can be operated by the occupant for input. Data obtained by voice recognition of the voice input via the microphone can be input to the integrated control unit 7600. For example, the input unit 7800 can be a remote control device using infrared or other radio waves, or can be an external connection device such as a mobile phone or a personal digital assistant (PDA) that is compatible with the operation of the vehicle control system 7000. For example, the input unit 7800 can be a camera. In this case, the occupant can input information through gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant can be input. In addition, for example, the input unit 7800 may include an input control circuit or the like that generates an input signal based on information input by an occupant or the like by using the above-mentioned input unit 7800, and outputs the generated input signal to the integrated control unit 7600. The occupant or the like inputs various data to the vehicle control system 7000 or gives instructions for processing operations by operating the input unit 7800.

[0216] The storage unit 7690 may include a read only memory (ROM) for storing various programs executed by the microcomputer, and a random access memory (RAM) for storing various parameters, operation results, sensor values, etc. In addition, the storage unit 7690 may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, or a magneto-optical storage device.

[0217] The general communication I / F 7620 is a general communication I / F that plays a role of relaying communication between various devices existing in the external environment 7750. The general communication I / F 7620 may implement a communication protocol such as a cellular communication protocol such as GSM (registered trademark) (global system for mobile communications), WiMAX (registered trademark) (worldwide interoperability for microwave access), LTE (registered trademark) (long term evolution) or LTE-A (LTE-advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark) (wireless fidelity)) or Bluetooth (registered trademark, etc.). For example, the general communication I / F 7620 may be connected to a device (e.g., an application server or a control server) existing on an external network (e.g., the Internet, a cloud network, or an enterprise operator-specific network) via a base station or an access point. In addition, for example, the general communication I / F 7620 can be connected to a terminal device existing near the vehicle (for example, the terminal device is a terminal device of a driver, pedestrian or store, or an MTC (machine type communication) terminal device) using P2P (peer to peer) technology.

[0218] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol developed for the purpose of use in a vehicle. For example, the dedicated communication I / F 7630 may implement a communication protocol that is a combination of IEEE802.11p as a lower layer and IEEE 1609 as an upper layer, namely WAVE (wireless access in vehicle environment), DSRC (dedicated short-range communications), or a standard protocol such as a cellular communication protocol. The dedicated communication I / F 7630 generally performs V2X communication, which is a concept that includes one or more of vehicle-to-vehicle communication, road-to-vehicle communication (vehicle-to-infrastructure), vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0219] For example, the positioning unit 7640 performs positioning by receiving a GNSS signal (e.g., a GPS signal from a GPS (global positioning system) satellite) from a global navigation satellite system (GNSS: global navigation satellite system), and generates position information including the latitude, longitude, and altitude of the vehicle. Incidentally, the positioning unit 7640 may clarify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal device having a positioning function, such as a mobile phone, a personal handyphone system (PHS: personal handyphone system), or a smart phone.

[0220] For example, the beacon receiving unit 7650 receives radio waves or electromagnetic waves emitted from a radio station installed on the road, etc., thereby obtaining information such as the current position, traffic congestion, road closure, or required time. Incidentally, the function of the beacon receiving unit 7650 can be included in the above-mentioned dedicated communication I / F 7630.

[0221] The vehicle-mounted device I / F 7660 is a communication interface that serves as a relay connection between the microcomputer 7610 and various vehicle-mounted devices 7760 present in the vehicle. The vehicle-mounted device I / F 7660 can establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (near field communication) or WUSB (wireless universal serial bus). In addition, the vehicle-mounted device I / F 7660 can also establish a wired connection such as USB (universal serial bus), HDMI (registered trademark) (high-definition multimedia interface), or MHL (mobile high-definition link) via a connection terminal not shown (if necessary, it can also be connected by a cable). For example, the vehicle-mounted device 7760 may include at least one of a mobile device or wearable device owned by an occupant and an information device loaded into or attached to the vehicle. The vehicle-mounted device 7760 may also include a car navigation device for performing a route search to an optional destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760 .

[0222] The in-vehicle network I / F 7680 is an interface that plays a role of relaying communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals and the like according to a predetermined protocol supported by the communication network 7010.

[0223] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle-mounted device I / F 7660, and the vehicle-mounted communication I / F 7680. For example, the microcomputer 7610 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information obtained about the inside and outside of the vehicle, and output a control instruction to the drive system control unit 7100. For example, the microcomputer 7610 can perform cooperative control aimed at realizing the functions of ADAS (Advanced Driver Assistance System), the functions of which include: vehicle collision avoidance or collision mitigation; follow-up driving based on the distance between vehicles; vehicle constant speed driving; vehicle collision warning; and vehicle lane departure warning, etc. In addition, microcomputer 7610 can control the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings, thereby performing cooperative control such as automatic driving that enables the vehicle to drive autonomously without relying on the driver's operation.

[0224] The microcomputer 7610 can generate three-dimensional distance information between the vehicle and nearby objects such as buildings and pedestrians, etc., and create local map information including nearby information about the current position of the vehicle based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle-mounted device I / F 7660, and the vehicle-mounted network I / F 7680. In addition, the microcomputer 7610 can also predict dangers such as a collision of the vehicle, the approach of pedestrians, etc., or the entry into a road where vehicles are prohibited from passing, based on the obtained information, and generate a warning signal. For example, the warning signal can be a signal for generating an alarm sound or lighting a warning light.

[0225] The sound / image output unit 7670 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.33In the example, as output devices, an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are shown. For example, the display unit 7720 may include at least one of an onboard display and a head-up display. The display unit 7720 may have an augmented reality (AR) display function. The output device may be a device other than these devices, for example, it may be: a headset; a wearable device such as a glasses-type display worn by an occupant; a projector; or a lamp, etc. In the case where the output device is a display device, the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or the information received from other control units in various formats such as text, images, tables, charts, etc. In addition, in the case where the output device is an audio output device, the audio output device converts an audio signal containing reproduced audio data or sound data into an analog signal, and outputs the analog signal audibly.

[0226] Note that Fig.33 In the example shown, at least two of the control units interconnected via the communication network 7010 can be integrated into one control unit. Alternatively, an individual control unit can be composed of multiple control units. In addition, the vehicle control system 7000 may include other control units not shown. In addition, in the above description, part or all of the functions undertaken by a certain control unit can be undertaken by other control units. In other words, as long as information can be sent and received via the communication network 7010, a configuration can be adopted in which any one of the control units performs a predetermined operation process. Similarly, a configuration can also be adopted in which a sensor or device connected to any one of the control units can be connected to other control units, and multiple control units can send and receive detection information to each other via the communication network 7010.

[0227] Note that for reference Figure 1 The computer program for each function of the camera device 1 according to the first embodiment described above can be installed on any control unit, etc. In addition, a computer-readable recording medium for storing such a computer program can also be provided. For example, the recording medium includes a magnetic disk, an optical disk, a magneto-optical disk, a flash memory, etc. In addition, for example, the above-mentioned computer program can be distributed via a network instead of using a recording medium.

[0228] In the vehicle control system 7000, referring to Figure 1 The imaging device 1 according to the first embodiment described above can be applied to Fig.33 The integrated control unit 7600 in the application example shown. For example, the imaging device 1 corresponds to the imaging unit 7410. For example, the dynamic range of the imaging unit 7410 can be expanded.

[0229] Note that this technology can adopt the following technical solutions. (1) A light detection device comprising: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit configured to count the number of times the first signal is output by the comparator; and The amplifier is connected to the first node and outputs a first analog signal.

[0230] (2) The light detection device according to (1), further comprising: an analog-to-digital conversion unit, which generates a digital signal based on the first analog signal; and A signal processing unit generates an image signal based on: the number of times the first signal is output from the comparator; and the digital signal.

[0231] (3) The light detection device according to (1) or (2), further comprising: A first transistor is connected between the first node and the photoelectric conversion unit.

[0232] (4) The light detection device according to (2) or (3), wherein: After the amplifier outputs the first analog signal, the reset unit resets the first node. After the reset unit resets the first node, the amplifier unit amplifies the potential of the first node, and the amplifier unit outputs a second analog signal to the analog-to-digital converter, and The analog-to-digital conversion section generates the digital signal based on the first analog signal and the second analog signal.

[0233] (5) The light detection device according to (4), wherein: The amplification section outputs the first analog signal after a sequence in which the first transistor is set to a conductive state and then set to a non-conductive state.

[0234] (6) The light detection device according to any one of (3) to (5), further comprising: a first charge holding portion connected to the photoelectric conversion portion via the first node; and A second charge holding portion is connected to the first node in parallel with the first charge holding portion.

[0235] (7) The light detection device according to (6), wherein The first charge holding portion is connected to the first node via a second transistor, and The second transistor is set to a conducting state during a first period, and the second transistor is set to a non-conducting state during a second period different from the first period.

[0236] (8) The light detection device according to (7), wherein: The amplifier outputs a third analog signal during the second period, and outputs a fourth analog signal after the first transistor is set to an on state.

[0237] (9) The light detection device according to (8), wherein: In the first period, the amplifier outputs the first analog signal after the first transistor is set to an on state, and outputs the second analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, and the fourth analog signal.

[0238] (10) The light detection device according to (9), further comprising: A third charge holding unit is connected to the first node via a third transistor.

[0239] (11) The light detection device according to (10), wherein: The amplifier outputs a fifth analog signal during a period in which the second transistor and the third transistor are set to an on state, and outputs a sixth analog signal after the first transistor is set to an on state, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

[0240] (12) The light detection device according to (10), wherein: The amplifier outputs a fifth analog signal during a period in which the second transistor and the third transistor are set to an on state, and outputs a sixth analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

[0241] (13) The light detection device according to (12), wherein: The reset unit is composed of a fourth transistor connected between the first node and the power supply unit. The channel potential of the second transistor in the non-conducting state is greater than the channel potential of the third transistor in the non-conducting state, and A channel potential of the fourth transistor in a non-conducting state is greater than a channel potential of the second transistor in a non-conducting state.

[0242] (14) The light detection device according to any one of (1) to (13), wherein: The first accumulation capacitor is composed of a metal-insulator-metal capacitor and is connected to the first node.

[0243] (15) The light detection device according to any one of (1) to (14), wherein: The photoelectric conversion unit is arranged in the first substrate, and The counting section is arranged in a second substrate stacked with the first substrate.

[0244] (16) The light detection device according to (15), wherein: The amplifying section includes a first amplifying transistor and a selecting transistor, The first amplifying transistor is arranged in the first substrate, and The selection transistor is arranged in the second substrate.

[0245] (17) The light detection device according to (15) or (16), wherein: The comparator includes a second amplifying transistor and a current mirror, The second amplifying transistor is arranged in the first substrate, and The current mirror is arranged in the second substrate.

[0246] (18) The light detection device according to any one of (1) to (17), wherein: The photoelectric conversion portion has a predetermined capacitance for accumulating charges, and The charges overflow to the first node when exceeding the predetermined capacitance.

[0247] (19) The light detection device according to any one of (1) to (18), wherein: The reset unit is composed of a fourth transistor, and the fourth transistor is connected between the first node and a power supply unit.

[0248] (20) An electronic device comprising: Optical systems; and light detection device, Wherein, the light detection device comprises: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit for counting the number of times the first signal is output by the comparator; as well as The amplifier is connected to the first node and outputs a first analog signal.

[0249] (21) An image sensor comprising: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit configured to count the number of times the first signal is output by the comparator; and The amplifier is connected to the first node and outputs a first analog signal.

[0250] Aspects of the present disclosure are not limited to the above-mentioned embodiments, but may also include various modifications that can be thought of by those skilled in the art. The effects of the present disclosure are also not limited to the above content. That is, various additions, modifications and partial deletions may be made without departing from the conceptual spirit and essence of the present disclosure derived from the contents specified in the claims and their equivalents.

[0251] [Explanation of Reference Numerals] 1: Camera device 101: Photoelectric conversion unit 102: First Accumulation Section 103a: Comparator 104: Reset unit 104a: Reset transistor 105: Counting unit 107: Transfer transistor 109: Second Accumulation 111: The Third Cumulative Part 115: Capacitor connected to transistor 200: Solid-state imaging device 260: Reading Circuit 280: Signal Processing Department

Claims

1. A light detection device, comprising: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit for counting the number of times the first signal is output by the comparator; as well as The amplifier is connected to the first node and outputs a first analog signal.

2. The light detection device according to claim 1, further comprising: an analog-to-digital conversion unit, which generates a digital signal based on the first analog signal; and A signal processing unit generates an image signal based on: the number of times the first signal is output from the comparator; and the digital signal.

3. The light detection device according to claim 2, further comprising: A first transistor is connected between the first node and the photoelectric conversion unit.

4. The light detection device according to claim 3, wherein: After the amplifier outputs the first analog signal, the reset unit resets the first node. After the reset unit resets the first node, the amplifier unit amplifies the potential of the first node, and the amplifier unit outputs a second analog signal to the analog-to-digital converter, and The analog-to-digital conversion section generates the digital signal based on the first analog signal and the second analog signal.

5. The light detection device according to claim 4, wherein: The amplification section outputs the first analog signal after a sequence in which the first transistor is set to a conductive state and then set to a non-conductive state.

6. The light detection device according to claim 3, further comprising: a first charge holding portion connected to the photoelectric conversion portion via the first node; and A second charge holding portion is connected to the first node in parallel with the first charge holding portion.

7. The light detection device according to claim 6, wherein: The first charge holding portion is connected to the first node via a second transistor, and The second transistor is set to a conducting state during a first period, and the second transistor is set to a non-conducting state during a second period different from the first period.

8. The light detection device according to claim 7, wherein: The amplifier outputs a third analog signal during the second period, and outputs a fourth analog signal after the first transistor is set to an on state.

9. The light detection device according to claim 8, wherein: In the first period, the amplifier outputs the first analog signal after the first transistor is set to an on state, and outputs the second analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, and the fourth analog signal.

10. The light detection device according to claim 9, further comprising: A third charge holding unit is connected to the first node via a third transistor.

11. The light detection device according to claim 10, wherein: The amplifier outputs a fifth analog signal during a period in which the second transistor and the third transistor are set to an on state, and outputs a sixth analog signal after the first transistor is set to an on state, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

12. The light detection device according to claim 10, wherein: The amplifier outputs a fifth analog signal during a period in which the second transistor and the third transistor are set to an on state, and outputs a sixth analog signal after the first node is set to the reset potential, and The analog-to-digital conversion section generates the digital signal based on the first analog signal, the second analog signal, the third analog signal, the fourth analog signal, the fifth analog signal, and the sixth analog signal.

13. The light detection device according to claim 12, wherein: The reset unit is composed of a fourth transistor connected between the first node and the power supply unit. The channel potential of the second transistor in the non-conducting state is greater than the channel potential of the third transistor in the non-conducting state, and A channel potential of the fourth transistor in a non-conducting state is greater than a channel potential of the second transistor in a non-conducting state.

14. The light detection device according to claim 1, wherein The first accumulation capacitor is composed of a metal-insulator-metal capacitor and is connected to the first node.

15. The light detection device according to claim 1, wherein The photoelectric conversion unit is arranged in the first substrate, and The counting section is arranged in a second substrate stacked with the first substrate.

16. The light detection device according to claim 15, wherein The amplifying section includes a first amplifying transistor and a selecting transistor, The first amplifying transistor is arranged in the first substrate, and The selection transistor is arranged in the second substrate.

17. The light detection device according to claim 15, wherein: The comparator includes a second amplifying transistor and a current mirror, The second amplifying transistor is arranged in the first substrate, and The current mirror is arranged in the second substrate.

18. The light detection device according to claim 1, wherein The photoelectric conversion portion has a predetermined capacitance for accumulating charges, and The charges overflow to the first node when exceeding the predetermined capacitance.

19. The light detection device according to claim 1, wherein: The reset unit is composed of a fourth transistor, and the fourth transistor is connected between the first node and a power supply unit.

20. Electronic equipment, including: Optical system; and light detection device, Wherein, the light detection device comprises: a photoelectric conversion unit that generates electric charge in response to receiving light; a first node connected to the photoelectric conversion unit; a comparator that outputs a first signal in response to detecting that the potential of the first node is at least a predetermined potential; a reset section that resets the first node to a reset potential in response to detecting the first signal; a counting unit configured to count the number of times the first signal is output by the comparator; and The amplifier is connected to the first node and outputs a first analog signal.

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