Semiconductor light receiving element

Abstract

This semiconductor light-receiving element (1) is provided with: a substrate (10); a semiconductor laminated part (20) that is formed on the substrate (10); and a first electrode (40) and a second electrode (50) that are electrically connected to the semiconductor laminated part (20). The semiconductor laminated portion (20) includes a light absorption layer (24) including InGaAs and including a first region (24a) of a first conductivity type, a first semiconductor layer (S1) located between the substrate (10) and the light absorption layer (24), a second semiconductor layer (S2) located on the opposite side of the substrate (10) with respect to the light absorption layer (24), and a first region (24a) of a second conductivity type formed of InP, InGaAsP, InAsP, InGaAsP, InAsP, InGaAsP, InAsP, InGaAsP, InAsP, InGaAsP, InGaAsP, InAsP, InGaAsP, InGaAsP, InAsP, InGaAsP, InGaAsP, InGaAsP, InGaAsP, InGaAsP, InGaAsP, and a capacitance reduction layer (23) of the first conductivity type, which has an arbitrary configuration of AlInGaAs and is positioned between the light absorption layer (24) and one of the first semiconductor layer (S1) and the second semiconductor layer (S2), and which has a carrier concentration of 5 * 1015 cm-3 or less and is higher than the carrier concentration of the first region (24a) of the light absorption layer (24). The band gap of the capacitance reduction layer (23) is larger than the band gap of the light absorption layer (24).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor light-receiving element. Background Art

[0002] Patent Document 1 describes a photoelectric conversion device having a stacked structure in which an n-InP substrate, a non-doped InP junction capacitance reducing layer, a non-doped InGaAs light absorbing layer, a non-doped InP junction capacitance reducing layer, and a p-InP window region are stacked in this order.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 6-275860 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In the photoelectric conversion device described in Patent Document 1, the thickness of each junction capacitance reducing layer is adjusted so that the travel time of electrons or holes is the same, thereby reducing the phase difference of the current generated by the travel of electrons and holes.

[0008] However, in a semiconductor light-receiving element such as the photoelectric conversion device described in Patent Document 1, if the potential barrier for electrons between the light-absorbing layer and the capacitance-reducing layer is large, electrons need to cross the potential barrier for detection, and response performance may deteriorate.

[0009] An object of the present disclosure is to provide a semiconductor light-receiving element capable of suppressing deterioration in response performance.

[0010] Technical solutions to solve problems

[0011] The semiconductor light-receiving element disclosed in the present invention is [1] "a semiconductor light-receiving element comprising: a substrate; a semiconductor stack portion formed on the substrate; and a first electrode and a second electrode electrically connected to the semiconductor stack portion, the semiconductor stack portion comprising: a light-absorbing layer comprising InGaAs and comprising a first region of a first conductivity type; a first semiconductor layer located between the substrate and the light-absorbing layer; a second semiconductor layer located on the opposite side of the substrate relative to the light-absorbing layer; and a first conductivity type capacitance-reducing layer comprising any one of InP, InGaAsP, InAsP, and AlInGaAs and located between one of the first semiconductor layer and the second semiconductor layer and the light-absorbing layer, the other of the first semiconductor layer and the second semiconductor layer comprising: a second region of a second conductivity type forming a PN junction with the first region of the light-absorbing layer, the first electrode being connected to the first semiconductor layer, the second electrode being connected to the second semiconductor layer, and the carrier concentration of the capacitance-reducing layer being 5×10 15 cm -3 The band gap of the capacitance-reducing layer is greater than the band gap of the light absorbing layer.

[0012] In the semiconductor light-receiving element, in the semiconductor stacking part, a first semiconductor layer, a light-absorbing layer, and a second semiconductor layer are stacked in sequence from the substrate side, and a capacitance reduction layer is interposed between one of the first semiconductor layer and the second semiconductor layer and the light-absorbing layer. In addition, the other of the first semiconductor layer and the second semiconductor layer forms a PN junction with the light-absorbing layer. Moreover, the carrier concentration of the capacitance reduction layer is higher than the carrier concentration of the first region of the first conductivity type of the light-absorbing layer. Therefore, compared with the case where the carrier concentration of the capacitance reduction layer is equal to or less than the carrier concentration of the light-absorbing layer, the barrier between the light-absorbing layer and the capacitance reduction layer for electrons becomes smaller. As a result, the deterioration of the response performance is suppressed. In addition, in the semiconductor light-receiving element, the band gap of the capacitance reduction layer is larger than the band gap of the light-absorbing layer. Therefore, the light absorbed in the light-absorbing layer is suppressed from being absorbed in the capacitance reduction layer. As a result, the generation of slow carriers is suppressed, and the reduction of the response speed is suppressed.

[0013] The semiconductor light-receiving element disclosed in the present invention may also be, [2] "the semiconductor light-receiving element according to [1], wherein the other semiconductor layer includes: a third region of the first conductivity type surrounding the second region when viewed from the stacking direction of the semiconductor stack portion". In this case, as an example, by diffusing impurities of the second conductivity type with respect to a portion of the semiconductor layer of the first conductivity type by methods such as thermal diffusion or ion implantation, it is possible to easily form a second region of the second conductivity type and a third region of the first conductivity type surrounding the second region.

[0014] The semiconductor light-receiving element of the present disclosure may also be, [3] "the semiconductor light-receiving element according to [2], wherein the second region extends from the other semiconductor layer to the interior of the light-absorbing layer". In this way, the second conductivity type semiconductor region may also extend to the interior of the light-absorbing layer.

[0015] The semiconductor light-receiving element of the present disclosure may also be, [4] "the semiconductor light-receiving element according to [1], wherein the other semiconductor layer is composed of the second region". In this case, as an example, a semiconductor layer composed of the second region of the second conductivity type can be easily formed by a method such as epitaxial growth.

[0016] The semiconductor light receiving element of the present disclosure may also be, [5] "the semiconductor light receiving element according to [4], wherein the second region includes: another light absorbing layer of the second conductivity type stacked on the light absorbing layer". In this case, the second conductivity type light absorbing layer can be in contact with the second conductivity type electrode.

[0017] The semiconductor light-receiving element of the present disclosure may also be, [6] "a semiconductor light-receiving element according to any one of [1] to [5], wherein the first semiconductor layer includes a buffer layer". In this case, the buffer layer can be used, for example, to form a contact with the first electrode, or to achieve a relaxation of strain caused by the difference in lattice constant between the substrate and the light-absorbing layer, etc., to produce various functions in the first semiconductor layer.

[0018] The semiconductor light-receiving element of the present disclosure may also be, [7] "the semiconductor light-receiving element according to [6], wherein the buffer layer has the first conductivity type, and the carrier concentration of the buffer layer is higher than the carrier concentration of the capacitance-reducing layer". In this case, the deterioration of the response performance can be reliably suppressed.

[0019] The semiconductor light receiving element of the present disclosure may also be [8] "the semiconductor light receiving element according to any one of [1] to [7], wherein the thickness of the light absorbing layer is 0.6 μm to 1.8 μm". In this case, the moving distance of electrons is shortened and the speed is increased.

[0020] The semiconductor light receiving element of the present disclosure may also be, [9] “the semiconductor light receiving element according to any one of [1] to [8], wherein the carrier concentration of the first region of the light absorbing layer is 1×10 14 cm -3 Above and 3×10 15 cm -3In this way, the carrier concentration in the first region of the light absorbing layer can be set as described above within a range lower than the carrier concentration in the second region of the capacitance reducing layer.

[0021] The semiconductor light-receiving element of the present disclosure may be

[10] "the semiconductor light-receiving element according to any one of [1] to [8], wherein the thickness of the capacitance-reducing layer is 0.1 μm to 3.0 μm". In this way, the thickness of the capacitance-reducing layer can be set within the above range.

[0022] The semiconductor light-receiving element of the present disclosure may also be,

[11] “the semiconductor light-receiving element according to any one of [1] to

[10] , wherein the carrier concentration of the capacitance-reducing layer is 1.5×10 14 cm -3 Above and 5×10 15 cm -3 In this case, the potential barrier caused by the capacitance reducing layer can be reduced, and depletion of the capacitance reducing layer when a bias is applied can be appropriately achieved.

[0023] The semiconductor light-receiving element disclosed in the present invention may also be,

[12] "a semiconductor light-receiving element according to any one of [1] to

[11] , wherein the sensitivity wavelength range of the capacitance reduction layer is 1.31 μm or less". In this case, the capacitance reduction layer can suppress absorption of light in the 1.3 μm band, the 1.55 μm band, and the 1.6 μm band, which is a wavelength band used for communication.

[0024] The semiconductor light receiving element of the present disclosure may also be,

[13] "the semiconductor light receiving element according to [6] or [7], wherein the thickness of the buffer layer is greater than or equal to 0.5 μm and less than or equal to 2.5 μm". In this way, the thickness of the buffer layer can be set to the above range.

[0025] The semiconductor light-receiving element of the present disclosure may also be,

[14] "the semiconductor light-receiving element according to any one of [6], [7], and

[13] , wherein the carrier concentration of the buffer layer is 5×10 16 cm -3 Above and 5×10 18 cm -3 In this way, the carrier concentration of the buffer layer can be set to the above range.

[0026] Effects of the Invention

[0027] According to the present disclosure, it is possible to provide a semiconductor light receiving element capable of suppressing deterioration in response performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1This is a schematic side view showing an optical device according to one embodiment.

[0029] Figure 2 yes Figure 1 A top view of the semiconductor light-receiving element shown.

[0030] Figure 3 It is along Figure 2 Cross-sectional view along line III-III.

[0031] Figure 4 It is along Figure 2 Cross-sectional view along line IV-IV.

[0032] Figure 5 It is along Figure 2 Cross-sectional view of line VV.

[0033] Figure 6 It is a cross-sectional view showing a semiconductor light-receiving element according to a modified example.

[0034] Figure 7 It is a cross-sectional view showing another modified example of a semiconductor light-receiving element.

[0035] Figure 8 A diagram showing a modified example of a method for mounting a semiconductor light-receiving element. DETAILED DESCRIPTION

[0036] Hereinafter, one embodiment will be described in detail with reference to the accompanying drawings. In addition, in each figure, the same reference numerals are attached to the same or corresponding elements, and overlapping descriptions may be omitted.

[0037] Figure 1 FIG. 1 is a schematic side view of an optical device according to one embodiment. Figure 1 As shown, the optical device A has a semiconductor light-receiving element 1. As an example, the optical device A can treat light in the 1.3 μm band (O-band (Original-band)), 1.55 μm band (C-band (Conventional-band)), and 1.6 μm band (L-band (Long-wavelength-band)) used for optical communication as a target, and can be used to convert the light into an electrical signal and output it.

[0038] The 1.3 μm band refers to, for example, a wavelength range of 1.26 μm or more and 1.36 μm or less. The 1.55 μm band refers to, for example, a wavelength range of 1.53 μm or more and 1.565 μm or less. The 1.6 μm band refers to, for example, a wavelength range of greater than 1.565 μm and 1.625 μm or less. In addition, light in a wavelength band used for communication refers to light having a peak within the wavelength range of any of the above-mentioned wavelength bands (i.e., wavelengths other than the peak may also be outside the wavelength range of the above-mentioned wavelength bands).

[0039] Therefore, the semiconductor light receiving element 1 can also be used for receiving the incident light L of at least one wavelength belonging to the above-mentioned wavelength band, and generating an electrical signal according to the incident light. The semiconductor light receiving element 1 is mounted on a sub mount A1. The light L is guided by the optical fiber A4 and focused toward the light receiving part of the semiconductor light receiving element 1 by the lens A3.

[0040] The electrical signal generated by the semiconductor light receiving element 1 is transmitted through the electrode pads (in Figure 1 etc., schematically shown by shadow) and wire input transformer impedance amplifier (TIA) A5, which is converted into voltage by transformer impedance amplifier A5 and output to the outside. In addition, here, the semiconductor light receiving element 1 is mounted on the sub-base A1 in a state where the back side 10b of the substrate 10 described later is facing the lens A3 and the optical fiber A4 side. That is, here, the semiconductor light receiving element 1 is a back-incident type that receives incident light from the substrate 10 side toward the semiconductor stack part 20 described later. More specifically, in this example, the semiconductor light receiving element 1 receives incident light from the back side 10b described later, and the light is guided from the substrate 10 side to the semiconductor stack part 20.

[0041] Figure 2 yes Figure 1 A top view of the semiconductor light-receiving element shown. Figure 3 It is along Figure 2 The cross-sectional view of line III-III. Figure 2 , 3 As shown, the semiconductor light-receiving element 1 includes a substrate 10 , a semiconductor stacked portion 20 , a first electrode 40 (a cathode in this case), and a second electrode 50 (an anode in this case).

[0042] The substrate 10 includes a semi-insulating semiconductor. Here, the substrate 10 is, for example, a semi-insulating semiconductor substrate composed of InP. The substrate 10 includes: a surface 10a, and a back surface 10b on the opposite side of the surface 10a. In addition, the substrate 10 includes: a plurality of regions RA, a region RB (first region), and a region RC arranged in sequence along the surface 10a and the back surface 10b. Region RB is a region between region RA and region RC. More specifically, region RB includes: a region RB1 on the center side, and a region RB2 located on both sides of region RB1 (region RA, RC side). Here, the back surface 10b of the substrate 10 is the incident surface of the light L, and a lens RL for focusing the light L is formed. The lens RL is formed to partially overlap with region RB2 with region RB1 as the center.

[0043] The semiconductor stack portion 20 is formed on the substrate 10. More specifically, the semiconductor stack portion 20 is formed on the surface 10a on the region RB of the substrate 10. The semiconductor stack portion 20 includes: a back surface 20b on the substrate 10 side, and a surface 20a on the opposite side of the substrate 10. The semiconductor stack portion 20 includes: a buffer layer 21, a buffer layer 22, a capacitance reduction layer 23, a light absorption layer 24, a cap layer 25, and a contact layer 26 stacked in order from the substrate 10 side. Here, the back surface 20b of the semiconductor stack portion 20 is the surface of the buffer layer 21 on the opposite side to the light absorption layer 24, and is in contact with the surface 10a of the substrate 10. In addition, the surface 20a of the semiconductor stack portion 20 is the surface of the contact layer 26 on the opposite side to the light absorption layer 24.

[0044] The buffer layer 21 has a first conductivity type (here, N type, as an example, N + Type). The buffer layer 21 is arranged to overlap with the region RB2 with the region RB1 as the center. The layers other than the buffer layer 21 of the semiconductor stack portion 20 (buffer layer 22, capacitance reduction layer 23, light absorption layer 24, cap layer 25, and contact layer 26) are arranged on the region of the buffer layer 21 that overlaps with the region RB1. Therefore, the buffer layer 21 has: a portion 21p exposed from the layers other than the buffer layer 21 of the semiconductor stack portion 20 and the protective film 60 described later, and the layers other than the buffer layer 21 of the semiconductor stack portion 20 constitute a semiconductor mesa (semiconductor mesa) M. In the semiconductor light receiving element 1, a junction with the first electrode 40 is formed in this portion 21p of the buffer layer 21. The buffer layer 21 includes, for example, InP, and as an example, N + -InP composition.

[0045] The buffer layer 22 has a first conductivity type (here, N type, as an example, N + The buffer layer 22 includes, for example, InP or InGaAsP, and as an example, N + -InP or N +The buffer layer 21 and the buffer layer 22 constitute a first semiconductor layer S1 (here, of the first conductivity type) located between the substrate 10 and the light absorbing layer 24 .

[0046] The carrier concentration of the buffer layer 22 is higher than that of the capacitance reducing layer 23 described later. As an example, the carrier concentration of the buffer layer 22 is 5×10 16 cm -3 Above and 5×10 18 cm -3 The thickness of the buffer layer 22 is, for example, not less than 0.5 μm and not more than 2.5 μm.

[0047] In addition, the buffer layers 21 and 22 may also function as strain relief layers by having a lattice constant between the lattice constant of the substrate 10 and the lattice constant of the light absorption layer 24. That is, the semiconductor stack portion 20 may also include: a plurality of strain relief layers (step layers) configured such that the lattice constant gradually approaches the lattice constant of the light absorption layer 24 as it moves from the substrate 10 toward the light absorption layer 24.

[0048] The capacitance reducing layer 23 has a first conductivity type (here, N type, as an example, N - The capacitance reduction layer 23 includes any of InP, InGaAsP, InAsP, and AlInGaAs. For example, N - -InP, N - -InGaAsP、N - -InAsP, and N - - Any structure among AlInGaAs. The capacitance reduction layer 23 is located between the first semiconductor layer S1 and the light absorbing layer 24. Here, the capacitance reduction layer 23 is in contact with the first semiconductor layer S1 and the light absorbing layer 24.

[0049] The light absorbing layer 24 has a first conductivity type (here, N type, as an example, N - Here, the light absorbing layer 24 is made of N - -In x Ga 1-xAs. The In composition x of the light absorbing layer 24 may also be greater than 0.55 (and less than 1). In this case, as an example, the In composition x is 0.59. In addition, the thickness of the light absorbing layer 24 (the thickness along the stacking direction of the semiconductor stacking part 20) is greater than 0.6μm and less than 1.8μm, and here, as an example, it is 0.7μm. In addition, the light absorbing layer 24 may also contain Al, P, Sb, N, and other materials (for example, it may also be an absorption layer of a mixed crystal of InGaAs and the material) within a band gap range of, for example, less than 0.72eV. In this case, as an example, the light absorbing layer 24 may also be composed of InGaAsP, AlGaInAs, InGaAsSb, or InGaAsN. The proportion of Al, P, Sb, and N (or other materials) mixed in InGaAs can be set to, for example, less than 5%, or less than 10%.

[0050] Here, as an example, the capacitance reducing layer 23 is 5×10 15 cm -3 The carrier concentration of the capacitance-reducing layer 23 is higher than that of the light-absorbing layer 24 in the following range. As an example, the carrier concentration of the capacitance-reducing layer 23 is 1.5×10 14 cm -3 Above and 5×10 15 cm -3 , the impurity concentration of the light absorbing layer 24 is 1×10 14 cm -3 Above and 3×10 15 cm -3 Furthermore, the capacitance reducing layer 23 has a band gap larger than the band gap of the light absorbing layer 24. When the band gap of the light absorbing layer 24 is 0.72 eV or less as described above, the band gap of the capacitance reducing layer 23 can be set to a range of more than 0.72 eV and 1.35 eV or less.

[0051] As described above, the capacitance reducing layer 23 is required to have a higher carrier concentration than the light absorbing layer 24 and to be depleted when a bias is applied. The reason for this is that, as described above, the capacitance reducing layer 23 has a larger band gap than the light absorbing layer 24, and therefore, when the carrier concentration is low, a potential barrier can be formed in the conduction band, and the movement of carriers with a large potential barrier is hindered, and thus, they may not be properly extracted.

[0052] In addition, since the capacitance-reducing layer 23 needs to be depleted when a bias is applied, the upper limit of the carrier concentration can be set to 5.0×10 15 cm -3. Furthermore, the capacitance reduction layer 23 may be a composition that does not absorb incident light (that is, the band gap may be wider than that of the light absorbing layer 24). This is because, if the capacitance reduction layer 23 absorbs incident light, carriers are generated in the capacitance reduction layer 23. The carriers are taken out as signals from the capacitance reduction layer 23 via the light absorbing layer 24, and thus become slow carriers, which may deteriorate the responsiveness characteristics. As an example, the sensitivity wavelength range of the capacitance reduction layer 23 can be set to be less than 1.31 μm.

[0053] Thus, by setting the relationship between the capacitance reducing layer 23 and the light absorbing layer 24 as described above, the capacitance can be reduced without reducing the response of carriers. As an example, the thickness of the capacitance reducing layer 23 can be set to be 0.1 μm or more and 3.0 μm or less.

[0054] In addition, in the semiconductor light-receiving element 1, the light-absorbing layer 24 is a single layer. The light-absorbing layer 24 is a single layer, which means that the light-absorbing layer 24 does not have a stacked structure composed of two or more layers with different compositions or characteristics. More specifically, the light-absorbing layer 24 is a single layer, which means, for example, that it does not have a superlattice structure composed of a plurality of layers with different compositions repeatedly stacked.

[0055] The cap layer 25 has a first conductivity type (here, N type, as an example, N - The cap layer 25 includes, for example, InP or InGaAsP. As an example, the cap layer 25 is made of N - -InP or N - -InGaAsP. The carrier concentration of the cap layer 25 is, for example, 1×10 14 cm -3 Above and 1×10 16 cm -3 The thickness of the cap layer 25 is, for example, 0.1 μm or more and 0.5 μm or less.

[0056] The contact layer 26 has a first conductivity type (here, N type, as an example, N - The contact layer 26 includes, for example, InGaAs, and as an example, N - -InGaAs. The carrier concentration of the contact layer 26 is, for example, 1×10 14 cm -3 Above and 1×10 16 cm -3 The thickness of the contact layer 26 is, for example, 0.1 μm or more and 0.2 μm or less.

[0057] The semiconductor stacked portion 20 is formed with a second conductivity type (here, P type, as an example, P +The second region 27 is formed by, for example, thermal diffusion or ion implantation. The second region 27 extends from the surface 20a of the semiconductor stack 20 toward the substrate 10 side. Here, the second region 27 is formed from the contact layer 26 to the light absorbing layer 24 via the cap layer 25. In this way, the cap layer 25 and the contact layer 26 constitute the second semiconductor layer S2 located on the opposite side of the substrate 10 relative to the light absorbing layer 24. The second semiconductor layer S2 includes a second region 27 (here, of the second conductivity type) that forms a PN junction with the light absorbing layer 24.

[0058] Here, the second region 27 is formed in a portion (e.g., a portion including the center) of the second semiconductor layer S2 in the width direction (a direction intersecting the stacking direction of the semiconductor stack portion 20). Therefore, here, the second semiconductor layer S2 includes: a third region 28 of the first conductivity type surrounding the second region 27 when viewed from the stacking direction of the semiconductor stack portion 20.

[0059] In addition, the second region 27 of the second semiconductor layer S2 may also extend from the second semiconductor layer to the inside of the light absorbing layer 24. In this case, the light absorbing layer 24 becomes a layer including: a fifth region 27a of the second conductivity type, which is an extension of the second region 27, and a first region 24a of the first conductivity type outside the fifth region 27a. In this case, when the thickness of the light absorbing layer 24 is set to 0.7 μm, for example, the fifth region 27a may be formed within a range of 0.2 μm on the side of the cap layer 25 of the light absorbing layer 24. That is, in this example, the inside of the light absorbing layer 24 includes a first region 24a of about 0.5 μm in thickness and a fifth region 27a of 0.2 μm in thickness, and a boundary between them is formed. In the fifth region 27a, P + In the case of type, as an example, the carrier concentration of the terminal is P type and becomes 1×10 17 cm -3 The following location.

[0060] On the other hand, when the second region 27 of the second semiconductor layer S2 does not reach the inside of the light absorbing layer 24, the entire light absorbing layer 24 becomes the first conductivity type first region 24a. + The carrier concentration of N-type is 1×10 17 cm -3 Above. - The carrier concentration of N-type is 3.0×10 16 cm -3 Below, it is relatively lower than N+ type. + The P-type carrier concentration is 1×10 17 cm -3 above.

[0061] Here, the semiconductor light receiving element 1 includes a protective film 60. The protective film 60 is, for example, an insulating film. A portion of the surface 20a (top surface) of the semiconductor stack portion 20 and a side surface 20s of the semiconductor stack portion 20 extending from the periphery of the surface 20a toward the substrate 10 side are covered by the protective film 60. On the other hand, the remaining portion of the surface 20a of the semiconductor stack portion 20, here, the surface of the second region 27 is exposed from the protective film 60. In addition, the second electrode 50 is formed on the portion exposed from the protective film 60 of the surface 20a, and the second electrode 50 and the second region 27 (contact layer 26) are bonded. That is, the second electrode 50 is connected to the second conductive type portion (second region 27) located on the opposite side of the substrate 10 relative to the light absorbing layer 24 in the semiconductor stack portion 20. On the other hand, the first electrode 40 is connected to the first conductive type portion 21p (the portion of the buffer layer 21 exposed from the protective film 60) located on the substrate 10 side relative to the light absorbing layer 24 in the semiconductor stack portion 20.

[0062] Figure 4 It is along Figure 2 The cross-sectional view of the line IV-IV. Figure 2 , 4 As shown, a semiconductor stack portion 70 is formed on the surface 10a of the substrate 10 via the buffer layer 21. The structure of the semiconductor stack portion 70 is the same as the structure of the semiconductor stack portion 20 other than the buffer layer 21, except that the second region 27 of the second conductivity type is not formed. The entire semiconductor stack portion 70 is covered by a protective film 60.

[0063] Here, the second electrode 50 extends from the surface 20a of the semiconductor stack portion 20 to the top surface 70a (the surface facing the opposite side of the substrate 10) of the semiconductor stack portion 70, and an anode pad 55 is formed on the top surface 70a. That is, on the top surface 70a of the semiconductor stack portion 70, an anode pad 55 electrically connected to the second electrode 50 is formed via the protective film 60.

[0064] Figure 5 It is along Figure 2 The cross-sectional diagram of the VV line. Figure 2 , 5 As shown, semiconductor stacking parts 80 and 90 are formed on the surface 10a of the substrate 10 via the buffer layer 21. The structure of the semiconductor stacking parts 80 and 90 is the same as the structure of the semiconductor stacking part 20 other than the buffer layer 21, except that the second region 27 of the second conductivity type is not formed. The entire semiconductor stacking parts 80 and 90 are covered by the protective film 60. Moreover, here, the first electrode 40 extends from the portion bonded to the buffer layer 21 to the top surface 90a (the surface on the opposite side facing the substrate 10) of the semiconductor stacking part 90, and a cathode pad 45 is formed on the top surface 90a.

[0065] That is, on the top surface 90a of the semiconductor stacked portion 90, a cathode pad 45 electrically connected to the first electrode 40 is formed via the protective film 60. On the other hand, on the top surface 80a of the semiconductor stacked portion 80, a dummy pad 100 is formed via the protective film 60. Figure 2 As shown, a pair of cathode pads 45 (and semiconductor stack portion 90 ) are formed so as to sandwich anode pad 55 (and semiconductor stack portion 70 ), and a pair of dummy pads 100 (and semiconductor stack portion 80 ) are also formed.

[0066] In the optical device A, the semiconductor light receiving element 1 is arranged so that the surface 10a of the substrate 10 faces the sub-base A1 side, that is, the back surface 10b of the substrate 10 faces the opposite side of the sub-base A1, and is mounted on the sub-base A1. Thus, a pair of cathode pads 45, anode pads 55, and a pair of dummy pads 100 are connected to the electrode pads provided on the sub-base A1. As a result, the cathode pads 45 and the anode pads 55 are connected to the electrodes electrically connected to the transformer impedance amplifier A5 on the sub-base A1.

[0067] As described above, in the semiconductor light receiving element 1 of the present embodiment, the first semiconductor layer S1, the light absorbing layer 24, and the second semiconductor layer S2 are sequentially stacked from the substrate 10 side in the semiconductor stacking part 20, and the capacitance reduction layer 23 is interposed between the first semiconductor layer S1 and the light absorbing layer 24. In addition, the second semiconductor layer S2 forms a PN junction with the light absorbing layer 24. Moreover, the carrier concentration of the capacitance reduction layer 23 is higher than the carrier concentration of the light absorbing layer 24 (the first region 24a of the first conductivity type). Therefore, compared with the case where the carrier concentration of the capacitance reduction layer 23 is equal to or less than the carrier concentration of the light absorbing layer 24, the barrier between the light absorbing layer 24 and the capacitance reduction layer 23 for electrons becomes smaller. As a result, the deterioration of the response performance is suppressed.

[0068] In the semiconductor light-receiving element 1 of the present embodiment, the band gap of the capacitance-reducing layer 23 is larger than the band gap of the light-absorbing layer 24. Therefore, light absorbed by the light-absorbing layer 24 is suppressed from being absorbed by the capacitance-reducing layer 23. As a result, the generation of slow carriers is suppressed, and a decrease in the response speed is suppressed.

[0069] In addition, in the semiconductor light-receiving element 1 of the present embodiment, the second semiconductor layer S2 includes: a third region 28 of the first conductivity type surrounding the second region 27 when viewed from the stacking direction of the semiconductor stack portion 20. In this case, as an example, the second conductivity type impurity region is diffused with respect to a part of the first conductivity type semiconductor layer by a method such as thermal diffusion or ion implantation, so that the second conductivity type second region 27 and the first conductivity type third region 28 surrounding the second region 27 can be easily formed.

[0070] In the semiconductor light receiving element 1 of the present embodiment, the second region 27 extends from the second semiconductor layer S2 to the inside of the light absorbing layer 24. In this way, the second conductivity type semiconductor region may also extend to the inside of the light absorbing layer 24.

[0071] In addition, in the semiconductor light receiving element 1 of the present embodiment, the first semiconductor layer S1 includes the buffer layers 21 and 22. Therefore, the buffer layers 21 and 22 can be used to generate various functions in the first semiconductor layer S1, for example, to form a contact with the first electrode 40 or to achieve the relaxation of strain caused by the difference in lattice constant between the substrate 10 and the light absorbing layer 24.

[0072] In the semiconductor light-receiving element 1 of the present embodiment, the buffer layer 22 has the first conductivity type, and the carrier concentration of the buffer layer 22 is higher than the carrier concentration of the capacitance-reducing layer 23. Therefore, it is possible to reliably suppress the deterioration of the response performance.

[0073] In the semiconductor light-receiving element 1 of the present embodiment, the thickness of the light-absorbing layer 24 is 0.6 μm or more and 1.8 μm or less. Therefore, the moving distance of electrons is shortened and the speed is increased.

[0074] In the semiconductor light-receiving element 1 of the present embodiment, the carrier concentration of the capacitance-reducing layer 23 is 1.5×10 14 cm -3 Above and 5×10 15 cm -3 Therefore, the potential barrier caused by the capacitance reducing layer 23 can be reduced, and depletion of the capacitance reducing layer 23 when a bias is applied can be appropriately achieved.

[0075] In the semiconductor light-receiving element 1 of the present embodiment, the sensitive wavelength range of the capacitance-reducing layer 23 is 1.31 μm or less. Therefore, the capacitance-reducing layer 23 can suppress absorption of light in the 1.3 μm band, the 1.55 μm band, and the 1.6 μm band, which is a wavelength band for communication.

[0076] The above embodiment describes one embodiment of the semiconductor light receiving element of the present invention. Therefore, the semiconductor light receiving element of the present invention can be modified and is not limited to the above one embodiment. Modifications will be described below.

[0077] Figure 6 It is a cross-sectional view showing a semiconductor light-receiving element according to a modified example. Figure 6 The cross section is equivalent to the Figure 2 The cross section of line III-III. Figure 6In the example shown, the entire second semiconductor layer S2 (ie, the cap layer 25 and the contact layer 26) is set to the second conductivity type (here, P type, as an example, P + That is, the second semiconductor layer S2 is composed of the second region 27. Such a second semiconductor layer S2 can be formed by epitaxially growing a semiconductor layer of the second conductivity type on the light absorbing layer 24, for example.

[0078] In this case, the second region 27 of the second conductivity type does not extend into the interior of the light absorbing layer 24. However, in this case, the second region 27 may include a second conductivity type (here, P type, as an example, P type) stacked on the light absorbing layer 24. + The light absorbing layer 27b corresponds to the light absorbing layer 24 and is located on the opposite side of the capacitance reducing layer 23. In this case, the entire light absorbing layer 24 becomes the first region 24a of the first conductivity type. The light absorbing layer 27b can be made of the same material as the above-mentioned material of the light absorbing layer 24, for example, including InGaAs, as an example, P + -InGaAs composition.

[0079] The thickness of the light absorbing layer 27b may be thicker or thinner than the thickness of the light absorbing layer 24. When the thickness of the light absorbing layer 27b is thinner than the thickness of the light absorbing layer 24, the response speed is improved. Figure 6 In the example shown, the contact layer 26 makes contact with the second electrode 50 , and by providing a second conductivity type light absorbing layer 27 b , the light absorbing layer 27 b can also make contact with the second electrode 50 .

[0080] Figure 7 It is a cross-sectional view showing another modified example of a semiconductor light-receiving element. Figure 7 The cross section is equivalent to the Figure 2 The cross section of line III-III. Figure 7 In the example shown, the buffer layer 21 and the buffer layer 22 have a second conductivity type (here, P type, for example P + The buffer layer 21 includes, for example, InP. + The buffer layer 22 is composed of, for example, InP or InGaAsP. + -InP or P + -InGaAsP composition.

[0081] In addition, Figure 7 In the example shown, the cap layer 25 and the contact layer 26 (the second region 27) have a first conductivity type (here, N type, for example N +The cap layer 25 includes, for example, InP or InGaAsP. As an example, the cap layer 25 is made of N + -InP or N + The contact layer 26 includes, for example, InGaAs, and as an example, N + -InGaAs composition. The conductivity types of the capacitance reducing layer 23 and the light absorbing layer 24 are the same as those in the above-mentioned embodiment.

[0082] In this way, Figure 7 In the example shown, the first semiconductor layer S1 has the second conductivity type, and the second semiconductor layer S2 is set to the first conductivity type. In addition, the capacitance reduction layer 23 is located between the light absorbing layer 24 and the second semiconductor layer S2. Therefore, in this example, the first semiconductor layer S1 includes: a second region 27 of the second conductivity type that forms a PN junction with the light absorbing layer 24.

[0083] Thus, the capacitance reducing layer 23 is located in one of the first semiconductor layer S1 and the second semiconductor layer S2 (in the above-mentioned embodiment and Figure 6 In the example of the first semiconductor layer S1, Figure 7 In the example, between the second semiconductor layer S2) and the light absorbing layer 24. In addition, the other semiconductor layer of the first semiconductor layer S1 and the second semiconductor layer S2 (in the above embodiment and Figure 6 In the example of the second semiconductor layer S2, Figure 7 In the example, the first semiconductor layer S1 includes a second conductivity type second region 27 that forms a PN junction with the light absorbing layer 24 (first region 24a).

[0084] In addition, Figure 7 In the example of , the buffer layer 22 includes: a first layer 22a provided from the region RB1 to the region RB2 of the substrate 10, and a second layer 22b formed on the region RB1 and not reaching the region RB2. The first layer 22a and the second layer 22b are stacked in sequence from the substrate 10 side. The first layer 22a includes a portion 22p exposed from the semiconductor mesa M (i.e., the second layer 22b) and the protective film 60, and the first electrode 40 is connected to the portion 22p.

[0085] Figure 8 FIG. 2 is a diagram showing a modified example of a method for mounting a semiconductor light-receiving element. Figure 8In the optical device B shown in (a), the semiconductor light receiving element 1 is mounted on the glass substrate B1 in such a manner that the back surface 10b of the substrate 10 faces the glass substrate B1, and is directly electrically connected to the transformer impedance amplifier A5 similarly mounted on the glass substrate B1 through a wire. The lens A3 and the optical fiber A4 are arranged on the surface of the glass substrate B1 opposite to the surface on which the semiconductor light receiving element 1 is mounted, and the light L is incident on the semiconductor light receiving element 1 from the back surface 10b side via the glass substrate B1. In addition, Figure 8 In the optical device C shown in (b), Figure 1 Compared with the optical device A shown in the figure, the lens A3 is omitted. Furthermore, the semiconductor light receiving element 1 may be directly mounted on the transformer impedance amplifier A5.

[0086] Thus, various methods are considered for the mounting method of the semiconductor light receiving element 1 and the optical device including the semiconductor light receiving element 1. In addition, in the above examples, the semiconductor light receiving element 1 is used as a back-incident type. However, the semiconductor light receiving element 1 can also be configured as a surface-incident type that receives incident light from the opposite side of the substrate 10 toward the semiconductor stacking portion 20. That is, the semiconductor light receiving element 1 can also be configured to receive incident light from the surface 10a side of the substrate 10. In this case, an opening can be formed in a manner that the light receiving portion is exposed relative to the second electrode 50 provided on the light receiving portion (second region 27).

[0087] Furthermore, when the semiconductor light receiving element 1 is used as a back-incident type (a method of causing light to be incident from the substrate 10 side toward the semiconductor stacking part 20), it can also be set to the following structure, that is, by reflection or refraction of the side surface of the substrate 10, the incident light is received from the side surface of the substrate 10 toward the semiconductor stacking part 20. At this time, the incident surface of the substrate 10 can also be the surface 10a or the back surface 10b. In addition, the side surface of the substrate 10 refers to a surface between the back surface 10b and the surface 10a, which intersects with the back surface 10b and the surface 10a. According to such a structure, a light path inclined relative to the thickness direction of the light absorbing layer 24 can be formed in the light absorbing layer 24, and further suppression of sensitivity reduction and speed increase can be achieved.

[0088] Furthermore, the semiconductor light receiving element 1 may be configured as a side-incident type that receives light incident from the side surface 20s of the semiconductor stacked portion 20 toward the light absorbing layer 24. In this case, the light may be incident on the side surface 20s via a waveguide formed on the substrate 10, or the light propagating in space or an optical fiber may be coupled to the end surface of the light absorbing layer 24.

[0089] In the above example, 0.7 μm is cited as the thickness of the light absorbing layer 24, and 0.59 is cited as the In composition x of the light absorbing layer 24. However, the thickness of the light absorbing layer 24 may be 1.8 μm or less, and the In composition x may be 0.55 or more. In particular, the In composition x of the light absorbing layer 24 may be 0.57 or more, and the thickness of the light absorbing layer may be 1.2 μm or less. Furthermore, the In composition x of the light absorbing layer 24 may be 0.59 or more, and the thickness of the light absorbing layer 24 may be 0.7 μm or less. In these cases, the speed is increased by further thinning the light absorbing layer.

[0090] In addition, the following lists examples of combinations of each wavelength band, the thickness of the light absorbing layer 24, and the In composition x of the light absorbing layer 24. In addition, for example, the following (5) is not limited to the C-band, and can be configured similarly in the O-band and L-band.

[0091] (1) C-band.

[0092] Sensitivity: 0.86A / W or more.

[0093] Cut-off frequency: 20 GHz or more (in the case of 28 GB, etc.).

[0094] Absorption layer thickness: 1.5μm (Details: N - Region (first region 24a) 1.3 μm, P + area (fifth area 27a) 0.2μm).

[0095] In composition x: x=0.55.

[0096] (2) C-band.

[0097] Sensitivity: 0.90A / W or more.

[0098] Cut-off frequency: 20 GHz or more (in the case of 28 GB high-sensitivity products).

[0099] Absorption layer thickness: 1.5μm (Details: N - Region (first region 24a) 1.3 μm, P + area (fifth area 27a) 0.2μm).

[0100] In composition x: x=0.57.

[0101] (3) C-band.

[0102] Sensitivity: 0.80A / W or more.

[0103] Cut-off frequency: 30 GHz or more (for 56 GB, etc.).

[0104] Absorption layer thickness: 1.2μm (Details: N - Region (first region 24a) 1.0 μm, P + area (fifth area 27a) 0.2μm).

[0105] In composition x: x=0.57.

[0106] (4) C-band.

[0107] Sensitivity 0.85A / W or above.

[0108] Cut-off frequency: 30 GHz or more (in the case of 56 GB high-sensitivity products).

[0109] Absorption layer thickness: 1.2μm (Details: N - Region (first region 24a) 1.0 μm, P + area (fifth area 27a) 0.2μm).

[0110] In composition x: x=0.59.

[0111] (5) C-band.

[0112] Sensitivity 0.7A / W or above.

[0113] Cut-off frequency: 45 GHz or higher (for 96 GB, etc.).

[0114] Absorption layer thickness: 0.7μm (Details: N - Region (first region 24a) 0.5 μm, P + area (fifth area 27a) 0.2μm).

[0115] In composition x: x=0.59.

[0116] (6) C-band.

[0117] Sensitivity 0.90A / W or above.

[0118] Cut-off frequency: 16 GHz or higher (for example, 25 GB).

[0119] Absorption layer thickness: 1.8μm (Details: N - Region (first region 24a) 1.6 μm, P + area (fifth area 27a) 0.2μm).

[0120] In composition x: x=0.55.

[0121] (7) C-band.

[0122] Sensitivity 0.93A / W or above.

[0123] Cut-off frequency: 16 GHz or higher (for example, 25 GB).

[0124] Absorption layer thickness: 1.8μm (Details: N - Region (first region 24a) 1.6 μm, P + area (fifth area 27a) 0.2μm).

[0125] In composition x: x=0.57.

[0126] In addition, in the semiconductor light receiving element 1, the semiconductor stacked portion 20 may include: a third semiconductor layer, which is provided between the light absorbing layer 24 and the cap layer 25 and has a band gap between the band gap of the light absorbing layer 24 and the band gap of the cap layer 25. The third semiconductor layer has a first conductivity type (e.g., N - Type), as an example, N - -InAsGaP composition In this case, since the band gap changes sharply between the cap layer 25 and the light absorbing layer 24, it is suppressed that carriers are difficult to extract.

[0127] In the semiconductor light receiving element 1, the buffer layer 21 may be semi-insulated and thickened by doping with Fe. In this case, the crystallinity is improved. Alternatively, in the semiconductor light receiving element 1, the buffer layer 21 may not be doped.

[0128] In addition, in the semiconductor light receiving element 1, a strain relaxation layer (buffer layer) may be used, which changes in a manner that the lattice constant approaches the lattice constant of the light absorbing layer 24 continuously as it moves from the substrate 10 toward the light absorbing layer 24. In addition, in the above-mentioned example, the semiconductor light receiving element 1 has a cap layer 25 and a contact layer 26 stacked in sequence on the light absorbing layer 24, and the second electrode 50 is connected to the surface of the second region 27 formed on the contact layer 26. However, in the semiconductor light receiving element 1, the cap layer 25 may be omitted, and the contact layer 26 may be directly formed on the light absorbing layer 24. In this case, the contact resistance of the second electrode 50 can also be reduced.

[0129] Furthermore, in the semiconductor light receiving element 1, the substrate 10 may be removed by etching or grinding, for example, and the semiconductor stacking portion 20 may be bonded to a substrate made of an insulator such as quartz or a semi-insulating semiconductor other than InP (for example, gallium arsenide, etc.). In other words, in the semiconductor light receiving element 1, the substrate 10 may include an insulator or a semi-insulating semiconductor, and may be separately formed from the semiconductor stacking portion 20, and the semiconductor stacking portion 20 may be bonded to the substrate 10 (for example, directly). In this way, the semiconductor light receiving element 1 can be manufactured by separately forming the substrate 10 and the semiconductor stacking portion 20 and bonding them, thereby achieving a larger aperture and suppressing costs by making optical components with inexpensive materials.

[0130] In addition, when the substrate 10 and the semiconductor stacking part 20, which are constructed separately from each other, are joined, direct bonding or bonding using resin can be adopted. When resin is used for joining the substrate 10 and the semiconductor stacking part 20, due to the properties of the resin, it is possible to absorb light in the target wavelength band, but if direct bonding is used, this possibility does not exist.

[0131] Industrial Applicability

[0132] A semiconductor light-receiving element capable of suppressing deterioration in response performance can be provided.

[0133] Description of Reference Numerals

[0134] 1…semiconductor light-receiving element; 10…substrate; 20…semiconductor stacking portion; 21, 22…buffer layers; 23…capacitance-reducing layer; 24…light-absorbing layer; 24a…first region; 27b…light-absorbing layer; 25…cap layer; 26…contact layer; 27…second region; 28…third region; S1…first semiconductor layer; S2…second semiconductor layer.

Claims

1. A semiconductor light receiving element, comprising: substrate; a semiconductor stacked portion formed on the substrate; and A first electrode and a second electrode electrically connected to the semiconductor stacking portion, The semiconductor stacked portion comprises: a light absorbing layer comprising InGaAs and comprising a first region of a first conductivity type; A first semiconductor layer, which is located between the substrate and the light absorbing layer; a second semiconductor layer located on an opposite side of the substrate relative to the light absorbing layer; as well as a first conductivity type capacitance reducing layer, which is made of any of InP, InGaAsP, InAsP, and AlInGaAs, and is located between one of the first semiconductor layer and the second semiconductor layer and the light absorbing layer; The other semiconductor layer of the first semiconductor layer and the second semiconductor layer includes: a second region of a second conductivity type forming a PN junction with the first region of the light absorbing layer; The first electrode is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The carrier concentration of the capacitance reduction layer is 5×10 15 cm -3 Below, and higher than the carrier concentration in the first region of the light absorbing layer, The capacitance reducing layer has a band gap greater than a band gap of the light absorbing layer.

2. The semiconductor light receiving element according to claim 1, wherein: The other semiconductor layer includes a first conductivity type third region surrounding the second region when viewed in the stacking direction of the semiconductor stacked portion.

3. The semiconductor light receiving element according to claim 2, wherein: The second region extends from the other semiconductor layer to the interior of the light absorbing layer.

4. The semiconductor light receiving element according to claim 1, wherein The other semiconductor layer is constituted by the second region.

5. The semiconductor light-receiving element according to claim 4, wherein: The second region includes: another light absorbing layer of the second conductivity type stacked on the light absorbing layer.

6. The semiconductor light receiving element according to claim 1, wherein The first semiconductor layer includes a buffer layer.

7. The semiconductor light receiving element according to claim 6, wherein: The buffer layer has the first conductivity type, The buffer layer has a higher carrier concentration than the capacitance reducing layer.

8. The semiconductor light receiving element according to claim 1, wherein The light absorbing layer has a thickness of 0.6 μm or more and 1.8 μm or less.

9. The semiconductor light receiving element according to claim 1, wherein: The carrier concentration of the first region of the light absorbing layer is 1×10 14 cm -3 Above and 3×10 15 cm -3 the following.

10. The semiconductor light receiving element according to claim 1, wherein The capacitance reducing layer has a thickness of 0.1 μm or more and 3.0 μm or less.

11. The semiconductor light receiving element according to claim 1, wherein The carrier concentration of the capacitance reduction layer is 1.5×10 14 cm -3 Above and 5×10 15 cm -3 the following.

12. The semiconductor light receiving element according to claim 1, wherein The capacitance-reducing layer has a sensitivity wavelength range of 1.31 μm or less.

13. The semiconductor light receiving element according to claim 6, wherein: The buffer layer has a thickness of 0.5 μm or more and 2.5 μm or less.

14. The semiconductor light-receiving element according to any one of claims 6, 7, and 13, wherein: The carrier concentration of the buffer layer is 5×10 16 cm -3 Above and 5×10 18 cm -3 the following.

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