A method for adaptively adjusting the clock frequency of an audio / video device

Abstract

The application provides a method for dynamically adjusting the clock frequency of an audio and video device, in which a receiving end FIFO stores data into the FIFO according to a sending clock and a control enable; the almost full and almost empty signals are generated by detecting the empty and full states in real time, and correspond to the overflow trend and underflow trend of the FIFO respectively; the decimal part of the latest PLL decimal frequency division coefficient is calculated according to whether the almost full and almost empty signals are high, and is sent into the PLL to calculate the decimal frequency division coefficient, the new reading frequency and the clock frequency is dynamically adjusted. The application also provides a circuit for dynamically adjusting the clock frequency of an audio and video device. The application detects the overflow in real time, improves the transmission efficiency and reduces unnecessary power consumption waste; the data of a packet does not need to be stored into a buffer, so that the size of the buffer is relatively free, and the area cost is saved; the sending clock frequency is converged to be consistent with the sampling clock frequency by the gradually approaching processing of the empty and full signals alternately, the overflow judgment is not needed all the time, and the efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital signal processing, in particular to a method for adaptively and dynamically adjusting the clock of an audio and video device. BACKGROUND

[0002] In the process of audio and video transmission, the audio and video transmission clock of the sending end and the audio and video sampling clock of the receiving end are generated by different crystal oscillators and different frequency division coefficients. Therefore, there is an error between the sending clock of the sending end and the sampling clock of the receiving end. This error will cause the buffer of the receiving end to overflow, resulting in distortion of the received audio and video of the receiving end. Therefore, a method for adaptively and dynamically adjusting the clock of an audio and video device is needed to eliminate the clock error between the sending end and the receiving end in the process of audio and video transmission.

[0003] The existing method for dynamically adjusting the frequency of the clock of an audio and video device mainly detects overflow by packet audio and video data, and adjusts the frequency of the sampling clock of the receiving end through the CPU, which is not conducive to system efficiency and audio and video transmission rate. Patent application 202210095189.1 discloses a method for dynamically adjusting the frequency of the clock of an audio and video device, which judges whether the data amount of the current received audio data packet will cause the buffer of the receiving end to overflow by packet, and returns an overflow interrupt to the CPU if it does, and then the CPU adjusts the frequency of the clock of the receiving end to prevent overflow of the receiving buffer. However, this frequency adjustment method based on overflow judgment of data packets and relying on CPU interrupt is not conducive to the overall efficiency of the system and the efficiency of audio transmission.

[0004] The existing technology for adjusting the clock of an audio and video device has at least the following disadvantages:

[0005] 1. The size of the data amount of each data packet is used to judge whether the buffer will overflow, which cannot perform parallel transmission of multiple data packets, affecting the transmission efficiency. In addition, packet detection requires the buffer to store the data of the packet, and the size of the data packet is unpredictable by the receiving end, which requires the buffer to be large enough to store data packets of different sizes, resulting in excessive cost of the area of the buffer.

[0006] 2. For a data packet, not the entire data packet will cause the buffer to overflow, but only the overflow part of the data packet will cause this situation. Frequency adjustment should only be performed on the overflow part, but if the frequency is adjusted for the entire data packet, the frequency will be unnecessarily high, causing power waste; if the frequency is reduced, it will cause unnecessary low frequency, reducing the transmission efficiency of the receiving end.

[0007] 3. The receiving end clock frequency is adjusted according to the data packet size and relies on CPU interrupt, and is adjusted up and down at times. In this process, firstly, the clock error cannot be solved, and the overflow judgment will be repeatedly executed as long as the data transmission is received, and the efficiency is not high. Secondly, the frequency adjustment relying on CPU interrupt will occupy the use of CPU resources, and the reaction speed of CPU is not as timely as the special circuit, that is, the overall operation efficiency of the system is reduced, and the transmission efficiency of the received audio and video data is also reduced. SUMMARY

[0008] The present application provides a method for adaptively and dynamically adjusting the clock frequency of an audio and video device, which comprises the following steps:

[0009] S1: The first-in first-out audio and video buffer FIFO of the receiving end stores the audio and video data into the buffer FIFO according to the sending clock and the control enable of the sending end.

[0010] S2: The buffer FIFO detects the empty and full states in real time, generates the almost full signal almost_full and the almost empty signal almost_empty, and the almost full signal almost_full and the almost empty signal almost_empty correspond to the overflow trend and the underflow trend of the FIFO respectively.

[0011] S3: If the almost full signal almost_full is high, the dynamic frequency adjustment process is started according to the almost_full signal.

[0012] S4: When the almost_full signal is high, the decimal part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is adjusted according to the last almost overflow state.

[0013] S5: If the almost_full signal is not high, it is further judged whether the almost_empty signal is high. If the almost_empty signal is not high, it is indicated that the frequency adjustment process is not needed temporarily; if the almost_empty signal is high, the dynamic frequency adjustment process is started according to the almost_empty signal.

[0014] S6: When the almost_empty signal is high, the adjusted FRAC is calculated according to the last almost overflow state.

[0015] S7: After the latest decimal part FRACnew in the fractional frequency division coefficient of the phase-locked loop PLL is calculated through the steps S4 and S6, the FRACnew is sent into the phase-locked loop PLL, the phase-locked loop PLL calculates the fractional frequency division coefficient according to the FRACnew, calculates the new reading frequency, and dynamically adjusts the clock frequency.

[0016] Step S4 further comprises: if the last FIFO approximate overflow state is approximate full, then adding a fraction part FRAC in a fractional part of a phase-locked loop PLL fractional frequency division coefficient by a step step; if the last FIFO approximate overflow state is not approximate full, then adding 1 / 2 times the step to the FRAC.

[0017] Step S6 further comprises: if the last FIFO approximate overflow state is approximate empty, then subtracting a fraction part FRAC in a fractional part of a phase-locked loop PLL fractional frequency division coefficient by a step step; if the last FIFO approximate overflow state is not approximate empty, then subtracting 1 / 2 times the step from the FRAC.

[0018] Further, after step S2 is executed, step S8 is further executed to determine whether the sampling frequency matches the sending frequency, if the sampling frequency matches the sending frequency, it is indicated that the sampling frequency has converged, and step S9 is executed to turn off the dynamic frequency modulation circuit to suspend the dynamic frequency modulation; if the sampling frequency does not match the sending frequency, the dynamic frequency modulation circuit is turned on, and subsequent steps are executed according to a determination result of the approximate full signal almost_full and the approximate empty signal almost_empty.

[0019] Further, step S10 is further included after step S9 is executed, after the dynamic frequency modulation circuit is turned off, step S2 is executed again in a process in which data is continuously stored in the FIFO, if one of the approximate full signal almost_full and the approximate empty signal almost_empty is high, it is indicated that a previous clock matching is failed, and a matching count value is increased, and then step S8 and subsequent processing are sequentially executed.

[0020] Further, the determination of whether the sampling frequency matches the sending frequency further comprises: a counter determines a number of times that a difference between the read pointer and the write pointer is continuously unchanged, and when the counter reaches a matching count value, it is indicated that the sampling clock frequency of the receiving end has converged to match the sending clock of the sending end.

[0021] A circuit for dynamically adjusting a clock frequency of an audio and video device is also provided, and the circuit comprises:

[0022] A splicing module reads in the approximate empty signal and the approximate full signal, performs bit splicing, and a splicing result identifies a current approximate empty and full state;

[0023] A D flip-flop synchronously updates data at a D flip-flop input end to an output end when a clock rising edge arrives, and determines whether to adjust a fraction part FRAC in a fractional part of a phase-locked loop PLL fractional frequency division coefficient and a step step according to the approximate empty and full state to determine whether to dynamically modulate the frequency.

[0024] The bit right shift module processes the step by dividing 2, and when the current approximate empty-full state is different from the last approximate empty-full state, the step is divided by 2;

[0025] The inequality judgment module judges whether the current approximate empty-full state is the same as the last approximate empty-full state, and sends the judgment result to the first two-way selector to select the input, if the current approximate empty-full state is not equal to the last approximate empty-full state, the step is adjusted to 1 / 2 of the original; if the current approximate empty-full state is equal to the last approximate empty-full state, the step is unchanged;

[0026] The second two-way selector updates the FRAC by adding or subtracting the step adjusted by the first two-way selector to generate FRACnew;

[0027] When the rising edge of the FIFO read clock rd_clk arrives, the D flip-flop outputs the calculated FRACnew, and the PLL calculates the decimal frequency division coefficient according to FRACnew to calculate the new read frequency, and dynamically adjusts the clock frequency.

[0028] Further, when the first two-way selector adjusts the step, if the current is approximate full and the last time is approximate full, the step does not change, if the last time is not approximate full, the step becomes 1 / 2 times; if the current is approximate empty and the last time is approximate empty, the step does not change, if the last time is not approximate empty, the step becomes 1 / 2 times;

[0029] When the second two-way selector adjusts the FRAC, if the current is approximate full, the FRAC is updated by adding the adjusted step to the FRAC; if the current is approximate empty, the FRAC is updated by subtracting the adjusted step from the FRAC.

[0030] The technical effects of the present application: during the processing, the overflow detection is not dependent on the packet by packet, but the overflow detection is more precise and real-time, thereby improving the transmission efficiency and reducing unnecessary power consumption waste, and since it is not necessary to store a packet of data in the buffer, the size of the buffer is relatively free, the size of the audio and video buffer is reduced, and the area cost overhead is saved; the frequency adjustment method is improved, the empty-full signal is alternately processed to gradually approach, the receiving end transmission clock frequency is converged to be consistent with the sampling clock frequency of the sending end, the overflow judgment is not needed all the time, the efficiency is improved; a special dynamic frequency adjustment circuit is designed, the overflow interrupt is not needed to be returned to the CPU, the resource consumption of the CPU is reduced and the response speed is improved, and the system operation efficiency and the audio and video transmission efficiency are improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a clock frequency dynamic adjustment logic block diagram of the present application;

[0032] Figure 2 is a clock frequency dynamic adjustment flowchart of the present application;

[0033] Figure 3 is a clock frequency dynamic adjustment flowchart of another embodiment of the present application;

[0034] Figure 4 is a dynamic frequency adjustment circuit structure diagram of the present application;

[0035] Figure 5 is a dynamic frequency adjustment flowchart of the present application; DETAILED DESCRIPTION

[0036] In the process of audio and video signal transmission, the clock difference between the sending end and the receiving end, thus resulting in the quality problem of audio and video transmission. For example, a typical application is that a notebook computer (sending end) is connected to a large-size display screen (receiving end) through an HDMI line, and the video and audio of the film played by the notebook computer are played through the large-size display screen to obtain a better audio-visual experience. If the clock difference problem between the notebook computer and the large-size display screen is not solved, the audio of the notebook computer film played on the large-size display screen will have audio loss, noise and screen flicker, black screen and other audio and video distortion phenomena.

[0037] The present application uses a receiving end buffer overflow detection method, cooperates with a special dynamic frequency adjustment circuit, and realizes self-adaptive dynamic adjustment of the audio and video equipment clock according to the approximate empty-full signal alternation of the FIFO and then the gradually approaching method.

[0038] The present application increases a dynamic frequency adjustment circuit on the basis of a first-in first-out audio and video buffer (FIFO), a phase-locked loop (PLL) and a crystal oscillator, as shown in Figure 1 . Figure 1 The related parameter meanings in the figure are as follows:

[0039] PLL: phase-locked loop.

[0040] ref_clk: crystal oscillator output clock.

[0041] tx_clk: sending clock from the sending end.

[0042] tx_data: audio and video data sent by the sending end.

[0043] din: data input port of the FIFO.

[0044] wr_clk: write clock of the FIFO.

[0045] dout: output data of the FIFO, which represents the audio and video data that has passed through the FIFO buffer and then output.

[0046] rd_clk: read clock of FIFO.

[0047] almost_full: almost full signal of FIFO.

[0048] almost_empty: almost empty signal of FIFO.

[0049] FRAC: fractional part in fractional division coefficient of PLL.

[0050] Figure 2 The first embodiment of the application is dynamic adjustment of clock frequency, in which the dynamic frequency adjustment process is not ended, and the sampling clock frequency of the receiving end is dynamically adjusted in real time. No matter how high the precision of the sending clock of the sending end is, the sampling clock of the receiving end can be dynamically adjusted accordingly. The advantage of this scheme is that it can match the sending clock of the sending end with any precision. However, since the dynamic frequency adjustment is always performed, additional power consumption is generated.

[0051] Figure 2 The dynamic adjustment of clock frequency includes the following steps:

[0052] S1: The first-in first-out audio and video buffer FIFO of the receiving end stores the audio and video data tx_data from the sending end into the FIFO through the data input port din according to the sending clock tx_clk of the sending end and the related control enable.

[0053] S2: In the process of continuously storing tx_data into the FIFO, the FIFO detects the empty and full state in real time according to the internal write pointer and the internal read pointer, and generates the almost full signal almost_full and the almost empty signal almost_empty according to the set threshold value by hardware circuit. The two signals represent the full and empty trend of the FIFO internally, which corresponds to the overflow (almost full) and underflow (almost empty) trend. Based on the basic function of the FIFO, whether the difference between the read and write pointers in the FIFO is greater than the set almost full and almost empty threshold value is calculated. If it is greater, it indicates that the FIFO currently has an almost empty and almost full state.

[0054] S3: If the almost full signal almost_full is high, it indicates that the FIFO has an overflow trend, and the almost_full signal will be sent to the dynamic frequency adjustment circuit to start the dynamic frequency adjustment process.

[0055] S4: In the case that the almost_full signal is high, the current almost_full signal high level is read, and the fractional part FRAC in the fractional division coefficient of the phase-locked loop PLL is adjusted according to the last almost overflow state.

[0056] If the last FIFO approximate overflow state is also approximate full, then the fractional part FRAC in the fractional division coefficient of the phase-locked loop PLL is added with a step, which is set differently according to different boards, to increase the FIFO reading frequency and inhibit the FIFO full condition; if the last FIFO trend is not approximate full, then FRAC is added with 1 / 2 times the step.

[0057] The method of alternately adjusting the fractional division in step S4 according to the FIFO approximate empty and full signals and then gradually approaching uses the last approximate empty and full state to recalculate the step, so as to achieve a convergence state. For example, if the FIFO is always an approximate full signal, it is indicated that the FIFO reading frequency needs to be actively increased, so FRAC is added with the step; but if the last FIFO trend is not approximate full, it is indicated that the current approximate full degree is not so urgent, and the FIFO reading frequency can not be so actively increased, so FRAC is added with 1 / 2 times the step, so as to achieve a convergence effect, and finally the sampling clock at the receiving end is consistent with the sending clock at the sending end.

[0058] S5: If the almost_full signal is not high, it is further judged whether the almost_empty signal is high. If the almost_empty signal is not high, it is indicated that the FIFO does not have an approximate overflow state at present, and the frequency adjustment processing is not needed temporarily. But it does not mean that the sampling frequency converges to be consistent with the sending frequency, and the whole frequency adjustment process still needs to continue. If the almost_empty signal is high, it is indicated that the FIFO has an underflow trend, and the almost_empty signal is sent into the dynamic frequency adjustment circuit to perform the processing of step S6.

[0059] S6: In the case that the almost_empty signal is high, the current almost_empty signal high level is read, and FRAC is reduced according to the last approximate overflow state.

[0060] If the last FIFO trend is also approximate empty, then the fractional part FRAC in the fractional division coefficient of the phase-locked loop PLL is subtracted with a step, which is set differently according to different boards, to reduce the FIFO reading frequency and inhibit the FIFO empty condition; if the last FIFO trend is not approximate empty, then FRAC is subtracted with 1 / 2 times the step.

[0061] Step S6 is to re-calculate step using the last almost empty signal, in order to achieve a convergence state, for example, if the FIFO is always almost empty, it means that the FIFO read frequency should be actively reduced, so FRAC will be reduced by step; but if the last trend of the FIFO is not almost empty, it means that the degree of current almost empty is not so urgent, so the FIFO read frequency can not be actively reduced, so FRAC will be reduced by 1 / 2 step, so as to achieve a convergence effect, and finally the sampling clock at the receiving end is consistent with the sending clock at the sending end.

[0062] S7: After the dynamic frequency adjustment circuit calculates the decimal part FRACnew of the latest phase-locked loop PLL fractional frequency division coefficient in step S4 and S6, it is sent to the phase-locked loop, and the phase-locked loop calculates the fractional frequency division coefficient according to FRACnew, and calculates a new read frequency to dynamically adjust the clock frequency.

[0063] Figure 3 The second embodiment of the application is to dynamically adjust the clock frequency, in which a certain condition is set to determine whether the sending clock frequency at the sending end and the sampling clock frequency at the receiving end match. When the two clocks match, the dynamic frequency adjustment circuit is turned off, and the dynamic frequency adjustment process is ended. Since dynamic frequency adjustment is not needed in the future, power consumption can be saved. The advantage of this scheme is that the dynamic frequency adjustment process can be ended, and power consumption can be saved without always dynamically adjusting the frequency, but only a certain precision clock matching can be performed. When the precision of the sending clock frequency at the sending end is too high, a matching blind area is easily generated, and a certain error is generated. In order to ensure matching success, an additional safety measure is designed to correct the matching error caused by the precision problem, and the matching count value is adjusted by dynamic adjustment to adapt to higher precision clock matching.

[0064] The operation flow of the second embodiment is as follows: after step S2 "FIFO real-time detection of empty and full states, generation of almost full signal almost_full and almost empty signal almost_empty" is executed in the overall flow of the first embodiment, step S8 is executed.

[0065] S8: Determine whether the sampling frequency has converged to match the sending frequency. If they match, it means that the sampling frequency has converged, and step S9 is executed. If they do not match, the dynamic frequency adjustment circuit is turned on, and it is further determined whether the almost full signal almost_full is high. If it is high, step S3 and subsequent steps are sequentially executed. If the almost full signal almost_full is not high, it is determined whether the almost empty signal almost_empty is high, and subsequent steps are executed according to the determination result.

[0066] In step S8, the judgment of whether the sending clock frequency of the sending end matches the sampling clock frequency of the receiving end is implemented. The FIFO has a read pointer and a write pointer. If the difference between the read pointer and the write pointer is the same for a relatively long time, it indicates that the change rate of the read pointer and the write pointer is consistent, which means that the read frequency and the write frequency of the FIFO are the same, and the sending clock of the sending end matches the sampling clock of the receiving end.

[0067] Therefore, a counter (cnt) is arranged in the FIFO to judge the number of times that the difference between the read and write pointers is continuously unchanged. When the counter reaches a certain value (matching count value), which can be set by software through a register, it indicates that the sampling clock frequency of the receiving end has converged to match the sending clock of the sending end through dynamic frequency adjustment.

[0068] The method can judge whether the clocks in a certain precision frequency range match. For example:

[0069] 1. If the matching count value of the current counter is set to 100, the frequency matching needs to be effectively judged in 100 periods, which requires that the ratio of the clock frequencies of the receiving end and the sending end is greater than 1.01 and less than 0.99. If the matching count value is set to 1000, the ratio of the clock frequencies of the receiving end and the sending end is required to be greater than 1.001 and less than 0.999. A simple example is as follows:

[0070] When the matching count value is set to 100, the frequency of the FIFO write clock A is 1000hz, and the frequency of the read clock B is 1010hz, and the ratio of the two frequencies is 1.01. At a certain time, the difference between the read and write pointers does not change, and the counter starts counting from 0 to count the number of times that the difference between the read and write pointers is continuously unchanged. When the counter counts to 99, if the read and write of the FIFO do not interrupt, the write pointer of the clock A increases by 100, the read pointer of the clock B increases by 101, and the difference between the read and write pointers increases by 1, which changes. The counter is cleared, and it is correctly detected that A and B have not matched

[0071] If the frequency of the FIFO write clock A is 1000hz, and the frequency of the read clock B is 1001hz, the ratio of the two frequencies is 1.001. At a certain time, the difference between the read and write pointers does not change, and the counter starts counting from 0 to count the number of times that the difference between the read and write pointers is continuously unchanged. When the counter counts to 99, if the read and write of the FIFO do not interrupt, the write pointer of the clock A increases by 100, and the read pointer of the clock B increases by 100.1 (which means that the read pointer is likely to also increase by 100), and the difference between the read and write pointers does not change. It is mistakenly believed that A and B have matched, but in fact A and B have not matched.

[0072] In the above example, when the matching count value is set to 100, and clock A is 1000 hz, if clock B is (990, 1000) (1000, 1010) hz, the method will default that A and B are matched, which can be called the matching blind area of the method.

[0073] In this case, only by increasing the matching count value, such as from 100 to 1000, the matching blind area becomes (999, 1000) to (1000, 1001) for A being 1000 hz, and B being 1001 hz, the method can successfully identify that A and B are not matched.

[0074] The difference between B being 1010 hz and B being 1001 hz can be equivalent to a change in clock accuracy frequency, i.e., the difference between 1.01 khz and 1.001 khz, so it can be seen that the higher the clock accuracy requirement, the larger the matching count value required. Therefore, under a fixed matching count value, it can only satisfy the clock frequency matching under a certain accuracy. In actual application, the matching count value can be set larger according to the application scenario, so that the sending end clock frequency of larger accuracy can be matched. Because the accuracy of the clock frequency is limited, setting a larger matching count value can cover most working conditions. The matching count value can also be dynamically increased to dynamically adapt to working scenarios with higher clock frequency accuracy.

[0075] S9: When the sending clock frequency of the sending end and the sampling clock frequency of the receiving end are consistent, the dynamic frequency adjustment circuit is turned off, and the dynamic frequency adjustment process is temporarily stopped.

[0076] S10: After the sending clock and the sampling clock are matched and the frequency adjustment circuit is turned off, since the data is continuously stored in the FIFO, step S2 will be executed again. If the almost full signal almost_full or the almost empty signal almost_empty is high, since the two signals represent the fullness trend of the FIFO inside, which corresponds to the overflow (almost full) and underflow (almost empty) trend, it means that the FIFO buffer output overflow state occurs, which means that the previous clock matching is failed. The clock matching failure indicates that the current matching count value cannot meet the current clock frequency accuracy requirement, and the matching count value needs to be increased by software / hardware configuration register. After the matching count value is increased, step S8 and the subsequent processing flow are executed in sequence.

[0077] The dynamic frequency modulation circuit alternately performs gradual approximation processing according to the empty and full signals, and adds or subtracts step or 1 / 2 step from a fractional part FRAC in a fractional frequency division coefficient of a phase-locked loop PLL through a current approximate empty and full state and a last approximate empty and full state, obtains FRACnew by adjusting the FRAC and transmits the FRACnew to the PLL, and the PLL adjusts a read frequency of a first-in first-out audio and video buffer FIFO according to the FRACnew, thereby realizing dynamic frequency modulation.

[0078] Figure 4 、 Figure 5 The dynamic frequency modulation circuit structure and the method flow chart of the application are respectively shown. Figure 4 The related parameter meanings and mark explanations are as follows:

[0079] rd_clk: read clock of the FIFO; EN: working enable of the D flip-flop; FRACnew: new FRAC value calculated and output by the dynamic frequency modulation circuit. ①: splicing module; ②: D flip-flop; ③: bit right shift module; ④: first two-way selector; ⑤: inequality judging module; ⑥: adder; ⑦: subtractor; ⑧: second two-way selector; ⑨: port of the dynamic frequency modulation circuit.

[0080] The working flow of the dynamic frequency modulation circuit is described in combination with Figures 4-5 .

[0081] The splicing module ① reads in approximate empty and full signals, performs bit splicing, and the spliced result indicates a current empty and full state. If the current empty and full state is 10, it indicates that the current state is an approximate empty state; if the current empty and full state is 01, it indicates that the current state is an approximate full state; if the current empty and full state is 00, it indicates that there is no approximate overflow at present, and no frequency modulation is performed; and there is no current empty and full state of 11, which indicates that it is both approximate empty and approximate full, and approximate empty and approximate full are mutually exclusive, and this situation cannot occur, which is not discussed here. (S12, S13, S17)

[0082] The D flip-flop ② synchronously updates the data at the input end of the D flip-flop to the output end of the D flip-flop when the clock rising edge comes, if the EN is high. If the approximate empty and full state is not 00 (that is, there is approximate empty or approximate full, and the EN is high at this time), it indicates that the FRAC and the step need to be adjusted, so the D flip-flop is triggered to update the FRAC and the step.

[0083] The bit right shift module ③ implements the processing of dividing the step by 2. In binary numbers, the data is moved one bit to the right, which indicates that the data is divided by 2. When the approximate empty and full state of this time is different from the approximate empty and full state of the last time, the step is divided by 2.

[0084] If the current empty-full state is 00, the two EN D flip-flops will not be enabled, the initial FRAC and step will not change, and the frequency modulation will not be performed this time (S21).

[0085] The processing procedure of the two-way selector is to judge whether the current condition is true or not. If the current condition is true, one input is selected to output; if the current condition is not true, the other input is selected to output. The current approximate empty-full state is judged by the inequality judging module 5 whether it is the same as the last approximate empty-full state, and the judging result is sent to the first two-way selector 4 to select the input. If the current approximate empty-full state is not equal to the last approximate empty-full state, the step is adjusted to the original 1 / 2; if the current approximate empty-full state is equal to the last approximate empty-full state, the step is not changed, and the step is adjusted (S14, S15, S18, S19).

[0086] More specifically, (1) if the current is approximate full, and the last time is approximate full, the step is not changed, FRAC+step; (2) if the current is approximate full, and the last time is approximate empty, the step is changed to 1 / 2 times, FRAC+step; (3) if the current is approximate empty, and the last time is approximate empty, the step is not changed, FRAC-step; (4) if the current is approximate empty, and the last time is approximate full, the step is changed to 1 / 2 times, FRAC-step; (5) if the current is approximate full, and the last time is not approximate empty full, the step is changed to 1 / 2 times, FRAC+step; (6) if the current is approximate empty, and the last time is not approximate empty full, the step is changed to 1 / 2 times, FRAC-step.

[0087] If the current empty-full state is approximate full (10), FRAC+step (S14, S15, S16); if the current empty-full state is approximate empty (01), FRAC-step (S18, S19, S20). The FRAC is updated by the second two-way selector 7 to select FRAC+step or FRAC-step.

[0088] When the rising edge of the rd_clk clock comes, the D flip-flop outputs the calculated FRACnew to 9 (S22).

[0089] As shown in Figure 5

[0090] S12: read the approximate empty and approximate full signals from the FIFO.

[0091] S13: judge whether the current is approximate full signal.

[0092] S14: if the current is approximate full, and the last time is approximate full, the step is not changed, FRAC+step.​

[0093] S15: If the current is approximately full, and the last time is approximately empty, then step is changed to 1 / 2 times, FRAC+step.

[0094] S16: If the current is approximately full, and the last time is not approximately empty full, then step is changed to 1 / 2 times, FRAC+step.

[0095] S17: If the current is not approximately full, then judge whether it is approximately empty.

[0096] S18: If the current is approximately empty, and the last time is approximately empty, then step is not changed, FRAC-step.

[0097] S19: If the current is approximately empty, and the last time is approximately full, then step is changed to 1 / 2 times, FRAC-step.

[0098] S20: If the current is approximately empty, and the last time is not approximately empty full, then step is changed to 1 / 2 times, FRAC-step.

[0099] S21: If the current is not approximately full, and not approximately full, then no processing is done, and step and FRAC are not changed.

[0100] S22: Output the adjusted FRACnew.

[0101] The application aims at audio and video transmission, improves the limitation caused by the packet overflow detection of the previous audio and video dynamic frequency modulation scheme, realizes multi-packet parallel transmission through real-time frequency adjustment, improves transmission efficiency and reduces unnecessary power waste, and can reduce the buffer size, without the need of a larger buffer to reduce data overflow.

[0102] The application proposes a dynamic frequency modulation convergence scheme, improves the shortcoming of the previous scheme of directly collecting data and always adjusting frequency, greatly reduces the frequency modulation times, improves the efficiency, and through fractional frequency gradual adjustment, does not produce a large frequency division coefficient, so that the phase-locked loop can stably enter the locked state, and does not affect the phase of the clock.

[0103] The application proposes a dynamic frequency modulation special circuit for dynamic frequency modulation, which can make the frequency modulation process not need software participation, reduces the interruption access to the CPU, responds more timely, so that the data at the receiving end will not be interrupted, thereby ensuring that the audio and video will not appear voice interruption, and improving the overall system efficiency and audio and video transmission efficiency.

[0104] The application proposes two solutions according to different clock precision and power consumption requirements, whether the sending clock of the sending end and the sampling clock frequency of the receiving end match.

[0105] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for adaptively and dynamically adjusting a clock frequency of an audio / video device, the method comprising: S1: storing audio / video data into a first-in-first-out (FIFO) buffer of a receiving end according to a sending clock of a sending end and a control enable; S2: detecting a fullness state of the buffer in real time to generate an almost full signal and an almost empty signal, which correspond to an overflow trend and an underflow trend of the FIFO, respectively; S3: if the almost full signal is high, starting a dynamic frequency adjustment process according to the almost full signal; S4: when the almost full signal is high, adjusting a fractional part FRAC of a fractional frequency division coefficient of a phase-locked loop (PLL) according to a last almost overflow state; S5: if the almost full signal is not high, further judging whether the almost empty signal is high, if the almost empty signal is not high, indicating that the frequency adjustment process is not needed temporarily, and if the almost empty signal is high, starting the dynamic frequency adjustment process according to the almost empty signal; S6: when the almost empty signal is high, calculating an adjusted FRAC according to the last almost overflow state; S7: after the latest FRACnew of the fractional frequency division coefficient of the PLL is calculated through the processes of steps S4 and S6, sending the FRACnew into the PLL, and the PLL calculating a new reading frequency according to the FRACnew to dynamically adjust the clock frequency.

2. The method of claim 1, wherein step S4 further comprises adding a step to the fractional part FRAC of the fractional frequency division coefficient of the PLL if the last almost overflow state of the FIFO is almost full, or adding 1 / 2 times the step to the FRAC if the last almost overflow state of the FIFO is not almost full.

3. The method of claim 1, wherein step S6 further comprises subtracting a step from the fractional part FRAC of the fractional frequency division coefficient of the PLL if the last almost overflow state of the FIFO is almost empty, or subtracting 1 / 2 times the step from the FRAC if the last almost overflow state of the FIFO is not almost empty.

4. The method of claim 1, wherein after step S2 is executed, step S8 is further executed to judge whether a sampling frequency matches a sending frequency, if the sampling frequency matches the sending frequency, indicating that the sampling frequency has converged, step S9 is executed to turn off a dynamic frequency adjustment circuit and suspend the dynamic frequency adjustment, and if the sampling frequency does not match the sending frequency, the dynamic frequency adjustment circuit is turned on, and subsequent steps are executed according to a judgment result of the almost full signal and the almost empty signal.

5. The method of claim 4, further comprising a step S10 after step S9, after the dynamic frequency adjustment circuit is closed, the data is continuously stored in the FIFO, and step S2 is executed again, if one of the almost full signal almost_full and the almost empty signal almost_empty is high, it indicates that the previous clock matching is failed, and the matching count value is increased, and then step S8 and the subsequent processing are executed in sequence.

6. The method of claim 4, wherein the step of judging whether the sampling frequency matches the sending frequency further comprises that a counter judges the number of times that the difference between the read and write pointers is continuously unchanged, and when the counter reaches a matching count value, it indicates that the sampling clock frequency of the receiving end has converged to match the sending clock of the sending end.

7. A circuit for dynamically adjusting the clock frequency of an audio and video device, the circuit comprising: a splicing module that reads in an almost empty and an almost full signal, performs bit splicing, and the splicing result identifies the current almost empty and full state; a D flip-flop that, when a clock rising edge arrives, if the work enable EN is high, synchronously updates the data at the input end of the D flip-flop to the output end, and according to the almost empty and full state, judges whether to adjust the fractional part FRAC and the step step in the fractional frequency division coefficient of a phase-locked loop PLL, and determines whether to dynamically adjust the frequency; a bit right shift module that performs a division by 2 processing on the step step, and when the current almost empty and full state is different from the last almost empty and full state, the step step is divided by 2; an inequality judging module that judges whether the current almost empty and full state is the same as the last almost empty and full state, and sends the judging result to a first two-way selector to select the input, if the current almost empty and full state is different from the last almost empty and full state, the step step is adjusted to be 1 / 2 of the original; if the current almost empty and full state is the same as the last almost empty and full state, the step step remains unchanged; a second two-way selector that adds or subtracts the step step adjusted by the first two-way selector to the FRAC to update the FRAC and generate FRACnew; when a read clock rd_clk rising edge of the FIFO arrives, the D flip-flop outputs the calculated FRACnew, the PLL calculates the fractional frequency division coefficient according to the FRACnew, calculates a new read frequency, and dynamically adjusts the clock frequency.

8. The circuit of claim 7, when the first two-way selector adjusts the step step, if the current is almost full and the last time is almost full, the step does not change, if the last time is not almost full, the step becomes 1 / 2 times; if the current is almost empty and the last time is almost empty, the step does not change, if the last time is not almost empty, the step becomes 1 / 2 times; when the second two-way selector adjusts the FRAC, if the current is almost full, the FRAC is updated by adding the adjusted step; if the current is almost empty, the FRAC is updated by subtracting the adjusted step.

Images