Floating-point number processing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a floating-point number processing method, a floating-point number processing device, electronic equipment and a storage medium, and the floating-point number processing method applied to a coprocessor comprises the steps that a floating-point addition operation instruction is received, the floating-point addition operation instruction comprises an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; a first operand is obtained, and the first operand is a numerical value stored in the memory address; performing floating point addition operation according to the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request according to the first operand, the second operand and the memory address, and sending the comparison and exchange request to the main processor; and in response to a processing result of the comparison and exchange request received from the main processor, determining whether the floating point add operation instruction is executed or not. According to the method, the memory bus is prevented from being occupied, the main processor can be prevented from falling into circulation, and the execution overhead of the main processor is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a floating point number processing method, a floating point number processing device, an electronic device, and a storage medium. Background Art

[0002] In heterogeneous computing architectures, floating-point operations are usually performed by coprocessors, and the data of floating-point operations are usually stored in the memory of the main processor. Before the coprocessor performs floating-point operations, it is necessary to load data from the main processor's memory to the coprocessor's corresponding storage space. After the coprocessor completes the floating-point operation, it is also necessary to store the operation results back to the main processor's memory. In some specific floating-point operations, such as floating-point accumulation operations, it is necessary to ensure that the data in the main processor's memory is not modified by other coprocessors during the period from when the coprocessor obtains data from the main processor's memory to when the operation results are stored back to the main processor's memory.

[0003] For example, when multiple coprocessors collaborate to perform floating-point accumulation operations, a coprocessor that currently accesses the content of the main processor can issue a lock instruction to the memory bus to lock the memory bus and prevent other coprocessors from accessing the memory. For another example, the coprocessor can also implement the compare and exchange atomic operation through software. When a coprocessor executes the atomic operation, other coprocessors cannot operate on the data in the memory. The compare and exchange atomic operation usually includes 4 steps, namely reading the original value of the destination address, comparing an operand with the original value, and when the operand is equal to the original value, writing another operand to the destination address, otherwise returning the original value.

[0004] However, locking the memory bus by the coprocessor will occupy memory resources for a long time, resulting in a waste of resources. The time required for the comparison and exchange atomic operation is relatively long, and there is a possibility that the operation will fail for a long time, which will bring a lot of execution overhead to the main processor. Summary of the invention

[0005] One or more embodiments of the present disclosure provide a floating point number processing method and apparatus, an electronic device, and a storage medium, which can be used to overcome the defect of the coprocessor occupying the memory of the main processor in the existing floating point number accumulation operation.

[0006] At least one embodiment of the present disclosure provides a floating-point number processing method, which is applied to a coprocessor, and includes: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for the floating-point addition operation; obtaining a first operand, wherein the first operand is a numerical value stored in the memory address; performing a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request according to the first operand, the second operand and the memory address, and sending the comparison and exchange request to a main processor; and determining whether the floating-point addition instruction has been executed in response to a processing result of the comparison and exchange request received from the main processor.

[0007] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, obtaining the first operand includes: generating a read request according to a memory address; and sending the read request to a main processor so that the main processor feeds back the first operand.

[0008] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the processing result includes a storage value of a memory address, and determining whether the floating-point addition instruction is executed completely includes: comparing the storage value with a first operand; when the storage value is the same as the first operand, determining that the floating-point addition instruction is executed completely; when the storage value is different from the first operand, determining that the floating-point addition instruction is not executed completely.

[0009] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when it is determined that the execution of the floating-point addition instruction is completed, generating and sending a completion response of the floating-point addition instruction.

[0010] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when it is determined that the floating-point addition instruction has not been executed, using the stored value as the first operand, regenerating a comparison and exchange request, and sending the regenerated comparison and exchange request to the main processor.

[0011] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the coprocessor includes a Peripheral Component Interconnect Express (PCIe) controller.

[0012] At least one embodiment of the present disclosure provides a floating-point data processing method, which is applied to a main processor, comprising: receiving a comparison and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address; accessing the memory address to read a storage value of the memory address; comparing the storage value with the first operand to obtain a comparison result; generating a processing result of the comparison and exchange request according to the storage value and the comparison result, and sending the processing result to the coprocessor, wherein the processing result includes the storage value; wherein when the comparison result indicates that the storage value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the storage value is different from the first operand, no storage operation is performed on the memory address.

[0013] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: receiving a read request obtained by a floating-point addition operation from a coprocessor, and accessing a memory address to read a first operand according to the read request; and feeding back the first operand to the coprocessor.

[0014] At least one embodiment of the present disclosure provides a floating-point data processing method, which is applied to a data processing device including a main processor and a coprocessor, comprising: receiving a floating-point addition instruction by the coprocessor, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; generating a comparison and exchange request by the coprocessor according to the floating-point addition instruction, and sending the comparison and exchange request to the main processor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address, wherein the first operand is a value stored in the memory address, and the second operand is obtained by the coprocessor performing a floating-point addition operation according to the first operand and the accumulated value; in response to the comparison and exchange request, performing a comparison and exchange operation by the main processor to obtain a comparison result; generating and sending a processing result by the main processor according to the comparison result to the coprocessor, wherein the processing result includes the stored value of the memory address; in response to the processing result, determining by the coprocessor whether the floating-point addition instruction is executed; wherein the main processor stores the second operand to the memory address when the comparison result indicates that the stored value is the same as the first operand, and does not perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0015] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: generating a read request by the coprocessor according to the memory address; sending the read request by the coprocessor to the main processor; accessing the memory address by the main processor to read the first operand according to the read request; and feeding back the first operand by the main processor to the coprocessor.

[0016] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the processing result includes a storage value of a memory address, and the coprocessor determines whether the floating-point addition instruction is executed, including: the coprocessor compares the storage value with a first operand; when the storage value is the same as the first operand, the coprocessor determines that the floating-point addition instruction is executed; when the storage value is different from the first operand, the coprocessor determines that the floating-point addition instruction is not executed.

[0017] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when the coprocessor determines that the execution of the floating-point addition instruction is completed, the coprocessor generates and sends a completion response of the floating-point addition instruction.

[0018] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when the coprocessor determines that the floating-point addition instruction has not been executed, using the stored value as the first operand, regenerating a comparison and exchange request, and sending the regenerated comparison and exchange request to the main processor.

[0019] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the main processor performs comparison and exchange operations to obtain a comparison result, including: the main processor accesses a memory address to read a storage value of the memory address; the main processor compares the storage value with the first operand to obtain a comparison result.

[0020] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the coprocessor includes a Peripheral Component Interconnect Express (PCIe) controller.

[0021] Optionally, in the floating-point number processing method of at least one embodiment of the present disclosure, the data processing device includes multiple coprocessors, and when each coprocessor of the multiple coprocessors determines that the corresponding floating-point addition instruction is executed, the multiple coprocessors complete the floating-point accumulation operation.

[0022] At least one embodiment of the present disclosure provides a floating-point number processing device, comprising: a receiving unit, configured to receive a floating-point addition operation instruction, wherein the floating-point addition operation instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; an operand acquisition unit, configured to acquire a first operand, wherein the first operand is a numerical value stored in the memory address; an operation unit, configured to perform a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand; a request generation unit, configured to generate a comparison and exchange request according to the first operand, the second operand and the memory address, and send the comparison and exchange request to a main processor; and a determination unit, configured to determine whether the floating-point addition operation instruction has been executed in response to a processing result of the comparison and exchange request received from the main processor.

[0023] Optionally, according to the floating-point number processing device of at least one embodiment of the present disclosure, the floating-point number processing device is implemented as a Peripheral Component Interconnect Express (PCIe) controller.

[0024] At least one embodiment of the present disclosure provides a floating-point number processing device, comprising: a receiving unit, configured to receive a comparison and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address; a memory access unit, configured to access the memory address to read a storage value of the memory address; a comparison unit, configured to compare the storage value with the first operand to obtain a comparison result; a result generation unit, configured to generate a processing result of the comparison and exchange request according to the storage value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the storage value; and a processing unit, configured to store the second operand to the memory address when the comparison result indicates that the storage value is the same as the first operand, and not perform a storage operation on the memory address when the comparison result indicates that the storage value is different from the first operand.

[0025] At least one embodiment of the present disclosure provides a floating-point number processing device, including: at least one processing device and a memory; wherein a computer program is stored in the memory, and when the computer program is executed by the at least one processing device, the floating-point number processing method of any of the above embodiments is implemented.

[0026] At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, the floating-point number processing method of any of the above embodiments is implemented.

[0027] At least one embodiment of the present disclosure provides an electronic device, including a floating-point number processing device according to any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a schematic diagram of a floating point number processing method provided by an embodiment of the present disclosure;

[0030] Figure 2 is a schematic diagram of another floating point number processing method provided by an embodiment of the present disclosure;

[0031] Figure 3is a schematic diagram of another floating point number processing method provided by an embodiment of the present disclosure;

[0032] Figure 4 is a schematic diagram of a data processing device provided by an embodiment of the present disclosure;

[0033] Figure 5 is a schematic diagram of a floating point number processing device provided by an embodiment of the present disclosure;

[0034] Figure 6 is a schematic diagram of a floating point number processing device provided by an embodiment of the present disclosure;

[0035] Figure 7 It is a schematic diagram of a floating point number processing device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present disclosure explicitly define such meanings.

[0038] The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0039] Heterogeneous systems usually include a main processor and one or more coprocessors. For operations such as accumulation of floating-point numbers, the operand in memory corresponding to the accumulation operation is a shared variable of multiple coprocessors, so all coprocessors will access the memory to obtain the operand. For example, there are a total of 4 coprocessors, all of which need to perform accumulation operations on operand 1 in the memory. The 4 coprocessors are recorded as coprocessor 1, coprocessor 2, coprocessor 3 and coprocessor 4. The main processor sends floating-point accumulation instructions to coprocessors 1~4. Coprocessors 1~4 do not have a fixed order for performing accumulation operations, and the execution order is not indicated in the instructions. After receiving the instructions, coprocessors 1~4 will access the memory of the main processor to obtain the operand. Due to transmission delays and other reasons, coprocessors 1~4 may not receive instructions from the main processor at the same time and may not be able to execute the instructions immediately after receiving the instructions, which may cause conflicts in the time when coprocessors 1~4 access the memory.

[0040] For example, if coprocessors 1 to 4 use a memory bus locked access mode, coprocessors 2 to 4 cannot access the memory when coprocessor 1 performs an accumulation operation. In the memory bus locked access mode, there will be no conflict in the memory access of coprocessors 1 to 4, but the memory bus lock causes all memory resources to be occupied, resulting in a waste of resources.

[0041] For another example, when coprocessors 1 to 4 use software to implement the compare and swap atomic operations to execute the above instructions, while coprocessor 1 has obtained operand 1 but has not yet stored the processing result in the memory, coprocessor 4 can access the memory and obtain operand 1. Coprocessor 1 normally stores the processing result in the memory, and the operand in the memory becomes operand 2. However, when coprocessor 4 obtains the processing result, the operand in the memory has changed from operand 1 to operand 2, which causes coprocessor 4 to be unable to store the processing result in the memory. At this time, the compare and swap atomic operations executed by coprocessor 4 will continue to fail, resulting in a large amount of execution overhead.

[0042] In order to solve the problem of excessive overhead caused by the memory bus locked access mode and the software-implemented atomic operation, the embodiments of the present disclosure provide a floating point number processing method and apparatus, an electronic device, and a storage medium.

[0043] At least one embodiment of the present disclosure provides a floating-point number processing method, which is applied to a coprocessor, and includes: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for the floating-point addition operation; obtaining a first operand, wherein the first operand is a numerical value stored in the memory address; performing a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request according to the first operand, the second operand and the memory address, and sending the comparison and exchange request to a main processor; and determining whether the floating-point addition instruction has been executed in response to a processing result of the comparison and exchange request received from the main processor.

[0044] At least one embodiment of the present disclosure provides a floating-point data processing method, which is applied to a main processor, comprising: receiving a comparison and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address; accessing the memory address to read a storage value of the memory address; comparing the storage value with the first operand to obtain a comparison result; generating a processing result of the comparison and exchange request according to the storage value and the comparison result, and sending the processing result to the coprocessor, wherein the processing result includes the storage value; wherein when the comparison result indicates that the storage value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the storage value is different from the first operand, no storage operation is performed on the memory address.

[0045] At least one embodiment of the present disclosure provides a floating-point data processing method, which is applied to a data processing device including a main processor and a coprocessor, comprising: receiving a floating-point addition instruction by the coprocessor, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; generating a comparison and exchange request by the coprocessor according to the floating-point addition instruction, and sending the comparison and exchange request to the main processor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address, wherein the first operand is a value stored in the memory address, and the second operand is obtained by the coprocessor performing a floating-point addition operation according to the first operand and the accumulated value; in response to the comparison and exchange request, performing a comparison and exchange operation by the main processor to obtain a comparison result; generating and sending a processing result by the main processor according to the comparison result to the coprocessor, wherein the processing result includes the stored value of the memory address; in response to the processing result, determining by the coprocessor whether the floating-point addition instruction is executed; wherein the main processor stores the second operand to the memory address when the comparison result indicates that the stored value is the same as the first operand, and does not perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0046] According to the floating-point data processing method provided by the embodiment of the present disclosure, the coprocessor obtains the first operand, and performs a floating-point addition operation based on the first operand and the accumulated value to obtain the second operand; a comparison and exchange request is generated based on the first operand, the second operand and the memory address, and the comparison and exchange request is sent to the main processor. The main processor executes the comparison and exchange request, and when the comparison result indicates that the stored value is different from the first operand, the storage operation is not performed on the memory address. The method provided by the embodiment of the present disclosure not only avoids the memory bus from being occupied, but also prevents the main processor from falling into a loop and reduces the execution overhead of the main processor.

[0047] In the embodiments of the present disclosure, the main processor may be a central processing unit (CPU), and the coprocessor may include a graphics processing unit (GPU), a tensor processing unit (TPU), or a neural network processing unit (NPU), etc.

[0048] Both the main processor and the coprocessor may have corresponding memory, for example, the CPU has memory, and the GPU also has its own memory. To avoid confusion, the memory in this disclosure refers to the memory of the main processor, and the memory of the coprocessor is called storage space or memory.

[0049] Figure 1 FIG. 1 is a flow chart of a floating point number processing method provided according to an embodiment of the present disclosure. Figure 1 As shown, the floating point number processing method 100 comprises the following steps:

[0050] Step S101, receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for a floating-point addition operation.

[0051] Step S102, obtaining a first operand, wherein the first operand is a value stored in a memory address; performing a floating-point addition operation on the first operand and the accumulated value to obtain a second operand.

[0052] Step S103: Generate a compare and exchange request according to the first operand, the second operand and the memory address, and send the compare and exchange request to the main processor.

[0053] Step S104, in response to receiving the processing result of the compare and swap request from the main processor, determining whether the floating point addition instruction is executed.

[0054] In this embodiment, the floating point number processing method 100 is executed by a coprocessor. Optionally, the floating point number processing method 100 is executed by a peripheral component interconnect express (PCIe) controller included in the coprocessor. In another optional implementation, the floating point number processing method 100 can be executed by a dedicated circuit. Optionally, the coprocessor in this embodiment includes a peripheral component interconnect express PCIe controller. For example, the floating point number processing method 100 is executed by a PCIe controller.

[0055] When executing step S101, a floating point addition instruction is received. For example, after the control module inside the coprocessor responds to the floating point accumulation instruction from the main processor, it generates and sends the floating point addition instruction to the PCIe controller. For example, the floating point addition instruction indicates a PCIe atomic operation, such as a FetchAdd operation.

[0056] The floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for the floating-point addition operation. For example, the floating-point addition instruction from the main processor will carry the accumulated value and the memory address, and the floating-point addition instruction is generated according to the accumulated value and the memory address carried by the floating-point addition instruction from the main processor. The floating-point addition instruction in this embodiment is different from the instruction of the atomic operation of PCIe. For example, after receiving the instruction of the atomic operation of PCIe, the execution of the atomic operation is uninterrupted, and the floating-point addition instruction in this implementation does not directly instruct the coprocessor to perform the atomic operation.

[0057] When executing step S102, in response to the floating-point addition instruction, a first operand is obtained from the memory. According to the memory address in the floating-point addition instruction, the memory is accessed, and the data stored in the memory address is the first operand. For example, the PCIe controller accesses the memory address through the memory bus to read the first operand. After obtaining the first operand, a single floating-point addition operation is performed according to the first operand and the accumulated value to obtain the second operand.

[0058] Optionally, obtaining the first operand includes: generating a read request according to the memory address; and sending the read request to a main processor so that the main processor feeds back the first operand.

[0059] For example, after receiving a floating-point addition instruction, a read request is generated according to the memory address, and the read request is sent to the main processor, and the main processor reads the first operand from the memory and sends it to the coprocessor.

[0060] When executing step S103, a compare and exchange request is generated according to the first operand, the second operand and the memory address, and the compare and exchange request is sent to the main processor. In this embodiment, the compare and exchange request can be an atomic operation, wherein the first operand is data read from the memory address, and the second operand is the result of the floating point addition operation.

[0061] When executing step S104, in response to receiving the processing result of the compare and swap request from the main processor, it is determined whether the floating point addition instruction is executed completely.

[0062] Optionally, the processing result includes the storage value of the memory address; determining whether the floating-point addition instruction is executed completely includes: comparing the storage value with the first operand; when the storage value is the same as the first operand, determining that the floating-point addition instruction is executed completely; when the storage value is different from the first operand, determining that the floating-point addition instruction is not executed completely. The storage value of the memory address is the storage value read from the memory address after the main processor receives the comparison and exchange request and before performing the exchange operation, and the value of the storage value may be equal to the first operand or other numerical value carried by the comparison and exchange request. In the case where the floating-point addition instruction is executed completely, the storage value should be equal to the first operand, and the storage value can be compared with the first operand to determine whether the floating-point addition instruction is executed completely.

[0063] Optionally, when it is determined that the floating-point addition instruction is executed, a completion response of the floating-point addition instruction is generated and sent. For example, when the PCIe controller determines that the floating-point addition instruction is executed, it will send a completion response to the control module to indicate that the floating-point addition operation for which the PCIe controller is responsible has been completed.

[0064] Optionally, when it is determined that the floating-point addition instruction has not been executed to completion, the stored value is used as the first operand, a compare and exchange request is regenerated, and the regenerated compare and exchange request is sent to the main processor.

[0065] For example, the failure to execute a floating-point addition instruction indicates that another coprocessor is simultaneously performing a floating-point addition operation on the data in the memory address, and the other coprocessor has completed the operation first. Therefore, the current coprocessor needs to perform a floating-point addition operation again, using the stored value as the first operand, regenerate the operation, and send a comparison and exchange request to the main processor.

[0066] Figure 2 FIG. 1 is a flow chart of a floating point number processing method provided according to an embodiment of the present disclosure. Figure 2 As shown, the floating point number processing method 200 includes the following steps:

[0067] Step S201, receiving a compare and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the compare and exchange request includes a first operand, a second operand and a memory address.

[0068] Step S202, access the memory address to read the storage value of the memory address; compare the storage value with the first operand to obtain a comparison result.

[0069] Step S203: Generate a processing result of the comparison and exchange request according to the stored value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the stored value.

[0070] The floating point number processing method 200 is executed by the main processor. For example, the floating point number processing method 200 is executed between the above-mentioned step S103 and step S104.

[0071] Before executing step S201, the main processor receives a read request obtained by a floating-point addition operation from the coprocessor, and accesses a memory address to read a first operand according to the read request; and feeds back the first operand to the coprocessor.

[0072] When executing step S202, the main processor executes the received comparison and exchange request, and the main processor accesses the memory according to the memory address and reads the storage value of the memory address. Then, the main processor compares the storage value with the first operand to obtain a comparison result. When the comparison result indicates that the storage value is the same as the first operand, the second operand is stored in the memory address. When the comparison result indicates that the storage value is different from the first operand, the storage operation is not performed on the memory address.

[0073] When executing step S203, the main processor can generate a processing result according to the stored value and the comparison result, so that the coprocessor can directly know the comparison result. The main processor can also generate a processing result only according to the stored value. In this case, the coprocessor needs to compare the stored value with the first operand to determine the comparison result.

[0074] In this embodiment, after the main processor compares the stored value and the first operand, the main processor will not fall into a loop due to an unequal comparison result, thereby reducing the execution overhead of the main processor.

[0075] Figure 3 FIG. 1 is a flow chart of a floating point number processing method provided according to an embodiment of the present disclosure. Figure 3 As shown, the floating point number processing method 300 includes the following steps:

[0076] Step S301: The coprocessor receives a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for a floating-point addition operation.

[0077] Step S302: The coprocessor generates a compare and exchange request according to the floating-point addition instruction, and sends the compare and exchange request to the main processor. The compare and exchange request includes a first operand, a second operand and a memory address, the first operand is a value stored in the memory address, and the second operand is obtained by the coprocessor performing a floating-point addition operation according to the first operand and the accumulated value.

[0078] Step S303, in response to the compare and swap request, the main processor performs a compare and swap operation to obtain a comparison result. When the comparison result indicates that the stored value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the stored value is different from the first operand, the storage operation is not performed on the memory address.

[0079] Step S304: The main processor generates and sends a processing result to the coprocessor based on the comparison result, wherein the processing result includes the storage value of the memory address. For example, when the comparison result indicates that the storage value is the same as the first operand, the storage value of the memory address included in the processing result is the second operand. For another example, when the comparison result indicates that the storage value is different from the first operand, the storage value of the memory address included in the processing result is not the second operand.

[0080] Step S305, in response to the processing result, the coprocessor determines whether the floating-point addition instruction is executed. Optionally, when the coprocessor determines that the floating-point addition instruction is executed, the coprocessor returns a completion response of the floating-point addition instruction. For example, the coprocessor includes a PCIe controller, and the floating-point addition instruction received by the PCIe controller comes from a control module, so that when the PCIe controller receives the processing result from the main processor and determines that the floating-point addition instruction is executed based on the processing result, the coprocessor returns a completion response of the floating-point addition instruction to the control module.

[0081] In this embodiment, the floating point number processing method 300 is applied to a data processing device, which includes a main processor and a coprocessor. The floating point number processing method 300 can be implemented by executing the floating point number processing method 200 by the main processor and executing the floating point number processing method 100 by the coprocessor.

[0082] Optionally, the coprocessor generates a read request according to the memory address; the coprocessor sends the read request to the main processor; the main processor accesses the memory address to read the first operand according to the read request; and the main processor feeds back the first operand to the coprocessor.

[0083] Optionally, the processing result includes a storage value of the memory address, and the coprocessor determines whether the floating-point addition instruction is executed, including: the coprocessor compares the storage value with the first operand; when the storage value is the same as the first operand, the coprocessor determines that the floating-point addition instruction is executed; when the storage value is different from the first operand, the coprocessor determines that the floating-point addition instruction is not executed.

[0084] Optionally, in at least one embodiment, the method further comprises: when the coprocessor determines that the execution of the floating-point addition instruction is completed, the coprocessor generates and sends a completion response of the floating-point addition instruction.

[0085] Optionally, in at least one embodiment, the method further includes: when the coprocessor determines that the floating-point addition instruction has not been executed, using the stored value as the first operand, regenerating the compare and exchange request, and sending the regenerated compare and exchange request to the main processor.

[0086] Optionally, the main processor performs the comparison and exchange operation to obtain the comparison result, including: the main processor accesses the memory address to read the storage value of the memory address; the main processor compares the storage value with the first operand to obtain the comparison result.

[0087] Optionally, the coprocessor in the data processing device includes a PCIe controller.

[0088] Optionally, the data processing device includes multiple coprocessors, and when each coprocessor in the multiple coprocessors determines that the corresponding floating-point addition instruction is executed, the multiple coprocessors complete the floating-point accumulation operation. For example, each coprocessor in the multiple coprocessors includes a PCIe controller, and each PCIe controller processes the corresponding floating-point addition instruction.

[0089] For example, the number of coprocessors is greater than or equal to 1. For example, when the number of coprocessors is 4, all four coprocessors will execute the steps in the floating point number processing method 300 , which can be considered as all four coprocessors executing the floating point number processing method 100 .

[0090] Figure 4 A schematic diagram of a data processing device 400 provided according to an embodiment of the present disclosure is shown.

[0091] The data processing device 400 includes a main processor 401, coprocessors 402-405 and a memory 406. The main processor 401 is connected to the coprocessors 402-405, and the main processor 401 is also connected to the memory 406. For example, the main processor 401 and the coprocessors 402-405 are connected via a PCIe bus.

[0092] Taking the data processing device 400 as an example, the execution method of the above floating point number processing method 300 is illustrated.

[0093] Coprocessors 402 - 405 receive floating-point addition operation instructions respectively. The floating-point addition operation instructions received by coprocessors 402 - 405 carry the same memory address and the same accumulated value, which is recorded as value A.

[0094] The coprocessors 402 - 405 generate read requests according to the floating point addition instruction, and the read requests carry the memory address. The coprocessors 402 - 405 send the read requests to the main processor 401 .

[0095] Assume that the coprocessor 402 first sends a read request to the main processor 401, and the main processor 401 accesses the memory 406 according to the memory address, reads the first operand value B, and then feeds the first operand value B back to the coprocessor 402. The coprocessor 402 performs a floating-point addition operation on the first operand value B and the accumulated value value A to obtain the second operand value C. The coprocessor 402 generates a comparison and exchange request according to the first operand value B, the second operand value C and the memory address, and sends the comparison and exchange request to the main processor 401. In response to the comparison and exchange operation, the main processor 401 accesses the memory 406 according to the memory address, and obtains the current storage value of the memory address, which is value B. The main processor 401 compares the storage value with the first operand. If the comparison result is the same, the second operand value C is stored in the memory address, and the processing result including the storage value value B is sent to the coprocessor 402. After receiving the processing result, the coprocessor 402 determines that the stored value value B is equal to the first operand value B, determines that the floating-point addition operation is completed, and sends a completion response of the floating-point addition operation instruction.

[0096] When the coprocessor 402 performs a floating-point addition operation, the coprocessor 403 sends a read request to the main processor 401. At this time, the main processor 401 has not received the comparison and exchange request from the coprocessor 402, so the first operand fed back by the main processor 401 to the coprocessor 403 is value B. After receiving the first operand value B, the coprocessor 403 performs a floating-point addition operation on the first operand value B and the accumulated value value A to obtain the second operand value C. The coprocessor 403 generates a comparison and exchange request according to the first operand value B, the second operand value C and the memory address, and sends the comparison and exchange request to the main processor 401. After processing the comparison and exchange request from the coprocessor 402, the main processor 401 receives the comparison and exchange request from the coprocessor 403. At this time, the main processor 401 accesses the memory 406 according to the memory address to obtain the current storage value of the memory address, which is value C. The main processor 401 compares the storage value and the first operand. If the comparison result is different, no operation is performed on the memory address, and a processing result including the storage value value C is sent to the coprocessor 403. After receiving the processing result, the coprocessor 403 determines that the storage value value C is not equal to the first operand value B, and determines that the floating-point addition operation is not completed, then the storage value value C is used as the new first operand, and a floating-point addition operation is performed according to the new first operand value C and the accumulated value value A to obtain a new second operand value D. The coprocessor 403 generates a comparison and exchange request according to the first operand value C, the second operand value D and the memory address, and sends the comparison and exchange request to the main processor 401. The main processor 401 accesses the memory 406 according to the memory address to obtain the current storage value of the memory address, which is value C. The main processor 401 compares the storage value value C with the first operand value C. If the comparison result is the same, the second operand value D is stored in the memory address, and a processing result including the storage value value C is sent to the coprocessor 402. After receiving the processing result, the coprocessor 403 determines that the stored value value C is equal to the first operand value C, determines that the floating-point addition operation is completed, and sends a completion response of the floating-point addition operation instruction.

[0097] The coprocessor 404 and the coprocessor 405 process the floating-point addition instruction in a similar manner as the coprocessor 403, and reference may be made to the description of the coprocessor 403. After receiving the processing result, if the coprocessors 402 to 405 determine that the floating-point addition operation is not completed according to the processing result, they will re-perform the floating-point addition operation and re-generate the comparison and exchange request according to the stored value in the processing result as the new first operand until the processing result indicates that the floating-point addition operation is completed.

[0098] By using the data processing device provided by the embodiment of the present disclosure, it is not necessary to predetermine the processing order of floating-point addition operations between coprocessors, and the main processing will not fall into an execution loop, thereby effectively reducing the execution overhead.

[0099] At least one embodiment of the present disclosure provides a floating-point number processing device, including: at least one processing device and a memory; wherein a computer program is stored in the memory, and when the computer program is executed by at least one processing device, a method such as any one of the floating-point number processing method 100 or the floating-point number processing method 200 in the above-mentioned embodiments is implemented.

[0100] Figure 5 A schematic diagram of a floating point number processing device provided according to at least one embodiment of the present disclosure is shown.

[0101] like Figure 5 As shown, the floating-point number processing device 500 includes a receiving unit 501, an operand acquisition unit 502, a computing unit 503, a request generating unit 504 and a determining unit 505, wherein the receiving unit 501 is connected to the operand acquisition unit 502, the operand acquisition unit 502 is connected to the computing unit 503, the request generating unit 504 is connected to the receiving unit 501, the operand acquisition unit 502 and the computing unit 503, and the determining unit 505 is connected to the computing unit 503 and the request generating unit 504.

[0102] The receiving unit 501 receives a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition. The operand acquisition unit 502 acquires a first operand, wherein the first operand is a value stored in the memory address. The operation unit 503 performs a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand. The request generation unit 504 generates a comparison and exchange request according to the first operand, the second operand and the memory address, and sends the comparison and exchange request to the main processor. The determination unit 505 determines whether the floating-point addition instruction is executed in response to the processing result of the comparison and exchange request received from the main processor.

[0103] Optionally, the floating point number processing device 500 can be implemented as a peripheral component interconnect standard PCIe controller. The PCIe controller can include modules that are the same or similar to the receiving unit 501, the operand acquisition unit 502, the operation unit 503, the request generation unit 504 and the determination unit 505 to achieve the same functions.

[0104] In this embodiment, the operand acquisition unit 502 acquires the memory address from the receiving unit 501, and acquires the first operand from the memory according to the memory address. Optionally, the operand acquisition unit 502 generates a read request according to the memory address, and sends the read request to the main processor so that the main processor feeds back the first operand.

[0105] Optionally, the determination unit 505 is further configured to compare the stored value with the first operand; when the stored value is the same as the first operand, determine that the floating-point addition instruction is executed; when the stored value is different from the first operand, determine that the floating-point addition instruction is not executed.

[0106] Optionally, the floating-point number processing apparatus of at least one embodiment of the present disclosure further includes: a response unit configured to generate and send a completion response of the floating-point addition instruction when it is determined that the execution of the floating-point addition instruction is completed.

[0107] Optionally, the determination unit 505 is further configured to, when determining that the floating-point addition instruction has not been executed, use the stored value as the first operand, regenerate a comparison and exchange request, and send the regenerated comparison and exchange request to the main processor. For example, when determining that the floating-point addition instruction has not been executed, the determination unit 505 sends the stored value to the operation unit 503 and the request generation unit 504, so that the operation unit 503 recalculates the second operand according to the stored value, and the request generation unit 504 regenerates the comparison and exchange request according to the updated first operand, the second operand and the original memory address, and sends the comparison and exchange request to the main processor again.

[0108] Figure 6 A schematic diagram of another floating-point number processing device provided according to at least one embodiment of the present disclosure is shown.

[0109] like Figure 6 As shown, at least one embodiment of the present disclosure provides a floating point number processing device 600, including: a receiving unit 601, a memory access unit 602, a comparison unit 603, a result generation unit 604 and a processing unit 605.

[0110] The receiving unit 601 is configured to receive a comparison and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the comparison and exchange request includes a first operand, a second operand and a memory address. The memory access unit 602 is configured to access the memory address to read the storage value of the memory address. The comparison unit 603 is configured to compare the storage value with the first operand to obtain a comparison result. The result generation unit 604 is configured to generate a processing result of the comparison and exchange request according to the storage value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the storage value. The processing unit 605 is configured to store the second operand to the memory address when the comparison result indicates that the storage value is the same as the first operand, and not perform a storage operation on the memory address when the comparison result indicates that the storage value is different from the first operand.

[0111] Optionally, the memory access unit in the floating-point processing device of at least one embodiment of the present disclosure is also configured to receive a read request obtained by a floating-point addition operation from a coprocessor, and access a memory address to read a first operand according to the read request; and feed back the first operand to the coprocessor.

[0112] Figure 7 A schematic structural diagram of another electronic device provided according to an embodiment of the present disclosure is shown.

[0113] For example, Figure 7 As shown, in some examples, the electronic device 700 includes a processing device (such as a central processing unit, a graphics processor, etc.) 701, which may include a floating-point number processing device of any of the above-mentioned embodiments, for example, including a main processor and a coprocessor, the main processor and the coprocessor include the above-mentioned corresponding floating-point number processing device, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the storage device 708 to the random access memory (RAM) 703. In RAM 703, various programs and data required for the operation of the computer system are also stored. The processor 701, ROM 702 and RAM 703 are connected to each other through a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0114] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed, so that the computer programs read therefrom are installed into the storage device 708 as needed. Although Figure 7 The electronic device 700 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0115] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0116] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0117] For example, the electronic device 700 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0118] At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, for example, any method in the floating-point number processing method 100 or any method in the floating-point number processing method 200 in the above-mentioned embodiments is executed.

[0119] At least one embodiment of the present disclosure provides an electronic device, comprising any one of the above-mentioned floating-point number processing devices.

[0120] It should be noted that the computer-readable medium of the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In an embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0121] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0122] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0123] It is worth noting that the step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given, and some steps can be performed in parallel, independently of each other, or in other appropriate orders. In addition, words such as "secondly", "then", "next", etc. are not intended to limit the order of the steps; these words are only used to guide the reader to read through the descriptions of these methods.

[0124] The block diagrams of devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. It should also be noted that in the apparatus and method of this application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this application.

[0125] In addition to the above non-limiting disclosure, the present disclosure also has the following points to be explained:

[0126] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to the general design.

[0127] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0128] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A floating point number processing method, applied to a coprocessor, comprising: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for a floating-point addition operation; Obtain a first operand, wherein the first operand is a value stored at the memory address; Performing a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand; generating a compare and swap request according to the first operand, the second operand and the memory address, and sending the compare and swap request to a main processor; In response to receiving a processing result of the compare and exchange request from the main processor, it is determined whether the floating point addition instruction is executed to completion.

2. The method according to claim 1, wherein: The obtaining of the first operand comprises: Generate a read request according to the memory address; The read request is sent to the main processor, so that the main processor feeds back the first operand.

3. The method according to claim 1, wherein: The processing result includes the storage value of the memory address, and the determining whether the floating-point addition instruction is executed includes: comparing the stored value to the first operand; When the stored value is the same as the first operand, determining that the floating-point addition instruction is executed; When the stored value is different from the first operand, it is determined that the floating-point addition instruction is not executed to completion.

4. The method according to claim 3, further comprising: When it is determined that the floating-point addition instruction is executed completely, a completion response of the floating-point addition instruction is generated and sent.

5. The method according to claim 3, further comprising: When it is determined that the floating-point addition instruction has not been executed to completion, the stored value is used as the first operand, the compare and exchange request is regenerated, and the regenerated compare and exchange request is sent to the main processor.

6. The method according to any one of claims 1 to 5, wherein: The coprocessor includes a Peripheral Component Interconnect Express (PCIe) controller.

7. A floating point data processing method, applied to a main processor, comprising: receiving a compare and exchange request obtained by a floating point addition instruction from a coprocessor, wherein the compare and exchange request includes the first operand, the second operand and a memory address; Accessing the memory address to read the storage value of the memory address; Compare the stored value with the first operand to obtain a comparison result; generating a processing result of the comparison and exchange request according to the stored value and the comparison result, and sending the processing result to the coprocessor, wherein the processing result includes the stored value; Wherein, when the comparison result indicates that the storage value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the storage value is different from the first operand, no storage operation is performed on the memory address.

8. The method according to claim 7, wherein: The method further comprises: receiving a read request obtained by a floating-point addition operation from the coprocessor, and accessing a memory address to read the first operand according to the read request; The first operand is fed back to the coprocessor.

9. A floating point data processing method, applied to a data processing device including a main processor and a coprocessor, comprising: The coprocessor receives a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; The coprocessor generates a comparison and exchange request according to the floating-point addition instruction, and sends the comparison and exchange request to the main processor, wherein the comparison and exchange request includes a first operand, a second operand and the memory address, the first operand is a value stored in the memory address, and the second operand is obtained by the coprocessor performing a floating-point addition operation according to the first operand and the accumulated value; In response to the compare and swap request, the main processor performs a compare and swap operation to obtain a comparison result; The main processor generates a processing result according to the comparison result and sends it to the coprocessor, wherein the processing result includes a storage value of the memory address; In response to the processing result, the coprocessor determines whether the floating-point addition instruction is executed; Wherein, when the comparison result indicates that the storage value is the same as the first operand, the main processor stores the second operand to the memory address, and when the comparison result indicates that the storage value is different from the first operand, does not perform storage operation on the memory address.

10. The method according to claim 9, wherein: The method further comprises: The coprocessor generates a read request according to the memory address; The coprocessor sends the read request to the main processor; The main processor accesses the memory address to read the first operand according to the read request; The first operand is fed back by the main processor to the coprocessor.

11. The method according to claim 9, wherein: The processing result includes the storage value of the memory address, and the coprocessor determines whether the floating-point addition instruction is executed, including: comparing, by the coprocessor, the stored value with the first operand; When the stored value is the same as the first operand, the coprocessor determines that the floating-point addition instruction is executed; When the stored value is different from the first operand, the coprocessor determines that the floating-point addition instruction is not executed to completion.

12. The method according to claim 11, further comprising: When the coprocessor determines that the floating-point addition instruction is executed completely, the coprocessor generates and sends a completion response of the floating-point addition instruction.

13. The method according to claim 11, further comprising: When the coprocessor determines that the floating-point addition instruction has not been executed to completion, the coprocessor uses the stored value as the first operand, regenerates the compare and exchange request, and sends the regenerated compare and exchange request to the main processor.

14. The method according to claim 9, wherein: The main processor performs the comparison and exchange operations to obtain the comparison result, which includes: The main processor accesses the memory address to read the storage value of the memory address; The main processor compares the stored value with the first operand to obtain the comparison result.

15. The method according to any one of claims 9 to 14, wherein: The coprocessor includes a Peripheral Component Interconnect Express (PCIe) controller.

16. The method according to any one of claims 9 to 14, wherein: The data processing device includes a plurality of coprocessors. When each coprocessor in the plurality of coprocessors determines that the corresponding floating-point addition instruction is executed, the plurality of coprocessors complete the floating-point accumulation operation.

17. A floating point number processing device, comprising: A receiving unit is configured to receive a floating-point addition operation instruction, wherein the floating-point addition operation instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; an operand acquisition unit, configured to acquire a first operand, wherein the first operand is a value stored in the memory address; an operation unit, configured to perform a floating-point addition operation according to the first operand and the accumulated value to obtain a second operand; a request generation unit configured to generate a compare and exchange request according to the first operand, the second operand and the memory address, and send the compare and exchange request to a main processor; and The determination unit is configured to determine whether the floating-point addition instruction is executed in response to a processing result of the comparison and exchange request received from the main processor.

18. The floating point number processing device according to claim 17, wherein: The floating point number processing device is implemented as a Peripheral Component Interconnect Express (PCIe) controller.

19. A floating point number processing device, comprising: a receiving unit configured to receive a compare and exchange request obtained by a floating-point addition instruction from a coprocessor, wherein the compare and exchange request includes the first operand, the second operand and a memory address; A memory access unit, configured to access the memory address to read a storage value of the memory address; a comparing unit, configured to compare the stored value with the first operand to obtain a comparison result; A result generating unit is configured to generate a processing result of the comparison and exchange request according to the stored value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the stored value; and The processing unit is configured to store the second operand to the memory address when the comparison result indicates that the storage value is the same as the first operand, and not perform a storage operation on the memory address when the comparison result indicates that the storage value is different from the first operand.

20. A floating point number processing device, comprising: at least one processing device and memory; Wherein, a computer program is stored in the memory, and when the computer program is executed by the at least one processing device, the method described in any one of claims 1 to 6 is implemented, or the method described in claim 7 or 8 is implemented.

21. A computer-readable storage medium having computer-executable instructions stored thereon, wherein: When the instructions are executed by a processor, the method according to any one of claims 1 to 6 or the method according to claim 7 or 8 is implemented.

22. An electronic device comprising the floating point number processing device according to any one of claims 17-20.

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