Periodic restart test circuit, method and equipment

Abstract

The embodiment of the invention provides a periodic restart test circuit, method and equipment, and relates to the technical field of electronic engineering. The circuit comprises a BMC and a timer chip, the output end of the BMC is connected with the first input end of the timer chip, the output end of the timer chip is connected with the input end of a power supply of the electronic equipment, and the power supply is used for supplying power to the electronic equipment and the BMC; the BMC is used for sending a reset signal to the timer chip after being powered on so as to reset the timer chip; and the timer chip is used for periodically controlling power-on and power-off of the power supply according to the reset signal. Therefore, the effect of reducing the periodic restart test cost of the electronic equipment is achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic engineering technology, and in particular to a periodic restart test circuit, method and device. Background Art

[0002] With the popularization of electronic products, the dependence of devices on power supply is increasing. In order to ensure that the devices can remain stable during power fluctuations, periodic restart tests on the devices have become an important means of detecting device performance and stability.

[0003] In the prior art, the method for periodic restart testing of equipment is mainly: using an external power supply controller to control voltage and frequency; then using a computer and control software to write a corresponding test program; based on the test program, linking the power supply controller and measuring instruments, and when the numerical value of the measuring instrument is stable, recording the corresponding test data, thereby obtaining multiple test data of the periodic restart test; and based on the test data, the stability and reliability of the equipment can be analyzed.

[0004] Since the testing method in the prior art requires the device to be connected to an external control device, the environment deployment is complex and the testing site is limited, the prior art has a technical problem of high cost for periodic restart testing of electronic devices. Summary of the invention

[0005] The embodiments of the present application provide a periodic restart test circuit, method and device to achieve the desired effect.

[0006] In a first aspect, an embodiment of the present application provides a periodic restart test circuit, comprising:

[0007] System management chip BMC and timer chip;

[0008] The output end of the BMC is connected to the first input end of the timer chip, and the output end of the timer chip is connected to the input end of the power supply of the electronic device, and the power supply is used to supply power to the electronic device and the BMC;

[0009] The BMC is used to send a reset signal to the timer chip after power-on to reset the timer chip;

[0010] The timer chip is used to reset the current timing duration to zero according to the reset signal, and restart the timing to obtain a new timing duration;

[0011] The timer chip is also used to periodically control the power on and off of the power supply according to the reset signal.

[0012] In a possible implementation manner, the timer chip is specifically used for:

[0013] According to the reset signal, start timing and obtain a new timing duration;

[0014] Send a power-off signal to the power supply;

[0015] When the new timing duration reaches the preset duration, a power-on signal is sent to the power supply.

[0016] In a possible implementation, the power supply includes a front-end power domain and a system operating power domain;

[0017] The output end of the timer chip is connected to the input end of the system working power domain, and the system working power domain is used to supply power to electronic equipment and BMC;

[0018] The second input terminal of the timer chip is connected to the output terminal of the front-stage power domain, and the front-stage power domain is used to continuously supply power to the timer chip.

[0019] In a possible implementation manner, the circuit further includes:

[0020] an oscillator frequency adjustment subcircuit, wherein the output end of the oscillator frequency adjustment subcircuit is connected to the third input end of the timer chip;

[0021] The oscillator frequency adjustment subcircuit is used to set the counting frequency of the timer chip.

[0022] In a possible implementation manner, the circuit further includes:

[0023] A reset module, wherein an output terminal of the reset module is connected to a fourth input terminal of the timer chip;

[0024] The reset module is used to send a reset signal to the timer chip when the timer chip is powered on, so as to reset the timer chip.

[0025] In a possible implementation manner, the circuit further includes:

[0026] A frequency divider, wherein an output terminal of the frequency divider is connected to a fifth input terminal of the timer chip;

[0027] The divider is used to set the timer count stage division ratio.

[0028] In a possible implementation manner, the circuit further includes:

[0029] A level selection module, wherein an output terminal of the level selection module is connected to a sixth input terminal of the timer chip;

[0030] The level selection module is used to control the effective level of the power-on signal sent by the timer chip to the system working power domain.

[0031] In a second aspect, an embodiment of the present application provides a periodic restart test method, including:

[0032] After power-on, the BMC sends a reset signal to the timer chip; wherein the output end of the BMC is connected to the first input end of the timer chip, and the output end of the timer chip is connected to the input end of the power supply of the electronic device, and the power supply is used to supply power to the electronic device and the BMC;

[0033] The timer chip periodically controls the power on and off according to the reset signal;

[0034] Collect test results of electronic equipment.

[0035] In a possible implementation, the timer chip periodically controls power on and off of the power supply according to the reset signal, including:

[0036] According to the reset signal, start timing and obtain a new timing duration;

[0037] Send a power-off signal to the power supply;

[0038] When the new timing duration reaches the first preset duration, a power-on signal is sent to the power supply.

[0039] In a possible implementation, after powering on, the BMC sends a reset signal to the timer chip, including:

[0040] After the BMC is powered on, it starts counting and gets the power-on duration.

[0041] When the power-on time reaches a second preset time, a reset signal is sent to the timer chip.

[0042] In a possible implementation manner, after the BMC is powered on and before sending a reset signal to the timer chip, the method further includes:

[0043] The timer chip obtains the counting frequency input by the oscillator frequency adjustment subcircuit and the timer counting level frequency division ratio input by the frequency divider;

[0044] The timer chip determines the first preset duration according to the counting frequency and the frequency division ratio of the timer counting stage.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, comprising the periodic restart test circuit of any one of the first aspects.

[0046] The periodic restart test circuit, method and device provided in the embodiment of the present application are periodic restart test circuit, method and device. By connecting the output end of the system management chip and the first input end of the timer chip, and connecting the output end of the timer chip and the power input end of the electronic device; after the system management chip is powered on, a reset signal is sent to the timer chip; the timer chip realizes the reset of the timing duration based on the reset signal and starts a new round of timing; at the same time, the timer chip sends a power-off signal to the power supply to prompt the power supply to turn off, and when the timing reaches a preset duration, a power-on signal is sent to the power supply to prompt the power supply to turn on. Thus, the on and off of the power supply is controlled by the periodic change characteristics of the timer chip, so as to achieve the purpose of controlling the periodic restart of the electronic device and promote the periodic restart test of the electronic device. Compared with the prior art, there is no need to access external devices, thereby achieving the effect of reducing the cost of periodic restart testing of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0048] Figure 1 The structure of the periodic restart test circuit provided in this application is shown as follows Figure 1 ;

[0049] Figure 2 The structure of the periodic restart test circuit provided in this application is shown as follows Figure 2 ;

[0050] Figure 3 A flowchart of the periodic restart test method provided in this application.

[0051] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] First, the terms involved in this application are explained:

[0054] Baseboard Management Controller (BMC): An important hardware component in servers and other computer systems that monitors and manages various aspects of the system. The BMC is usually integrated into the motherboard and is responsible for various management tasks, especially when the operating system is not running.

[0055] General Purpose Input / Output (GPIO): refers to the general purpose input and output port of the BMC. The specific usage of the port can be set to realize the information output and information reception of the BMC. It is mainly used for the interaction between the BMC and external devices.

[0056] Timer chips: are important components in electronic devices for generating precise time delays, timing, and event scheduling. These chips can provide a reliable time base for a variety of applications and are widely used in microcontrollers, computer systems, and embedded devices.

[0057] Auto Reset (AR): is a function used in electronic devices, microcontrollers or systems that automatically restores the device or system to its initial state under certain conditions. This concept is widely used in various electronic and embedded systems, especially when abnormal situations need to be handled.

[0058] Manual Reset (MR): A mechanism that requires manual intervention by the user to restore a device or system to a normal state when a fault or abnormal condition occurs. Compared with automatic reset (AR), active reset usually requires user action, such as pressing a button, switching a switch, or restarting the device, or actively triggering it using a controller.

[0059] Select Level (SEL) is a mechanism or function used in electronic circuits and systems to select signals of different levels. It is often used in multiplexers, data selectors, control signals, etc. to determine which input signal is selected and passed to the output. In different designs and applications, level selection can have different functions and implementations.

[0060] A frequency divider is a circuit or device that reduces the frequency of an input signal to a specific ratio, thereby obtaining a lower frequency output signal. Frequency dividers are widely used in digital circuits, clock generation, and synchronization.

[0061] In the prior art, due to the popularity of electronic products, the operation of various industries has been increasingly dependent on electronic products. Therefore, the demand for reliability testing of electronic products has also been increasing. Among them, in view of the high dependence of electronic products on power supply, periodic restart testing of equipment has become an important means of reliability testing of electronic equipment. In the prior art, the main method of periodic restart testing of equipment is: for the electronic equipment to be tested, network access is performed, and the power controller and related equipment detectors are connected; the power controller is used to periodically switch the power supply that the equipment depends on, so as to obtain multiple test data, and the reliability analysis of the electronic equipment is realized based on the multiple test data.

[0062] However, in the prior art, the periodic restart test of electronic devices is mainly achieved by connecting external devices, and the deployment of external devices needs to be combined with the working environment of the electronic equipment to determine whether it is applicable. For example, in the prior art, a power controller is often used in a computer room environment to control the power supply of the server equipment in the computer room, and then a detection device is used to detect the data generated by the server equipment when the power supply changes periodically. In non-computer room scenarios or when changing to other computer rooms, the equipment for the relevant periodic restart test needs to be redeployed, and the use place of this method is fixed and is not suitable for other test environments. Therefore, there is a technical problem in the prior art that the cost of periodic restart testing of electronic devices is high.

[0063] In view of the above technical problems, the present application proposes the following concept: In the prior art, the method for periodic restart test of electronic equipment is to switch the power supply through an external power supply controller and perform data detection of the electronic equipment. Since the applicable scene of this method is fixed, and the relevant equipment needs to be redeployed when switching the place, the test cost is high. Therefore, it can be modified from the inside of the electronic equipment to avoid external equipment access and can be applied to a variety of scenarios. Specifically: using the periodic change characteristics of the timer chip, the timer chip is used to control the open source on and off of the power supply of the electronic equipment; the first input connection end of the timer chip is connected to the output end of the system management chip to receive the reset signal from the system management chip; the output end of the timer chip is connected to the input end of the power supply to send a power-on signal or a power-off signal to the power supply. When the timer receives the reset signal, the timer chip counts and resets, and sends a power-off signal to the power supply to control the power supply to disconnect; when the timer chip counts to a preset time, a power-on signal is sent to the power supply to control the power supply to be connected, thereby achieving periodic switching control of the power supply. While ensuring that multiple devices are applicable, there is no need to deploy additional external devices, thereby achieving the effect of reducing the cost of periodic restart testing of electronic devices.

[0064] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0065] Figure 1 The structure of the periodic restart test circuit provided in this application is shown as follows Figure 1 ,like Figure 1 As shown, the test circuit includes: BMC110 and a timer chip 120.

[0066] The output terminal 111 of the BMC 110 is connected to the first input terminal 121 of the timer chip 120 . The output terminal 127 of the timer chip 120 is connected to the input terminal 133 of the power supply 130 of the electronic device 100 . The power supply 130 is used to supply power to the electronic device 100 and the BMC 110 .

[0067] In this embodiment, the types of timer chip 120 include but are not limited to: monostable timer, bistable timer, multivibrator, microcontroller built-in timer, digital timer. This application does not limit the specific type of timer chip. In actual applications, the appropriate timer chip can be selected based on the proposed method and the actual need for the device to perform AC power periodic restart test.

[0068] Optionally, the BMC 110 is configured to send a reset signal to the timer chip 120 after power-on, so as to reset the timer chip 120 .

[0069] The timer chip 120 is used to periodically control power on and off of the power supply according to the reset signal.

[0070] In a possible implementation, the timer chip 120 is specifically used for:

[0071] According to the reset signal, start timing and obtain a new timing duration.

[0072] A power-off signal is sent to the power supply 130 .

[0073] When the new timing duration reaches the preset duration, a power-on signal is sent to the power supply 130 .

[0074] In this embodiment, the power-on signal and the power-off signal refer to control signals sent by the timer chip 120, which are used to instruct the power supply 130 of the electronic device 100 to turn on and off. The timer chip 120 and the BMC 110 can be deployed in other devices except the current electronic device 100, and use other power supplies as power supply. Or the timer chip 120 and the BMC 110 are deployed in the current electronic device 100, and use the current power supply 130 as the power supply.

[0075] In a possible implementation, the power supply 130 includes a front-end power domain 131 and a system operating power domain 132;

[0076] The output terminal 127 of the timer chip 120 is connected to the input terminal 133 of the system working power domain 132, and the system working power domain 132 is used to supply power to the electronic device 100 and the BMC 110;

[0077] The second input terminal 122 of the timer chip 120 is connected to the output terminal 134 of the front-stage power domain 131 . The front-stage power domain 131 is used to supply power to the timer chip 120 .

[0078] In this embodiment, when the timer chip 120 controls the power on and off of the electronic device 100, the timer chip 120 always remains in a powered state, that is, whether the front-stage power domain 131 and the system working power domain 132 are powered is not synchronized, and the front-stage power domain 131 always remains in a powered state after the power supply 130 is powered on, thereby ensuring that the timer chip 120 used for power on and off control always remains in a powered state.

[0079] It should be noted that the second input terminal 122 of the timer chip 120 in the present application refers to a power supply port of the timer chip 120. Different timer chips have different voltage requirements, so the voltage range received by the second input terminal 122 is not fixed. For example, if the timer chip 120 used is a monostable timer, the power supply range that the timer chip 120 can accept can be determined to be 1.5V-15V. Therefore, when the power supply voltage exceeds this range, the second input terminal 122 cannot be powered normally, causing the timer chip 120 to fail to work normally.

[0080] In a possible implementation, the test circuit further includes: an oscillator frequency adjustment subcircuit 140, wherein an output terminal 141 of the oscillator frequency adjustment subcircuit 140 is connected to the third input terminal 123 of the timer chip 120;

[0081] The oscillator frequency adjustment subcircuit 140 is used to set the counting frequency of the timer chip 120 .

[0082] In this embodiment, the oscillator frequency adjustment subcircuit 140 is composed of a resistor and capacitor oscillator circuit, and uses resistors and electrophoretic elements to generate periodic waveforms, and can generate low-frequency signals of 1Hz to 1MHzd. Exemplarily, a specific implementation method of setting the counting frequency of the timer chip 120 based on the oscillator frequency adjustment subcircuit 140 is: based on the resistor R1, the resistor R2 and the capacitor C1 to form the oscillator frequency adjustment subcircuit 140, by changing the resistance values ​​of the resistor R1 and the resistor R2, and changing the capacitance value of the capacitor C1, to adjust the output frequency of the oscillator frequency adjustment subcircuit 140. The third input terminal 123 of the timer chip 120 can be used as the clock input pin of the timer chip 120, and the frequency output by the oscillator frequency adjustment subcircuit 140 can be used as the clock frequency of the timer chip 120, that is, the counting frequency.

[0083] In a possible implementation, the test circuit further includes: a reset module 150, wherein an output terminal 151 of the reset module 150 is connected to the fourth input terminal 124 of the timer chip 120;

[0084] The reset module 150 is used to send a reset signal to the timer chip 120 when the timer chip 120 is powered on, so as to reset the timer chip 120 .

[0085] In this embodiment, the reset module 150 is used to realize the automatic reset of the timer chip 120. Exemplarily, a specific implementation method of automatically resetting the timer chip 120 based on the reset module 150 can be: when the timer chip 120 has a reset pin, the reset pin can be regarded as the fourth input terminal 124; the reset module 150 can be regarded as a delay circuit composed of a resistor and a capacitor. The default level of the reset module 150 is set to a high level. When the timer chip 120 is powered on, the capacitor in the reset module 150 is temporarily short-circuited, resulting in the output level of the reset module 150 being a low level. The reset pin receives a low level, triggering the reset of the timer chip 120.

[0086] In a possible implementation, the test circuit further includes: a frequency divider 160, wherein an output terminal 161 of the frequency divider 160 is connected to a fifth input terminal 125 of the timer chip 120;

[0087] The frequency divider 160 is used to set the frequency division ratio of the counting stage of the timer 120 .

[0088] In this embodiment, the frequency divider 160 is a commonly used digital circuit component, which is used to reduce the frequency of an input signal to a specific output frequency.

[0089] The counting level frequency division ratio includes: counting type, counter level corresponding to the technology type, and counting value. For example, the counting type is represented by AB, the counter level is represented by N, and the counting value is represented by 2N. Then the four technology types are: AB=00, N=13, 2N=8192; AB=01, N=10, 2N=1024; AB=10, N=8, 2N=256; AB=11, N=16, 2N=65535.

[0090] The count value may also be used to calculate the preset duration of the timer chip 120. For example, if the clock input frequency of the timer chip 120 is 500 Hz and the count value is 8192, the calculated preset duration may be determined to be 16 seconds.

[0091] In a possible implementation, the detection circuit further includes: a level selection module 170, an output terminal 171 of the level selection module 170 is connected to the sixth input terminal 126 of the timer chip 120;

[0092] The level selection module 170 is used to control the timer chip 120 to send a valid level of a power-on signal to the system working power domain 132 .

[0093] In this embodiment, the level selection module 170 is used to output effective level information. After receiving the effective level information, the timer chip 120 outputs a power-up signal or a power-down signal based on the effective level information and the output terminal 127 .

[0094] For example, a specific implementation method of implementing the up and down electrical signal transmission of the timer chip 120 based on the level selection module 170 may be:

[0095] The effective level of the power-on signal selected by the level selection module 170 is high level effective; the timer chip 120 receives the selection information of the effective level of the power-on signal sent by the level selection module based on the sixth input terminal 126. When the timer chip 120 is triggered to reset, the timer chip 120 determines that the signal currently required to be sent based on the output terminal 127 is a power-off signal based on the reset signal. At this time, the effective level of the power-on signal defined in the level selection module 170 is high level, and the output terminal 127 of the timer chip 120 sends a low level effective power-off signal to the outside.

[0096] When the timing duration of the timer chip 120 reaches the preset duration, the timer chip 120 ends timing and needs to send a power-on signal based on the output terminal 127. At this time, the effective level of the power-on signal determined by the level selection module 170 is a high level, and the output terminal 127 of the timer chip 120 sends a power-on signal corresponding to the high level.

[0097] It should be noted that the description of the level selection module in the present application is only an exemplary description, and in actual application scenarios, a variety of methods can be used to implement the external signal output control of the timer chip.

[0098] The periodic restart test circuit provided by the embodiment of the present application is connected by connecting the output end of the system management chip and the first input end of the timer chip, and connecting the output end of the timer chip and the power input end of the electronic device; after the system management chip is powered on, a reset signal is sent to the timer chip; the timer chip resets the timing duration based on the reset signal and starts a new round of timing; at the same time, the timer chip sends a power-off signal to the power supply to prompt the power supply to turn off, and when the timing reaches a preset duration, a power-on signal is sent to the power supply to prompt the power supply to turn on. Thus, the power supply is controlled by the periodic even characteristic of the timer chip, so as to provide a periodic AC power supply to the electronic device and promote the periodic restart test of the electronic device. Compared with the prior art, there is no need to access external devices, thereby achieving the effect of reducing the cost of the periodic restart test of the device.

[0099] Figure 2 The structure of the periodic restart test circuit provided in this application is shown as follows Figure 2 .exist Figure 1 Based on the embodiment shown in the figure, this embodiment further describes the detection circuit in detail. Figure 2 As shown, the detection circuit includes: a timer chip 201, a front-stage power domain 202, a system working power domain 203, an oscillator frequency adjustment subcircuit 204, a reset module 205, a whole machine power input module 206, a level selection module 207, a divider 208, a system power switch 209, a system working power input module 210, and a BMC 211.

[0100] The front-end power domain 202 includes: a timer chip 201, a system working power domain 203, an oscillator frequency adjustment subcircuit 204, a reset module 205, a whole machine power input module 206, a level selection module 207, a frequency divider 208, and a system power switch 209. The system working power domain 203 includes: a system working power input module 210 and a BMC 211.

[0101] The timer chip 201 includes: a power pin VDD, which is used to connect the whole machine power input module 206 to obtain power supply. An input pin f is used to connect the oscillator frequency adjustment subcircuit 204 to obtain clock input. An automatic reset pin AR is used to connect the reset module 205 to obtain a reset signal and trigger the automatic reset of the timer chip 201. An active reset pin MR is used to connect the BMC, receive an active reset signal from the BMC, and trigger the active reset of the timer chip 201. An output level selection pin SEL is used to connect the level selection module 207, and determine whether a high level or a low level should be output according to the level selection information of the level selection module 207. A frequency division setting pin AB is used to connect the frequency divider 208, to receive the counting level frequency division ratio output by the frequency divider 208, and to count and set the clock frequency based on the counting level frequency division ratio. A level output pin Q is used to connect the system power switch 209, and output a high level or a low level to the system power switch 209 to control the on and off of the system power source 209. The whole machine power input module 206 is also connected to the system power switch 209, and the system power switch 209 is connected to the system working power input module 210. The on and off of the system power switch 209 determines whether the system working power input module 210 is in a powered state; the system working power input module 210 is used to supply power to BMC211.

[0102] The BMC 211 includes an output pin GPIO, which is used to be connected to an active reset pin MR of the timer chip 201 , and sends an active reset signal to the timer chip 201 through the output pin GPIO based on a script program running in the BMC.

[0103] In this embodiment, a circuit structure of integrating a timer chip into a system mainboard or a power mainboard of an electronic device is described in detail, and the periodic state change characteristics of the timer chip are used to realize the periodic on-off control of the working power of the electronic device, thereby realizing the periodic switching of the AC power supply inside the electronic device. Compared with the method of switching using an external power controller in the prior art, large-scale redeployment is not required, thereby reducing the cost of periodic restart testing of the device.

[0104] Figure 3 The following is a flow chart of a periodic restart test method provided by the present application. Based on the above embodiments, the present application provides a periodic restart test method, such as Figure 3 As shown, the method includes:

[0105] S301, the timer chip obtains the counting frequency input by the oscillator frequency adjustment subcircuit and the timer counting stage frequency division ratio input by the frequency divider.

[0106] S302: The timer chip determines a first preset duration according to a counting frequency and a division ratio of a timer counting stage.

[0107] In this step, the counting frequency of the timer chip can be set in the range of 0 to 100kHZ, and a specific counting frequency can be obtained by adjusting the oscillator frequency adjustment subcircuit. The calculation method of the first preset duration can be: determine the frequency division counting category of the timer chip based on the timer counting level division ratio, determine the counter level based on the frequency division technology category, determine the count value based on the counter level, and determine the first preset duration based on the count value and the counting frequency. Exemplarily, if the frequency division counting category is 01, the corresponding counter level is 10, and the count value obtained by calculating 2 to the power of 10 is 1024. The counting frequency input by the oscillator frequency adjustment subcircuit is 100Hz, then based on the count value divided by the count frequency, the first preset duration obtained is 10.24 seconds, which is rounded to the integer, and the first preset duration finally determined is 10 seconds.

[0108] S303: After powering on, the BMC sends a reset signal to the timer chip.

[0109] The execution subject of this embodiment is the periodic restart test circuit referred to in any one of the above embodiments.

[0110] In this step, the output end of the BMC is connected to the first input end of the timer chip, and the output end of the timer chip is connected to the input end of the power supply of the electronic device, and the power supply is used to supply power to the electronic device and the BMC.

[0111] Optionally, after the BMC is powered on, a possible implementation method of sending a reset signal to the timer chip includes:

[0112] S3031. After power-on, the BMC starts timing to obtain the power-on duration.

[0113] S3032: When the power-on duration reaches a second preset duration, a reset signal is sent to the timer chip.

[0114] In this step, the second preset duration represents the power-on duration of the BMC and the electronic device corresponding to the BMC. For example, if the duration from the electronic device being connected to the power supply to being fully started is 20 seconds, the second preset duration can be set to 20 seconds, and the startup reliability analysis of the electronic device can be realized by detecting the startup data or operation data generated by each component in the electronic device within the second preset duration.

[0115] S304: The timer chip periodically controls power on and off according to the reset signal.

[0116] Optionally, a possible implementation method of the timer chip periodically controlling the power on and off of the power supply according to the reset signal is:

[0117] S3041. Start timing according to the reset signal and obtain a new timing duration.

[0118] In this step, the reset signal can be regarded as a control signal. When the timer chip receives the reset signal, it will reset the internal state of the timer chip, that is, restore the internal state of the timer chip to the default state. For example, in the normal working mode, the timer chip starts timing and records the timing duration since the last reset; when the reset signal is activated, the timer chip immediately responds and clears the current timer value, that is, clears the timing duration; after clearing, the timer chip restarts a new round of timing.

[0119] S3042. Send a power-off signal to the power supply.

[0120] In this step, the power-off signal is an effective level for controlling the power-off of the power supply. When the effective level of the power-on signal determined by the timer chip is a low level, if the timer chip needs to send a power-off signal, a low level can be sent to the power supply through the output end; when the power-on signal determined by the timer chip is a high level, if the timer chip needs to send a power-off signal, a high level can be sent through the output end.

[0121] In this step, a possible implementation method of the timer chip sending a power-off signal to the power supply of the electronic device is:

[0122] S30421. After receiving the reset signal, the timer chip will output a power-off signal and send the power-off signal to the power supply of the electronic device. The power-off signal can be a change in logic level from high to low, or a specific output pulse.

[0123] S30422. After the power supply receives the power-off signal, the management circuit corresponding to the power supply will execute a shutdown procedure to gradually reduce the system power consumption of the electronic device.

[0124] S3043: When the new timing duration reaches the first preset duration, a power-on signal is sent to the power supply.

[0125] In this step, a possible implementation method of the timer chip sending a power-on signal to the power supply of the electronic device is:

[0126] S30431. When the timer chip detects that the timing duration reaches a first preset duration, the timer chip sends a power-on signal to the power supply of the electronic device through a specific pin; the power-on signal can be a logic high level signal.

[0127] S30432. After receiving the power-on signal, the power supply will continuously connect the power supply to various components of the electronic device by starting the main power supply, and perform initialization processing on each component to guide the complete startup of the electronic device and its corresponding BMC.

[0128] S305: Collect test results of the electronic equipment.

[0129] In this step, a possible implementation method of collecting the test results of the electronic device is:

[0130] S3051. Set a preset collection period based on a restart period of the electronic device.

[0131] S3052: Acquire the operating status data of the electronic device when it is started and the operating status data of the electronic device when it is shut down based on a preset collection period.

[0132] S3053: Perform performance analysis, reliability analysis, and stability analysis on the electronic device based on the operating status data when the electronic device is started and shut down, and obtain test results of the electronic device.

[0133] The periodic restart test method provided in the embodiment of the present application controls the timer chip to reset actively through the BMC, and sends a power-off signal to the power supply of the electronic device based on the reset of the timer chip; performs periodic timing using a first preset time length and sends a power-on signal to the power supply of the electronic device when the timing reaches a cycle; thereby controlling the periodic power switching of the electronic device. The periodic restart of the electronic device is achieved by periodic power switch control. When performing reliability and stability testing on the electronic device, the reliability analysis result or stability test result of the electronic device can be obtained by detecting the operating data generated by the electronic device in the periodic power switching state and analyzing the operating data, thereby avoiding the high-cost deployment of the power controller and achieving the effect of reducing the periodic testing cost of the device.

[0134] The present application also provides an electronic device, comprising a periodic restart test circuit described in any one of the above embodiments and possible implementation methods. The effect of the electronic device is consistent with the effect of the test circuit described in the above embodiments, and will not be repeated here.

[0135] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A periodic restart test circuit, characterized in that: include: System management chip BMC and timer chip; The output end of the BMC is connected to the first input end of the timer chip, and the output end of the timer chip is connected to the input end of a power supply of the electronic device, and the power supply is used to supply power to the electronic device and the BMC; The BMC is used to send a reset signal to the timer chip after power-on to reset the timer chip; The timer chip is used to periodically control the power on and off of the power supply according to a reset signal.

2. The periodic restart test circuit according to claim 1, characterized in that: The timer chip is specifically used for: According to the reset signal, start timing and obtain a new timing duration; Sending a power-off signal to the power supply; When the new timing duration reaches the preset duration, a power-on signal is sent to the power supply.

3. The periodic restart test circuit according to claim 1, characterized in that: The power supply includes a front-stage power domain and a system working power domain; The output end of the timer chip is connected to the input end of the system working power domain, and the system working power domain is used to supply power to the electronic device and the BMC; The second input terminal of the timer chip is connected to the output terminal of the front-stage power domain, and the front-stage power domain is used to supply power to the timer chip.

4. The periodic restart test circuit according to any one of claims 1 to 3, characterized in that: Also includes: an oscillator frequency adjustment subcircuit, wherein the output end of the oscillator frequency adjustment subcircuit is connected to the third input end of the timer chip; The oscillator frequency adjustment subcircuit is used to set the counting frequency of the timer chip.

5. The periodic restart test circuit according to any one of claims 1 to 3, characterized in that: Also includes: A reset module, wherein an output terminal of the reset module is connected to a fourth input terminal of the timer chip; The reset module is used to send a reset signal to the timer chip when the timer chip is powered on, so as to reset the timer chip.

6. The periodic restart test circuit according to any one of claims 1 to 3, characterized in that: Also includes: A frequency divider, wherein an output terminal of the frequency divider is connected to a fifth input terminal of the timer chip; The frequency divider is used to set the frequency division ratio of the timer counting stage.

7. The periodic restart test circuit according to claim 2 or 3, characterized in that: Also includes: A level selection module, wherein an output end of the level selection module is connected to a sixth input end of the timer chip; The level selection module is used to control the timer chip to send the effective level of the power-on signal to the system working power domain.

8. A periodic restart test method, characterized in that: The periodic restart test circuit according to any one of claims 1 to 7, characterized in that it comprises: After power-on, the system management chip BMC sends a reset signal to the timer chip; wherein the output end of the BMC is connected to the first input end of the timer chip, and the output end of the timer chip is connected to the input end of the power supply of the electronic device, and the power supply is used to supply power to the electronic device and the BMC; The timer chip periodically controls power on and off of the power supply according to the reset signal; Collect test results of the electronic device.

9. The method according to claim 8, characterized in that The timer chip periodically controls the power on and off of the power supply according to the reset signal, including: According to the reset signal, start timing and obtain a new timing duration; Sending a power-off signal to the power supply; When the new timing duration reaches the first preset duration, a power-on signal is sent to the power supply.

10. The method according to claim 8 or 9, characterized in that: After powering on, the BMC sends a reset signal to the timer chip, including: After the BMC is powered on, it starts timing and obtains the power-on duration; When the power-on time reaches a second preset time, a reset signal is sent to the timer chip.

11. The method according to claim 8 or 9, characterized in that: After the BMC is powered on, before sending a reset signal to the timer chip, the method further includes: The timer chip obtains the counting frequency input by the oscillator frequency adjustment subcircuit and the timer counting level frequency division ratio input by the frequency divider; The timer chip determines the first preset duration according to the counting frequency and the timer counting stage frequency division ratio.

12. An electronic device, characterized in that: Comprising a periodic restart test circuit as described in any one of claims 1-7.

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