Matrix operation processing method of parallel computing device and related equipment

Abstract

The matrix operation processing method of a parallel computing device and related devices proposed in the embodiments of the present application include: obtaining a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied; obtaining intermediate block parameters, and generating row block parameters and column block parameters; calculating the block data occupancy based on the intermediate block parameters, row block parameters and column block parameters, and iteratively updating the intermediate block parameters; calculating the number of block operation tasks based on the row matrix parameters, row block parameters, column matrix parameters and column block parameters, and iteratively updating the row block parameters and column block parameters; finally, matrix blocking the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate block parameters, row block parameters and column block parameters to perform matrix multiplication operations, effectively utilizing the parallel computing resources of the parallel computing device, and improving the data processing reliability of matrix operations in the parallel computing device.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a matrix operation processing method and related equipment for a parallel computing device. Background Art

[0002] With the continuous development of neural networks, scientific computing and artificial intelligence, these disciplines have gradually been applied to life and work in recent years. As the input feature maps used in these fields become larger and larger, and the number of layers and coupling relationships of the models used become more and more complex, computing performance has become one of the key indicators in these fields. Among them, matrix multiplication operations are widely used in these disciplines. Therefore, improving the performance of matrix multiplication operations is crucial.

[0003] In the related art, for the multiplication operation of high-dimensional matrices, usually before performing the matrix operation, the matrix to be multiplied is divided into multiple block matrices according to the preset matrix block size for matrix multiplication, so as to give full play to the parallel computing ability of the hardware to improve the efficiency of the multiplication operation. However, since different hardware devices have different processing capabilities at the same time, and the dimensions of the matrix to be multiplied for each matrix multiplication are also different, the use of the preset matrix block size for matrix division is prone to the situation that the matrix division is too large, resulting in the hardware device being unable to perform matrix multiplication, or the situation that the division matrix is ​​too small to waste too many idle computing resources, resulting in the low reliability of this matrix multiplication operation processing method. Summary of the invention

[0004] The embodiments of the present application provide a matrix operation processing method and related devices for a parallel computing device, which can improve the data processing reliability of matrix operations in parallel computing hardware.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a matrix operation processing method of a parallel computing device, the method comprising:

[0006] Obtaining a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied, wherein the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes the intermediate matrix parameter and a column matrix parameter;

[0007] Obtaining intermediate block parameters, and generating row block parameters and column block parameters based on a ratio of the row matrix parameters to the column matrix parameters;

[0008] The block data occupancy amount is calculated based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy amount exceeds the preset buffer capacity, the intermediate block parameter is reduced, and the block data occupancy amount is recalculated based on the updated intermediate block parameter until the block data occupancy amount does not exceed the preset buffer capacity;

[0009] The number of block operation tasks is calculated based on the row matrix parameter, the row block parameter, the column matrix parameter and the column block parameter. When the number of block operation tasks exceeds the number of available tasks, the row block parameter and the column block parameter are increased, and the number of block operation tasks is recalculated based on the updated row block parameter and the column block parameter until the number of block operation tasks does not exceed the number of available tasks;

[0010] Matrix blocking is performed on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameters, the row blocking parameters and the column blocking parameters to perform a matrix multiplication operation.

[0011] In some embodiments, generating row blocking parameters and column blocking parameters based on the ratio of the row matrix parameter to the column matrix parameter includes:

[0012] Obtaining a first adjustment parameter based on a ratio of the row matrix parameter to the column matrix parameter;

[0013] obtaining a second adjustment parameter based on the value of the first adjustment parameter;

[0014] The row blocking parameter and the column blocking parameter are generated based on the second adjustment parameter.

[0015] In some embodiments, obtaining the second adjustment parameter based on the value of the first adjustment parameter includes:

[0016] Acquire a plurality of preset threshold intervals and a preset adjustment parameter corresponding to each of the preset threshold intervals;

[0017] A preset threshold interval matching the value of the first adjustment parameter is selected from the plurality of preset threshold intervals as a target interval, and a preset adjustment parameter corresponding to the target interval is used as the second adjustment parameter.

[0018] In some embodiments, generating the row blocking parameter and the column blocking parameter based on the second adjustment parameter includes:

[0019] When the second adjustment parameter exceeds a preset threshold parameter, the column block parameter is generated, and the row block parameter is obtained based on the product of the column block parameter and the second adjustment parameter;

[0020] When the second adjustment parameter does not exceed a preset threshold parameter, the row blocking parameter is generated, and the column blocking parameter is obtained based on a ratio of the row blocking parameter to the second adjustment parameter.

[0021] In some embodiments, the block data occupancy includes a first block data occupancy, a second block data occupancy, and a third block data occupancy, and the block data occupancy is calculated based on the intermediate block parameter, the row block parameter, and the column block parameter, including:

[0022] Get the data volume parameters;

[0023] Obtaining the first block data occupancy amount based on the product of the row block parameter, the intermediate block parameter and the data amount parameter;

[0024] Obtaining the second block data occupancy amount based on the product of the middle block parameter, the column block parameter and the data amount parameter;

[0025] The third block data occupancy is obtained based on the product of the row block parameter, the column block parameter and the data amount parameter.

[0026] In some embodiments, when the block data occupancy exceeds a preset buffer capacity, reducing the intermediate block parameter, and recalculating the block data occupancy based on the updated intermediate block parameter, comprises:

[0027] When at least one of the first block data occupancy, the second block data occupancy, and the third block data occupancy exceeds the preset buffer capacity, reducing the intermediate block parameter, and recalculating the block data occupancy based on the updated intermediate block parameter;

[0028] When the updated block data occupancy exceeds the preset buffer capacity and the intermediate block parameter is reduced to the preset intermediate minimum parameter, the row block parameter and the column block parameter are updated based on the updated intermediate block parameter, and the block data occupancy is recalculated based on the updated intermediate block parameter, the row block parameter and the column block parameter.

[0029] In some embodiments, the calculating the number of block operation tasks based on the row matrix parameter, the row block parameter, the column matrix parameter, and the column block parameter includes:

[0030] Obtaining a row parameter ratio based on a ratio of the row matrix parameter to the row block parameter;

[0031] Obtaining a column parameter ratio based on a ratio of the column matrix parameter to the column blocking parameter;

[0032] The number of block operation tasks is obtained based on the product of the row parameter ratio and the column parameter ratio.

[0033] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application proposes a matrix operation processing device of a parallel computing device, the device comprising:

[0034] a matrix dimension acquisition module, used to acquire a first matrix dimension of a first matrix to be multiplied, and to acquire a second matrix dimension of a second matrix to be multiplied, wherein the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes the intermediate matrix parameter and a column matrix parameter;

[0035] An initial block parameter acquisition module, used to acquire intermediate block parameters, and generate row block parameters and column block parameters based on the intermediate block parameters;

[0036] A first adjustment module is configured to calculate the block data occupancy based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy exceeds a preset buffer capacity, reduce the intermediate block parameter, and recalculate the block data occupancy based on the updated intermediate block parameter until the block data occupancy does not exceed the preset buffer capacity;

[0037] A second adjustment module is used to calculate the number of block operation tasks based on the row matrix parameters and the row block parameters, the column matrix parameters and the column block parameters, and when the number of block operation tasks exceeds the number of available tasks, increase the row block parameters and the column block parameters, and recalculate the number of block operation tasks based on the updated row block parameters and the column block parameters until the number of block operation tasks does not exceed the number of available tasks;

[0038] The block execution module is used to perform matrix blocking on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameter, the row blocking parameter and the column blocking parameter to perform a matrix multiplication operation.

[0039] To achieve the above-mentioned purpose, the third aspect of an embodiment of the present application proposes an electronic device, which includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements the matrix operation processing method of the parallel computing device as described in the first aspect.

[0040] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application proposes a storage medium, which is a computer-readable storage medium, and the storage medium stores a computer program. When the computer program is executed by a processor, it implements the matrix operation processing method of the parallel computing device described in the first aspect above.

[0041] The matrix operation processing method of a parallel computing device and related devices proposed in the embodiment of the present application include: first, obtaining a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied, the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes an intermediate matrix parameter and a column matrix parameter; then, obtaining an intermediate block parameter, and generating a row block parameter and a column block parameter based on a ratio of the row matrix parameter to the column matrix parameter; secondly, calculating the block data occupancy based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy exceeds a preset buffer capacity, reducing the intermediate block parameter, and The block data occupancy is recalculated based on the updated intermediate blocking parameters until the block data occupancy does not exceed the preset buffer capacity; next, the number of block operation tasks is calculated based on the row matrix parameters, the row blocking parameters, the column matrix parameters and the column blocking parameters. When the number of block operation tasks exceeds the number of available tasks, the row blocking parameters and the column blocking parameters are increased, and the number of block operation tasks is recalculated based on the updated row blocking parameters and the column blocking parameters until the number of block operation tasks does not exceed the number of available tasks; finally, the first matrix to be multiplied and the second matrix to be multiplied are matrix blocked based on the intermediate blocking parameters, the row blocking parameters and the column blocking parameters to perform matrix multiplication operations. The embodiment of the present application utilizes the intermediate block parameters preset in the parallel computing device and the ratio of the row matrix parameters to the column matrix parameters to generate the row block parameters and the column block parameters, and then iteratively updates the intermediate block parameters using the numerical relationship between the calculated block data occupancy and the preset buffer capacity determined by the parallel computing device, and further iteratively updates the row block parameters and the column block parameters using the numerical relationship between the calculated number of block operation tasks and the number of available tasks determined by the parallel computing device, so as to obtain the intermediate block parameters, row block parameters and column block parameters that are most suitable for the multiplication operation of the first matrix to be multiplied and the second matrix to be multiplied in the parallel computing device, and utilizes the intermediate block parameters, row block parameters and column block parameters to split the first matrix to be multiplied and the second matrix to be multiplied and then perform the operation, so as to effectively utilize the parallel computing resources of the parallel computing device, and also avoid the situation where the matrix division is too large, resulting in the inability of the hardware device to perform matrix multiplication, and the situation where the division matrix is ​​too small, wasting too many idle computing resources, thereby improving the data processing reliability of matrix operations in the parallel computing device.

[0042] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1It is a structural diagram of a parallel computing hardware provided in one embodiment of the present application.

[0044] Figure 2 It is a flowchart of data parallel processing in parallel computing hardware provided by another embodiment of the present application.

[0045] Figure 3 This is a flowchart of a matrix operation processing method of a parallel computing device provided by another embodiment of the present application.

[0046] Figure 4 This is a schematic diagram of the principle of general matrix multiplication block parallel operation provided by another embodiment of the present application.

[0047] Figure 5 yes Figure 3 Flow chart of step 302 in FIG.

[0048] Figure 6 yes Figure 5 Flowchart of step 502 in FIG.

[0049] Figure 7 yes Figure 5 Flow chart of step 503 in FIG.

[0050] Figure 8 yes Figure 3 Flow chart of step 303 in FIG.

[0051] Fig. 9 yes Figure 3 Another flow chart of step 303 in FIG.

[0052] Fig.10 yes Figure 3 Flow chart of step 304 in FIG.

[0053] Fig.11 It is a schematic block diagram of the process of matrix operation processing in parallel computing hardware provided by another embodiment of the present application.

[0054] Fig.12 It is a structural diagram of a matrix operation processing device of a parallel computing device provided in one embodiment of the present application.

[0055] Fig.13 It is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0057] It should be noted that although the functional modules are divided in the device schematic and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0059] With the continuous development of neural networks, scientific computing and artificial intelligence, these disciplines have gradually been applied to life and work in recent years. As the input feature maps used in these fields become larger and larger, and the number of layers and coupling relationships of the models used become more and more complex, computing performance has become one of the key indicators in these fields. Among them, matrix multiplication operations are widely used in these disciplines. Therefore, improving the performance of matrix multiplication operations is crucial.

[0060] In the related art, for the multiplication operation of high-dimensional matrices, usually before performing the matrix operation, the matrix to be multiplied is divided into multiple block matrices according to the preset matrix block size for matrix multiplication, so as to give full play to the parallel computing ability of the hardware to improve the efficiency of the multiplication operation. However, since different hardware devices have different processing capabilities at the same time, and the dimensions of the matrix to be multiplied for each matrix multiplication are also different, the use of the preset matrix block size for matrix division is prone to the situation that the matrix division is too large, resulting in the hardware device being unable to perform matrix multiplication, or the situation that the division matrix is ​​too small to waste too many idle computing resources, resulting in the low reliability of this matrix multiplication operation processing method.

[0061] In order to improve the data processing reliability of matrix operations in parallel computing hardware, an embodiment of the present application uses the intermediate block parameters pre-set in the parallel computing device and the ratio of the row matrix parameters to the column matrix parameters to generate row block parameters and column block parameters, and then iteratively updates the intermediate block parameters using the numerical relationship between the calculated block data occupancy and the preset buffer capacity determined by the parallel computing device, and further iteratively updates the row block parameters and column block parameters using the numerical relationship between the calculated number of block operation tasks and the number of available tasks determined by the parallel computing device, so as to obtain the intermediate block parameters, row block parameters and column block parameters that are most suitable for the first matrix to be multiplied and the second matrix to be multiplied to perform multiplication operations in the parallel computing device, and uses the intermediate block parameters, row block parameters and column block parameters to split the first matrix to be multiplied and the second matrix to be multiplied and then perform operations, so as to effectively utilize the parallel computing resources of the parallel computing device, and also avoid the situation where the matrix division is too large, resulting in the hardware device being unable to perform matrix multiplication, and the division matrix is ​​too small to waste too many idle computing resources, thereby improving the data processing reliability of matrix operations in the parallel computing device.

[0062] In order to better describe the matrix operation processing method of the parallel computing device provided by the present application, the following first describes the parallel computing hardware applied to the matrix operation processing method of the parallel computing device. Parallel computing hardware refers to a hardware device that can perform multiple computing tasks simultaneously. These hardware devices usually have a high degree of parallel computing capabilities and efficient computing resource management capabilities, and can achieve efficient computing and data processing. Figure 1 , is a schematic diagram of the structure of a parallel computing hardware provided in an embodiment of the present application. Figure 1 As shown in , the parallel computing hardware includes multiple smart chips (AICore) and a global buffer (Global Memory). Each smart chip includes a corresponding index (such as block_idx=0 corresponding to AI Core0, etc.). The global buffer stores data blocks corresponding to the processing of each smart chip (such as the data processed by index block0 corresponding to AICore0, etc.).

[0063] In parallel computing hardware, multiple intelligent chips can process corresponding computing data in parallel to effectively improve the computing efficiency of data processing. Figure 2 , is a schematic diagram of a flow chart of data parallel processing in a parallel computing hardware provided in an embodiment of the present application. Figure 2 As shown in the figure, taking three smart chips set in parallel computing hardware as an example, the corresponding data slice to be processed is input to each smart chip respectively, and then the corresponding process processing is performed in the corresponding smart chip to output the corresponding processing completed data slice, so as to realize the parallel processing calculation process in the parallel computing hardware.

[0064] In conjunction with the above-mentioned parallel computing hardware, the matrix operation processing method of the parallel computing device provided in the embodiment of the present application and related devices will be further described below. The matrix operation processing method of the parallel computing device provided in the embodiment of the present application can be applied to a parallel computing device, or a processing device equipped with a parallel computing device.

[0065] The matrix operation processing method of the parallel computing device in the embodiment of the present application will be described in detail below. Figure 3 , which is an optional flowchart of a matrix operation processing method of a parallel computing device provided in an embodiment of the present application, Figure 3 The method in the embodiment may include but is not limited to steps 301 to 305. Figure 3 The order of step 301 to step 305 is not specifically limited, and the order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0066] Step 301: Obtain a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied.

[0067] The following is a detailed description of step 301.

[0068] In some embodiments, when responding to a multiplication operation of a complex matrix (including a first matrix A to be multiplied and a second matrix B to be multiplied), a first matrix dimension of the input first matrix A to be multiplied and a second matrix dimension of the input second matrix B to be multiplied are first analyzed.

[0069] Among them, the first matrix dimension includes the row matrix parameter M and the intermediate matrix parameter K of the first matrix A to be multiplied, that is, ; Similarly, the second matrix dimension includes the second matrix A to be multiplied and the intermediate matrix parameter K and the column matrix parameter N, that is, .

[0070] When the first matrix dimension and / or the second matrix dimension is too large, it is impossible to directly perform the matrix operation processing on a single intelligent chip of the parallel computing device, and the first matrix A to be multiplied and the second matrix B to be multiplied need to be processed. Figure 4 , is a schematic diagram of a general matrix multiplication block parallel operation principle provided by an embodiment of the present application. Figure 4As shown in , the first matrix A to be multiplied and the second matrix B to be multiplied need to be divided to obtain a plurality of smaller first matrix A to be multiplied corresponding to the first block matrix A', and a plurality of smaller second matrix B to be multiplied corresponding to the second block matrix B', so that each first block matrix A' and the corresponding second block matrix B' are input into the corresponding intelligent chip for matrix multiplication operation, so as to make full use of the parallel computing capability of the parallel computing device and improve the computational efficiency of the matrix multiplication operation. Among them, the matrix dimension of the first block matrix A' is M0*K0, the matrix dimension of the second block matrix B' is K0*N0, and the physical core 0 of the corresponding intelligent chip is: A0*B0+A1*B1+A2*B2+A3*B3.

[0071] In order to further improve the computing resource utilization of multiple intelligent chips in a parallel computing device, it is necessary to set appropriate matrix partitioning parameters, that is, to divide the first matrix A to be multiplied into multiple intermediate block parameters and row block parameters of a first block matrix A', and to divide the second matrix B to be multiplied into multiple intermediate block parameters and column block parameters of a second block matrix B', as described below.

[0072] Step 302: Obtain intermediate blocking parameters, and generate row blocking parameters and column blocking parameters based on the ratio of row matrix parameters to column matrix parameters.

[0073] Step 302 is described in detail below.

[0074] In some embodiments, after obtaining the first matrix A to be multiplied and the second matrix B to be multiplied, a preliminary and more suitable intermediate block parameter is preselected. The following example uses the first matrix A to be multiplied and the second matrix B to be multiplied to obtain the target product matrix C by performing a product operation.

[0075]

[0076] (1)

[0077] Among them, the row matrix parameter M of the first matrix A to be multiplied is 16384, the intermediate matrix parameter K is 128, the intermediate matrix parameter of the second matrix B to be multiplied is 128, and the column matrix parameter N is 64. At this time, 128 can be directly selected as the initial intermediate block parameter.

[0078] Then, the initial row blocking parameter BM and column blocking parameter BN are further generated based on the initial intermediate blocking parameter BK, as described in detail below.

[0079] Reference Figure 5 , generating row block parameters and column block parameters based on the ratio of row matrix parameters to column matrix parameters, including the following steps 501 to 503.

[0080] Step 501: Obtain a first adjustment parameter based on a ratio of a row matrix parameter to a column matrix parameter.

[0081] Step 502: Obtain a second adjustment parameter based on the value of the first adjustment parameter.

[0082] Steps 501 to 502 are described in detail below.

[0083] In some embodiments, after obtaining the initial intermediate block parameter BK, the first adjustment parameter a=M / N is obtained based on the ratio of the row matrix parameter M to the column matrix parameter N. In the example of the above formula (1), a=16384 / 64=256. Next, a suitable second adjustment parameter b is obtained based on the value of the first adjustment parameter a, as described below.

[0084] Reference Figure 6 , obtaining the second adjustment parameter based on the value of the first adjustment parameter, includes the following steps 601 to 602.

[0085] Step 601: Acquire multiple preset threshold intervals and a preset adjustment parameter corresponding to each preset threshold interval.

[0086] Step 602: Select a preset threshold interval that matches the value of the first adjustment parameter from a plurality of preset threshold intervals as a target interval, and use the preset adjustment parameter corresponding to the target interval as a second adjustment parameter.

[0087] Steps 601 to 602 are described in detail below.

[0088] In some embodiments, in addition to obtaining the first adjustment parameter a, it is also necessary to obtain multiple preset threshold intervals associated with the first adjustment parameter a and preset adjustment parameters corresponding to each preset threshold interval and associated with the second adjustment parameter b. For example, the preset threshold interval includes , , , as well as , and the corresponding preset adjustment parameters include 4, 2, 1, 1 / 2 and 1 / 4. Then, a preset threshold interval matching the value of the first adjustment parameter a is selected from multiple preset threshold intervals as the target interval, and the preset adjustment parameter corresponding to the target interval is used as the second adjustment parameter b, as shown in the following formula (2).

[0089]

[0090] Step 503: Generate row blocking parameters and column blocking parameters based on the second adjustment parameter and the intermediate blocking parameter.

[0091] Steps 501 to 503 are described in detail below.

[0092] In some embodiments, after obtaining the second adjustment parameter b according to the first adjustment parameter a, the corresponding row block parameter BM and column block parameter BN are further generated according to the second adjustment parameter b and the pre-generated intermediate block parameter BK, as described in detail below.

[0093] Reference Figure 7 , generating row blocking parameters and column blocking parameters based on the second adjustment parameters, including the following steps 701 to 702.

[0094] Step 701: when the second adjustment parameter exceeds the preset threshold parameter, a column blocking parameter is generated, and a row blocking parameter is obtained based on the product of the column blocking parameter and the second adjustment parameter.

[0095] Step 702: When the second adjustment parameter does not exceed the preset threshold parameter, a row blocking parameter is generated, and a column blocking parameter is obtained based on a ratio of the row blocking parameter to the second adjustment parameter.

[0096] Steps 701 to 702 are described in detail below.

[0097] In some embodiments, after obtaining the second adjustment parameter b, the second adjustment parameter is judged according to a preset threshold parameter (i.e., 1). When the second adjustment parameter b exceeds the preset threshold parameter, i.e., b>1, a column block parameter BN is first generated, such as BN=16, and then a row block parameter is further obtained based on the product of the column block parameter BN and the second adjustment parameter b. In contrast, when the second adjustment parameter b does not exceed the preset threshold parameter, that is, , then first generate the row block parameter BM, such as BN=16, and then further obtain the row block parameter based on the product of the column block parameter BN and the second adjustment parameter b. .

[0098] Through the above steps 501 to 503, steps 601 to 602, and steps 701 to 702, the value of the first adjustment parameter generated by the ratio of the row matrix parameter and the column matrix parameter is used to match the second adjustment parameter corresponding to the dimension size of the first matrix to be multiplied and the dimension size of the second matrix to be multiplied, and further based on the value of the second adjustment parameter, relatively suitable row block parameters and column block parameters are preliminarily generated, so as to facilitate subsequent iterative updates based on the relatively suitable row block parameters and column block parameters, so as to improve the calculation efficiency of obtaining the most suitable intermediate block parameters, row block parameters and column block parameters.

[0099] Step 303: The block data occupancy is calculated based on the intermediate block parameters, the row block parameters and the column block parameters. When the block data occupancy exceeds the preset buffer capacity, the intermediate block parameters are reduced, and the block data occupancy is recalculated based on the updated intermediate block parameters until the block data occupancy does not exceed the preset buffer capacity.

[0100] The following is a detailed description of step 303.

[0101] In some embodiments, after the intermediate block parameter BK, the row block parameter BM and the column block parameter BN are preliminarily obtained, in order to generate the most appropriate intermediate block parameter BK, the row block parameter BM and the column block parameter BN to divide the first matrix A to be multiplied and the second matrix B to be multiplied, so as to maximize the use of the parallel computing capability of the parallel computing device for block matrix multiplication operations, it is necessary to further calculate the corresponding block data occupancy based on the current intermediate block parameter BK, the row block parameter BM and the column block parameter BN, so as to facilitate the subsequent iterative update of the intermediate block parameter BK, the row block parameter BM and the column block parameter BN using the block data occupancy, so as to ensure that the first block matrix and the second block matrix after blocking can perform matrix calculations on one smart chip without cache overflow, as described below.

[0102] Reference Figure 8 , based on the middle block parameter, the row block parameter and the column block parameter, the block data occupancy is calculated, including the following steps 801 to 804.

[0103] Step 801: Obtain data volume parameters.

[0104] Step 802: Obtain the first block data occupancy based on the product of the row block parameter, the intermediate block parameter and the data volume parameter.

[0105] Step 803: Obtain the second block data occupancy based on the product of the middle block parameter, the column block parameter and the data volume parameter.

[0106] Step 804: Obtain the third block data occupancy based on the product of the row block parameter, the column block parameter and the data volume parameter.

[0107] Steps 801 to 804 are described in detail below.

[0108] In some embodiments, after the intermediate block parameter BK, the row block parameter BM and the column block parameter BN are initially obtained, the data volume parameter . It is understandable that the data volume parameter It refers to the number of bytes required by a single data under a given data type (i.e., the data type of the first matrix A to be multiplied and the data type of the second matrix B to be multiplied). The block data occupancy includes the first block data occupancy corresponding to the first block matrix, the second block data occupancy corresponding to the second block matrix, and the third data occupancy of the target block matrix constituting the target product matrix.

[0109] Next, based on the row block parameter BM, the intermediate block parameter BK and the data volume parameter The product of gets the first block data occupancy as: ; Similarly, based on the intermediate block parameter BK, the column block parameter BN and the data volume parameter The product of gets the second block data occupancy as: ; and, based on the row block parameter BM, the column block parameter BN and the data volume parameter The product of gets the third block data occupancy as: .

[0110] After obtaining the block data occupancy corresponding to the current intermediate block parameter BK, row block parameter BM and column block parameter BN, the block data occupancy is further compared with the preset buffer capacity. When at least one of the first block data occupancy, the second block data occupancy and the third block data occupancy exceeds the preset buffer capacity, it means that a buffer overflow has occurred, and at least one of the intermediate block parameter BK, the row block parameter BM and the column block parameter BN needs to be adjusted.

[0111] The preset buffer capacity is ,in Represents the size in bytes of the cache space in the smart chip; Represents the number of shares that the cache actually needs to be divided into. If the algorithm design adopts a double buffering strategy, there are usually , otherwise there is usually .

[0112] The following will further describe how to adjust at least one of the intermediate block parameter BK, the row block parameter BM and the column block parameter BN when at least one of the first block data occupancy, the second block data occupancy and the third block data occupancy exceeds the preset buffer capacity.

[0113] Reference Fig. 9 When the block data occupancy exceeds the preset buffer capacity, the intermediate block parameter is reduced, and the block data occupancy is recalculated based on the updated intermediate block parameter, including the following steps 901 to 902.

[0114] Step 901: when at least one of the first block data occupancy, the second block data occupancy and the third block data occupancy exceeds the preset buffer capacity, reduce the intermediate block parameter and recalculate the block data occupancy based on the updated intermediate block parameter.

[0115] Step 902: When the updated block data occupancy exceeds the preset buffer capacity and the intermediate block parameter is reduced to the preset intermediate minimum parameter, the row block parameter and the column block parameter are updated based on the updated intermediate block parameter, and the block data occupancy is recalculated based on the updated intermediate block parameter, the row block parameter and the column block parameter.

[0116] Steps 901 to 902 are described in detail below.

[0117] In some embodiments, when it is determined that at least one of the first block data occupancy, the second block data occupancy, and the third block data occupancy exceeds the preset buffer capacity, the value of the intermediate block parameter BK is first reduced. It can be reduced by a preset reduction value (such as 1), or it can be reduced by customizing it as needed, and then the block data occupancy (including the first block data occupancy, the second block data occupancy, and the third block data occupancy) is calculated again according to the reduced intermediate block parameter BK.

[0118] When the updated block data occupancy (including the first block data occupancy, the second block data occupancy and the third block data occupancy) still exceeds the preset buffer capacity, and the intermediate block parameter BK at this time has been reduced to the preset intermediate minimum parameter (such as 128), a smaller column block parameter BN (or row block parameter BM) will be regenerated according to the relevant description of the above steps 701 to 702 to generate a corresponding smaller row block parameter BM (or column block parameter BN), and then the block data occupancy (including the first block data occupancy, the second block data occupancy and the third block data occupancy) will be recalculated until the first block data occupancy, the second block data occupancy and the third block data occupancy do not exceed the preset buffer capacity.

[0119] Through the above step 305, step 801 to step 804, and step 901 to step 902, the current first block data occupancy, second block data occupancy and third block data occupancy corresponding to different block matrices are calculated in real time according to the current intermediate block parameter, row block parameter and column block parameter, and further compared with the preset buffer capacity of the smart chip, so as to iteratively update at least one of the intermediate block parameter, row block parameter and column block parameter to ensure that cache overflow does not occur, thereby improving the reliability of matrix operation processing in the parallel computing device.

[0120] Step 304: Calculate the number of block operation tasks based on the row matrix parameters, row block parameters, column matrix parameters and column block parameters. When the number of block operation tasks exceeds the number of available tasks, increase the row block parameters and column block parameters, and recalculate the number of block operation tasks based on the updated row block parameters and column block parameters until the number of block operation tasks does not exceed the number of available tasks.

[0121] Step 304 is described in detail below.

[0122] In some embodiments, after obtaining the intermediate block parameter BK, row block parameter BM and column block parameter BN that meet the preset buffer capacity, in order to further generate the most suitable intermediate block parameter BK, row block parameter BM and column block parameter BN to divide the first matrix A to be multiplied and the second matrix B to be multiplied, so as to maximize the use of the parallel computing capability of the parallel computing device for block matrix multiplication operations, it is necessary to further calculate the corresponding number of block operation tasks based on the current row block parameter BM and column block parameter BN, so as to facilitate the subsequent iterative update of the row block parameter BM and column block parameter BN using the number of block operation tasks, so as to ensure that the first block matrix and the second block matrix after block division can maximize the use of the parallel computing capability of the parallel computing device, as described below.

[0123] Reference Fig.10 , the number of block operation tasks is calculated based on the row matrix parameters, the row block parameters, the column matrix parameters and the column block parameters, including the following steps 1001 to 1003.

[0124] Step 1001: Obtain a row parameter ratio based on a ratio of a row matrix parameter to a row block parameter.

[0125] Step 1002: Obtain a column parameter ratio based on a ratio of a column matrix parameter to a column blocking parameter.

[0126] Step 1003: Obtain the number of block operation tasks based on the product of the row parameter ratio and the column parameter ratio.

[0127] Steps 1001 to 1003 are described in detail below.

[0128] In some embodiments, after obtaining the intermediate block parameter BK, the row block parameter BM and the column block parameter BN that satisfy the preset buffer capacity, the row parameter ratio M / BM is obtained based on the ratio of the row matrix parameter M and the row block parameter BM of the first matrix A to be multiplied, and the column parameter ratio N / BN is obtained based on the ratio of the column matrix parameter N and the column block parameter BN of the second matrix B to be multiplied. Then, further, the number of block operation tasks is obtained based on the product of the row parameter ratio and the column parameter ratio: .

[0129] When the number of block computing tasks When the number of available tasks of the current parallel computing device (i.e., the number of physical cores of the multi-core) is exceeded, it means that the number of divided block matrices is too large, resulting in too many block matrix multiplication tasks. In this case, the number of divided block matrices needs to be reduced. Specifically, the proportional relationship between the row block parameter BM and the column block parameter BN (i.e., as described in the above steps 701 to 702) is kept unchanged, and the row block parameter BM and the column block parameter BN are respectively increased by 2 times, i.e. , , in order to reduce unnecessary additional computing tasks in the row and column directions, further exert the computing power of each smart chip single core, and improve the parallel processing of computing parallel computing devices. Then, the number of block computing tasks is recalculated based on the updated row block parameters and column block parameters. Iteratively update the column matrix parameter BM and column block parameter BN until the number of block operation tasks is Do not exceed the number of available tasks.

[0130] Through the above step 304 and steps 1001 to 1003, the number of block operation tasks of the current corresponding block matrix operation is calculated in real time according to the current row block parameters and column block parameters, and is further compared with the number of available tasks representing the number of physical cores of the parallel computing device, so as to iteratively update the row block parameters and column block parameters to maximize the computing power of each single core of the smart chip, so as to improve the parallel processing performance of the parallel computing device, and further improve the resource utilization of matrix operation processing in the parallel computing device.

[0131] Step 305: Perform matrix blocking on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameters, the row blocking parameters and the column blocking parameters to perform a matrix multiplication operation.

[0132] Step 305 is described in detail below.

[0133] In some embodiments, after obtaining the intermediate block parameter BK, the row block parameter BM, and the column block parameter BN that satisfy the preset buffer capacity and the number of available tasks, the intermediate block parameter BK, the row block parameter BM, and the column block parameter BN at this time are used as the block parameters that are most suitable for the current first matrix to be multiplied and the second matrix to be multiplied to perform block matrix multiplication operations in the parallel computing device. Then, based on the intermediate block parameter BK and the row block parameter BM at this time, the first matrix to be multiplied A is divided to obtain a plurality of first block matrices A', and based on the intermediate block parameter BK and the column block parameter BN at this time, the second matrix to be multiplied B is divided to obtain a plurality of second block matrices B', so as to use the plurality of first block matrices A' and the plurality of second block matrices B' to perform matrix multiplication operations in a plurality of intelligent chips in the parallel computing device.

[0134] Reference Fig.11 , is a schematic block diagram of a process flow of matrix operation processing in parallel computing hardware provided by an embodiment of the present application. Fig.11 As shown in , the parallel computing device first determines the initial intermediate block parameter (i.e., BK=BK_max) according to the size of the matrix dimension (including M, N, K) of the input matrix (including the first matrix to be multiplied and the second matrix to be multiplied), and then calculates the ratio of M to N as the first adjustment parameter a, and then further sets the initial row block parameter BM and column block parameter BN that satisfy the proportional relationship according to the first adjustment parameter a, and calculates the corresponding block data occupancy based on the current intermediate block parameter BK, row block parameter BM and column block parameter BN, so as to determine whether the cache space of a single smart chip is met according to the block data occupancy to iteratively update the intermediate block parameter; and then after the cache space is met, Finally, the corresponding number of block operation tasks is calculated based on the current intermediate block parameter BK, row block parameter BM and column block parameter BN, so as to determine whether the parallel capability of the parallel computing device is met (i.e., whether it is less than the number of physical cores) according to the number of block operation tasks, so as to iteratively adjust the row block parameter BM and column block parameter BN; until the cache space of a single smart chip and the parallel capability requirements of the parallel computing device are met, the intermediate block parameter BK, row block parameter BM and column block parameter BN at this time are used as the block size of the task situation to execute the block matrix operation, thereby effectively utilizing the parallel computing resources of the parallel computing device and improving the data processing reliability of matrix operations in the parallel computing device.

[0135] In some embodiments, the matrix operation processing method of the parallel computing device provided by the present application takes into account the uneven shape of the narrow and long matrix, abandons the traditional square block strategy, and adaptively adjusts the corresponding block shape according to the matrix shape to achieve balanced task division in the M, N, and K directions. In addition, the solution provided by the present application also has good robustness, and each input matrix size can obtain the corresponding optimal block size through several simple calculations and conditional judgments. In addition, the calculation process of obtaining the optimal row block parameter BM, column block parameter BN, and intermediate block parameter BK through the row matrix parameter M, column matrix parameter N, and intermediate matrix parameter K is simple and suitable for completion on the host side. The device side directly applies the block size calculated by the host to perform efficient matrix multiplication operations, effectively utilizing hardware resources and reducing invalid task occupancy of the device.

[0136] The matrix operation processing method of a parallel computing device and related devices proposed in an embodiment of the present application include: first, obtaining a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied, the first matrix dimension including a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension including an intermediate matrix parameter and a column matrix parameter; then, obtaining an intermediate block parameter, and based on the ratio of the row matrix parameter to the column matrix parameter, obtaining a first adjustment parameter, obtaining multiple preset threshold intervals and preset adjustment parameters corresponding to each preset threshold interval, selecting a preset threshold interval that matches the value of the first adjustment parameter from the multiple preset threshold intervals as a target interval, and The preset adjustment parameter corresponding to the target interval is used as the second adjustment parameter. When the second adjustment parameter exceeds the preset threshold parameter, a column block parameter is generated, and the row block parameter is obtained based on the product of the column block parameter and the second adjustment parameter. When the second adjustment parameter does not exceed the preset threshold parameter, a row block parameter is generated, and the column block parameter is obtained based on the ratio of the row block parameter and the second adjustment parameter. Secondly, the data volume parameter is obtained, and the first block data occupancy is obtained based on the product of the row block parameter, the intermediate block parameter and the data volume parameter, and the second block data occupancy is obtained based on the product of the intermediate block parameter, the column block parameter and the data volume parameter. The product of the parameter and the data volume parameter obtains the third block data occupancy. When at least one of the first block data occupancy, the second block data occupancy and the third block data occupancy exceeds the preset buffer capacity, the intermediate block parameter is reduced, and the block data occupancy is recalculated based on the updated intermediate block parameter. When the updated block data occupancy exceeds the preset buffer capacity and the intermediate block parameter is reduced to the preset intermediate minimum parameter, the row block parameter and the column block parameter are updated based on the updated intermediate block parameter, and the block data occupancy is recalculated based on the updated intermediate block parameter, the row block parameter and the column block parameter until the block data occupancy does not exceed The preset buffer capacity is exceeded; next, a row parameter ratio is obtained based on the ratio of the row matrix parameter and the row block parameter, a column parameter ratio is obtained based on the ratio of the column matrix parameter and the column block parameter, and the number of block operation tasks is obtained based on the product of the row parameter ratio and the column parameter ratio. When the number of block operation tasks exceeds the number of available tasks, the row block parameter and the column block parameter are increased, and the number of block operation tasks is recalculated based on the updated row block parameter and the column block parameter until the number of block operation tasks does not exceed the number of available tasks; finally, matrix blocking is performed on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate block parameter, the row block parameter and the column block parameter to perform matrix multiplication operation.

[0137] The embodiment of the present application utilizes the value of the first adjustment parameter generated by the ratio of the row matrix parameter and the column matrix parameter to match and obtain the second adjustment parameter corresponding to the dimension size of the first matrix to be multiplied and the dimension size of the second matrix to be multiplied, and further preliminarily generates relatively suitable row block parameters and column block parameters according to the value of the second adjustment parameter, so as to facilitate subsequent iterative update based on the relatively suitable row block parameters and column block parameters, so as to improve the calculation efficiency of obtaining the most suitable intermediate block parameters, row block parameters and column block parameters; and, according to the current intermediate block parameters, row block parameters and column block parameters, real-time calculation of the current corresponding to different blocks The first block data occupancy, the second block data occupancy and the third block data occupancy of the block matrix are calculated, and further compared with the preset buffer capacity of the intelligent chip, so as to iteratively update at least one of the intermediate block parameters, the row block parameters and the column block parameters to ensure that no cache overflow occurs, thereby improving the reliability of matrix operation processing in the parallel computing device; and, according to the current row block parameters and column block parameters, the number of block operation tasks of the current corresponding block matrix operation is calculated in real time, and further compared with the number of available tasks representing the number of physical cores of the parallel computing device, so as to update the row block parameters and the column block parameters. It is iteratively updated to maximize the computing power of each single core of the intelligent chip, so as to improve the parallel processing of the computing parallel computing device, and then improve the resource utilization of the matrix operation processing in the parallel computing device; in short, the row block parameter and the column block parameter are generated by using the intermediate block parameters preset in the parallel computing device and the ratio of the row matrix parameter to the column matrix parameter, and then the intermediate block parameters are iteratively updated by using the numerical relationship between the calculated block data occupancy and the preset buffer capacity determined by the parallel computing device, and further the numerical relationship between the calculated number of block operation tasks and the number of available tasks determined by the parallel computing device is used. The row block parameters and the column block parameters are iteratively updated in a relational manner to obtain the intermediate block parameters, row block parameters and column block parameters that are most suitable for the first matrix to be multiplied and the second matrix to be multiplied to perform multiplication operations in a parallel computing device, and the first matrix to be multiplied and the second matrix to be multiplied are split using the intermediate block parameters, row block parameters and column block parameters for operations, so as to effectively utilize the parallel computing resources of the parallel computing device, avoid the situation where the matrix division is too large, resulting in the hardware device being unable to perform matrix multiplication, and avoid the situation where the matrix division is too small, wasting too many idle computing resources, thereby improving the data processing reliability of matrix operations in the parallel computing device.

[0138] The present application also provides a matrix operation processing device for a parallel computing device, which can implement the matrix operation processing method of the parallel computing device. Fig.12 , the device 1200 comprises:

[0139] A matrix dimension acquisition module 1210 is used to acquire a first matrix dimension of a first matrix to be multiplied, and to acquire a second matrix dimension of a second matrix to be multiplied, wherein the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes an intermediate matrix parameter and a column matrix parameter;

[0140] An initial block parameter acquisition module 1220 is used to acquire intermediate block parameters and generate row block parameters and column block parameters based on the ratio of row matrix parameters to column matrix parameters;

[0141] A first adjustment module 1230 is configured to calculate the block data occupancy based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy exceeds the preset buffer capacity, reduce the intermediate block parameter, and recalculate the block data occupancy based on the updated intermediate block parameter until the block data occupancy does not exceed the preset buffer capacity;

[0142] The second adjustment module 1240 is used to calculate the number of block operation tasks based on the row matrix parameters and the row block parameters, the column matrix parameters and the column block parameters, and when the number of block operation tasks exceeds the number of available tasks, increase the row block parameters and the column block parameters, and recalculate the number of block operation tasks based on the updated row block parameters and the column block parameters until the number of block operation tasks does not exceed the number of available tasks;

[0143] The blocking execution module 1250 is used to perform matrix blocking on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameter, the row blocking parameter and the column blocking parameter to perform a matrix multiplication operation.

[0144] In some embodiments, the initial block parameter acquisition module 1220 is further used to:

[0145] Obtaining a first adjustment parameter based on a ratio of the row matrix parameter to the column matrix parameter;

[0146] obtaining a second adjustment parameter based on the value of the first adjustment parameter;

[0147] A row blocking parameter and a column blocking parameter are generated based on the second adjustment parameter.

[0148] In some embodiments, the initial block parameter acquisition module 1220 is further used to:

[0149] Obtaining a plurality of preset threshold intervals and a preset adjustment parameter corresponding to each preset threshold interval;

[0150] A preset threshold interval matching the value of the first adjustment parameter is selected from a plurality of preset threshold intervals as a target interval, and a preset adjustment parameter corresponding to the target interval is used as a second adjustment parameter.

[0151] In some embodiments, the initial block parameter acquisition module 1220 is further used to:

[0152] When the second adjustment parameter exceeds the preset threshold parameter, a column block parameter is generated, and a row block parameter is obtained based on the product of the column block parameter and the second adjustment parameter;

[0153] When the second adjustment parameter does not exceed the preset threshold parameter, a row blocking parameter is generated, and a column blocking parameter is obtained based on a ratio of the row blocking parameter to the second adjustment parameter.

[0154] In some embodiments, the first adjustment module 1230 is further configured to:

[0155] Get the data volume parameters;

[0156] The data occupancy of the first block is obtained based on the product of the row block parameter, the intermediate block parameter and the data amount parameter;

[0157] The second block data occupancy amount is obtained based on the product of the middle block parameter, the column block parameter and the data amount parameter;

[0158] The data occupancy of the third block is obtained based on the product of the row block parameter, the column block parameter and the data amount parameter.

[0159] In some embodiments, the first adjustment module 1230 is further configured to:

[0160] When at least one of the first block data occupancy, the second block data occupancy, and the third block data occupancy exceeds the preset buffer capacity, reducing the intermediate block parameter, and recalculating the block data occupancy based on the updated intermediate block parameter;

[0161] When the updated block data occupancy exceeds the preset buffer capacity and the intermediate block parameter is reduced to the preset intermediate minimum parameter, the row block parameter and the column block parameter are updated based on the updated intermediate block parameter, and the block data occupancy is recalculated based on the updated intermediate block parameter, the row block parameter and the column block parameter.

[0162] In some embodiments, the second adjustment module 1240 is further configured to:

[0163] A row parameter ratio is obtained based on a ratio of a row matrix parameter to a row block parameter;

[0164] A column parameter ratio is obtained based on a ratio of the column matrix parameter and the column block parameter;

[0165] The number of block operation tasks is obtained based on the product of the row parameter ratio and the column parameter ratio.

[0166] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, the specific implementation method of the matrix operation processing device of the parallel computing device is basically the same as the specific implementation method of the matrix operation processing method of the above parallel computing device, and will not be repeated here.

[0167] In the embodiment of the present application, the matrix operation processing device of the parallel computing device uses the value of the first adjustment parameter generated by the ratio of the row matrix parameter and the column matrix parameter to match the second adjustment parameter corresponding to the dimension size of the first matrix to be multiplied and the dimension size of the second matrix to be multiplied, and further preliminarily generates relatively suitable row block parameters and column block parameters based on the value of the second adjustment parameter, so as to facilitate subsequent iterative updates based on the relatively suitable row block parameters and column block parameters to improve the calculation efficiency of obtaining the most suitable intermediate block parameters, row block parameters and column block parameters; and, based on the current intermediate block parameters, row block parameters and column block parameters, the matrix operation processing device of the parallel computing device The first block data occupancy, the second block data occupancy and the third block data occupancy corresponding to the different block matrices are calculated at the same time, and are further compared with the preset buffer capacity of the intelligent chip, so as to iteratively update at least one of the intermediate block parameter, the row block parameter and the column block parameter to ensure that no cache overflow occurs, thereby improving the reliability of matrix operation processing in the parallel computing device; and, according to the current row block parameter and the column block parameter, the number of block operation tasks of the current corresponding block matrix operation is calculated in real time, and is further compared with the number of available tasks representing the number of physical cores of the parallel computing device, so as to update the row block parameter. The number and column block parameters are iteratively updated to maximize the computing power of each single core of the intelligent chip, so as to improve the parallel processing performance of the parallel computing device, and thus improve the resource utilization of matrix operation processing in the parallel computing device; in short, the row block parameters and column block parameters are generated by using the intermediate block parameters preset in the parallel computing device and the ratio of the row matrix parameters to the column matrix parameters, and then the intermediate block parameters are iteratively updated by using the numerical relationship between the calculated block data occupancy and the preset buffer capacity determined by the parallel computing device, and the calculated number of block operation tasks and the number of available tasks determined by the parallel computing device are further used to iteratively update the intermediate block parameters. The row blocking parameters and the column blocking parameters are iteratively updated according to the numerical relationship between them, so as to obtain the intermediate blocking parameters, row blocking parameters and column blocking parameters that are most suitable for the first matrix to be multiplied and the second matrix to be multiplied to perform multiplication operations in the parallel computing device, and the first matrix to be multiplied and the second matrix to be multiplied are split using the intermediate blocking parameters, row blocking parameters and column blocking parameters for performing operations, so as to effectively utilize the parallel computing resources of the parallel computing device, avoid the situation where the matrix division is too large, resulting in the hardware device being unable to perform matrix multiplication, and avoid the situation where the matrix division is too small, wasting too many idle computing resources, thereby improving the data processing reliability of matrix operations in the parallel computing device.

[0168] The present application also provides an electronic device, including:

[0169] at least one memory;

[0170] at least one processor;

[0171] at least one program;

[0172] The program is stored in the memory, and the processor executes the at least one program to implement the matrix operation processing method of the parallel computing device implemented in the present application. The electronic device can be any intelligent terminal including a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc.

[0173] See also Fig.13 , Fig.13 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0174] The processor 1301 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0175] The memory 1302 can be implemented in the form of ROM (Read Only Memory), static storage device, dynamic storage device or RAM (Random Access Memory). The memory 1302 can store operating systems and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1302, and the processor 1301 calls and executes the matrix operation processing method of the parallel computing device in the embodiments of this application;

[0176] Input / output interface 1303, used to implement information input and output;

[0177] The communication interface 1304 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0178] A bus 1305 that transmits information between various components of the device (e.g., the processor 1301, the memory 1302, the input / output interface 1303, and the communication interface 1304);

[0179] The processor 1301 , the memory 1302 , the input / output interface 1303 and the communication interface 1304 are connected to each other in communication within the device via a bus 1305 .

[0180] An embodiment of the present application also provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the matrix operation processing method of the parallel computing device is implemented.

[0181] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0182] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0183] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0184] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0185] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0186] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0187] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0188] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0189] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0190] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0191] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0192] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A matrix operation processing method for a parallel computing device, characterized in that: The method comprises: Obtaining a first matrix dimension of a first matrix to be multiplied and a second matrix dimension of a second matrix to be multiplied, wherein the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes the intermediate matrix parameter and a column matrix parameter; Obtaining intermediate block parameters, and generating row block parameters and column block parameters based on a ratio of the row matrix parameters to the column matrix parameters; The block data occupancy amount is calculated based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy amount exceeds the preset buffer capacity, the intermediate block parameter is reduced, and the block data occupancy amount is recalculated based on the updated intermediate block parameter until the block data occupancy amount does not exceed the preset buffer capacity; The number of block operation tasks is calculated based on the row matrix parameter, the row block parameter, the column matrix parameter and the column block parameter. When the number of block operation tasks exceeds the number of available tasks, the row block parameter and the column block parameter are increased, and the number of block operation tasks is recalculated based on the updated row block parameter and the column block parameter until the number of block operation tasks does not exceed the number of available tasks; Matrix blocking is performed on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameters, the row blocking parameters and the column blocking parameters to perform a matrix multiplication operation.

2. The matrix operation processing method of a parallel computing device according to claim 1, characterized in that: The generating row block parameters and column block parameters based on the ratio of the row matrix parameters to the column matrix parameters comprises: Obtaining a first adjustment parameter based on a ratio of the row matrix parameter to the column matrix parameter; obtaining a second adjustment parameter based on the value of the first adjustment parameter; The row blocking parameter and the column blocking parameter are generated based on the second adjustment parameter.

3. The matrix operation processing method of the parallel computing device according to claim 2, characterized in that: The obtaining the second adjustment parameter based on the value of the first adjustment parameter includes: Acquire a plurality of preset threshold intervals and a preset adjustment parameter corresponding to each of the preset threshold intervals; A preset threshold interval matching the value of the first adjustment parameter is selected from the plurality of preset threshold intervals as a target interval, and a preset adjustment parameter corresponding to the target interval is used as the second adjustment parameter.

4. The matrix operation processing method of a parallel computing device according to claim 2, characterized in that: The generating the row blocking parameter and the column blocking parameter based on the second adjustment parameter comprises: When the second adjustment parameter exceeds a preset threshold parameter, the column block parameter is generated, and the row block parameter is obtained based on the product of the column block parameter and the second adjustment parameter; When the second adjustment parameter does not exceed a preset threshold parameter, the row blocking parameter is generated, and the column blocking parameter is obtained based on a ratio of the row blocking parameter to the second adjustment parameter.

5. The matrix operation processing method of a parallel computing device according to claim 1, characterized in that: The block data occupancy includes the first block data occupancy, the second block data occupancy and the third block data occupancy, and the block data occupancy is calculated based on the intermediate block parameter, the row block parameter and the column block parameter, including: Get the data volume parameters; Obtaining the first block data occupancy amount based on the product of the row block parameter, the intermediate block parameter and the data amount parameter; Obtaining the second block data occupancy amount based on the product of the middle block parameter, the column block parameter and the data amount parameter; The third block data occupancy is obtained based on the product of the row block parameter, the column block parameter and the data amount parameter.

6. The matrix operation processing method of the parallel computing device according to claim 5, characterized in that: When the block data occupancy exceeds the preset buffer capacity, reducing the intermediate block parameter, and recalculating the block data occupancy based on the updated intermediate block parameter, comprises: When at least one of the first block data occupancy, the second block data occupancy, and the third block data occupancy exceeds the preset buffer capacity, reducing the intermediate block parameter, and recalculating the block data occupancy based on the updated intermediate block parameter; When the updated block data occupancy exceeds the preset buffer capacity and the intermediate block parameter is reduced to the preset intermediate minimum parameter, the row block parameter and the column block parameter are updated based on the updated intermediate block parameter, and the block data occupancy is recalculated based on the updated intermediate block parameter, the row block parameter and the column block parameter.

7. The matrix operation processing method of a parallel computing device according to claim 1, characterized in that: The calculating the number of block operation tasks based on the row matrix parameters, the row block parameters, the column matrix parameters and the column block parameters includes: Obtaining a row parameter ratio based on a ratio of the row matrix parameter to the row block parameter; Obtaining a column parameter ratio based on a ratio of the column matrix parameter to the column blocking parameter; The number of block operation tasks is obtained based on the product of the row parameter ratio and the column parameter ratio.

8. A matrix operation processing device for a parallel computing device, characterized in that: The device comprises: A matrix dimension acquisition module, used to acquire a first matrix dimension of a first matrix to be multiplied, and to acquire a second matrix dimension of a second matrix to be multiplied, wherein the first matrix dimension includes a row matrix parameter and an intermediate matrix parameter, and the second matrix dimension includes the intermediate matrix parameter and a column matrix parameter; An initial block parameter acquisition module, used to acquire intermediate block parameters, and generate row block parameters and column block parameters based on the intermediate block parameters; A first adjustment module is configured to calculate the block data occupancy based on the intermediate block parameter, the row block parameter and the column block parameter, and when the block data occupancy exceeds a preset buffer capacity, reduce the intermediate block parameter, and recalculate the block data occupancy based on the updated intermediate block parameter until the block data occupancy does not exceed the preset buffer capacity; A second adjustment module is used to calculate the number of block operation tasks based on the row matrix parameters and the row block parameters, the column matrix parameters and the column block parameters, and when the number of block operation tasks exceeds the number of available tasks, increase the row block parameters and the column block parameters, and recalculate the number of block operation tasks based on the updated row block parameters and the column block parameters until the number of block operation tasks does not exceed the number of available tasks; The block execution module is used to perform matrix blocking on the first matrix to be multiplied and the second matrix to be multiplied based on the intermediate blocking parameter, the row blocking parameter and the column blocking parameter to perform a matrix multiplication operation.

9. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the matrix operation processing method of the parallel computing device according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the matrix operation processing method of the parallel computing device according to any one of claims 1 to 7 is implemented.

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