A method for metal interconnect capacitance parameter extraction in a layered medium
By dividing the computational domain into metal interconnect and layered dielectric regions, and combining the finite element method with analytical solutions, the problem of efficient capacitance parameter extraction for complex metal interconnect structures is solved, achieving efficient and low-resource-consumption capacitance parameter calculation.
Patent Information
- Application Number
- CN202411573524.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2044-11-06
AI Technical Summary
Existing technologies suffer from high computational resource consumption and long solution time when dealing with complex metal interconnect structures, making it difficult to achieve efficient and accurate extraction of capacitance parameters.
The computational domain is divided into a metal interconnect region and a stacked dielectric region. The finite element method is used for spatial discretization and matrix equations are constructed. Numerical boundary equations are constructed by combining the analytical solution with the finite element method. By combining the finite element method and the analytical solution, the potential distribution is efficiently solved to calculate the capacitance value.
It improves computational efficiency, reduces computational resource consumption, maintains high accuracy, and significantly shortens solution time.
Smart Images
Figure CN119323158B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of numerical simulation calculation, in particular, to a method for extracting metal interconnection capacitance parameters in laminated dielectric. BACKGROUND
[0002] With the continuous reduction of integrated circuit size, the influence of metal interconnection on integrated circuit performance becomes more and more significant. In order to ensure the design quality, shorten the design cycle and reduce the cost, it is necessary to accurately and efficiently extract the metal interconnection capacitance.
[0003] The extraction of metal interconnection capacitance parameters can be mainly divided into three methods: analytical model, empirical formula technology and numerical method. Analytical model and empirical formula technology can provide fast approximate results, however, when applied to complex structure scenarios, their accuracy will be severely reduced. In contrast, numerical methods such as finite element method and boundary element method have high accuracy in dealing with complex metal interconnection structures, but at the same time, they face the challenges of long solution time and high consumption of computing resources. SUMMARY
[0004] In view of the defects in the prior art, the purpose of the present application is to provide a method for extracting metal interconnection capacitance parameters in laminated dielectric, which has the advantages of high calculation efficiency and low consumption of computing resources.
[0005] To solve the above problems, the technical scheme of the present application is:
[0006] A method for extracting metal interconnection capacitance parameters in laminated dielectric, the method comprising the following steps:
[0007] S1: dividing the entire solution region into a metal interconnection region and a laminated dielectric region above and below it;
[0008] S2: spatially discretizing the metal interconnection region, setting excitation and partial boundary conditions, and using the finite element method to construct a matrix equation;
[0009] S3: for the upper and lower laminated dielectrics, respectively constructing numerical boundary equations on the upper and lower interface through analytical solution;
[0010] S4: assembling and solving the matrix equation of the metal interconnection region and the numerical boundary equation on the interface to obtain the potential distribution result;
[0011] S5: calculating the metal conductor surface charge distribution according to the potential distribution result, and then obtaining the interconnection capacitance value.
[0012] Preferably, in the step S1, the whole calculation region can be divided into three regions in the order from top to bottom: the upper layer of dielectric region, the metal interconnection region and the lower layer of dielectric region; the upper interface is between the upper layer of dielectric region and the metal interconnection region, and the lower interface is between the lower layer of dielectric region and the metal interconnection region; wherein, in the upper and lower layer of dielectric region, only contains several stacked rectangular uniform dielectric layers; in the metal interconnection region, contains irregularly shaped metal conductors and conformal dielectric.
[0013] Preferably, in the step S2, the metal interconnection region is spatially discretized using triangular mesh units, and the excitation and partial boundary conditions are set as follows: selecting the metal conductor k, setting it as a constant voltage of 1V, and setting other conductors as a constant voltage of 0V, and the two side edges of the metal interconnection region are set as insulating boundary conditions.
[0014] Preferably, in the process of constructing the matrix equation using the finite element method, the electrostatic field control equation in the medium region to be solved is:
[0015]
[0016] Wherein, u is the electric potential, and ε is the dielectric constant;
[0017] In each spatially discretized unit e, the electric potential u e can be approximated by the node value and its corresponding shape function as:
[0018]
[0019] Wherein, is the shape function corresponding to node j; substituting into the electrostatic field control equation and performing Galerkin test to obtain the weighted residual R e of the unit e as:
[0020] R e = K e u e -f e
[0021] Wherein,
[0022]
[0023]
[0024]
[0025] Γ e is the edge surrounding the region S e of the unit e, n eis the unit outer normal vector; by assembling all the elements and processing the boundary conditions, the matrix equation is obtained:
[0026] Ku-f = b
[0027] where b is a vector related to the boundary conditions.
[0028] Preferably, in the step S3, the lower layer of the medium area contains N layers, from top to bottom, the first, second, …, N layers, wherein the thickness and relative permittivity of the jth layer are t j and ε j , and the width of each layer of medium is w; the two sides of the lower layer of the medium area are insulating boundaries, the lower boundary is set as a 0V voltage boundary condition, and the upper boundary is set as a voltage boundary condition of u(x); the adjacent two layers of medium satisfy the following potential and electric flux continuity conditions:
[0029]
[0030]
[0031] By separation of variables, the Fourier series form of the analytical solution of the electric potential in the lower layer of the medium area can be obtained as:
[0032]
[0033] where λ m = mπ / w, A m,j and B m,j are the coefficients of the mth order;
[0034] Through the boundary conditions of the above lower layer of the medium area and the continuity conditions between the medium layers, the expression of all the coefficients can be obtained as:
[0035]
[0036] A 0,j+1 = A 0,j +B 0,j t i ,B 0,j+1 = B 0,j ε j ε j+1
[0037]
[0038] B m,N = coth(λ m t N )
[0039]
[0040] Am,j+1 = A m,j [cosh(λ m t j )-B m,j sinh(λ m t j )]
[0041] The electric flux of the lower interface can be obtained by derivation of the electric potential:
[0042]
[0043] In the expression, B 0,1 and A m,1 are related to u(x), and u(x) is expressed as the expression of the electric potential and the shape function on the interface:
[0044]
[0045] where P is the number of discrete nodes on the lower interface, and N p is the shape function corresponding to the node p; the above expression is substituted into the expression of the electric flux of the lower interface, and can be written as follows:
[0046]
[0047] The above analytical expression establishes the relationship between the electric flux and the electric potential on the lower interface, that is, the numerical boundary equation; similarly, the numerical boundary equation on the upper interface corresponding to the upper layered medium region can be obtained by the same steps.
[0048] Preferably, in the step S4, the analytical expression of D(x) obtained in the step S3 is substituted into the corresponding f of the nodes on the upper and lower interfaces based on the matrix equation established by the finite element method in the metal interconnection region, and the following can be obtained:
[0049]
[0050] Therefore, the original matrix equation in the step S2 can be rewritten as follows:
[0051] (K-F)u = b
[0052] The linear equation set is solved to obtain the electric potential result u.
[0053] Preferably, in the step S5, the total charge of the metal conductor g can be obtained by the electric potential:
[0054]
[0055] Since the voltage applied to the metal conductor k is 1V, the size of the capacitance between the metal conductor k and the conductor g is
[0056]
[0057] Compared with the prior art, the present application has the following beneficial effects:
[0058] 1. In the solution of the metal interconnection region, by using the flexible finite element method, the complex irregular shape of the metal conductor and the surrounding conformal medium can be processed in the calculation, and high precision is maintained;
[0059] 2. In the solution of the upper and lower stacked medium regions, by using the accurate and fast analytical solution, the numerical boundary equation on the upper and lower interfaces can be efficiently obtained;
[0060] 3. The suitable method is used in different regions, the advantages of flexible numerical solution and fast analytical solution are exerted, and compared with the traditional finite element method, since only spatial discretization is needed in the metal interconnection region, the size of the matrix equation to be solved is significantly reduced, so the calculation efficiency is greatly improved. BRIEF DESCRIPTION OF DRAWINGS
[0061] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:
[0062] Figure 1 The method flow chart for the present application for extracting the metal interconnection capacitance parameter in the stacked medium is shown in the figure;
[0063] Figure 2 The schematic diagram for the calculation region decomposition is shown in the figure;
[0064] Figure 3 The schematic diagram for the lower stacked medium region is shown in the figure;
[0065] Figure 4 The metal interconnection structure diagram of a specific embodiment containing multiple layers of medium is shown in the figure. DETAILED DESCRIPTION
[0066] The present application will be described in detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, a number of changes and improvements can be made. These all belong to the protection scope of the present application.
[0067] Specifically, the present application provides a method for extracting the metal interconnection capacitance parameter in the stacked medium, as shown in Figure 1 The method comprises the following steps:
[0068] S1: divide the whole solving region into metal interconnection region and its upper and lower stacked dielectric region;
[0069] Specifically, in the step S1, as shown in the figure, the whole calculation region can be divided into three regions in the order from top to bottom: upper stacked dielectric region, metal interconnection region and lower stacked dielectric region. The upper interface is between the upper stacked dielectric region and the metal interconnection region, and the lower interface is between the lower stacked dielectric region and the metal interconnection region. Among them, in the upper and lower stacked dielectric regions, only a plurality of stacked rectangular uniform dielectric layers are contained; in the metal interconnection region, irregularly shaped metal conductors and conformal dielectric are contained. Figure 2
[0070] S2: spatially disperse the metal interconnection region, set excitation and partial boundary conditions, and use finite element method to construct matrix equation;
[0071] Specifically, in the step S2, the metal interconnection region is spatially dispersed using triangular grid elements, and the boundary conditions are: the two sides of the metal interconnection region are insulating boundary conditions, a selected metal conductor k is set to a constant voltage of 1V, and other metals are set to a constant voltage boundary condition of 0V.
[0072] In the process of using finite element method to construct matrix equation, the electrostatic field control equation in the medium region to be solved is:
[0073]
[0074] Wherein, u is the electric potential, and ε is the dielectric constant.
[0075] In each spatially dispersed element e, the electric potential u e can be approximated by the node value u j e and its corresponding shape function as:
[0076]
[0077] Wherein, is the shape function corresponding to node j. Substitute into the electrostatic field control equation and perform Galerkin test to obtain the weighted residual R e of element e as:
[0078] R e = K e u e -f e
[0079] Wherein,
[0080]
[0081]
[0082]
[0083] Γ e It is the region S surrounding unit e. e The edge, n e It is the unit outward normal vector. By assembling all elements and processing the boundary conditions, the matrix equation is obtained:
[0084] Ku-f=b
[0085] Where b is a vector related to the boundary conditions.
[0086] S3: For the upper and lower stacked media, construct the numerical boundary equations on the upper and lower interfaces respectively through analytical solutions;
[0087] Specifically, in step S3, such as Figure 3 As shown, the lower stacked dielectric region contains N layers, numbered 1, 2, ..., N from top to bottom, where the thickness and relative permittivity of the j-th layer are t and t, respectively. j and ε j Each dielectric layer has a width of w. The two sides of the lower dielectric layer region are insulating boundaries, the lower boundary is set to a 0V voltage boundary condition, and the upper boundary is set to a u(x) voltage boundary condition. The following potential and current flux continuity conditions are satisfied between adjacent dielectric layers:
[0088]
[0089]
[0090] Using the method of separation of variables, the analytical solution of the potential in the Fourier series form within the lower layered dielectric region can be obtained as follows:
[0091]
[0092] Where, λ m =mπ / w, A m,j and B m,j It is the coefficient of the m-th order.
[0093] Based on the boundary conditions of the lower-layer stacked medium region and the continuity conditions between the medium layers, the expressions for all coefficients can be obtained as follows:
[0094]
[0095] A 0,j+1 =A 0,j +B 0,j t i B 0,j+1 =B 0,jε j ε j+1
[0096]
[0097] B m,N = coth (λ m t N )
[0098]
[0099] A m,j+1 = A m,j [cosh (λ m t j ) - B m,j sinh (λ m t j )]
[0100] The electric flux of the lower interface can be obtained by derivation of the electric potential:
[0101]
[0102] In the expression, B 0,1 and A m,1 are related to u(x), and u(x) is expressed as the expression of the electric potential and the shape function on the interface:
[0103]
[0104] Where P is the number of discrete nodes on the lower interface, and N p is the shape function corresponding to the node p. Substituting the above formula into the electric flux expression of the lower interface, it can be written as follows:
[0105]
[0106] The above analytical expression establishes the relationship between the electric flux and the electric potential on the lower interface, that is, the numerical boundary equation. In specific implementation, the infinite series in the formula is selected to 500 orders, which can meet the calculation accuracy requirement.
[0107] Similarly, the numerical boundary equation on the upper interface corresponding to the upper layered dielectric region can be obtained through the same steps.
[0108] S4: Assembling and solving the matrix equation of the metal interconnection region and the numerical boundary equation on the interface to obtain the electric potential distribution result;
[0109] Specifically, in the step S4, based on the matrix equation established in the metal interconnection region by the finite element method, the analytical expression of D(x) obtained in step S3 is substituted into the corresponding f of the nodes on the upper and lower interfaces, which can be obtained:
[0110]
[0111] Therefore, the original matrix equation in step S2 can be rewritten as follows:
[0112] (K-F)u = b
[0113] Solving the linear equations can obtain the potential result u.
[0114] S5: According to the potential distribution result, the metal conductor surface charge distribution is calculated, and then the interconnection capacitance value is obtained.
[0115] Specifically, in step S5, the total charge of the metal conductor g can be obtained by the potential:
[0116]
[0117] Since the voltage applied to the metal conductor k is 1V, the capacitance size between the metal conductor k and the conductor g is
[0118]
[0119] According to the above extraction method, a specific embodiment is calculated.
[0120] In this embodiment, a metal interconnection structure containing 36 layers of stacked media is considered, as shown in Figure 4 The metal interconnection region in the middle of the structure contains four conductors, and the numbers of the conductors are also shown in Figure 4
[0121] The traditional finite element method and the method of the present application are used for simulation respectively, the metal conductor 1 is set as the main conductor, and the interconnection capacitance results are summarized in Table 1. It can be seen that the results of the method of the present application and the traditional finite element method are consistent, and the weighted average relative error is only 0.36%, which fully illustrates the accuracy of the method of the present application.
[0122]
[0123] Table 1
[0124] In terms of efficiency, the traditional finite element method generates 67721 meshes by spatially discretizing the whole structure, while the method of the present application only generates 3029 meshes by discretizing the metal interconnection region, so the number of unknowns is reduced to about 1 / 22. In terms of calculation memory and time, the traditional finite element method consumes 153.1 MB of memory and takes 13.5 s to calculate, while the method of the present application only uses 7.3 MB of memory and takes only 0.7 s to calculate, which is 4.8% and 5.2% of the traditional finite element method respectively, fully embodying the advantages of the method of the present application in terms of consumption of calculation resources.
[0125] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be arbitrarily combined with each other without conflict.
Claims
1. A method for metal interconnect capacitance parameter extraction in a stacked dielectric, characterized by, The method comprises the following steps: The entire solving region is divided into a metal interconnection region and a laminated dielectric region above and below the metal interconnection region; The metal interconnection region is discretized in space, excitation and partial boundary conditions are set, a matrix equation is constructed using the finite element method, the space is discretized using the finite element method, in each discretized unit, the electric potential is represented by node values and corresponding shape functions, then the electric potential is substituted into the electrostatic field control equation for Galerkin testing to obtain a unit stiffness matrix equation, the overall stiffness matrix equation is obtained by assembling all units and processing the boundary conditions; For the upper and lower laminated dielectrics, numerical boundary equations on the upper and lower interfaces are constructed by analytical solutions, the two sides of the lower laminated dielectric region are insulating boundaries, the lower boundary is set as a 0V boundary condition, the upper boundary is set as a voltage boundary condition, and the electric potential and electric flux are continuous between adjacent two layers of dielectrics; Fourier series form electric potential and electric flux analytical solutions in the upper and lower laminated dielectric regions are obtained by the separation of variables method as the numerical boundary equations; The matrix equation of the metal interconnection region and the numerical boundary equation on the interface are assembled and solved to obtain the electric potential distribution result, the matrix equation obtained is updated based on the matrix equation of the metal interconnection region established by the finite element method and the electric flux analytical expression obtained in the step of constructing the numerical boundary equation on the upper and lower interfaces by analytical solutions, and the electric potential result is obtained by solving the updated matrix equation; The electric charge distribution on the surface of the metal conductor is calculated according to the electric potential distribution result, and then the interconnection capacitance value is obtained.
2. The method for metal interconnect capacitance parameter extraction in stacked dielectric medium of claim 1, wherein, In the step of dividing the entire solving region into a metal interconnection region and a laminated dielectric region above and below the metal interconnection region, the entire calculation region is divided into three regions in order from top to bottom: an upper laminated dielectric region, a metal interconnection region, and a lower laminated dielectric region; the upper interface is between the upper laminated dielectric region and the metal interconnection region, and the lower interface is between the lower laminated dielectric region and the metal interconnection region; wherein, in the upper and lower laminated dielectric regions, only a plurality of stacked rectangular uniform dielectric layers are included; in the metal interconnection region, irregularly shaped metal conductors and conformal dielectrics are included.
3. The method for metal interconnect capacitance parameter extraction in stacked dielectric medium of claim 1, wherein, In the step of discretizing the metal interconnection region in space, setting excitation and partial boundary conditions, and constructing a matrix equation using the finite element method, the metal interconnection region is discretized in space using triangular grid units, and the excitation and partial boundary conditions are set as follows: the target metal conductor is selected and set as a constant voltage of 1V, and other conductors are set as constant voltages of 0V, and the two sides of the metal interconnection region are insulating boundary conditions.
4. The method for metal interconnect capacitance parameter extraction in stacked dielectric medium of claim 1, wherein, In the step of calculating the electric charge distribution on the surface of the metal conductor according to the electric potential distribution result, and then obtaining the interconnection capacitance value, the total electric charge of each metal conductor is calculated according to the obtained electric potential distribution result, and the metal interconnection capacitance is calculated accordingly.