A highly integrated analog computer chip

Abstract

The present application discloses a highly integrated analog computer chip, which relates to the field of artificial intelligence chips. The analog computer chip includes an input end, multiple storage modules, multiple operation modules and an output end; the input end includes multiple input interfaces for inputting external voltage signals; the storage modules and the operation modules are both composed of analog devices, and are respectively configured as n-level storage modules and n-level operation modules, and the storage modules and operation modules at each level are cascaded in sequence; the output end includes multiple output interfaces for outputting the voltage signal generated by the n-th level operation module. The storage module and the operation module of the analog computer chip only require a few analog components to realize the transfer operation, which improves the integration of the chip. At the same time, the input voltage signal is nonlinearly transformed through the storage module, and then the accumulation operation is performed through the operation module, and then enters the next level to circulate in sequence, which greatly simplifies the network architecture and further improves the integration of the chip.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence chips, and in particular to a highly integrated analog computer chip. Background Art

[0002] With the rise and development of artificial intelligence technology, artificial intelligence chips that can realize certain specific functions have received widespread attention and application. However, artificial intelligence chips in the prior art are usually digital computer chips, whose core computing units use digital operations, and a single core computing unit requires tens of thousands to hundreds of thousands of transistors, so that only a few thousand core computing units can be integrated in existing artificial intelligence chips. At this time, if tens of thousands or even hundreds of millions of data are to be calculated simultaneously, a large number of core computing units must be used for parallel processing. This leads to the problems of large size, slow speed and high power consumption in the prior art of using digital computer chips as artificial intelligence chips.

[0003] In addition, when processing data, the AI ​​chip in the prior art needs to first perform a linear transformation on the input data, then send the linearly transformed data to the activation function for nonlinear transformation, then accumulate through the adder, and then perform the next linear transformation, and then send it to the activation function again, and so on. Therefore, the network architecture of the AI ​​chip in the prior art is relatively complex, which is not conducive to the integration of AI chips. Summary of the invention

[0004] The purpose of the present invention is to provide a highly integrated analog computer chip, whose core computing unit is composed of a storage module and a computing module, and both the storage module and the computing module use analog devices to perform analog calculations, thereby solving the problems of low integration and complex network architecture of existing artificial intelligence chips.

[0005] To achieve the above object, the present invention discloses the following technical solution:

[0006] In a first aspect of the present invention, a highly integrated analog computer chip is provided, the analog computer chip comprising an input terminal, a plurality of storage modules, a plurality of operation modules and an output terminal;

[0007] The input end includes a plurality of input interfaces for inputting external voltage signals;

[0008] The storage module and the operation module are both composed of analog devices and are respectively configured as n-level storage modules and n-level operation modules, and the storage modules and operation modules at each level are cascaded in sequence, and n is a positive integer;

[0009] Wherein, the first-level storage module is connected to the input interface, generates a first-level current signal after performing nonlinear transformation on the external voltage signal, and inputs the first-level current signal to the first-level operation module; the first-level operation module generates a first-level voltage signal after performing superposition operation on the first-level current signal, and inputs the first-level voltage signal to the second-level storage module; the second-level storage module generates a second-level current signal after performing nonlinear transformation on the first-level voltage signal, and inputs the second-level current signal to the second-level operation module; ... and so on, the n-level operation module generates an n-level voltage signal after performing superposition operation on the n-level current signal, and inputs the n-level voltage signal to the output end;

[0010] The output end includes a plurality of output interfaces for outputting the n-th level voltage signal.

[0011] In a possible implementation, the number of the input interfaces and the number of operation modules in each level of operation modules are the same or different; the number of operation modules in the nth level operation module is the same as the number of the output ports.

[0012] In a possible implementation, the storage module includes a first switch tube M1, a second switch tube M2, a third switch tube M3 and a fourth switch tube M4;

[0013] The source of the first switch tube M1 is connected to its drain and connected to a first voltage VCG, the source of the second switch tube M2 is connected to its drain and connected to a second voltage VG; the gate of the first switch tube M1, the gate of the second switch tube M2 and the gate of the third switch tube M3 are connected, and the gate of the fourth switch tube M4 is connected to a first control voltage VC1; the drain of the third switch tube M3 is connected to a third voltage VM, the source of the third switch tube M3 is connected to the drain of the fourth switch tube M4, and the source of the fourth switch tube M4 is connected to a fourth voltage VS.

[0014] In a possible implementation manner, the first switch tube M1 and the second switch tube M2 are both PMOS tubes, and the third switch tube M3 and the fourth switch tube M4 are both NMOS tubes.

[0015] In a possible implementation, when the storage module is a first-level storage module, the first voltage VCG is an external voltage input by the input interface; when the storage module is not a first-level storage module, the first voltage VCG is an output voltage of a previous-level computing module;

[0016] The second voltage VG is 0V; the third voltage VM is a coupling voltage generated by the mutual coupling between the storage module at this level and the operation module at this level; and the fourth voltage VS is a fixed value.

[0017] In a possible implementation, the transfer function of the storage module is:

[0018] ;

[0019] In the formula, represents the storage current IM flowing through the third switch tube M3, represents the first voltage VCG, , and are respectively the electron mobility, oxide layer capacitance and width-to-length ratio of the third switch tube M3, CC1 is the equivalent capacitance of the first switch tube M1, CC2 is the equivalent capacitance of the second switch tube M2, is the turn-on threshold voltage of the third switch tube M3;

[0020] The transfer function of the storage module is determined by the turn-on threshold voltage Make adjustments;

[0021] The magnitude of the storage current IM of the storage module is determined by the magnitude of the first voltage VCG and the turn-on threshold voltage The size of the

[0022] In a possible implementation, the computing module includes a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a first capacitor C1;

[0023] The fifth switch tube M5 and the sixth switch tube M6 form a current mirror structure, the control end of the fifth switch tube M5 is connected to the control end of the sixth switch tube M6 and connected to the drain of the fifth switch tube M5, and the drain of the fifth switch tube M5 is connected to the source of the seventh switch tube M7, and the drain of the sixth switch tube M6 is connected to the drain of the eighth switch tube M8; the control end of the seventh switch tube M7 is connected to the control end of the eighth switch tube M8 and connected to the second control voltage VC2, the drain of the seventh switch tube M7 outputs the storage current IM to the storage module at the same level and generates a third voltage VM at its drain end; the low voltage end of the first capacitor C1 is connected to the source of the eighth switch tube M8 and grounded, and the high voltage end of the first capacitor C1 is connected to the drain of the eighth switch tube M8 and outputs the first voltage VCG.

[0024] In a possible implementation manner, the fifth switch tube M5 , the sixth switch tube M6 , and the seventh switch tube M7 are all PMOS tubes, and the eighth switch tube M8 is an NMOS tube.

[0025] In one possible implementation, when the operation module is an n-th level operation module, the high voltage end of the first capacitor C1 inputs the first voltage VCG to the output interface; when the operation module is not an n-th level operation module, the high voltage end of the first capacitor C1 inputs the first voltage VCG to the next-level storage module.

[0026] In a possible implementation, the first voltage VCG output by the operation module is:

[0027] ;

[0028] In the formula, is the charging current flowing through the sixth switch tube M6 and is related to the storage current IM. is the charging time of the charging current IMC for the first capacitor C1, is the capacitance value of the first capacitor;

[0029] The first voltage VCG output by the operation module is adjusted by the storage current IM.

[0030] A second aspect of the present invention provides a method for operating a highly integrated analog computer chip, the method being applied to the analog computer chip as described in the first aspect, comprising the following steps:

[0031] Using an external computer to train an artificial intelligence model to obtain parameter values ​​of transfer functions of each storage module in the analog computer chip;

[0032] Connecting the analog computer chip to an external regulating circuit, adjusting the turn-on threshold voltage of the corresponding switch tube according to the parameter value of the transfer function of each storage module, and obtaining a model of the analog computer chip;

[0033] The external voltage signal is input into the analog computer chip through multiple input interfaces, and after being transmitted and transformed by each level of storage modules and operation modules in sequence, a final voltage signal is generated, and the final voltage signal is output through multiple output interfaces.

[0034] The effects provided in the content of the invention are only the effects of the embodiments, not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0035] The present application provides a highly integrated analog computer chip, whose core computing unit is composed of a plurality of storage modules and a plurality of operation modules, and is respectively configured as n-level storage modules and n-level operation modules, and each level of storage modules and operation modules are cascaded in sequence for processing and calculating signals. Each storage module and each operation module are composed of analog devices, and only a few analog components are needed to realize the transfer operation, which significantly improves the integration of the chip. At the same time, the analog computer chip performs a nonlinear transformation on the input voltage signal through the storage module, and then performs an accumulation operation through the operation module, and then enters the next level of storage module to continue the nonlinear transformation, and circulates in sequence, which greatly simplifies the network architecture and further improves the integration of the chip. Using this highly integrated analog computer chip as an artificial intelligence chip can greatly reduce the size of the artificial intelligence chip, improve the processing speed and reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0037] Figure 1 A network architecture diagram of a highly integrated analog computer chip according to an embodiment of the present application;

[0038] Figure 2 for Figure 1 The circuit schematic diagram of the storage module;

[0039] Figure 3 for Figure 1 The circuit schematic diagram of the operation module in the figure;

[0040] Figure 4 for Figure 1 A schematic diagram of the structure of the core computing unit of a simulated computer chip;

[0041] Figure 5 A schematic flow chart of a working method of a highly integrated analog computer chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] It should be noted that references to "one embodiment", "embodiment", "example embodiment", etc. in this specification refer to the embodiment being described which may include specific features, structures or characteristics, but not every embodiment must include these specific features, structures or characteristics. In addition, such expressions do not refer to the same embodiment. Furthermore, when describing specific features, structures or characteristics in conjunction with an embodiment, whether or not there is an explicit description, it is indicated that incorporating such features, structures or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0044] As described in the background technology, the existing digital computer chips as artificial intelligence chips have the problems of large size, slow speed and high power consumption. In addition, the existing artificial intelligence chip network architecture is relatively complex, which limits the degree of integration of the chip. Based on this, the embodiment of the present application provides a highly integrated analog computer chip, which aims to meet the requirements of artificial intelligence applications for high performance and low energy consumption of chips by simplifying the network architecture and improving the integration.

[0045] refer to Figure 1 , Figure 1 The network architecture diagram of a highly integrated analog computer chip of an embodiment of the present application is shown. The analog computer chip includes an input terminal, multiple storage modules, multiple operation modules and an output terminal. The input terminal includes multiple input interfaces (in1, in2, in3...) for inputting external voltage signals. The storage module and the operation module are both composed of analog devices and are respectively configured as n-level storage modules and n-level operation modules, and each level of storage module and operation module is cascaded in sequence, where n is a positive integer. Figure 1 Each solid arrow in represents each storage module. Among them, the first-level storage module is connected to the input interface, and after performing nonlinear transformation on the external voltage signal, a first-level current signal is generated, and the first-level current signal is input to the first-level operation module (operation module 11, operation module 12, operation module 13...); the first-level operation module performs superposition operation on the first-level current signal to generate a first-level voltage signal, and inputs the first-level voltage signal to the second-level storage module; the second-level storage module performs nonlinear transformation on the first-level voltage signal to generate a second-level current signal, and inputs the second-level current signal to the second-level operation module (operation module 21, operation module 22, operation module 23...); ... and so on, the n-th level operation module (operation module n1, operation module n2, operation module n3...) performs superposition operation on the n-th level current signal to generate an n-th level voltage signal, and inputs the n-th level voltage signal to the output end. The output end includes multiple output interfaces (out1, out2, out3...) for outputting the n-th level voltage signal.

[0046] In the analog computer chip of this embodiment, each storage module and each operation module are composed of simple analog devices, which improves the integration of the chip. At the same time, the analog computer chip performs nonlinear transformation on the input voltage signal through the storage module, and then performs accumulation operation through the operation module, and then enters the next level of storage module to continue nonlinear transformation, and the cycle is repeated in sequence, which greatly simplifies the network architecture and further improves the integration of the chip.

[0047] In some embodiments, the number of input interfaces and the number of operation modules in each level of operation modules (first level operation module, second level operation module, ..., nth level operation module) may be the same or different. The number of operation modules in the nth level operation module is the same as the number of output ports.

[0048] Figure 2 for Figure 1 The circuit schematic diagram of the storage module. Figure 2 As shown, the storage module of this embodiment includes a first switch tube M1, a second switch tube M2, a third switch tube M3 and a fourth switch tube M4. Among them, the source of the first switch tube M1 is connected to its drain and connected to the first voltage VCG, the source of the second switch tube M2 is connected to its drain and connected to the second voltage VG; the gate of the first switch tube M1, the gate of the second switch tube M2 and the gate of the third switch tube M3 are connected, and the gate of the fourth switch tube M4 is connected to the first control voltage VC1; the drain of the third switch tube M3 is connected to the third voltage VM, the source of the third switch tube M3 is connected to the drain of the fourth switch tube M4, and the source of the fourth switch tube M4 is connected to the fourth voltage VS. Preferably, the first switch tube M1 and the second switch tube M2 are both PMOS tubes, and the third switch tube M3 and the fourth switch tube M4 are both NMOS tubes.

[0049] In some embodiments, when the storage module is a first-level storage module, the first voltage VCG is an external voltage input by the input interface; when the storage module is not a first-level storage module, the first voltage VCG is the output voltage of the previous-level operation module; the second voltage VG is 0V; the third voltage VM is a coupling voltage generated by the mutual coupling between the storage module at this level and the operation module at this level; and the fourth voltage VS is a fixed value.

[0050] based on Figure 2 The circuit structure of the storage module in the figure has the following working principle:

[0051] When the storage module is not working, the first control voltage VC1 is at a low level, the fourth switch tube M4 is in an off state, and no current flows through the third switch tube M3.

[0052] When the storage module starts working and is in the adjustment mode, the external adjustment circuit (not shown in the present application) is connected to the storage module, the first control voltage VC1 is at a low level, and the fourth switch tube M4 is in the off state. At this time, the external adjustment circuit changes the floating gate charge value of the third switch tube M3 by controlling the magnitude of the first voltage VCG and the working time of the adjustment circuit, thereby adjusting the turn-on threshold voltage of the third switch tube M3.

[0053] When the storage module starts working and is in the transfer mode, the external regulation circuit is not connected to the storage module, the first control voltage VC1 is at a high level, the fourth switch tube M4 is in the on state, and the storage current IM flows through the third switch tube M3. At the same time, when designing the circuit, the equivalent capacitance CC1 of the first switch tube M1 and the equivalent capacitance CC2 of the second switch tube M2 are both known, so at this time, it can be obtained that the gate voltage of the third switch tube M3 It is also known from the common technical knowledge in this field that the storage current flowing through the third switch tube M3 is ,in, is the electron mobility, is the oxide layer capacitance, is the ratio of the width to the length of the MOS tube, is the voltage difference between the gate and the source, is the turn-on threshold voltage. , and are all fixed values, and the gate-source voltage difference of the third switch tube M3 is ,in, and the fourth voltage VS are both fixed values. Therefore, for a specific input first voltage VCG, the turn-on threshold voltage can be adjusted To achieve the regulation of the storage current IM.

[0054] From the above analysis, it can be seen that when the storage current IM is recorded as y and the first voltage VCG is recorded as x, it can be obtained that , this function can be regarded as the transfer function of the storage module. At this time, when the turn-on threshold voltage is adjusted When the transfer function of the storage module is adjusted, the transfer function of the storage module can be adjusted.

[0055] Figure 3 for Figure 1 The circuit schematic diagram of the operation module in Figure 2. Figure 3As shown, the operation module of this embodiment includes a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a first capacitor C1. The fifth switch tube M5 and the sixth switch tube M6 form a current mirror structure, the control end of the fifth switch tube M5 is connected to the control end of the sixth switch tube M6 and connected to the drain of the fifth switch tube M5, the source of the fifth switch tube M5 is connected to the source of the sixth switch tube M6 and connected to the input voltage VDD, and the drain of the fifth switch tube M5 is connected to the source of the seventh switch tube M7, and the drain of the sixth switch tube M6 is connected to the drain of the eighth switch tube M8; the control end of the seventh switch tube M7 is connected to the control end of the eighth switch tube M8 and connected to the second control voltage VC2, the drain of the seventh switch tube M7 outputs the storage current IM to the storage module at this level and generates a third voltage VM at its drain end; the low voltage end of the first capacitor C1 is connected to the source of the eighth switch tube M8 and grounded, and the high voltage end of the first capacitor C1 is connected to the drain of the eighth switch tube M8 and outputs the first voltage VCG. Preferably, the fifth switch tube M5 , the sixth switch tube M6 , and the seventh switch tube M7 are all PMOS tubes, and the eighth switch tube M8 is an NMOS tube.

[0056] In some embodiments, when the operation module is an nth-level operation module, the high-voltage end of the first capacitor C1 inputs the first voltage VCG to the output interface; when the operation module is not an nth-level operation module, the high-voltage end of the first capacitor C1 inputs the first voltage VCG to the next-level storage module.

[0057] based on Figure 3 The circuit structure of the operation module in the figure has the following working principle:

[0058] When the operation module is not working, the second control voltage VC2 is in a high level state, at this time, the eighth switch tube M8 is turned on, and the fifth switch tube M5, the sixth switch tube M6 and the seventh switch tube M7 are all turned off. Therefore, the first capacitor C1 is discharged through the eighth switch tube M8, and the first voltage VCG output by the first capacitor C1 is 0V.

[0059] When the operation module starts to work, the second control voltage VC2 switches to a low level state. At this time, the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. Afterwards, the control terminal voltage of the fifth switch tube M5 and the control terminal voltage of the sixth switch tube M6 are pulled down through the seventh switch tube M7, and the fifth switch tube M5 and the sixth switch tube M6 are turned on. At this time, the storage current IM flows through the branch formed by the fifth switch tube M5 and the seventh switch tube M7. Since the fifth switch tube M5 and the sixth switch tube M6 form a current mirror structure, a charging current IMC related to the size of the storage current IM flows through the sixth switch tube M6, and the charging current IMC flows into the first capacitor C1 to charge the first capacitor C1. At this time, it can be known from the technical common sense in the field that the capacitor charge , where I is the charging current, that is, the charging current IMC, T is the charging time, C is the capacitance value, that is, the first capacitor C1, and V is the capacitor voltage after charging, that is, the first voltage VCG. Therefore, the first voltage At this time, since the capacitance value of the first capacitor C1 is a fixed value, the control of the first voltage VCG by the charging current IMC can be achieved by fixing the charging time T. That is, at this time, the time for the second control voltage VC2 to be kept at a low level is set to TC, so the charging time of the charging current IMC for the first capacitor C1 is TC, so it can be obtained that, Therefore, the first voltage VCG changes with the change of the charging current IMC, that is, changes with the change of the storage current IM.

[0060] according to Figure 1 The network architecture diagram of the simulated computer chip is combined with Figure 2 Storage modules and Figure 3 The circuit structure of the computing module in the embodiment of the present application is obtained by combining the storage module and the computing module to obtain the core computing unit structure as shown in FIG. Figure 4 shown. Figure 4 The core computing unit shown includes only three storage modules at the same level (storage module 211, storage module 212, storage module 213) and three storage modules at the next level (storage module 311, storage module 321, and storage module 331). It should be noted that this is only an example. In actual applications, the number of storage modules at the same level and the number of storage modules at the next level corresponding to a single computing module in the core computing unit are far more than three.

[0061] Depend on Figure 4 It can be known that when the storage module 211, the storage module 212, the storage module 213 and the operation module 21 all start to work, and the storage module 211, the storage module 212 and the storage module 213 all work in the transfer mode, the corresponding first storage sub-current IM211 can be obtained according to the voltage VCG11 and the turn-on threshold voltage of the relevant switch tube in the storage module 211, that is, the corresponding first storage sub-current IM211 is obtained according to the transfer function of the storage module 211. The corresponding second storage sub-current IM212 can be obtained according to the voltage VCG12 and the turn-on threshold voltage of the relevant switch tube in the storage module 212, that is, the corresponding second storage sub-current IM212 is obtained according to the transfer function of the storage module 212. The corresponding third storage sub-current IM213 can be obtained according to the voltage VCG13 and the turn-on threshold voltage of the relevant switch tube in the storage module 213, that is, the corresponding third storage sub-current IM213 is obtained according to the transfer function of the storage module 213.

[0062] At the same time, it can be seen from the circuit structure that after the first storage sub-current IM211, the second storage sub-current IM212 and the third storage sub-current IM213 are added together, the first storage current IM21 flowing out of the operation module 21 can be obtained. At this time, it can be seen from the above analysis that the magnitude of the voltage VCG21 output by the operation module 21 of this stage can be obtained according to the first storage current IM21, and the voltage VCG21 is input to the storage module 311, the storage module 321 and the storage module 331 of the next stage. The storage module 311, the storage module 321 and the storage module 331 of the next stage can obtain the corresponding storage sub-current according to the transfer function of each module, and so on, and finally the voltage VCGnm output by the operation module of the nth stage to the output interface is obtained, where m is the number of output interfaces.

[0063] In summary, the highly integrated analog computer chip provided by the present application has a core computing unit composed of a storage module and a computing module. Both a single storage module and a single computing module use analog devices for analog computing, and a single storage module and a single computing module only need a few analog components to realize transfer computing, so it has a super high integration, and can realize simultaneous computing of hundreds of millions of data. Therefore, when the highly integrated analog computer chip is used as an artificial intelligence chip, the volume of the artificial intelligence chip can be greatly reduced, the speed of the artificial intelligence chip can be improved, and the power consumption of the artificial intelligence chip can be reduced. At the same time, the analog computer chip of the present application can directly perform nonlinear transformation on the input voltage signal through the storage module, and then after the accumulation operation is performed by the computing module, the nonlinear transformation is directly performed through the storage module of the next level, and so on and so forth, making the network architecture of the analog computer chip more streamlined, further improving the integration of the analog computer chip. In addition, the storage module of the analog computer chip of the present application has a dual working mode, and the adjustment and operation of the transfer function can be realized simultaneously without adding additional devices inside the analog computer chip, thereby further improving the integration of the analog computer chip.

[0064] It should be noted that the highly integrated analog computer chip structure provided in this embodiment is only a preferred circuit structure for achieving the purpose of the present invention. In other embodiments, each circuit module or device may also use other circuit structures that can achieve the same function, and the present application is not limited thereto.

[0065] In addition, the present application also provides a method for operating a highly integrated analog computer chip, which is applied to the analog computer chip in the above embodiment. Figure 5 As shown, the method comprises the following steps:

[0066] S110, using an external computer to perform artificial intelligence model training to obtain parameter values ​​of transfer functions of each storage module in the simulated computer chip;

[0067] S120, connecting the analog computer chip to an external adjustment circuit, adjusting the turn-on threshold voltage of the corresponding switch tube according to the parameter value of the transfer function of each storage module, and obtaining a model of the analog computer chip;

[0068] S130, inputting the external voltage signal into the analog computer chip through multiple input interfaces, and generating a final voltage signal after being transmitted and transformed by each level of storage modules and operation modules in sequence, and outputting the final voltage signal through multiple output interfaces.

[0069] For the contents not described in detail in the working method of the simulated computer chip in this embodiment, reference may be made to the relevant parts of the simulated computer chip in the above embodiments, which will not be described in detail here.

[0070] The above description is only a preferred embodiment of the present invention and does not limit the present invention in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes and apply it to other fields. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A highly integrated analog computer chip, characterized in that: It includes an input terminal, a plurality of storage modules, a plurality of operation modules and an output terminal; The input end includes a plurality of input interfaces for inputting external voltage signals; The storage module and the operation module are both composed of analog devices and are respectively configured as n-level storage modules and n-level operation modules, and the storage modules and operation modules at each level are cascaded in sequence, and n is a positive integer; Wherein, the first-level storage module is connected to the input interface, and generates a first-level current signal after directly performing nonlinear transformation on the external voltage signal, and inputs the first-level current signal to the first-level operation module; the first-level operation module generates a first-level voltage signal after performing superposition operation on the first-level current signal, and inputs the first-level voltage signal to the second-level storage module; the second-level storage module generates a second-level current signal after directly performing nonlinear transformation on the first-level voltage signal, and inputs the second-level current signal to the second-level operation module; ... and so on, the n-th-level operation module generates an n-th-level voltage signal after performing superposition operation on the n-th-level current signal, and inputs the n-th-level voltage signal to the output end; The output end includes a plurality of output interfaces for outputting the n-th level voltage signal; The nonlinear transformation is to generate current signals corresponding to each level according to the nonlinear transfer functions of each level of storage modules, and the nonlinear transfer functions of each level of storage modules are adjusted by the turn-on threshold voltages of the relevant switch tubes in each level of storage modules.

2. The analog computer chip according to claim 1, characterized in that: The number of the input interfaces and the number of operation modules in each level of operation modules are the same or different; the number of operation modules in the nth level operation module is the same as the number of the output ports.

3. The analog computer chip according to claim 2, characterized in that: The storage module includes a first switch tube M1, a second switch tube M2, a third switch tube M3 and a fourth switch tube M4; The source of the first switch tube M1 is connected to its drain and connected to a first voltage VCG, the source of the second switch tube M2 is connected to its drain and connected to a second voltage VG; the gate of the first switch tube M1, the gate of the second switch tube M2 and the gate of the third switch tube M3 are connected, and the gate of the fourth switch tube M4 is connected to a first control voltage VC1; the drain of the third switch tube M3 is connected to a third voltage VM, the source of the third switch tube M3 is connected to the drain of the fourth switch tube M4, and the source of the fourth switch tube M4 is connected to a fourth voltage VS.

4. The analog computer chip according to claim 3, characterized in that: The first switch tube M1 and the second switch tube M2 are both PMOS tubes, and the third switch tube M3 and the fourth switch tube M4 are both NMOS tubes.

5. The analog computer chip according to claim 4, characterized in that: When the storage module is a first-level storage module, the first voltage VCG is an external voltage input by the input interface; when the storage module is not a first-level storage module, the first voltage VCG is an output voltage of a previous-level computing module; The second voltage VG is 0V; the third voltage VM is a coupling voltage generated by the mutual coupling between the storage module at this level and the operation module at this level; and the fourth voltage VS is a fixed value.

6. The analog computer chip according to claim 5, characterized in that: The transfer function of the storage module is: ； In the formula, represents the storage current IM flowing through the third switch tube M3, represents the first voltage VCG, are respectively the electron mobility, oxide layer capacitance and the ratio of the width to the length of the MOS tube of the third switch tube M3, CC1 is the equivalent capacitance of the first switch tube M1, CC2 is the equivalent capacitance of the second switch tube M2, is the turn-on threshold voltage of the third switch tube M3; The transfer function of the storage module is determined by the turn-on threshold voltage Make adjustments; The magnitude of the storage current IM of the storage module is determined by the magnitude of the first voltage VCG and the turn-on threshold voltage The size of the 7. The analog computer chip according to any one of claims 1 to 6, characterized in that: The operation module includes a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a first capacitor C1; The fifth switch tube M5 and the sixth switch tube M6 form a current mirror structure, the control end of the fifth switch tube M5 is connected to the control end of the sixth switch tube M6 and connected to the drain of the fifth switch tube M5, and the drain of the fifth switch tube M5 is connected to the source of the seventh switch tube M7, and the drain of the sixth switch tube M6 is connected to the drain of the eighth switch tube M8; the control end of the seventh switch tube M7 is connected to the control end of the eighth switch tube M8 and connected to the second control voltage VC2, the drain of the seventh switch tube M7 outputs the storage current IM to the storage module at the same level and generates a third voltage VM at its drain end; the low voltage end of the first capacitor C1 is connected to the source of the eighth switch tube M8 and grounded, and the high voltage end of the first capacitor C1 is connected to the drain of the eighth switch tube M8 and outputs the first voltage VCG.

8. The analog computer chip according to claim 7, characterized in that: The fifth switch tube M5 , the sixth switch tube M6 , and the seventh switch tube M7 are all PMOS tubes, and the eighth switch tube M8 is an NMOS tube.

9. The analog computer chip according to claim 8, characterized in that: When the operation module is an n-th level operation module, the high voltage end of the first capacitor C1 inputs the first voltage VCG to the output interface; when the operation module is not an n-th level operation module, the high voltage end of the first capacitor C1 inputs the first voltage VCG to the next level storage module.

10. The analog computer chip according to claim 9, characterized in that: The first voltage VCG output by the operation module is: ； In the formula, is the charging current flowing through the sixth switch tube M6 and is related to the storage current IM. is the charging time of the charging current IMC for the first capacitor C1, is the capacitance value of the first capacitor; The first voltage VCG output by the operation module is adjusted by the storage current IM.

11. A method for operating a highly integrated analog computer chip, characterized in that: The analog computer chip applied to any one of claims 1 to 10 comprises the following steps: Using an external computer to train an artificial intelligence model to obtain parameter values ​​of transfer functions of each storage module in the analog computer chip; Connecting the analog computer chip to an external regulating circuit, adjusting the turn-on threshold voltage of the corresponding switch tube according to the parameter value of the transfer function of each storage module, and obtaining a model of the analog computer chip; The external voltage signal is input into the analog computer chip through multiple input interfaces, and after being transmitted and transformed by each level of storage modules and operation modules in sequence, a final voltage signal is generated, and the final voltage signal is output through multiple output interfaces.

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