Memory device and method of manufacturing semiconductor device

Abstract

A memory device includes an array having a plurality of one-time programmable (OTP) memory cells, a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of control gate (CG) lines formed on a side of a substrate. Each OTP memory cell includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and second fuse resistors are connected to respective ones of the BLs, and the first and second transistors are gated by first and second ones of the CG lines, respectively. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer among a plurality of metallization layers disposed on a side of a substrate. The embodiment of the invention also discloses a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and a method of manufacturing a semiconductor device. Background Art

[0002] A one-time programmable (OTP) memory device is a type of nonvolatile memory device used in integrated circuits to adjust the circuit after the integrated circuit is manufactured. For example, an OTP memory device is used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is to tune analog circuits by fine-tuning their capacitance or resistance values ​​or enabling and disabling portions of the system. A recent trend is that the same product may be manufactured in different manufacturing facilities despite using a common process technology. Despite the best engineering efforts, the process at each facility may be slightly different. The use of OTP memory devices allows the product functionality of each manufacturing facility to be optimized independently. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: an array including a plurality of one-time programmable (OTP) memory cells formed above one side of a substrate; a plurality of word lines (WL); a plurality of bit lines (BL); and a plurality of control gate (CG) lines; wherein each OTP memory cell comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor, wherein the first fuse resistor and the second fuse resistor are connected to a corresponding one of the BLs, and the first transistor and the second transistor are respectively selected by a first CG line and a second CG line of the CG lines, and wherein the first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer of a plurality of metallization layers arranged on the side of the substrate.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell formed on one side of a substrate, and comprising: a first fuse resistor; a second fuse resistor; a first transistor connected in series to the first fuse resistor; and a second transistor connected in series to the second fuse resistor, wherein the memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state after the second fuse resistor is blown, and wherein the first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer among a plurality of metallization layers arranged on the side of the substrate.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a first word line transistor and a second word line transistor along a main surface on one side of a substrate; forming a first metallization layer among a plurality of metallization layers arranged on the first word line transistor and the second word line transistor, wherein the first word line transistor and the second word line transistor are commonly selected and commonly connected to a power rail; forming a second metallization layer among a plurality of metallization layers above the first metallization layer among the plurality of metallization layers; forming a first control gate transistor and a second control gate transistor in the second metallization layer among the plurality of metallization layers, wherein the first control gate transistor and the second control gate transistor are respectively selected; forming a third metallization layer among the plurality of metallization layers above the first metallization layer among the plurality of metallization layers; and forming a first fuse resistor and a second fuse resistor in the third metallization layer among the plurality of metallization layers, wherein the first fuse resistor is connected between the first control gate transistor and a bit line, and wherein the second fuse resistor is connected between the second control gate transistor and the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory system including a memory array according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A schematic diagram showing a plurality of memory cells according to some embodiments Figure 1 An example schematic diagram of a portion of a memory array.

[0009] Figure 3 A schematic diagram showing a plurality of memory cells according to some embodiments Figure 1 Another example schematic diagram of a portion of a memory array.

[0010] Figure 4 and Figure 5 The following are shown according to some embodiments. Figure 2 An example of programming the two memory cells shown in FIG.

[0011] Figure 6 According to some embodiments, the Figure 2 An example of two memory cells is shown in FIG.

[0012] Figure 7 According to some embodiments, a method for Figure 1 Flowchart of an example method for generating PUF bits for a memory array.

[0013] Fig. 8A According to some embodiments, the Figure 2 An example circuit diagram of a memory device showing a memory cell is shown.

[0014] Figure 8B According to an embodiment, the Fig. 8A A cross-sectional view of a memory device implemented by the circuit diagram shown.

[0015] Figure 8C According to another embodiment, Fig. 8A A cross-sectional view of a memory device implemented by the circuit diagram shown.

[0016] Fig.8D According to yet another embodiment, a method based on Fig. 8A A cross-sectional view of a memory device implemented by the circuit diagram shown.

[0017] Fig. 9A According to some embodiments, the Figure 3 An example circuit diagram of a memory device showing a memory cell is shown.

[0018] Fig. 9B According to an embodiment, the Fig. 9A A cross-sectional view of a memory device implemented by the circuit diagram shown.

[0019] Fig. 9C According to another embodiment, Fig. 9A A cross-sectional view of a memory device implemented by the circuit diagram shown.

[0020] Fig.10 A flowchart of an example method for fabricating a semiconductor device according to some embodiments is shown.

[0021] Fig.11 An example diagram of a thin film transistor implemented as a CG transistor in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0024] Physically Unclonable Functions (PUFs) are commonly used for authentication and key storage without the need for secure Electrically Erasable Programmable Read-Only Memory (EEPROM) and / or other expensive hardware (e.g., battery-backed static random access memory). Instead of storing secrets in digital memory, PUFs derive secrets from the physical properties of an integrated circuit (IC). PUFs are based on the idea that even if the same manufacturing process is used to manufacture multiple ICs, each IC may be slightly different due to manufacturing variability. PUFs exploit this variability to derive “secret” information (e.g., silicon biometrics) that is unique to each IC. Typically, this secret information is referred to as the “PUF signature” of the IC. Furthermore, due to the manufacturing variability that defines the PUF signature, no two identical ICs can be manufactured, even if the design of the IC is fully understood. Various types of variability in the IC can be used to define this signature, such as gate delays, the power-on state of the memory device, and / or any of a variety of physical characteristics of the IC.

[0025] Embodiments of the present disclosure provide various systems and methods for generating at least one bit (referred to as a PUF bit) of a PUF signature for a memory device including a plurality of memory cells. In one aspect of the present disclosure, each memory cell is implemented as an efuse (electrical fuse) cell (referred to as an "mT2R structure") including a plurality of transistors and two fuse resistors. One end of the two fuse resistors is usually connected to a bit line, through which a programming voltage is applied. According to various embodiments, even if the two fuse resistors are formed with the same size and the same material and are programmed with the same level of programming voltage at the same time, one of the fuse resistors may be blown (or burned) before the other. Therefore, one of the two fuse resistors can be randomly (and pre-) programmed to equivalently form an open circuit, while the other remains in a short circuit state. Depending on which fuse resistor is broken down first, the disclosed system (e.g., integrated with a memory device) can generate a PUF bit for / from a memory cell of the memory device. Applying the same principle to all memory cells, the disclosed system can generate a unique PUF signature for / from a memory device.

[0026] In some embodiments, a memory device includes an array including a plurality of one-time programmable (OTP) memory cells, a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of control gate (CG) lines formed on one side (e.g., the front side) of a substrate. Each OTP memory cell includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are usually connected to a corresponding one of the BLs, and the first transistor and the second transistor are respectively selected by a first CG line and a second CG line of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are formed in the first, second, third, and fourth metallization layers of the plurality of metallization layers respectively disposed on the side of the substrate, so that the first and second fuse resistors and the first and second transistors are formed in the back end process (BEOL), thereby resulting in a reduction in the memory cell area and an increase in the memory cell density in the memory device.

[0027] Figure 1 1 shows a block diagram of a memory system 100 according to various embodiments. Figure 1 In the illustrated embodiment, memory system 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuitry 108, authentication circuitry 110, and control logic circuitry 112. Figure 1 1, all components of the memory system 100 may be coupled to each other and to the control logic circuit 112. Figure 1In the illustrated embodiment, each component is shown as a separate block for clarity of illustration, but in some other embodiments. Figure 1 Some or all of the components shown in can be integrated together. For example, memory array 102 can include an embedded authentication circuit (eg, 110).

[0028] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., Y direction). Each row and each column may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to a voltage or current through the corresponding conductive structure of the column and row. For example, each row may include a corresponding word line (WL), and each column may include a corresponding bit line (BL) and a plurality of corresponding control gate (CG) lines.

[0029] In some embodiments, each memory cell 103 is implemented as an efuse (electric fuse) memory cell, which may include a first fuse resistor, a second fuse resistor, a first control / cascade gate (CG) selector / transistor, a second CG selector / transistor, and one or more WL selectors / transistors. The first fuse resistor, the first CG transistor, and at least one of the WL transistors are coupled in series with each other, and the second fuse resistor, the second CG transistor, and at least one WL transistor are coupled in series with each other. In addition, the corresponding WL can be connected to the corresponding one or more gates of the one or more WL transistors, the corresponding BL can be connected to the corresponding ends of the first and second fuse resistors, the corresponding first CG line can be connected to the gate of the first CG transistor, and the corresponding second CG line can be connected to the gate of the second CG transistor, which will refer to Figure 2 and Figure 3 Further detailed discussion.

[0030] Although in various embodiments of the present disclosure, the memory cell 103 is implemented as an efuse memory cell including a plurality of fuse resistors, each fuse resistor being formed as a metal track in a corresponding metallization layer, the fuse resistor of the memory cell 103 can be implemented based on other resistor-based storage configurations. For example, the memory cell 103 can be formed as a resistive random access memory (RRAM) configuration, a phase change random access memory (PCRAM) configuration, or a magnetoresistive random access memory (MRAM) configuration. In some other embodiments, the fuse resistor of the memory cell 103 can be implemented based on a through-hole structure or a polysilicon structure. In addition, in some other embodiments, the memory cell 103 can be implemented as an efuse memory cell including a plurality of fuse capacitors, wherein the fuse capacitors can each be formed as a metal insulator metal (MIM) capacitor or a metal oxide metal (MOM) capacitor.

[0031] In short, one or more WL transistors and the first and second CG transistors can be turned on to program the corresponding first and second fuse resistors. For example, when the corresponding WL line, the first CG line and the second CG line are turned on, the two fuse resistors can be programmed simultaneously by applying the same programming voltage on the BL. Randomly, one of the first and second fuse resistors may blow faster than the other, and therefore, the logic state of the memory cell can be determined based on which of the two fuse resistors has blown. This randomly programmed logic state of the memory cell can form the basis of the PUF signature. The following will refer to Figure 4 , Figure 5 and Figure 6 A detailed description regarding the configuration and operation of the memory unit 103 and its application in generating a PUF signature is discussed.

[0032] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert multiple conductive structures (e.g., BL and one or more CG lines) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The authentication circuit 110 is a hardware component that can generate a PUF signature based on the respective logical states of the memory cells read by the I / O circuit 108. The control logic circuit 112 is a hardware component that can control the coupled components (e.g., 102 to 110). Refer to the following Figure 7 The flowchart of FIG. 1 provides a detailed description of the configuration and operation of the memory system 100 .

[0033] Figure 2 and Figure 3 Example schematic diagrams 200 and 300 respectively illustrate portions of a memory device 100 (eg, some memory cells 103) according to some embodiments. Figure 2 and Figure 3 In the illustrated example, efuse memory cells 103A, 103B, 103C, and 103D of the memory array 102 are shown, and each efuse memory cell 103A-103D includes at least two fuse resistors. Although four efuse memory cells 103A, 103B, 103C, and 103D are shown, it should be understood that the memory array 102 can have any number of similar efuse memory cells while still being within the scope of the present disclosure.

[0034] The memory cells 103 may be arranged in an array (as described above). Figure 1 ). Figure 2 and Figure 3 , memory cells 103A and 103B may be arranged in the same row but in different columns; and memory cells 103C and 103D may be arranged in the same row but in different columns. For example, memory cells 103A and 103B are arranged in row R0, but in columns C0 and C1, respectively; and memory cells 103C and 103D are arranged in row R1, but in columns C0 and C1, respectively. With such a configuration, each memory cell may be operably coupled to access lines in corresponding rows and columns, respectively. In various embodiments, along each row, a plurality of efuse memory cells 103 are coupled to a corresponding WL; and along each column, a plurality of efuse memory cells 103 are coupled to a corresponding BL and a plurality of corresponding CG lines. For example, efuse memory cells 103A and 103B are respectively coupled to WL0 arranged in row R0, and coupled to BL0, CG0, CG1 arranged in column C0 and BL1, CG2, CG3 arranged in column C1; and efuse memory cells 103C and 103D are respectively coupled to WL1 arranged in row R1, and coupled to BL0, CG0, CG1 arranged in column C0 and BL1, CG2, CG3 arranged in column C1.

[0035] In some embodiments, the efuse memory unit 103 may include a first fuse resistor, a second fuse resistor, a first CG transistor, a second CG transistor, a first WL transistor, and a second WL transistor, wherein the source / drain terminals of the first CG transistor and the second CG transistor are grounded through the first WL transistor and the second WL transistor, respectively. Figure 2In other embodiments, the efuse memory unit 103 may include a first fuse resistor, a second fuse resistor, a first CG transistor, a second CG transistor, and a common WL transistor, wherein the source / drain terminals of the first CG transistor and the second CG transistor are grounded through the common WL transistor, such as Figure 3 illustrative example shown.

[0036] First reference Figure 2 200 , each efuse memory cell 103A- 103D includes a first fuse resistor 210 , a second fuse resistor 220 , a first CG transistor 230 , a second CG transistor 240 , a first WL transistor 250 , and a second WL transistor 260 . Figure 2 This schematic design in is referred to as a 4-transistor-2-resistor (4T2R) configuration. The first CG transistor 230, the second CG transistor 240, the first WL transistor 250, and the second WL transistor 260 can each be implemented as an n-type transistor. However, it should be understood that each of these transistors can be implemented as a p-type transistor while still within the scope of the present disclosure. The first fuse resistor 210, the first CG transistor 230, and the first WL transistor 250 are connected in series with each other between BL0 and ground; the second fuse resistor 220, the second CG transistor 240, and the second WL transistor 260 are also connected in series with each other between BL0 and ground.

[0037] Taking the efuse memory cell 103A as a representative example, the first end (or terminal) of the first fuse resistor 210 is connected to BL0, and the second end (or terminal) is connected to the first source / drain terminal of the first CG transistor 230; the second fuse resistor 220 has a first end (or terminal) also connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the second CG transistor 240; the first CG transistor 230 has a second source / drain terminal connected to the first source / drain terminal of the first WL transistor 250, and the second drain / source terminal of the first WL transistor 250 is connected to ground; the second CG transistor 240 has a second source / drain terminal connected to the first source / drain terminal of the second WL transistor 260, and the second drain / source terminal of the second WL transistor 260 is connected to ground. In addition, the respective gate terminals of the first WL transistor 250 and the second WL transistor 260 are commonly connected to WL0 (i.e., commonly selected by WL0); the gate terminal of the first CG transistor 230 is connected to CG0 (i.e., selected by CG0); and the gate terminal of the second CG transistor 240 is connected to CG1 (i.e., selected by CG1).

[0038] Next reference Figure 3300 , each efuse memory cell 103A- 103D includes a first fuse resistor 310 , a second fuse resistor 320 , a first CG transistor 330 , a second CG transistor 340 , and a common WL transistor 350 . Figure 3 This schematic design in is referred to as a 3-transistor-2-resistor (3T2R) configuration. The first CG transistor 330, the second CG transistor 340, and the WL transistor 350 can each be implemented as an n-type transistor. However, it should be understood that each of these transistors can be implemented as a p-type transistor while still within the scope of the present disclosure. The first fuse resistor 310, the first CG transistor 330, and the WL transistor 350 are connected in series between BL0 and ground; the second fuse resistor 320, the second CG transistor 340, and the WL transistor 350 are also connected in series between BL0 and ground.

[0039] Taking the efuse memory cell 103A as a representative example, the first end (or terminal) of the first fuse resistor 310 is connected to BL0, and the second end (or terminal) is connected to the first source / drain terminal of the first CG transistor 330; the second fuse resistor 320 has a first end (or terminal) also connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the second CG transistor 340; and the first CG transistor 330 and the second CG transistor 340 both have a second source / drain terminal connected to the first source / drain terminal of the WL transistor 350, and the second drain / source terminal of the WL transistor 350 is connected to the ground. In addition, the gate terminal of the WL transistor 350 is connected to WL0 (i.e., usually selected by WL0); the gate terminal of the first CG transistor 330 is connected to CG0 (i.e., selected by CG0); the gate terminal of the second CG transistor 340 is connected to CG1 (i.e., selected by CG1).

[0040] In order to program the efuse memory cell 103, the corresponding WL transistor and the first and second CG transistors are first activated. In the example where these transistors are all implemented as n-type transistors, one or more WL transistors and the first and second CG transistors are activated (e.g., turned on) by applying a signal of a logic high state to each of the WL and CG lines. Next, a programming signal (e.g., voltage) is applied to the BL. In the case where the WL transistor and the first and second CG transistors (and the corresponding WL transistors) are all turned on, a programming voltage can be applied to the first and second fuse resistors. In other words, two conductive paths can be obtained by at least the first fuse resistor and the second fuse resistor, respectively.

[0041] Due to process variability, even if the two fuse resistors are made of the same material and have the same size, one of the fuse resistors may blow faster than the other. For example, once one of the fuse resistors blows (e.g., one of the fuse resistors becomes open and the other remains short), a sudden drop in voltage may occur on BL, which automatically stops the programming process on the efuse memory cell 103. As a result, the efuse memory cell 103 can be "randomly" programmed to the first logic state or the second logic state. Whether the first or second logic state is programmed into the memory cell can correspond to which fuse resistor has blown (earlier than the other), which can be determined (or detected) based on the reading process.

[0042] In order to read the efuse memory cell 103, the corresponding one or more WL transistors and only one of the first or second CG transistors are first activated (e.g., turned on). In some embodiments, the selection of which CG transistor to activate is fixed across the entire memory array. For example, in all columns of the memory array, one of the even CG lines (e.g., CG0) or the odd CG lines (e.g., CG1) is activated during the reading process. Next, a read signal (e.g., voltage) is applied to the BL. Since one of the fuse resistors has been randomly programmed (blown), a conductive path can only be established from the BL, through the unblown fuse resistor and the selected (activated) CG transistor, to the ground. On the other hand, a conductive path cannot be established from the BL, through the blown fuse resistor and the selected (activated) CG transistor, to the ground. For example, if the selected CG transistor is connected to a blown fuse resistor, a conductive path will not be established; if the selected CG transistor is connected to an unblown fuse resistor, a conductive path will be established.

[0043] In some embodiments, in the absence of a conductive path (i.e., the fuse resistor connected to the selected CG transistor has been blown), the efuse memory cell 103 is determined to be in a first logic state (e.g., logic 1); and with the establishment of a conductive path (i.e., the fuse resistor connected to the selected CG transistor has not yet been blown), the efuse memory cell 103 is determined to be in a second logic state (e.g., logic 0). In other words, each efuse memory cell 103 can be randomly programmed to logic 1 or 0. Based on this randomly programmed logic state on each efuse memory cell, a PUF signature (formed by the individual PUF bits of the efuse memory cell) can be generated.

[0044] Figure 4 and Figure 5An example of efuse memory cells 103A and 103D being sequentially programmed according to some embodiments is shown. According to the above principles, each of the efuse memory cells 103A and 103D can be randomly programmed to a first logic state (e.g., a logic 1 with a blown fuse resistor) or a second logic state (e.g., a logic 0 with a good fuse resistor). The values ​​of the signals discussed below are for illustrative purposes only, and therefore, other values ​​may be considered while remaining within the scope of the present disclosure.

[0045] First reference Figure 4 , in order to program the efuse memory cell 103A, WL0 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while the other word lines (e.g., WL1) are each applied with a voltage signal corresponding to a logic low state (e.g., about 0V). At the same time or subsequently, CG0 and CG1 are also asserted by applying a voltage signal of about 0.75V, while the other control gate lines (e.g., CG2 and CG3) are applied with a voltage signal of about 0V. Therefore, the WL transistors 250 and 260 and the CG transistors 230 and 240 of the efuse memory cell 103A can be turned on, while the WL transistors and CG transistors of the other efuse memory cells remain in a deactivated state. Next, a programming voltage (e.g., about 1.2V-1.5V) is applied to BL0, while the other bit lines (e.g., BL1) are each applied with a voltage signal of about 0V. Therefore, two conductive paths 401 and 403 can be used to conduct current from BL0 to ground. As described above, one of the fuse resistors (eg, 210) will blow earlier than the other (eg, 220). As a result, the voltage present on BL0 will suddenly drop, which will cause the programming process (eg, on the still intact fuse resistor 220) to stop.

[0046] Next reference Figure 5, in order to program the efuse memory cell 103D, WL1 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while the other word lines (e.g., WL0) are each applied with a voltage signal corresponding to a logic low state (e.g., about 0V). At the same time or subsequently, CG2 and CG3 are also asserted by applying a voltage signal of about 0.75V, while the other control gate lines (e.g., CG0 and CG1) are applied with a voltage signal of about 0V. Therefore, the WL transistors 250 and 260 and the CG transistors 230 and 240 of the efuse memory cell 103D can be turned on, while the WL transistors and CG transistors of the other efuse memory cells remain in a deactivated state. Next, a programming voltage (e.g., about 1.2V-1.5V) is applied to BL1, while the other bit lines (e.g., BL0) are each applied with a voltage signal of about 0V. Therefore, two conductive paths 501 and 503 can be used to conduct current from BL1 to ground. As described above, one of the fuse resistors (eg, 220) will blow earlier than the other (eg, 210). As a result, the voltage present on BL1 will suddenly drop, which will cause the programming process (eg, on the still intact fuse resistor 210) to stop.

[0047] Figure 6 An example of sequentially reading efuse memory cells 103A and 103D (after programming) is shown in accordance with some embodiments. Figure 4-Figure 5 Examples discussed in Figure 6 As shown, fuse resistor 210 of efuse memory cell 103A is blown, while fuse resistor 220 of efuse memory cell 103D is blown. The values ​​of the signals discussed below are for illustration purposes only, and thus other values ​​are contemplated while remaining within the scope of the present disclosure.

[0048] To read the efuse memory cell 103A, WL0 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while the other word lines (e.g., WL1) are each applied with a signal corresponding to a logic low state (e.g., about 0V). At the same time or subsequently, one of CG0 or CG1 (e.g., CG0) is asserted by applying a voltage signal of about 0.75V, while the other control gate lines (e.g., CG1, CG2, and CG3) are each applied with a voltage signal of about 0V. Therefore, the WL transistors 250 and 260 and the CG transistor 230 of the efuse memory cell 103A can be turned on, while the CG transistor 240 of the efuse memory cell 103A remains in a deactivated state. Next, a read voltage (e.g., about 1.2V-1.5V) is applied to BL0, while the other bit lines (e.g., BL1) are each applied with a voltage signal of about 0V. One conductive path 601 can be used to conduct current from BL0 to ground through the fuse resistor 210, the CG transistor 230, and the WL transistor 250. Since the fuse resistor 210 has been burned out (i.e., programmed to an open circuit), no current can flow through such a conductive path 601. Therefore, there is no current (or the current level is less than a predefined threshold) on BL0, and thus the efuse memory cell 103A can be determined to be permanently programmed to a logic 1 (e.g., having a blown fuse resistor connected to an activated CG transistor).

[0049] Similarly, to read the efuse memory cell 103D, WL1 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while the other word lines (e.g., WL0) are each applied with a signal corresponding to a logic low state (e.g., about 0V). At the same time or subsequently, one of CG2 or CG3 (e.g., CG2) is asserted by applying a voltage signal of about 0.75V, while the other control gate lines (e.g., CG3, CG0, and CG1) are each applied with a voltage signal of about 0V. Therefore, the WL transistors 250 and 260 and the CG transistor 230 of the efuse memory cell 103D can be turned on, while the CG transistor 240 of the efuse memory cell 103D remains in a deactivated state. Next, a read voltage (e.g., about 1.2V-1.5V) is applied to BL1, while the other bit lines (e.g., BL0) are each applied with a voltage signal of about 0V. One conductive path 603 can be used to conduct current from BL1 to ground through the fuse resistor 210, the CG transistor 230, and the WL transistor 250. Since the fuse resistor 210 is not burned (i.e., programmed to an open circuit), current can flow through such a conductive path 603. Therefore, there is current (or a current level above a predefined threshold) on BL1, and thus the efuse memory cell 103D can be determined to be permanently programmed to a logic 0 (e.g., having an intact fuse resistor connected to an activated CG transistor).

[0050] Figure 7 A flowchart of an example method 700 for generating a physical unclonable function (PUF) signature based on an efuse memory cell including a pair of fuse resistors and multiple CG / WL transistors (“mT2R” configuration) according to various embodiments is shown. The operations of the method 700 are at least Figure 1 and Figure 2 For the purpose of discussion, we will combine Figure 1 and Figure 2 The following embodiment of method 700 is described. The illustrated embodiment of method 700 is merely an example, and thus any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present disclosure.

[0051] Method 700 may begin with operation 702 of a programming process. In some embodiments, operation 702 may include an operation 704 of selecting a column, an operation 706 of selecting a row, and an operation 708 of applying a programming voltage on the BL of the selected column. It should be noted that the order of operations 704 to 708 may be changed while still within the scope of the present disclosure. For example, operations 704 and 706 may be swapped.

[0052] Referring first to operation 704, the control logic circuit 112 may provide a column address to the column decoder 106 to select columns C1 to C2 of the memory array 102. N In some embodiments, the column address used during programming may not specify which CG line is to be selected. In other words, column decoder 106 may assert the CG line and BL of the selected column. When a column is selected, I / O circuitry 108 may assert each CG line (e.g., Figure 2 CG0 and CG1 of FIG. 2 provide a voltage (eg, corresponding to a logic high state when the CG transistor is an n-type transistor). Therefore, CG transistors 230 and 240 may be turned on.

[0053] Next, in operation 706, the control logic circuit 112 may provide a row address to the row decoder 104 to select rows R1 to R2 of the memory array 102. M In some embodiments, the row address may specify which WL is to be selected. When a row is selected, I / O circuit 108 may send a WL (e.g., Figure 2 The WL0 of the selected column and row can be provided with a voltage (e.g., corresponding to a logic high state when the WL transistor is an n-type transistor). Therefore, the WL transistors 250 and 260 can be turned on. Therefore, the memory cell (e.g., 103A) arranged at the intersection of the selected column and row can be programmed.

[0054] Next, in operation 708, the BL (eg Figure 2 By turning on CG transistors 230-240 and WL transistors 250-260, two conductive paths can be formed, one of which extends from BL0, through fuse resistor 210, CG transistor 230 and WL transistor 230, to ground, and the other extends from BL0, through fuse resistor 220, CG transistor 240 and WL transistor 260, to ground. Therefore, the programming voltage applied to BL0 can randomly blow one of fuse resistor 210 or fuse resistor 220.

[0055] Next, the method 700 may continue to operation 710 to determine whether one of the fuse resistors of the selected memory cell has been blown (i.e., programmed). If so, the method 700 may continue to operation 712 including one or more read processes. If not, the method 700 may return to operation 702 to perform the programming process again. In various embodiments, as described above, the I / O circuit 108 may determine whether one of the fuse resistors has been blown based on detecting a voltage drop present on the selected BL (e.g., BL0).

[0056] In some embodiments, operation 712 may include an operation 714 of selecting a column, an operation 716 of selecting a row, and an operation 718 of applying a read voltage on the BL of the selected column. It should be noted that the order of operations 714 to 718 may be changed while still within the scope of the present disclosure. For example, operations 714 and 716 may be swapped.

[0057] Referring first to operation 714, the control logic circuit 112 may provide a column address to the column decoder 106 to select columns C1 through C2 of the memory array 102. N In some embodiments, the column address used during the read process may specify which CG lines are to be selected. In other words, column decoder 106 may assert only one of the CG line and BL of the selected column. After selecting a column, I / O circuit 108 may assert the CG lines (e.g., Figure 2 The CG0 of the CG transistor 230 provides a voltage (eg, corresponding to a logic high state when the CG transistor is an n-type transistor). Thus, the CG transistor 230 may be turned on, while the other CG transistor 240 may be turned off.

[0058] Next, in operation 716, the control logic circuit 112 may provide a row address to the row decoder 104 to select rows R1 to R2 of the memory array 102. M In some embodiments, the row address may specify which WL is to be selected. When a row is selected, I / O circuit 108 may send a WL (e.g., Figure 2 The WL0 of the memory cell 200 provides a voltage (e.g., corresponding to a logic high state when the WL transistor is an n-type transistor). Therefore, the WL transistors 250 and 260 can be turned on. Therefore, the memory cell (e.g., 103A) arranged at the intersection of the selected column and row can be read.

[0059] Next, in operation 718, the BL of the selected column (eg Figure 2 A read voltage is applied to BL0 of BL0. By turning on CG transistor 230 and WL transistors 250-260, a conductive path extending from BL0 through fuse resistor 210, CG transistor 230, WL transistor 250 and reaching ground can be obtained, depending on whether fuse resistor 210 is randomly blown. For example, if fuse resistor 210 remains intact (not blown), the read voltage applied to BL0 can generate a current flowing through the conductive path. In other words, a short circuit is formed (or maintained) from BL0, through fuse resistor 210, CG transistor 230 and WL transistor 250, to ground. On the other hand, if fuse resistor 210 has been blown, no current can be generated. In other words, an open circuit is formed between BL0 and ground.

[0060] The method 700 may continue to operation 720, where a logic state programmed into the memory cell is determined, and a bit of a PUF signature is generated based on the determined logic state. For example, the control logic circuit 112 may determine the logic state programmed into the memory cell 103A based on the read process 712, for example, whether there is a current on BL0. If a current or a sufficiently high current level is detected (e.g., by the I / O circuit 108), the control logic circuit 112 may determine that the memory cell 103A (or specifically, the fuse resistor connected to the selected CG transistor) is not blown, and thus the programming logic state is determined to be a logic 0. If no current is detected or a sufficiently low current level is detected (e.g., by the I / O circuit 108), the control logic circuit 112 may determine that the memory cell 103A (or specifically, the fuse resistor connected to the selected CG transistor) has been blown, and thus the programming logic state is determined to be a logic 1. Next, the control logic circuit 112 may provide the determined logic state to the authentication circuit 110 to generate a PUF bit. Since the logic state is randomly determined based on the process variation of a pair of fuse resistors, the logic state (ie, PUF bit) can be randomly generated, which advantageously improves the security of the memory system 100 .

[0061] Fig. 8A According to some embodiments, the Figure 2 800A. In some embodiments, according to Figure 2 Schematic design 200 (“4T2R” configuration), the memory cell 103 in the memory device 800A is implemented as an efuse memory cell, so the reuse Figure 2 Some references. Fig. 8A The memory cell 103 in corresponds to Figure 2 Memory cell 103C in and used as a representative example, however, Fig. 8A The memory cell 103 may be Figure 2 Any one of the memory cells 103A-103D.

[0062] like Fig. 8AAs shown, the memory device 800A includes at least a memory cell 103, and the memory cell 103 includes a first fuse resistor 210, a second fuse resistor 220, a first CG transistor 230, a second CG transistor 240, a first WL transistor 250, and a second WL transistor 260. The first fuse resistor 210, the first CG transistor 230, and the first WL transistor 250 are connected in series between BL0 and ground. The second fuse resistor 220, the second CG transistor 240, and the second WL transistor 260 are also connected in series between BL0 and ground. The first WL transistor 250 and the second WL transistor 260 are usually selected by WL1 selected from a plurality of WLs. The first CG transistor 230 and the second CG transistor 240 are respectively selected by the CG0 line and the CG1 line selected from a plurality of CG lines.

[0063] During programming, the first WL transistor 250 and the second WL transistor 260 of the memory cell 103 are activated simultaneously by applying a voltage (e.g., about 0.75V) to their gate terminals, and then a programming voltage (e.g., about 1.2V-1.5V) is applied to BL0. As a result, the first fuse resistor 210 or the second fuse resistor 220 is blown. The memory cell 103 is configured to randomly present a first logic state (e.g., logic 1) when the first fuse resistor 210 is blown, or to randomly present a second logic state (e.g., logic 0) when the second fuse resistor 220 is blown. Therefore, the first logic state or the second logic state is used as a bit (logic 1 or logic 0) of the PUF signature of the memory cell 103, thereby generating a PUF signature bit of the memory cell.

[0064] During the reading process, the first WL transistor 250 and the second WL transistor 260 of the memory cell 103 are simultaneously activated by applying a voltage (e.g., about 0.75 V) to their gate terminals, while only one of the first CG transistor 230 or the second CG transistor 240 is activated by applying a voltage (e.g., about 0.75 V) to its gate terminal. As a result, a bit (logic 1 or logic 0) of the PUF signature of the memory cell 103 is read or detected.

[0065] Reference Figure 8B-Figure 8D The cross-sectional diagram is discussed as follows Fig. 8A Further details of the implementation of the memory device 800A designed in the 4T2R configuration are shown and will be repeated using Fig. 8A Some references. Figure 8B 8 shows a cross-sectional view of a memory device 800B according to an embodiment. It should be understood that for the purpose of illustration, Figure 8B The cross-sectional view shown is simplified, and thus the cross-sectional view 800B may include various other components while remaining within the scope of the present disclosure.

[0066] like Figure 8B As shown, the memory device 800B includes a substrate 801 having a front side 803 and a back side 805, an active area 802 formed along a main surface of the front side surface 803 and extending in a first lateral direction (e.g., X direction), and a first gate structure 812 and a second WL gate structure 814 covering the active area 802 and extending laterally in a second lateral direction (e.g., Y direction).

[0067] In some embodiments, such active regions and gate structures are referred to as part of a "front end of line (FEOL) process / network" because they are formed along the main surface of the front side of the substrate. On the front side surface of the substrate, multiple front side metallization layers (referred to as part of a "middle of line (MEOL) process / network") may be formed. Above and away from the main surface of the front side of the substrate, multiple front side metallization layers (referred to as part of a "back end of line (BEOL) process / network") may be formed. Over the back side 805 of the substrate 801, multiple back side metallization layers (e.g., BMO) may be formed.

[0068] In some embodiments, the active region 802 is formed by a stacked structure (not shown) protruding from the main surface 803 of the substrate 801 in the FEOL network. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and separated vertically from each other. Portions of the semiconductor nanostructures covered by the gate structures 812 and 814 in the stack remain, while other portions are replaced by a number of epitaxial structures. The remaining portions of the semiconductor structure can be configured as a channel of a corresponding transistor, the epitaxial structures coupled to both sides (or ends) of the remaining portions of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., crossing) the remaining portions of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0069] As Figure 8B In a representative example, in a FEOL network, the portion of the active region portion 802 covered by the gate structure 812 can be used as Fig. 8A The portion of the active area portion 802 disposed on the opposite side of the gate structure 812 is replaced by the epitaxial structure and can thus be used as the source / drain terminal of the first WL transistor 250, respectively. The gate structure 812 can be used as the gate terminal of the first WL transistor 250. Similarly, the portion of the active area portion 802 covered by the gate structure 814 can be used as Fig. 8A The active region portion 802 is provided on the opposite side of the gate structure 814 and is replaced by an epitaxial structure, and thus can be used as the source / drain terminals of the second WL transistor 260, respectively. The gate structure 814 can be used as the gate terminal of the second WL transistor 260. In this way, Fig. 8A The first WL transistor 250 and the second WL transistor 260 in the FEOL network are formed along the main surface of the front side of the substrate.

[0070] like Figure 8B As shown, in the MEOL network, a plurality of middle-end interconnect structures (such as 822, 824, and 826) are formed on the corresponding source / drain terminals of the first WL transistor 250 and the second WL transistor 260. The middle-end interconnect structure (referred to as MD) can connect the corresponding source / drain terminals to the upper interconnect structure through a middle-end via structure (also referred to as VD, such as VD1, VD2). The gate structure can be coupled to the upper interconnect structure through another middle-end via structure (referred to as VG, such as VG1, VG2). Therefore, the gate structures 812 and 814 can be coupled to one or more metal tracks formed thereon.

[0071] Over these intermediate end structures on the front side of the substrate, a plurality of metallization layers (e.g., M0, M1, M2, M3, M4) may be formed, each of which includes a plurality of metal tracks or lines embedded in a corresponding dielectric material (e.g., intermetallic dielectric (IMD) / interlayer dielectric (ILD)). Figure 8B As shown, memory device 800B includes metal tracks 832, 834, 836, and 838 in the M0 layer; metal tracks 842 and 844 in the M1 layer; metal tracks 852 and 854 in the M2 layer; metal track 862 in the M3 layer; and metal tracks 872, 874, 876, and 878 in the M4 layer.

[0072] For example, gate structure 812 is coupled to M0 metal rail 834 through VG1, and gate structure 814 is coupled to M0 metal rail 836 through VG2. MD 822, together with at least M0 metal rail 832 and M1 metal rail 842, can couple one of the source / drain terminals (e.g., epitaxial structure) of WL transistor 250 to one end of M4 metal rail 872; MD 826, together with at least M0 metal rail 838 and M1 metal rail 844, can couple one of the source / drain terminals (e.g., epitaxial structure) of WL transistor 260 to one end of M4 metal rail 878. The other of the source / drain terminals of WL transistors 250 and 260 is typically coupled to MD 824. In some embodiments, MD 824 is coupled to a power supply voltage (VSS), and in other embodiments, is coupled to ground (GND).

[0073] like Figure 8BAs shown, the memory device 800B also includes a metal track 892 in the first backside metallization layer (hereinafter referred to as "BM0 track 892"), which is the bottommost metallization layer relative to the backside surface 805 of the substrate 801. For simplicity, Figure 8B Only BM0 is shown in FIG. However, on the back side of the substrate, multiple metallization layers (referred to as BM0, BM1, BM2, BM3) may be formed, each metallization layer comprising one or more metal tracks or lines embedded in a corresponding dielectric material (e.g., an intermetallic dielectric (IMD) or an interlayer dielectric (ILD)).

[0074] In addition, the memory device 800B further includes a first CG transistor 230 and a second CG transistor 240 and a first fuse resistor 210 and a second fuse resistor 220, both of which are formed in a metallization layer (e.g., M4) of a plurality of metallization layers (e.g., M1, M2, M3, M4) in a BEOL network over the front side 803 of the substrate 801, and both of which are formed in another metallization layer (e.g., M2) of the plurality of metallization layers (e.g., M1, M2, M3, M4) of the BEOL network over the front side 803. Figure 8B As shown, in some embodiments, the first CG transistor 230 and the second CG transistor 240 formed in the BEOL network are vertically farther from the main surface of the front side 803 than the second fuse resistor 220 and the first fuse resistor 210 formed in the BEOL network.

[0075] Reference Fig. 8A and Figure 8B , M2 metal tracks 852 and 854 can be used as the first fuse resistor 210 and the second fuse resistor 220. In some embodiments, the first fuse resistor 210 and the second fuse resistor 220 are generally coupled to the BL. Figure 8B As shown, one end of the first fuse resistor 210 and one end of the second fuse resistor 220 are commonly coupled to an M3 metal track 862 that serves as part of BLO.

[0076] like Fig. 8A and Figure 8BAs shown, the source / drain terminal of the first CG transistor 230 is coupled to the source / drain terminal of the first WL transistor 250 through at least MD 822, M0 metal track 832, M1 metal track 842, M4 metal track 872, and some vias; the other source / drain terminal of the first CG transistor 230 is coupled to the other end of the first fuse resistor 210 through at least M4 metal track 874. Similarly, the source / drain terminal of the second CG transistor 240 is coupled to the source / drain terminal of the second WL transistor 260 through at least MD 826, M0 metal track 838, M1 metal track 844, M4 metal track 878, and some vias; the other source / drain terminal of the second CG transistor 240 is coupled to the other end of the second fuse resistor 220 through at least M4 metal track 876.

[0077] Thus, by forming CG transistors and fuse resistors in one or more metallization layers in the BEOL network, the area and programming voltage of each memory cell of the memory device can be reduced, thereby increasing the density of memory cells in the memory device and improving the performance of the memory device.

[0078] Figure 8C According to an embodiment, the Fig. 8A 800C is a cross-sectional view of a memory device 800C implemented by the circuit diagram shown. The configuration of the memory device 800C is substantially similar to the memory device 800B, but there are some differences. The memory device 800C includes a memory cell 103 designed in a "4T2R" configuration and formed over the front side 803 of the substrate 801, and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4, M5) respectively disposed over the front side 803 of the substrate 801.

[0079] Similarly, if Figure 8C As shown, the memory cell 103 includes a first WL transistor 250 and a second WL transistor 260 formed along the main surface of the front side 803 in the FEOL network, a first CG transistor 230 and a second CG transistor 240 formed in a first metallization layer (e.g., M5) of a plurality of metallization layers in the BEOL network, and a first fuse resistor 210 and a second fuse resistor 220 formed in a second metallization layer (e.g., M2) and a third metallization layer (e.g., M4) of a plurality of metallization layers in the BEOL network, respectively. Figure 8B The situation shown in is different, as Figure 8C As shown in FIG. 1 , the first fuse resistor 210 and the second fuse resistor 220 are respectively formed in different metallization layers (eg, M2 and M4 ) among a plurality of metallization layers in the BEOL network.

[0080] Similarly, if Figure 8CAs shown, the first WL transistor 250 and the second transistor 260 are commonly selected to WL1. The first CG transistor 230 and the second CG transistor 240 are selected to CG0 and CG1, respectively. The first WL transistor 250, the first CG transistor 230 and the first fuse resistor 210 are coupled in series between BL0 (for example, implemented by the M3 metal track 862) and the power supply voltage (Vss) or ground (GND); the second WL transistor 260, the second CG transistor 240 and the second fuse resistor 220 are coupled in series between BL0 and the power supply voltage (Vss) or ground (GND).

[0081] Fig.8D The embodiment based on Fig. 8A 800D is a cross-sectional view of a memory device 800D implemented by the circuit diagram in FIG. The configuration of the memory device 800D is substantially similar to the memory device 800B, but there are some differences. The memory device 800D includes a memory cell 103 designed in a "4T2R" configuration and formed over a front side 803 of a substrate 801, and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4) respectively disposed over the front side 803.

[0082] like Fig.8D As shown, the memory cell 103 includes a first WL transistor 250 and a second WL transistor 260, a first CG transistor 230 and a second CG transistor 240, and a first fuse resistor 210 and a second fuse resistor 220. The first WL transistor 250 and the second WL transistor 260 are formed along the main surface of the front side 803 in the FEOL network, the first CG transistor 230 and the second CG transistor 240 are formed in a first metallization layer (e.g., M2) among a plurality of metallization layers in the BEOL network, and the first fuse resistor 210 and the second fuse resistor 220 are formed in a second metallization layer (e.g., M3) among a plurality of metallization layers in the BEOL network. However, unlike the example Figure 8B Unlike the situation shown in , the first and second fuse resistors 210 and 220 formed in the BEOL network are farther away from the front side 803 in the vertical direction than the first and second CG transistors 230 and 240 formed in the BEOL network.

[0083] Fig. 9A According to some embodiments, the Figure 3 An example circuit diagram of a memory device 900A of a memory cell is shown. Figure 3 Schematic design 300 (“3T2R” configuration), the memory cell 103 of the memory device 900A is implemented as an efuse memory cell, and Figure 3 Some of the references will be reused. Fig. 9A The memory cell 103 in Figure 3 The memory cell 103C in FIG. 1 is used as a representative example and may be Figure 3 Any one of the memory cells 103A-103D.

[0084] The memory device 900A includes at least a memory cell 103, and the memory cell 103 includes a first fuse resistor 310, a second fuse resistor 320, a first CG transistor 330, a second CG transistor 340, and a single WL transistor 350. The first fuse resistor 310, the first CG transistor 330, and the single WL transistor 350 are connected in series between BL0 and Vss (or ground). The second fuse resistor 320, the second CG transistor 340, and the single WL transistor 350 are also connected in series between BL0 and Vss (or ground). The single WL transistor 350 is selected by WL1 selected from a plurality of WLs. The first CG transistor 330 and the second CG transistor 340 are respectively selected by the CG0 line and the CG1 line.

[0085] During programming, a single WL transistor 350 of the memory cell 103 is activated by applying a voltage (e.g., about 0.75V) to its gate terminal, and then a programming voltage (e.g., about 1.2V-1.5V) is applied to BL0. As a result, the first fuse resistor 310 or the second fuse resistor 320 is blown. The memory cell 103 is configured to randomly present a first logic state (e.g., logic 1) when the first fuse resistor 310 is blown, or to randomly present a second logic state (e.g., logic 0) when the second fuse resistor 320 is blown. Therefore, the first logic state or the second logic state is used as a bit (logic 1 or logic 0) of the PUF signature of the memory cell 103, thereby generating a PUF signature bit in the memory cell 103.

[0086] During the reading process, the single WL transistor 350 is activated by applying a voltage (e.g., about 0.75 V) to its gate terminal, and only one of the first CG transistor 330 or the second CG transistor 340 is activated by applying a voltage of about 0.75 V to its gate terminal. Thus, a bit (logic 1 or logic 0) of the PUF signature of the memory cell 103 is detected.

[0087] Reference will be made to Fig. 9B and Fig. 9C Various embodiments shown in cross-sectional views are discussed in detail with respect to Fig. 9A Further details of the configuration and / or implementation of the memory device of circuit diagram 900A are provided. Fig. 9A Some references will be in Fig. 9B and Fig. 9C Repeated use in.

[0088] Fig. 9BThe embodiment based on Fig. 9A 900B is a cross-sectional view of a memory device 900B implemented by the circuit diagram in FIG. It should be understood that for the purpose of illustration, Fig. 9B The cross-sectional view 900B shown is simplified, and thus the cross-sectional view 900B may include various other components while remaining within the scope of the present disclosure.

[0089] The memory device 900B includes a memory cell 103 designed in a "3T2R" configuration and formed over the front side of a substrate 901, and a plurality of metallization layers (e.g., M1, M2, M3, M4) respectively disposed over the front side 903 of the substrate 901 in a BEOL network. The memory cell 103 includes a single WL transistor 350 formed in an active region 902 along a major surface of the front side 903 in the FEOL network, a first CG transistor 330 and a second CG transistor 340 formed in a first metallization layer (e.g., M4) among the plurality of metallization layers in the BEOL network, and a first fuse resistor 310 and a second fuse resistor 320 both formed in a second metallization layer (e.g., M2) among the plurality of metallization layers in the BEOL network.

[0090] like Fig. 9A and Fig. 9B As shown, in some embodiments, a single WL transistor 350 is gated to WL1. A first CG transistor 330 and a second CG transistor 340 are gated to CG lines (e.g., CG0 and CG1), respectively. A single WL transistor 350, a first CG transistor 330, and a first fuse resistor 310 are coupled in series between BL0 (e.g., formed by an M3 metal track) and Vss; and a single WL transistor 350, a second CG transistor 340, and a second fuse resistor 320 are coupled in series between BL0 and Vss.

[0091] like Fig. 9B As shown, in some embodiments, the first CG transistor 330 and the second CG transistor 340 in the first metallization layer (e.g., M4) of the plurality of metallization layers formed in the BEOL network are vertically farther away from the front side 903 of the substrate 901 than the first fuse resistor 310 and the second fuse resistor 320 in the second metallization layer (e.g., M2) of the plurality of metal layers formed in the BEOC network.

[0092] Fig. 9C According to another embodiment, a Fig. 9A 00C is a cross-sectional view of a semiconductor device 900C implemented by the circuit diagram in FIG. Fig. 9C The configuration of the memory device 900C in Fig. 9BThe memory device 9001B shown in FIG. 1 is substantially similar, but has some differences.

[0093] Similarly, if Fig. 9C As shown, the memory device 900C includes a memory cell 103 designed in a "3T2R" configuration and formed over a front side 903 of a substrate 901, and a plurality of metallization layers (e.g., M1, M2, M3, M4) respectively disposed over the front side 903 in a BEOL network. The memory cell 103 includes a single WL transistor 350, a first CG transistor 330, and a second CG transistor 340, and a first fuse resistor 310 and a second fuse resistor 320. The single WL transistor 350 is formed in an active region 902 and is formed along a major surface of the front side 903 in a FEOL network. The first CG transistor 330 and the second CG transistor 340 are formed in a first metallization layer (e.g., M2) among the plurality of metallization layers in the BEOL network. The first fuse resistor 310 and the second fuse resistor 320 are both formed in a second metallization layer (e.g., M3) among the plurality of metallization layers in the BEOL network.

[0094] The difference is that, Fig. 9C As shown, in the memory device 900C, the first fuse resistor 310 and the second fuse resistor 320 formed in the BEOL network are farther from the front side 903 in the vertical direction than the first CG transistor 330 and the second CG transistor 340 formed in the BEOL network.

[0095] Fig.10 1 is a flowchart of an exemplary method 1000 for manufacturing a semiconductor device according to some embodiments. It should be noted that the method 1000 is merely an example and is not intended to limit the present disclosure. Therefore, it can be understood that in Figure 1 Additional operations may be provided before, during, and after method 1000. And some other operations may only be briefly described here. The order of operations may be interchangeable.

[0096] For example, method 1000 may be performed to form Fig.8DThe memory device 800D in the embodiment of the present invention is a memory device 800D, so some references used above may be reused in the following discussion of the method 1000. As described above, the memory device 800D includes a memory cell 103 designed in a 4T2R configuration and formed on a front side 803 of a substrate 801, and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4) respectively disposed above the front side 803 of the substrate 801. The memory cell 103 includes a first WL transistor 250 and a second WL transistor 260, a first CG transistor 230 and a second CG transistor 240, and a first fuse resistor 210 and a second fuse resistor 220. The first WL transistor 250 and the second WL transistor 260 are both formed along the main surface of the front side 803 of the substrate 801 in the FEOL network, the first CG transistor 230 and the second CG transistor 240 are both formed in a first metallization layer (e.g., M2) among multiple metallization layers in the BEOL network, and the first fuse resistor 210 and the second fuse resistor 220 are both formed in a second metallization layer (e.g., M3) among multiple metallization layers in the BEOL network.

[0097] According to various embodiments, method 1000 starts from operation 1002, where a substrate is provided. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering the bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0098] According to various embodiments, method 1000 continues to operation 1004, where a stack including an alternating series of first and second nanostructures is formed. This stack can be formed based on one of the above-mentioned (active area) patterns. The stack can be formed on the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. This stack can be called a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure can be SiGe 25%. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It is understood that the percentage of Ge in each SiGe sacrificial nanostructure can be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductors have different etching characteristics (e.g., etching rates), respectively.

[0099] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next layer until the desired number and desired thickness of nanostructures are reached. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Depending on the type of transistor, the epitaxial silicon, silicon germanium and / or carbon-doped silicon (Si:C) can be doped during the deposition process by adding dopants, n-type dopants (such as phosphorus or arsenic) or p-type dopants (such as boron or gallium) (in situ doping).

[0100] According to various embodiments, method 1000 continues to operation 1006, where a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-described (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, and thus, the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0101] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while still within the scope of the present disclosure. The a-Si is then flattened to the desired level. A hard mask is deposited and patterned on the flattened a-Si. The hard mask can be formed by a nitride or oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After the pseudo gate structure is formed, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials) followed by directional etching (e.g., RIE).

[0102] According to various embodiments, method 1000 proceeds to operation 1008, where an internal spacer is formed by replacing the end of each SiGe sacrificial nanostructure with a dielectric material. After forming a pseudo gate structure covering certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacer is formed by filling the recess of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric substance having a dielectric constant k less than about 5).

[0103] According to various embodiments, method 1000 proceeds to operation 1010, wherein a plurality of epitaxial structures are formed. After forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form a doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and P-type devices can be formed by injecting boron (B). After forming the epitaxial structure, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0104] According to various embodiments, method 1000 proceeds to operation 1012, where the dummy gate structure and the remaining SiGe sacrificial nanostructures are replaced with corresponding active gate structures. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructures are removed by applying a selective etch (e.g., hydrochloric acid (HCl)) while keeping the Si channel nanostructures substantially intact. After removing the SiGe sacrificial nanostructures, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls in contact with the dielectric fin structure. Next, multiple active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls in contact with the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). After forming the active gate structure, a transistor of the memory device can be formed. Referring to, for example Fig.8D , the first WL transistor 250 and the second WL transistor 260 of the memory device 800D are formed along the main surface of the front side 803 of the substrate 801 in the FEOL network.

[0105] Method 1000 proceeds to operation 1014, where a plurality of front-side interconnect structures are formed according to various embodiments. After forming the WL transistors (e.g., 250 and 260), a plurality of middle-end interconnect structures (e.g., VG, MD) are formed on the transistors. For example, referring to Figure 8B , multiple VGs (e.g., VG1 and VG2) can be formed to couple to the gate terminals of the transistors, respectively, and multiple sub-MDs (e.g., 822, 824, and 826) can be formed to couple to the source / drain terminals of the CG transistors 250 and 260. In addition, multiple back-end interconnect structures can be formed above the intermediate end interconnect structure. Such back-end interconnect structures include the above-mentioned M0 tracks (e.g., 832, 834, 836, 838) in the M0 layer, and other metal tracks (e.g., 852, 854, 872, 874, 876, 878) in the upper metallization layers (e.g., M1, M2, M3, M4). Each of the WL transistors 250 and 260 can be enabled by at least VG. For example, as Figure 8B As shown, WL transistors 250 and 260 may be commonly gated to WL1.

[0106] The front-side interconnect structure can be formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure can be formed by covering the front side of the substrate with the above-mentioned metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating or a combination thereof.

[0107] The method 1000 proceeds to operation 1016, where a first CG transistor and a second CG transistor are formed in a first metallization layer of a plurality of metallization layers in a BEOL network above the first WL transistor and the second WL transistor. Similarly, at least some of the above processes for forming the WL transistor can be used to form the CG transistor. For example, referring to Fig.8D In the memory device 800D, the first CG transistor 230 and the second CG transistor 240 are formed in the metallization layer M2 in the BEOL network above the first WL transistor 250 and the second WL transistor 260 formed in the FEOL network. And the first CG transistor 230 and the second CG transistor 240 are respectively selected by the front-side interconnect structure. The first CG transistor 230 and the second CG transistor 240 are respectively connected in series to the first WL transistor 250 and the second WL transistor 260 via the front-side interconnect structure.

[0108] The method 1000 proceeds to operation 1018, where a first fuse resistor and a second fuse resistor are formed in a second metallization layer of a plurality of metallization layers in a BEOL network above the first WL transistor and the second WL transistor. Fig.8D , the first fuse resistor 210 and the second fuse resistor 220 in the memory device 800D are formed in the metallization layer M3. The first fuse resistor 210 and the second fuse resistor 220 are commonly connected to the bit line BL0 via the front-side interconnect structure. Through the interconnect structure, the first fuse resistor 210 is connected between the first CG transistor 230 and BL0, and the second fuse resistor 220 is connected between the second CG transistor 240 and BL0. Fig.8D As shown, M4 metal track 862 may be implemented as part of bit line BL0.

[0109] The method 1000 proceeds to operation 1020, where a plurality of backside interconnect structures are formed according to various embodiments. After forming the back-end metal track, the substrate is flipped over, and a plurality of backside interconnect structures (e.g., BM0 track, BM1, BM3 track) are formed on the back side of the substrate. For example, after flipping the substrate, a polishing process can be performed on the back side of the substrate until the bottom surface of the epitaxial structure (e.g., the source / drain terminal formed in operation 1010) is exposed. Next, one or more dielectric layers are formed on the polished backside surface, and then backside via structures are formed, each of which can extend through the one or more dielectric layers to the bottom surface of the corresponding epitaxial structure. Next, the backside interconnect structures can be formed in the corresponding backside metallization layer.

[0110] The backside interconnect structure is formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The backside interconnect structure can be formed by covering the back side of the substrate with the above-mentioned metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating or a combination thereof.

[0111] Fig.11 1 shows an example diagram of a thin film transistor 1100 according to some embodiments. In some embodiments, as Fig.11 The thin film transistor 1100 shown can be implemented as follows Figures 8A-9C CG transistors 230 and 240 are shown. Fig.11 As shown, the thin film transistor 1100 includes a bottom gate 1116, a gate dielectric 1118 disposed on the bottom gate 1116, a channel structure 1120 disposed above the gate dielectric 1118, and a pair of source / drain structures 1122 and 1124 disposed above the channel structure 1120. The thin film transistor 1100 may be referred to as a "two-dimensional back-gate transistor" or a "2D transistor". The term "two-dimensional back-gate transistor" may refer to a transistor whose gate is formed as a relatively flat or thinner structure and whose channel structure contacts the top surface of its gate. In some embodiments, the bottom gate 1116 includes TiN, the gate dielectric 1118 includes a high-K dielectric material (such as HfO2), the channel structure 1120 includes InGaZnO (IGZO), and the source / drain structures 1122 and 1124 include TiN.

[0112] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes an array having a plurality of one-time programmable (OTP) memory cells, a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of control gate (CG) lines formed above one side of a substrate. Each OTP memory cell includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are connected to a corresponding one of the BLs, and the first transistor and the second transistor are respectively selected by the first CG line and the second CG line of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer in a plurality of metallization layers arranged on the side of the substrate.

[0113] In some embodiments, a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer of the plurality of metallization layers are formed on a side of the substrate, and wherein the first metallization layer and the second metallization layer of the plurality of metallization layers are identical to each other.

[0114] In some embodiments, a first metallization layer and a second metallization layer in the plurality of metallization layers are different from a third metallization layer or a fourth metallization layer in the plurality of metallization layers.

[0115] In some embodiments, the OTP memory cells are arranged in a plurality of columns and a plurality of rows, each row includes a corresponding one WL, and each column includes a corresponding one BL and a corresponding pair of CG lines.

[0116] In some embodiments, each OTP memory cell further includes a third transistor and a fourth transistor formed along a major surface of a side of the substrate, and wherein the third transistor and the fourth transistor are commonly gated by a corresponding one of the word lines in the WL.

[0117] In some embodiments, a first fuse resistor, a first transistor, and a third transistor are connected in series between the corresponding BL and a power rail carrying a supply voltage, and wherein a second fuse resistor, a second transistor, and a fourth transistor are connected in series between the corresponding BL and the power rail.

[0118] In some embodiments, each OTP memory cell further includes a third transistor formed along a major surface of a side of the substrate, and wherein the third transistor is gated by a corresponding one of the WLs.

[0119] In some embodiments, a first fuse resistor, a first transistor, and a third transistor are connected in series between a corresponding BL and a power rail carrying a power supply voltage, and wherein a second fuse resistor, a second transistor, and a third transistor are connected in series between the corresponding BL and the power rail.

[0120] In some embodiments, each OTP memory cell is configured to permanently assume a logic state based on whether the first fuse resistor or the second fuse resistor is randomly blown.

[0121] In some embodiments, the logic state is identified based on activating one of the first transistor or the second transistor.

[0122] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell formed on one side of a substrate. The memory cell includes a first fuse resistor, a second fuse resistor, a first transistor connected in series to the first fuse resistor, and a second transistor connected in series to the second fuse resistor. The memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state after the second fuse resistor is blown. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer among a plurality of metallization layers arranged on the side of the substrate.

[0123] In some embodiments, a first metallization layer, a second metallization layer, a third metallization layer, and a fourth metallization layer among a plurality of metallization layers are formed on a side of a substrate, wherein the first metallization layer and the second metallization layer among the plurality of metallization layers are identical to each other, and wherein the first logic state or the second logic state is used as a bit of a physically unclonable function (PUF) signature of the memory cell.

[0124] In some embodiments, the memory cell further includes: a third transistor connected in series to the first transistor; and a fourth transistor connected in series to the second transistor, wherein the third transistor and the fourth transistor are formed along a main surface of a side of the substrate.

[0125] In some embodiments, when programming the memory cell to randomly blow the first fuse resistor or the second fuse resistor, the third transistor and the fourth transistor are activated simultaneously, and the first transistor and the second transistor are activated simultaneously.

[0126] In some embodiments, when the memory cell is read to identify the first logic state or the second logic state, the third transistor and the fourth transistor are activated simultaneously, and only one of the first transistor and the second transistor is activated.

[0127] In some embodiments, the memory cell further includes: a third transistor serially connected to each of the first transistor and the second transistor, wherein the third transistor is formed along a major surface of a side of the substrate.

[0128] In some embodiments, when the memory cell is programmed to randomly blow the first fuse resistor or the second fuse resistor, the third transistor is activated, and the first transistor and the second transistor are activated simultaneously.

[0129] In some embodiments, when the memory cell is read to identify the first logic state or the second logic state, the third transistor is activated and only one of the first transistor or the second transistor is activated.

[0130] In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed. The method includes: forming a first word line transistor and a second word line transistor along a main surface of one side of a substrate; forming a first metallization layer of a plurality of metallization layers disposed on the first word line transistor and the second word line transistor, wherein the first word line transistor and the second word line transistor are commonly selected and commonly connected to a power rail; forming a second metallization layer of a plurality of metallization layers above the first metallization layer of the plurality of metallization layers; forming a first control gate transistor and a second control gate transistor in the second metallization layer of the plurality of metallization layers, wherein the first control gate transistor and the second control gate transistor are respectively selected; forming a third metallization layer of a plurality of metallization layers above the first metallization layer of the plurality of metallization layers; and forming a first fuse resistor and a second fuse resistor in the third metallization layer of the plurality of metallization layers, wherein the first fuse resistor is connected between the first control gate transistor and a bit line, and wherein the second fuse resistor is connected between the second control gate transistor and the bit line.

[0131] In some embodiments, a third metallization layer among the plurality of metallization layers is taller than the second metallization layer.

[0132] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0133] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: an array comprising a plurality of one-time programmable memory cells formed over one side of a substrate; multiple word lines; a plurality of bit lines; as well as a plurality of control gate lines; Each of the one-time programmable memory cells includes a first fuse resistor, a second fuse resistor, a first transistor and a second transistor. wherein the first fuse resistor and the second fuse resistor are connected to a corresponding one of the bit lines, and the first transistor and the second transistor are respectively selected by a first control gate line and a second control gate line of the control gate lines, and The first transistor, the second transistor, the first fuse resistor and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer and a fourth metallization layer among a plurality of metallization layers arranged on the side of the substrate.

2. The memory device according to claim 1, wherein: The first, second, third and fourth metallization layers of the plurality of metallization layers are formed on the side of the substrate, and wherein the first and second metallization layers of the plurality of metallization layers are identical to each other.

3. The memory device according to claim 2, wherein: The first metallization layer and the second metallization layer of the plurality of metallization layers are different from the third metallization layer or the fourth metallization layer of the plurality of metallization layers.

4. The memory device according to claim 1, wherein: The one-time programmable memory cells are arranged in a plurality of columns and a plurality of rows, each row includes a corresponding one of the word lines, and each column includes a corresponding one of the bit lines and a corresponding pair of the control gate lines.

5. The memory device according to claim 1, wherein: Each of the one-time programmable memory cells further includes a third transistor and a fourth transistor formed along a major surface of the side of the substrate, and wherein the third transistor and the fourth transistor are commonly gated by a corresponding one of the word lines.

6. The memory device according to claim 1, wherein: Each of the one-time programmable memory cells is configured to permanently assume a logic state based on whether the first fuse resistor or the second fuse resistor is randomly blown.

7. A memory device comprising: A memory cell is formed over one side of a substrate and includes: a first fuse resistor; a second fuse resistor; a first transistor connected in series to the first fuse resistor; and a second transistor, connected in series to the second fusing resistor, wherein the memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state when the second fuse resistor is blown, and The first transistor, the second transistor, the first fuse resistor and the second fuse resistor are respectively formed in a first metallization layer, a second metallization layer, a third metallization layer and a fourth metallization layer among a plurality of metallization layers arranged on the side of the substrate.

8. The memory device according to claim 7, wherein: The first, second, third, and fourth metallization layers of the plurality of metallization layers are formed over the side of the substrate, wherein the first and second metallization layers of the plurality of metallization layers are identical to each other, and wherein the first logic state or the second logic state is used as a bit of a physically unclonable functional signature of the memory cell.

9. The memory device according to claim 7, wherein: The memory unit further comprises: a third transistor connected in series to the first transistor; and a fourth transistor, connected in series to the second transistor, The third transistor and the fourth transistor are formed along the main surface of the side of the substrate.

10. A method for manufacturing a semiconductor device, comprising: forming a first word line transistor and a second word line transistor along a main surface of one side of the substrate; forming a first metallization layer of a plurality of metallization layers disposed over the first word line transistor and the second word line transistor, wherein the first word line transistor and the second word line transistor are commonly gated and commonly connected to a power rail; forming a second metallization layer among the plurality of metallization layers over the first metallization layer among the plurality of metallization layers; forming a first control gate transistor and a second control gate transistor in the second metallization layer among the plurality of metallization layers, wherein the first control gate transistor and the second control gate transistor are respectively turned on; forming a third metallization layer among the plurality of metallization layers over the first metallization layer among the plurality of metallization layers; and A first fuse resistor and a second fuse resistor are formed in the third metallization layer of the plurality of metallization layers, wherein the first fuse resistor is connected between the first control gate transistor and a bit line, and wherein the second fuse resistor is connected between the second control gate transistor and the bit line.

Images