Three-phase four-level neutral-point-clamped inverter and neutral-point voltage balancing control method

Abstract

The application discloses a three-phase four-level neutral-point-clamped inverter and a neutral-point voltage balance control method. The three-phase four-level neutral-point-clamped inverter comprises a direct-current power supply, three series-connected direct-current bus capacitors and twelve switch tubes. The first switch tube to the sixth switch tube constitute a chopping unit, the seventh switch tube to the twelfth switch tube constitute a three-phase bridge arm circuit, the three series-connected direct-current bus capacitors are connected with the chopping unit, the chopping unit is also connected with the input end of the three-phase bridge arm circuit, and the neutral points of each bridge arm of the three-phase bridge arm circuit are connected with three-phase alternating current ends. The three-phase four-level neutral-point-clamped inverter has the advantages of low cost, simple control and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of midpoint clamped type inverters, and in particular to a three-phase four-level midpoint clamped type inverter and a midpoint voltage balancing control method. BACKGROUND

[0002] The neutral point clamped (NPC) inverter is a kind of multi-level inverter topology widely used in medium-voltage systems such as new energy power generation, electric vehicles, rail transit, and motor drives. Compared with a three-level NPC inverter, a four-level inverter has lower total harmonic distortion and better electromagnetic compatibility; compared with a five-level NPC inverter, the four-level inverter has fewer electrolytic capacitors and power devices, and has greater advantages in cost, loss, and size. Therefore, the four-level inverter has competitiveness in industrial applications.

[0003] In existing four-level midpoint clamped type inverter topologies, at least 18 power switching tubes are used for three-phase, resulting in high cost, complex control, and reduced reliability. In recent years, multi-level topologies with reduced switching device numbers have become a new development trend due to their lower cost and higher reliability.

[0004] Midpoint voltage imbalance has always been a common problem for four-level midpoint clamped type inverters. Using a midpoint voltage balancing control strategy can ensure uniform stress distribution of power devices, reduce harmonic content in output voltage, improve voltage waveform quality, reduce interference to the power grid or load, and improve the power quality of the system, thereby meeting the higher requirements of modern power systems and industrial applications for power quality. Therefore, it is necessary to provide a four-level midpoint clamped type inverter with low cost and high reliability, and a midpoint voltage balancing control strategy. SUMMARY

[0005] The present application aims to at least partially solve the technical problems in the related art. To this end, a first object of the present application is to provide a three-phase four-level midpoint clamped type inverter with low cost, simple control, and high reliability.

[0006] A second object of the present application is to provide a midpoint voltage balancing control method.

[0007] A third object of the present application is to provide a computer-readable storage medium.

[0008] A fourth object of the present application is to provide an electronic device.

[0009] To achieve the above objects, the present application is implemented by the following technical solutions:

[0010] The application discloses a three-phase four-level neutral-point-clamped inverter, which comprises a direct-current power supply, three series-connected direct-current bus capacitors and twelve switch tubes, wherein the first switch tube to the sixth switch tube constitute a chopping unit, the seventh switch tube to the twelfth switch tube constitute a three-phase bridge arm circuit, the three series-connected direct-current bus capacitors are connected with the chopping unit, the chopping unit is also connected with the input end of the three-phase bridge arm circuit, and the neutral points of each bridge arm of the three-phase bridge arm circuit are connected with three-phase alternating current ends respectively.

[0011] Preferably, the twelve switch tubes are MOS tubes.

[0012] Preferably, the source of the first switch tube and the drain of the second switch tube are connected and have a first node, the source of the second switch tube and the drain of the fifth switch tube are connected and have a second node, and the source of the fifth switch tube and the drain of the sixth switch tube are connected and have a third node; the source of the third switch tube and the drain of the fourth switch tube are connected with the second node, the drain of the first switch tube is connected with the positive end of the first direct-current bus capacitor and the positive end of the direct-current power supply, the source of the sixth switch tube is connected with the negative end of the third direct-current bus capacitor and the negative end of the direct-current power supply, and the drain of the third switch tube and the source of the fourth switch tube are connected with the positive end and the negative end of the second direct-current bus capacitor respectively.

[0013] Preferably, in the three-phase bridge arm circuit, the source of each upper half-bridge arm switch tube of each phase is connected with the drain of a corresponding lower half-bridge arm switch tube, the drain of each upper half-bridge arm switch tube of each phase is connected with the first node, and the source of each lower half-bridge arm switch tube of each phase is connected with the third node.

[0014] To achieve the above object, the application provides a neutral-point voltage balance control method, which is applied to the three-phase four-level neutral-point-clamped inverter.

[0015] The method comprises the following steps of:

[0016] The method comprises the following steps of:

[0017] The method comprises the following steps of:

[0018] Preferably, the space vector distribution comprises six sectors.

[0019] Preferably, the second direct-current bus capacitor voltage balance control is realized based on the space vector distribution, and the method comprises the following steps of:

[0020] determining at least one switch combination in which the second DC bus capacitor is in a charging state for each sector, and determining at least one switch combination in which the second DC bus capacitor is in a discharging state;

[0021] the action time of the first vector corresponding to the sector is adjusted by the first adjustment factor and the action time of the at least one switch combination in which the second DC bus capacitor is in the charging state, and the action time of the second vector corresponding to the sector is adjusted by the first adjustment factor and the action time of the at least one switch combination in which the second DC bus capacitor is in the discharging state, so as to act on the three-phase four-level neutral-point-clamped inverter based on the adjusted action time of the first vector and the action time of the second vector, to realize the second DC bus capacitor voltage balance control.

[0022] Preferably, the first DC bus capacitor voltage and the third DC bus capacitor voltage dynamic balance control comprises:

[0023] determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a charging state for each sector, and determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a discharging state;

[0024] the action time of the charging vector corresponding to the sector is adjusted by the second adjustment factor and the action time of the at least one switch combination in which the first DC bus capacitor is in the charging state, or the action time of the at least one switch combination in which the third DC bus capacitor is in the discharging state; and

[0025] the action time of the discharging vector corresponding to the sector is adjusted by the second adjustment factor and the action time of the at least one switch combination in which the first DC bus capacitor is in the discharging state, or the action time of the at least one switch combination in which the third DC bus capacitor is in the charging state;

[0026] act on the three-phase four-level neutral-point-clamped inverter based on the adjusted action time of the charging vector and the action time of the discharging vector, to realize the first DC bus capacitor voltage and the third DC bus capacitor voltage dynamic balance control.

[0027] To achieve the above object, the third aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the above-mentioned midpoint voltage balance control method.

[0028] To achieve the above object, the fourth aspect of the present application provides an electronic device, which comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor executes the computer program to realize the above-mentioned midpoint voltage balance control method.

[0029] The present application has at least the following technical effects:

[0030] The present application provides a three-phase four-level neutral-point-clamped inverter, comprising a DC power supply, three series DC bus capacitors and twelve switching tubes, wherein the first switching tube to the sixth switching tube constitute a chopping unit, the seventh switching tube to the twelfth switching tube constitute a three-phase bridge arm circuit, the three series DC bus capacitors are connected with the chopping unit, the chopping unit is connected with the input end of the three-phase bridge arm circuit, and the neutral points of each bridge arm of the three-phase bridge arm circuit are connected with three-phase AC ends respectively, the three-phase four-level neutral-point-clamped inverter has the advantages of less switching devices, low cost, simple control and high reliability; in addition, the present application also provides a neutral-point-voltage balance control method, which can realize voltage balance control of each DC bus capacitor by using simplified space vector distribution modulation technology, and further realize neutral-point-voltage balance of the three-phase four-level neutral-point-clamped inverter.

[0031] Additional aspects and advantages of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a structure schematic diagram of the three-phase four-level neutral-point-clamped inverter of the embodiment of the present application.

[0033] Figure 2 It is a flow chart of the neutral-point-voltage balance control method of the embodiment of the present application.

[0034] Fig. 3 is an equivalent circuit diagram of six switching combinations of the embodiment of the present application.

[0035] Figure 4 It is a space vector distribution diagram of the three-phase four-level neutral-point-clamped inverter of the embodiment of the present application.

[0036] Figure 5 It is a capacitor voltage balance control principle diagram of the embodiment of the present application.

[0037] Fig. 6(a) is a DC bus capacitor voltage simulation diagram of the embodiment of the present application.

[0038] Fig. 6(b) is a phase voltage and phase current simulation diagram of the embodiment of the present application.

[0039] Fig. 6(c) is a phase current FFT simulation diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0040] The present embodiment is described in detail below, examples of which are shown in the accompanying drawings, wherein identical or similar labels denote identical or similar elements or elements having identical or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0041] A three-phase four-level neutral-point-clamped inverter and a neutral-point voltage balancing control method of the present embodiment are described below with reference to the accompanying drawings.

[0042] Figure 1 A structural schematic diagram of a three-phase four-level neutral-point-clamped inverter of the present embodiment is shown in FIG. 1. As shown in the figure, the three-phase four-level neutral-point-clamped inverter comprises a DC power supply, three series-connected DC bus capacitors C1-C3 and twelve switching tubes S1-S12. Figure 1 The twelve switching tubes are MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tubes, and can also be IGBT (Insulated Gate Bipolar Transistor) or SiC (Silicon Carbide) devices. The first switching tube S1 to the sixth switching tube S6 constitute a chopping unit, the seventh switching tube S7 to the twelfth switching tube S12 constitute a three-phase bridge arm circuit, the three series-connected DC bus capacitors are connected with the chopping unit, the chopping unit is also connected with the input end of the three-phase bridge arm circuit, and the midpoints of each bridge arm of the three-phase bridge arm circuit are connected with the A-phase, B-phase and C-phase three-phase AC ends. 12 12 The twelve switching tubes are MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tubes, and can also be IGBT (Insulated Gate Bipolar Transistor) or SiC (Silicon Carbide) devices. The first switching tube S1 to the sixth switching tube S6 constitute a chopping unit, the seventh switching tube S7 to the twelfth switching tube S12 constitute a three-phase bridge arm circuit, the three series-connected DC bus capacitors are connected with the chopping unit, the chopping unit is also connected with the input end of the three-phase bridge arm circuit, and the midpoints of each bridge arm of the three-phase bridge arm circuit are connected with the A-phase, B-phase and C-phase three-phase AC ends.

[0043] Specifically, the source of the first switching tube S1 and the drain of the second switching tube S2 are connected and have a first node, the source of the second switching tube S2 and the drain of the fifth switching tube S5 are connected and have a second node, and the source of the fifth switching tube S5 and the drain of the sixth switching tube S6 are connected and have a third node; the source of the third switching tube S3 and the drain of the fourth switching tube S4 are both connected with the second node, the drain of the first switching tube S1 is connected with the positive end of the first DC bus capacitor C1 and the positive end of the DC power supply, the source of the sixth switching tube S6 is connected with the negative end of the third DC bus capacitor C3 and the negative end of the DC power supply, and the drain of the third switching tube S3 and the source of the fourth switching tube S4 are respectively connected with the positive end and the negative end of the second DC bus capacitor C2.

[0044] In the three-phase bridge arm circuit, the source of each upper half-bridge arm switching tube is connected with the drain of the corresponding lower half-bridge arm switching tube, the drain of each upper half-bridge arm switching tube such as S7, S9 and S11 is connected with the first node, and the source of each lower half-bridge arm switching tube such as S8, S10 and S12 is connected with the third node. 11 10 12

[0045] In the present embodiment, the three-phase bridge arm circuit shares one chopping unit, and different switching combinations can generate 0, U / 2 and U.​​​​dc / 3, 2U dc / 3 and U dc four levels, U dc is a DC bus voltage. The three-phase four-level neutral-point-clamped inverter proposed in this embodiment has only 12 power switching tubes and can output four levels, and has the advantages of fewer switching devices, low cost, simple control and high reliability.

[0046] Figure 2 is a flowchart of the neutral-point voltage balance control method of the embodiment of the application. As shown in the figure, the method comprises: Figure 2

[0047] S101: Obtain a plurality of switching combinations of the three-phase four-level neutral-point-clamped inverter, and divide the plurality of switching combinations into four vectors.

[0048] S102: Obtain the spatial vector distribution of the three-phase four-level neutral-point-clamped inverter based on the plurality of switching combinations in the four vectors.

[0049] S103: Realize second DC bus capacitor voltage balance control and first DC bus capacitor voltage and third DC bus capacitor voltage dynamic balance control based on the spatial vector distribution, so as to realize neutral-point voltage balance control.

[0050] In this embodiment, all switching states of the three-phase four-level neutral-point-clamped inverter topology are shown in Table 1, wherein the switching combination represents the corresponding switching conduction, and the plurality of switching combinations are divided into four vectors, i.e., 0 vector-4 vector.

[0051] Table 1: Switching state table of three-phase four-level neutral-point-clamped inverter topology

[0052]

[0053]

[0054] Figure 3 is an equivalent circuit diagram of six switching combinations, which is described in detail as follows:

[0055] As shown in Figure 3(a), the second switching tube S2, the fourth switching tube S4, the fifth switching tube S5, the seventh switching tube S7, the tenth switching tube S 10 and the twelfth switching tube S 12 are turned on, obtaining the 0 vector switching state 111a, in which no current flows, and the first DC bus capacitor C1, the second DC bus capacitor C2 and the third DC bus capacitor C3 are not affected.

[0056] As shown in Figure 3(b), the second switching tube S2, the fourth switching tube S4, the sixth switching tube S6, the seventh switching tube S7, the tenth switching tube S 10 ​and the twelfth switch S 12 is turned on, obtaining a 1 -vector switch state 100. When the neutral point current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged; when the neutral point current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0057] As shown in FIG. 3(c), the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the tenth switch S 10 and the twelfth switch S 12 is turned on, obtaining a 1 -vector switch state 100. When the neutral point current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged; when the neutral point current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0058] As shown in FIG. 3(c), the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the tenth switch S 10 and the twelfth switch S 12 is turned on, obtaining a 1 -vector switch state 100. When the neutral point current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged; when the neutral point current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0059] As shown in FIG. 3(c), the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the tenth switch S 10 and the twelfth switch S 12 is turned on, obtaining a 1 -vector switch state 100. When the neutral point current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged; when the neutral point current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0060] As shown in FIG. 3(c), the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the tenth switch S 10 and the twelfth switch S 12 is turned on, obtaining a 1 -vector switch state 100. When the neutral point current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged; when the neutral point current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0061] Figure 4The space vector distribution of the three-phase four-level neutral point clamped inverter is shown, and the space vector distribution includes six sectors. Figures 3(a)-3(f) From the analysis, it can be known that the first DC bus capacitor C1 to the third DC bus capacitor C3 are only charged and discharged under the 1 vector and the 2 vector, and the 0 vector and the 3 vector have no influence on the neutral point current.

[0062] Based on this, the second DC bus capacitor voltage balance control is realized based on the space vector distribution, including: for each sector, determining at least one switching combination in which the second DC bus capacitor C2 is in a charging state, and determining at least one switching combination in which the second DC bus capacitor C2 is in a discharging state; adjusting the action time of the first vector, i.e., the 1 vector, corresponding to the sector through the first adjustment factor k and the action time of the at least one switching combination in which the second DC bus capacitor C2 is in the charging state, and adjusting the action time of the second vector, i.e., the 2 vector, corresponding to the sector through the first adjustment factor k and the action time of the at least one switching combination in which the second DC bus capacitor C2 is in the discharging state, so as to realize the second DC bus capacitor voltage balance control based on the adjusted action time of the first vector and the second vector acting on the three-phase four-level neutral point clamped inverter.

[0063] Taking sector I as an example, the second DC bus capacitor C2 is charged under the switching states 100, 110, 322 and 332, and is discharged under the switching states 200, 220, 311 and 331. Therefore, the first adjustment factor k is introduced to redistribute the action time of the 1 vector and the 2 vector, so as to adjust the charging and discharging time of the second DC bus capacitor C2. The action time of the 1 vector and the 2 vector after the distribution is shown in formula (1):

[0064]

[0065] Wherein, T 1矢量 , T 2矢量 represent the action time of the 1 vector and the 2 vector respectively, T 100 , T 110 , T 322 , T 332 , T 200 , T 220 , T 311 , T 331 represent the action time of the switching states 100, 110, 322, 332, 200, 220, 311 and 331 respectively. The adjusted action time of the 1 vector and the 2 vector acting on the three-phase four-level neutral point clamped inverter can realize the second DC bus capacitor voltage balance control.

[0066] For sector II, the second DC bus capacitor C2 charges in switching states 110, 010, 332 and 232, and discharges in switching states 220, 020, 331 and 131. To this end, a first adjustment factor k can be introduced to redistribute the action time of the 1-vector and 2-vector of sector II, so as to adjust the charging and discharging time of the second DC bus capacitor C2.

[0067] In an embodiment of the present application, the dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage comprises:

[0068] For each sector, at least one switching combination in which the first DC bus capacitor C1 or the third DC bus capacitor C3 is in a charging state is determined, and at least one switching combination in which the first DC bus capacitor C1 or the third DC bus capacitor C3 is in a discharging state is determined; the action time of the charging vector of the corresponding sector is adjusted by a second adjustment factor s and the action time of the at least one switching combination in which the first DC bus capacitor C1 is in a charging state, or the action time of the at least one switching combination in which the third DC bus capacitor C3 is in a discharging state; and the action time of the discharging vector of the corresponding sector is adjusted by the second adjustment factor s and the action time of the at least one switching combination in which the first DC bus capacitor C1 is in a discharging state, or the action time of the at least one switching combination in which the third DC bus capacitor C3 is in a charging state; and the three-phase four-level neutral-point-clamped inverter is acted on based on the adjusted action time of the charging vector and the action time of the discharging vector, so as to achieve the dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage.

[0069] Under ideal conditions, the charging and discharging currents of the first DC bus capacitor C1 and the third DC bus capacitor C3 are the same, and balance can be maintained. However, in actual conditions, factors such as the capacitance value, the internal resistance of the electrolytic capacitor, and the oscillation frequency of the capacitor voltage need to be considered, and appropriate control still needs to be applied. It should be noted that the three DC bus capacitors are all electrolytic capacitors.

[0070] Taking sector I as an example, the first DC bus capacitor C1 charges in switching states 100, 110, 200 and 220, and discharges in switching states 322, 332, 311 and 331; and the third DC bus capacitor C3 discharges in switching states 100, 110, 200 and 220, and charges in switching states 322, 332, 311 and 331. In order to maintain the balance of the upper capacitor C1 and the lower capacitor C3, a second adjustment factor s is introduced to allocate the action time of the charging vector and the discharging vector of these switching redundant states, and the allocated action time of the charging vector and the discharging vector is shown in formula (2):

[0071]

[0072] Wherein, T1, T2 are the action time of the charging vector and the discharging vector respectively. The action time of the adjusted charging vector and the action time of the discharging vector are applied to the three-phase four-level neutral point clamped inverter, so that the first DC bus capacitor voltage and the third DC bus capacitor voltage dynamic balance control can be realized, the three-capacitor balance control can be realized, and the neutral point voltage balance control of the three-phase four-level neutral point clamped inverter can be realized.

[0073] Figure 5 The capacitor voltage balance control principle is given. The voltage U C1 and U C3 of the first DC bus capacitor C1 and the third DC bus capacitor C3 are taken as the PI (proportional integral) controller input, the second adjustment factor s is controlled in real time, and the dynamic balance of the upper and lower capacitor voltages is maintained. The voltage U C2 and U dc of the second DC bus capacitor C2 are taken as the PI controller input, the first adjustment factor k is maintained near 1 / 2, and thus the second DC bus capacitor C2 balance control is realized.

[0074] In order to demonstrate the feasibility of the three-phase four-level neutral point clamped inverter topology, a simulation model is built according to the simulation parameters in Table 2, and the simulation results are shown in Figures 6(a)-6(c) .

[0075] Table 2 Simulation model parameter table

[0076]

[0077] In the simulation, the initial voltages of the three DC bus capacitors are 400V. As can be seen from Fig. 6(a), when the traditional carrier layer superposition modulation technology is used, the first DC bus capacitor C1 and the third DC bus capacitor C3 are continuously charged, the second DC bus capacitor C2 is continuously discharged, and the three DC bus capacitors cannot realize self-balance. When the capacitor voltage balance control algorithm is added at t=1s, the three DC bus capacitor voltages reach U dc / 3, and dynamic balance is achieved. Fig. 6(b) shows the simulation results of the phase voltage and the phase current, and the phase voltage contains 0, U dc / 3, 2U dc / 3 and U dc four levels. Fig. 6(c) shows the simulation results of the phase current FFT (fast Fourier transform), and the total harmonic distortion rate of the current is 2.34%. The simulation results prove the feasibility of the three-phase four-level neutral point clamped inverter topology of the embodiment.

[0078] Further, the application also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the above-mentioned neutral point voltage balance control method.

[0079] Further, the present application also provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the midpoint voltage balance control method when executing the computer program.

[0080] It should be noted that the relationship terms, such as first and second, and the like, are used herein merely to distinguish one entity or action from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or actions. In addition, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0081] Although the content of the present application has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present application. After reading the above content, various modifications and alternatives of the present application will be apparent to those skilled in the art. Therefore, the protection scope of the present application should be defined by the appended claims.

Claims

1. A three-phase four-level neutral-point clamping inverter, characterized in that, include: The circuit consists of a DC power supply, three DC bus capacitors connected in series, and twelve switching transistors. The first to sixth switching transistors form a chopper unit, and the seventh to twelfth switching transistors form a three-phase bridge arm circuit. The three DC bus capacitors connected in series are connected to the chopper unit, and the chopper unit is also connected to the input terminal of the three-phase bridge arm circuit. The midpoint of each bridge arm of the three-phase bridge arm circuit is connected to the three-phase AC terminal. The source of the first switching transistor and the drain of the second switching transistor are connected and have a first node; the source of the second switching transistor and the drain of the fifth switching transistor are connected and have a second node; the source of the fifth switching transistor and the drain of the sixth switching transistor are connected and have a third node; the source of the third switching transistor and the drain of the fourth switching transistor are both connected to the second node; the drain of the first switching transistor is connected to the positive terminal of the first DC bus capacitor and the positive terminal of the DC power supply; the source of the sixth switching transistor is connected to the negative terminal of the third DC bus capacitor and the negative terminal of the DC power supply; the drain of the third switching transistor and the source of the fourth switching transistor are respectively connected to the positive and negative terminals of the second DC bus capacitor. In a three-phase bridge arm circuit, the source of the upper half-bridge arm switch of each phase is connected to the drain of the corresponding lower half-bridge arm switch, the drain of the upper half-bridge arm switch of each phase is connected to the first node, and the source of the lower half-bridge arm switch of each phase is connected to the third node.

2. The three-phase four-level neutral-point clamping inverter as described in claim 1, characterized in that, All twelve switching transistors are MOSFETs.

3. A method for controlling midpoint voltage balance, characterized in that, Applied to a three-phase four-level neutral-point clamping inverter as described in claim 1 or 2, the method includes: Obtain multiple switching combinations of a three-phase four-level neutral-point clamped inverter and divide the multiple switching combinations into four vectors; The spatial vector distribution of a three-phase four-level neutral-point clamped inverter is obtained based on multiple switch combinations in four vectors. Based on the aforementioned spatial vector distribution, the voltage balance control of the second DC bus capacitor and the dynamic balance control of the voltage of the first DC bus capacitor and the voltage of the third DC bus capacitor are realized, so as to achieve midpoint voltage balance control.

4. The midpoint voltage balance control method as described in claim 3, characterized in that, The spatial vector distribution comprises six sectors.

5. The midpoint voltage balance control method as described in claim 4, characterized in that, The second DC bus capacitor voltage balance control is achieved based on the aforementioned space vector distribution, including: For each sector, determine at least one switch combination in which the second DC bus capacitor is in a charging state, and determine at least one switch combination in which the second DC bus capacitor is in a discharging state. The duration of the first vector in the corresponding sector is obtained by adjusting the duration of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a charging state, and the duration of the second vector in the corresponding sector is obtained by adjusting the duration of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a discharging state. This allows the voltage balance control of the second DC bus capacitor to be achieved by applying the adjusted durations of the first and second vectors to the three-phase four-level neutral point clamping inverter.

6. The midpoint voltage balance control method as described in claim 5, characterized in that, Dynamic balance control of the voltages of the first and third DC bus capacitors includes: For each sector, determine at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a charging state, and determine at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a discharging state. The duration of the corresponding sector charging vector is adjusted by the duration of at least one switching combination when the second adjustment factor and the first DC bus capacitor are in a charging state, or the duration of at least one switching combination when the third DC bus capacitor is in a discharging state; and The duration of the discharge vector of the corresponding sector is obtained by adjusting the duration of the second adjustment factor and at least one switch combination in the discharge state of the first DC bus capacitor, or the duration of the third DC bus capacitor in the charging state of the switch combination. The adjusted charging vector and discharging vector are applied to the three-phase four-level neutral point clamping inverter to achieve dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the midpoint voltage balance control method as described in any one of claims 3-6.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the midpoint voltage balance control method as described in any one of claims 3-6.

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