Output stage structure of rail-to-rail operational amplifier and rail-to-rail operational amplifier

Abstract

The invention provides an output stage structure of a rail-to-rail operational amplifier and the rail-to-rail operational amplifier. The output stage structure comprises a current adder, a floating current source and a Class AB output stage, the current adder is used for integrating and amplifying differential current signals of the input stage of the rail-to-rail operational amplifier and converting the differential current signals into input signals of the Class AB output stage; the floating current source is used for providing static bias for the Class AB output stage and controlling the power consumption of the Class AB output stage; the floating current source is provided with a high-order effect suppression structure, and the high-order effect suppression structure is used for suppressing the high-order effect of the floating current source.

Description

Technical Field

[0001] The present invention relates to the technical field of operational amplifiers, and in particular to an output stage structure of a rail-to-rail operational amplifier and a rail-to-rail operational amplifier. Background Art

[0002] Rail-to-rail operational amplifiers are a type of circuit with a wide input and output voltage range and high gain, and are widely used in various power electronic systems. With the rise of portable and wearable devices, the demand for low power circuits is increasing day by day. Portable devices such as smart watches need to use low-power rail-to-rail operational amplifiers to build more complex instrumentation amplifiers, which can amplify sensor signals and suppress common-mode noise while maintaining long working time. At a reasonable power supply voltage, they can output signals that match the input range of the subsequent analog-to-digital converter to the greatest extent possible to give full play to their performance. Therefore, low-power rail-to-rail operational amplifiers have received widespread attention in both academia and industry.

[0003] The output stage of a low-power rail-to-rail operational amplifier often adopts a Class AB structure, which has higher energy utilization efficiency than the Class A structure and stronger dynamic driving capability than the Class B structure. In order to control the static operating point of the Class AB output stage, a floating current source structure is often used to adjust the static current of the Class AB output stage through a linear transconductance loop, reduce power supply sensitivity, and achieve lower static power consumption. However, since operational amplifiers are often used under closed-loop conditions, the static operating point of the output stage of the operational amplifier will change with different application loads and fluctuations in process and temperature. Due to the Class AB structure biased by a floating current source, its gain will first increase and then decrease with the increase of the output static voltage, which will lead to a decrease in gain performance under heavy loads and distortion of large input signals, which will have an adverse effect on the application of operational amplifiers. Summary of the invention

[0004] In view of the above problems, the present invention provides an output stage structure of a rail-to-rail operational amplifier and a rail-to-rail operational amplifier.

[0005] According to a first aspect of the present invention, there is provided an output stage structure of a rail-to-rail operational amplifier, comprising: a current adder, a floating current source and a Class AB output stage; the current adder is used to integrate and amplify the current signal of the input stage of the rail-to-rail operational amplifier, and convert it into an input signal of the Class AB output stage; the floating current source is used to provide a static bias for the Class AB output stage and control the power consumption of the Class AB output stage; the floating current source is configured with a high-order effect suppression structure, and the high-order effect suppression structure is used to suppress the high-order effects of the floating current source.

[0006] According to an embodiment of the present invention, the floating current source includes a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube is connected to the drain and gate of the second NMOS tube; the first NMOS tube and the second NMOS tube are isolation devices, the substrate of the first NMOS tube is short-circuited with the source of the first NMOS tube, and the substrate of the second NMOS tube is short-circuited with the source of the second NMOS tube to form a high-order effect suppression structure, and the substrate is an independent well for providing a potential separately.

[0007] According to an embodiment of the present invention, the floating current source also includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a third NMOS tube, a first current source and a second current source; the source of the third PMOS tube is connected to the positive input voltage, the gate and drain of the third PMOS tube are connected to the source of the second PMOS tube, the gate and drain of the second PMOS tube are connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the first PMOS tube is connected to the source and substrate of the first NMOS tube, the source and substrate of the second NMOS tube are connected to the drain and gate of the third NMOS tube, and the source of the third NMOS tube is grounded; the positive electrode of the first current source is connected to the positive input voltage, the negative electrode is connected to the gate of the first NMOS tube and the drain and gate of the second NMOS tube, the gate and drain of the second PMOS tube and the gate of the first PMOS tube are connected to the positive electrode of the second current source, and the negative electrode of the second current source is grounded.

[0008] According to an embodiment of the present invention, the bias voltage of the floating current source is zero.

[0009] According to an embodiment of the present invention, the current adder includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube; the drain of the fourth PMOS tube is connected to the source of the first PMOS tube and the drain of the first NMOS tube, the source of the fourth PMOS tube is connected to the drain of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the positive input voltage, the gate of the fourth PMOS tube is connected to the gate of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the seventh PMOS tube, the source of the sixth PMOS tube is connected to the drain of the seventh PMOS tube, and the source of the seventh PMOS tube is connected to the positive input voltage. voltage, the drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the gate of the first PMOS tube and the drain and gate of the second PMOS tube; the drain of the eighth PMOS tube is connected to the drain of the sixth NMOS tube and the gate of the seventh NMOS tube, the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the seventh NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the first PMOS tube and the source and substrate of the first NMOS tube, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube is grounded.

[0010] According to an embodiment of the present invention, the Class AB output stage includes an output stage PMOS tube and an output stage NMOS tube; the source of the output stage PMOS tube is connected to the positive input voltage, the gate of the output stage PMOS tube is connected to the drain of the fourth PMOS tube, the source of the first PMOS tube and the drain of the first NMOS tube, the drain of the output stage PMOS tube is connected to the drain of the output stage NMOS tube, the gate of the output stage NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the first PMOS tube and the source and substrate of the first NMOS tube, and the source of the output stage NMOS tube is grounded.

[0011] According to an embodiment of the present invention, it also includes: a first capacitor and a second capacitor, which constitute a Miller compensation capacitor; the first end of the first capacitor is connected to the gate of the output stage PMOS tube, the drain of the fourth PMOS tube, the source of the first PMOS tube and the drain of the first NMOS tube, the second end of the first capacitor is connected to the second end of the second capacitor, the second end of the first capacitor and the second end of the second capacitor are connected to the drain of the output stage PMOS tube and the drain of the output stage NMOS tube, and the first end of the second capacitor is connected to the gate of the output stage NMOS tube, the drain of the fourth NMOS tube, the drain of the first PMOS tube, the source and substrate of the first NMOS tube.

[0012] According to an embodiment of the present invention, the static current of the output stage is controlled by a first linear transconductance loop and a second linear transconductance loop, the first linear transconductance loop is composed of an output stage PMOS tube, a first PMOS tube, a second PMOS tube, and a third PMOS tube, and the first linear transconductance loop is composed of an output stage NMOS tube, a first NMOS tube, a second NMOS tube, and a third NMOS tube.

[0013] According to a second aspect of the present invention, there is provided a rail-to-rail operational amplifier, comprising: an input stage for converting an input differential voltage signal into a differential current signal; and an output stage structure as described above, the output stage structure being used to process the differential current signal to achieve rail-to-rail output.

[0014] According to an embodiment of the present invention, it also includes: a transconductor, the source of the fourth PMOS tube and the drain of the fifth PMOS tube are connected to the first end of the transconductor, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected to the second end of the transconductor; the source of the sixth PMOS tube and the drain of the seventh PMOS tube are connected to the third end of the transconductor; the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected to the fourth end of the transconductor; the fifth end and the sixth end of the transconductor are connected to a pair of differential voltage signals; the transconductor is used to convert a pair of differential voltage signals into two pairs of differential current signals.

[0015] The output stage structure of the rail-to-rail operational amplifier and the rail-to-rail operational amplifier provided by the present invention have at least the following technical effects:

[0016] By improving the floating current source and setting a high-order effect suppression structure, the gain can be kept stable under different loads and different operating points. At the same time, it can work in a wider power supply voltage range, suppress the influence of high-order effects on the gain, and thus effectively suppress the gain nonlinearity of closed-loop applications and alleviate the distortion problem in signal processing. The structure is simple, and stable gain at different operating points can be achieved without consuming additional power consumption, without sacrificing power consumption, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A structural diagram of a rail-to-rail operational amplifier according to an embodiment of the present invention is shown;

[0019] Figure 2 A structural diagram of an output stage of a rail-to-rail operational amplifier according to an embodiment of the present invention is shown;

[0020] Figure 3A diagram schematically shows a change in drain current and output impedance as drain-source voltage changes, taking a 5V NMOS device at a 0.18 μm process node as an example according to an embodiment of the present disclosure;

[0021] Figure 4 Schematically showing a small signal model affected by the SCBE effect according to an embodiment of the present disclosure: (a) the substrate is connected to the ground; (b) the substrate is connected to the source end;

[0022] Figure 5 The gain comparison result diagram of the traditional structure and the output stage structure of the embodiment of the present disclosure at different static operating points of the output node is schematically shown. DETAILED DESCRIPTION

[0023] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0025] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0027] Figure 1 A structural diagram of a rail-to-rail operational amplifier according to an embodiment of the present invention is shown.

[0028] like Figure 1As shown, it includes: an input stage for converting an input differential voltage signal into a differential current signal; and an output stage structure of a rail-to-rail operational amplifier for processing the converted differential current signal to achieve rail-to-rail output.

[0029] The output stage structure of the rail-to-rail operational amplifier includes: a current adder, a floating current source, and a Class AB output stage.

[0030] The current adder is used to integrate and amplify the current signal of the input stage of the rail-to-rail operational amplifier and convert it into the input signal of the Class AB output stage.

[0031] The floating current source is used to provide a static bias for the Class AB output stage and to control the power consumption of the Class AB output stage; the floating current source is configured with a high-order effect suppression structure, and the high-order effect suppression structure is used to suppress the high-order effect of the floating current source.

[0032] Through the output stage structure of the rail-to-rail operational amplifier of the embodiment of the present disclosure, stable gain at different operating points can be achieved without consuming additional power consumption, and the range of the power supply operating voltage can be improved, thereby effectively suppressing the gain nonlinearity of closed-loop applications and alleviating distortion problems in signal processing.

[0033] Figure 2 A structural diagram of an output stage of a rail-to-rail operational amplifier according to an embodiment of the present invention is shown.

[0034] like Figure 2 As shown, in some embodiments, the floating current source includes a first NMOS transistor M N1 and the second NMOS tube M N2 , the first NMOS tube M N1 The gate of the second NMOS tube M N2 The drain and gate of

[0035] The first NMOS tube M N1 and the second NMOS tube M N2 The first NMOS tube M is an isolation device. N1 The substrate and the first NMOS tube M N1 The source of the second NMOS tube M is short-circuited. N2 The substrate and the second NMOS tube M N2 The source is short-circuited to form a high-order effect suppression structure. The substrate is an independent well used to provide a potential separately. At the same time, adjusting the appropriate channel length can play a role in suppressing high-order effects, thereby achieving gain stability under different output load conditions.

[0036] In some other embodiments, the floating current source further includes a first PMOS transistor M P1 , the second PMOS tube MP2 , the third PMOS tube M P3 , the third NMOS tube M N3 , a first current source I1 and a second current source I2.

[0037] The third PMOS tube M P3 The source of the third PMOS tube M is connected to the positive input voltage VDD. P3 The gate and drain of the second PMOS tube M P2 The source of the second PMOS tube M P2 The gate and drain of the first PMOS tube M are connected P1 The gate of the first PMOS tube M P1 The source of the first NMOS tube M N1 The drain of the first PMOS tube M P1 The drain of the first NMOS tube M N1 The source and substrate of the second NMOS tube M N2 The source and substrate of the third NMOS tube M are connected N3 The drain and gate of the third NMOS tube M N3 The source of the first current source I1 is grounded; the positive electrode is connected to the positive input voltage, and the negative electrode is connected to the first NMOS tube M N1 The gate of the second NMOS tube M N2 The drain and gate of the second PMOS tube M P2 The gate and drain of the first PMOS tube M P1 The gate of is connected to the positive electrode of the second current source I2, and the negative electrode of the second current source I2 is grounded GND.

[0038] In some other embodiments, the bias voltage of the floating current source is zero.

[0039] Continue reading Figure 2 In some embodiments, the current adder includes a fourth PMOS transistor M P4 , the fifth PMOS tube M P5 , the sixth PMOS tube M P6 , the seventh PMOS tube M P7 , the eighth PMOS tube M P8 , the fourth NMOS tube M N4 , the fifth NMOS tube M N5 , the sixth NMOS tube M N6 , the seventh NMOS tube M N7 .

[0040] The fourth PMOS tube M P4 The drain of the first PMOS tube M P1 The source and the first NMOS tube M N1The drain of the fourth PMOS tube M P4 The source of the fifth PMOS tube M P5 The drain of the fifth PMOS tube M P5 The source of the fourth PMOS tube M is connected to the positive input voltage. P4 The gate of the sixth PMOS tube M P6 The gate of the fifth PMOS tube M P5 The gate of the seventh PMOS tube M P7 The gate of the sixth PMOS tube M P6 The source of the seventh PMOS tube M P7 The drain of the seventh PMOS tube M P7 The source of the sixth PMOS tube M is connected to the positive input voltage. P6 The drain of the eighth PMOS tube M P8 The source of the eighth PMOS tube M P8 The gate of the first PMOS tube M P1 The gate and the second PMOS tube M P2 of the drain and gate.

[0041] The eighth PMOS tube M P8 The drain of the sixth NMOS tube M N6 The drain of the seventh NMOS tube M N7 The gate of the sixth NMOS tube M N6 The source of the seventh NMOS tube M N7 The drain of the seventh NMOS tube M N7 The source of the sixth NMOS tube M is grounded. N6 The gate of the fourth NMOS tube M N4 The gate of the seventh NMOS tube M N7 The gate of the fifth NMOS tube M N5 The gate of the fourth NMOS tube M N4 The drain of the first PMOS tube M P1 The drain and the first NMOS tube M N1 The source and substrate of the fourth NMOS tube M N4 The source of the fifth NMOS tube M is connected N5 The drain of the fifth NMOS tube M N5 The source is grounded.

[0042] In some other embodiments, the input stage structure may include: a transconductor GM, a fourth PMOS transistor M P4 The source and the fifth PMOS tube M P5 The drain of the fourth NMOS tube M N4 The source of the fifth NMOS tube M N5The drain of the sixth PMOS tube M P6 The source and the seventh PMOS tube M P7 The drain of the sixth NMOS tube M is connected to the third end of the transconductor GM; P6 The source of the seventh NMOS tube M P7 The drain of the transconductor GM is connected to the fourth terminal; the fifth and sixth terminals of the transconductor GM are connected to a pair of differential voltage signals V N 、V P The transconductance GM converts a pair of differential voltage signals V N 、V P Converted into two pairs of differential current signals.

[0043] Continue reading Figure 2 In some embodiments, the Class AB output stage includes an output stage PMOS transistor M P0 And output stage NMOS tube M N0 .

[0044] Output stage PMOS tube M P0 The source of the output stage is connected to the positive input voltage, and the output stage PMOS tube M P0 The gate of the fourth PMOS tube M P4 The drain of the first PMOS tube M P1 The source and the first NMOS tube M N1 The drain of the output stage PMOS tube M P0 The drain of the output stage NMOS tube M N0 The drain of the output stage NMOS tube M N0 The gate of the fourth NMOS tube M N4 The drain of the first PMOS tube M P1 The drain and the first NMOS tube M N1 The source and substrate of the output stage NMOS tube M N0 The source is grounded.

[0045] In some other embodiments, the output stage structure further includes: a first capacitor C1 and a second capacitor C2, which constitute a Miller compensation capacitor. The first end of the first capacitor C1 is connected to the output stage PMOS transistor M P0 The gate of the fourth PMOS tube M P4 The drain of the first PMOS tube M P1 The source and the first NMOS tube M N1 The drain of the first capacitor C1 is connected to the second end of the second capacitor C2, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to the output stage PMOS tube M P0 The drain and output stage NMOS tube M N0 The drain of the second capacitor C2 is connected to the output stage NMOS tube MN0 The gate of the fourth NMOS tube M N4 The drain of the first PMOS tube M P1 The drain and the first NMOS tube M N1 source and substrate.

[0046] In some other embodiments, the quiescent current of the output stage is controlled by a first linear transconductance loop and a second linear transconductance loop. The first linear transconductance loop is composed of the output stage PMOS transistor M. P0 , the first PMOS tube M P1 , the second PMOS tube M P2 , the third PMOS tube M P3 The first linear transconductance loop is composed of the output stage NMOS tube M N0 , the first NMOS tube M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 constitute.

[0047] In order to more clearly illustrate the advantages of the rail-to-rail operational amplifier and the output stage structure of the rail-to-rail operational amplifier provided by the embodiments of the present disclosure, the following will continue to refer to Figure 2 , the principle is explained in detail. In order to simplify the description, each device is represented by its number below.

[0048] When the output quiescent operating point is half the power supply voltage, the floating current source M P1 With M N1 All work normally. At this time, the floating current source is approximately short-circuited for the AC signal, and its open-loop gain A VO The expression is:

[0049] (1)

[0050] where GM is the transconductance of the rail-to-rail input stage; r Ap With r Bn They are the small signal impedances from point A to the power supply and from point B to the ground, as shown in the formula With As shown; R L Indicates load resistance; g m , g mb 、r o They represent the transconductance of the MOS transistor, the transconductance caused by the bias effect, and the output impedance respectively, and the subscripts represent the corresponding transistor numbers.

[0051] (2)

[0052] (3)

[0053] If the output drives a heavy load, the output quiescent point is close to the power supply voltage or ground. P0 It needs to be in the saturation region to reach the current level that can drive heavy loads, so M at point A P0 The gate voltage of M is reduced due to external feedback, which forces M P1 Cutoff. Since the flow through M P4 All current flows through M N1 , so M at point B N1 The source voltage drops, causing M N0 In the cut-off region, the open-loop gain A VO for:

[0054] (4)

[0055] where r An is the small signal impedance from point A to ground, as shown in the formula As shown:

[0056] (5)

[0057] Pass-through With When r An When is large enough, the gain at both quiescent operating points is of the same order of magnitude. However, when the output quiescent operating point is close to the supply voltage, the voltage across the floating current source is as follows: If the system application requires a power supply potential close to the device nominal voltage, then M P1 or M N1 The output impedance will be reduced due to higher-order effects such as the Drain-Induced Barrier Lowering (DIBL) effect, resulting in r An In addition, due to the M N1 The substrate of the MOSFET is often connected to the ground, so due to the influence of the substrate bias effect, there will be worse gain nonlinearity.

[0058] (6)

[0059] For operational amplifiers, the power consumption is mainly reflected in the quiescent current. In order to meet the demand for low power consumption, it is necessary to reduce the quiescent current, such as I1 and I2. At this time, M P1 and M N1 The gate-source voltage V gs Close to the threshold voltage V th , so M P1 and M N1When it is in the subthreshold region during normal operation, its basic current expression is as follows: As shown:

[0060] (7)

[0061] Where μ represents the channel carrier mobility, C ox It represents the gate oxide capacitance per unit area. W and L represent the channel width and channel length of the transistor respectively. V T represents the thermoelectric potential, η represents the subthreshold factor, V th is the threshold voltage of the transistor, Middle and V ds The related term characterizes the channel length modulation effect (CLM). In the subthreshold region, It can be expressed as The form shown:

[0062] (8)

[0063] Where γ is the background factor, 2Φ B is the surface potential in inversion, V sbn1 M N1 The voltage difference between the source and substrate. The output impedance of the MOSFET is r on1 The size is related to the static bias point and will be affected by factors such as channel length modulation, drain-induced barrier lowering (DIBL), and substrate current induced body effect (SCBE).

[0064] Figure 3 The diagram schematically shows the change of drain current and output impedance with the change of drain-source voltage, taking a 5V NMOS device at a 0.18 μm process node as an example according to an embodiment of the present disclosure.

[0065] like Figure 3 As shown in the figure, according to the influencing factors, it is mainly divided into four areas, namely linear region influence, CLM influence, DIBL influence and SCBE influence.

[0066] Since the floating current source bears a large voltage when working, its drain-source voltage is much larger than 4 times the thermoelectric potential V T , according to the formula The channel length modulation effect can be ignored; when driving heavy loads, the quiescent operating point of the output node is close to the power supply voltage or ground, M N1 or M P1It will bear most of the power supply voltage and will be affected by the DIBL effect and SCBE effect, resulting in a decrease in output impedance and open-loop gain.

[0067] Taking the static operating point of the output node close to the power supply voltage as an example, in the area where the DIBL effect plays a major role, M N1 The output impedance can be expressed as The DIBL effect shown in the Early voltage V ADIBLn1 Characterization, V ADIBLn1 Characterization M N1 The intersection of the tangent line at the static bias point in the output characteristic curve and the drain-source voltage on the horizontal axis. Therefore, the formula It can be further expressed as The form shown, V ADIBLn1 The size of r will directly affect An The numerical value of .

[0068] (9)

[0069] (10)

[0070] DIBL effect Early voltage V ADIBLn1 The expression is as follows As shown:

[0071] (11)

[0072] Where V gstn1 is the overdrive voltage, expressed as As shown; A bulk is the body charge effect factor, characterizing the V dsn1 The impact of channel charge non-uniformity on threshold voltage; θ rout (L) is the formula The factors related to the channel length L are shown.

[0073] (12)

[0074] (13)

[0075] Where P DIBLC1 , P DIBLC2 With D ROUT is the coefficient related to the DIBL effect in the saturation region, l t is the characteristic length, and its expression is as follows As shown:

[0076] (14)

[0077] Among them, εSi With ε ox are the relative dielectric constants of Si and SiO2, T ox is the gate oxide thickness, N CH is the channel charge concentration, X dep is the depletion layer width, which is related to the surface potential Φ S and the bias voltage V bsn1 Related, such as As shown:

[0078] (15)

[0079] By ~ It can be seen that the Early voltage V caused by the DIBL effect ADIBL and the bias voltage V bsn1 Strongly related to the channel length L, the bias voltage V bsn1 The smaller the absolute value, the greater the Early voltage V in this area. ADIBLn1 The higher the voltage, the more isolated the NMOS device is. Therefore, an isolated NMOS device is used to replace the original ordinary NMOS so that its substrate potential can be independently led out, V bsn1 The absolute value can be less than the original 2V gst ; Since the parasitic diode between the source and the substrate needs to avoid forward bias, that is, V bsn1 ≤0, so connecting the substrate and source of the isolated NMOS can get a higher V ADIBLn1 , thereby suppressing the gain nonlinearity. In addition, using a transistor with a longer channel length L can also reduce the impact of the DIBL effect, but it will lead to an increase in the bias effect, so it is still necessary to make V bsn1 Set to 0 to suppress the background bias effect.

[0080] When the drain-source voltage continues to increase, the SCBE effect plays a dominant role. The SCBE effect is caused by the strong electric field strength in the drain depletion region when the transistor is saturated, which generates hot carriers. Some of the hot carriers enter the gate oxide layer or flow out through the drain, and the other part of the hot carriers flow through the substrate parasitic resistance, which in turn causes the substrate potential inside the transistor to change, triggering the non-ideal situation of the body effect. Since the energy of holes in the PMOS channel is much lower than that of electrons in the NMOS channel, the SCBE effect has a more significant impact on NMOS devices.

[0081] In the SCBE-dominated region, there is an additional current path from the drain to the substrate, and the substrate current is as follows: As shown:

[0082] (16)

[0083] Among them, P SCBE1 and P SCBE2is the coefficient related to the SCBE effect, and the relationship between l is as follows: As shown, the substrate current will also induce the bias effect on M N1 The threshold voltage is affected.

[0084] (17)

[0085] Based on the above analysis, it can be obtained that when the SCBE effect exists, r An The small signal model of the substrate current due to hot carriers is composed of the resistor r connected across the drain and substrate. scbe Characterization; by I sub The drain current change caused by the bias effect is controlled by the voltage-controlled current source g mscbe· v dsn1 reflect.

[0086] Figure 4 Schematic diagrams of a small signal model affected by the SCBE effect according to an embodiment of the present disclosure are shown as follows: (a) the substrate is connected to the ground; and (b) the substrate is connected to the source terminal.

[0087] like Figure 4 As shown in (a), if M N1 The substrate is connected to the ground, then r scbe With a larger r An The parallel connection results in a decrease in the overall output impedance, as shown in the formula As shown:

[0088] (18)

[0089] like Figure 4 As shown in (b), if M N1 The substrate is connected to its source, then r scbe As M N1 Part of the shading effect on r An To enlarge, As shown:

[0090] (19)

[0091] Due to the substrate current I sub The induced drain current is much higher than I sub Self, old style Japanese style Can be simplified to Japanese style , so M N1 Connecting the substrate to the source can result in higher output impedance, thereby increasing gain.

[0092] (20)

[0093] (twenty one)

[0094] Figure 5 The gain comparison result diagram of the traditional structure and the output stage structure of the embodiment of the present disclosure at different static operating points of the output node is schematically shown.

[0095] like Figure 5 As shown in the figure, the solid line is the gain curve of the new structure. Compared with the traditional structure of the dotted line, the relative gain change is reduced from 39.9% to 13.6%. The Class AB output stage with the new structure can effectively suppress the influence of high-order effects such as DIBL and SCBE, stabilize the open-loop gain performance under different loads, and alleviate the distortion problem in signal processing.

[0096] Based on the above principles and experimental data, it can be known that the rail-to-rail operational amplifier and the output stage structure of the rail-to-rail operational amplifier provided by the embodiments of the present disclosure suppress the influence of high-order effects on the gain from a mechanism perspective, and the gain improvement is more obvious; it can maintain the stability of the gain to a greater extent under different loads and different operating points, effectively suppress the gain nonlinearity of closed-loop applications, and alleviate the distortion problem in signal processing; it can operate within a wider power supply voltage range and support low power supply voltage; without additionally increasing the complexity and power consumption of the circuit.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems and methods according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the above-mentioned module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0098] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0099] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. An output stage structure of a rail-to-rail operational amplifier, characterized in that: include: Current adder, floating current source and Class AB output stage; The current adder is used to integrate and amplify the differential current signal of the input stage of the rail-to-rail operational amplifier and convert it into an input signal of the Class AB output stage; The floating current source is used to provide static bias for the Class AB output stage and control the power consumption of the Class AB output stage; the floating current source is configured with a high-order effect suppression structure, and the high-order effect suppression structure is used to suppress the high-order effect of the floating current source.

2. The output stage structure according to claim 1, characterized in that: The floating current source comprises a first NMOS tube and a second NMOS tube, wherein the gate of the first NMOS tube is connected to the drain and the gate of the second NMOS tube; The first NMOS tube and the second NMOS tube are isolation devices, the substrate of the first NMOS tube is short-circuited with the source of the first NMOS tube, and the substrate of the second NMOS tube is short-circuited with the source of the second NMOS tube to form the high-order effect suppression structure, and the substrate is an independent well for providing a potential separately.

3. The output stage structure according to claim 2, characterized in that: The floating current source also includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a third NMOS tube, a first current source and a second current source; The source of the third PMOS tube is connected to the positive input voltage, the gate and drain of the third PMOS tube are connected to the source of the second PMOS tube, the gate and drain of the second PMOS tube are connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the first PMOS tube is connected to the source and substrate of the first NMOS tube, the source and substrate of the second NMOS tube are connected to the drain and gate of the third NMOS tube, and the source of the third NMOS tube is grounded; the positive electrode of the first current source is connected to the positive input voltage, the negative electrode is connected to the gate of the first NMOS tube and the drain and gate of the second NMOS tube, the gate and drain of the second PMOS tube and the gate of the first PMOS tube are connected to the positive electrode of the second current source, and the negative electrode of the second current source is grounded.

4. The output stage structure according to claim 2 or 3, characterized in that: The bias voltage of the floating current source is zero.

5. The output stage structure according to claim 3, characterized in that: The current adder includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube; The drain of the fourth PMOS tube is connected to the source of the first PMOS tube and the drain of the first NMOS tube, the source of the fourth PMOS tube is connected to the drain of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the positive input voltage, the gate of the fourth PMOS tube is connected to the gate of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the seventh PMOS tube, the source of the sixth PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the positive input voltage, the drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube, and the gate of the eighth PMOS tube is connected to the gate of the first PMOS tube and the drain and gate of the second PMOS tube; The drain of the eighth PMOS tube is connected to the drain of the sixth NMOS tube and the gate of the seventh NMOS tube, the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the seventh NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the first PMOS tube and the source and substrate of the first NMOS tube, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube is grounded.

6. The output stage structure according to claim 5, characterized in that: The Class AB output stage includes an output stage PMOS tube and an output stage NMOS tube; The source of the output-stage PMOS tube is connected to the positive input voltage, the gate of the output-stage PMOS tube is connected to the drain of the fourth PMOS tube, the source of the first PMOS tube and the drain of the first NMOS tube, the drain of the output-stage PMOS tube is connected to the drain of the output-stage NMOS tube, the gate of the output-stage NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the first PMOS tube and the source and substrate of the first NMOS tube, and the source of the output-stage NMOS tube is grounded.

7. The output stage structure according to claim 6, characterized in that: Also includes: The first capacitor and the second capacitor constitute a Miller compensation capacitor; The first end of the first capacitor is connected to the gate of the output-stage PMOS tube, the drain of the fourth PMOS tube, the source of the first PMOS tube and the drain of the first NMOS tube, the second end of the first capacitor is connected to the second end of the second capacitor, the second end of the first capacitor and the second end of the second capacitor are connected to the drain of the output-stage PMOS tube and the drain of the output-stage NMOS tube, and the first end of the second capacitor is connected to the gate of the output-stage NMOS tube, the drain of the fourth NMOS tube, the drain of the first PMOS tube, and the source and substrate of the first NMOS tube.

8. The output stage structure according to claim 6, characterized in that: The static current of the output stage is controlled by a first linear transconductance loop and a second linear transconductance loop, wherein the first linear transconductance loop is composed of the output stage PMOS tube, the first PMOS tube, the second PMOS tube, and the third PMOS tube, and the first linear transconductance loop is composed of the output stage NMOS tube, the first NMOS tube, the second NMOS tube, and the third NMOS tube.

9. A rail-to-rail operational amplifier, characterized in that: include: An input stage, used for converting an input differential voltage signal into a differential current signal; The output stage structure according to any one of claims 5 to 8, wherein the output stage structure is used to process the differential current signal to achieve rail-to-rail output.

10. The rail-to-rail operational amplifier according to claim 9, characterized in that: The input stage comprises: A transconductor, wherein the source of the fourth PMOS tube and the drain of the fifth PMOS tube are connected to a first end of the transconductor, and the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected to a second end of the transconductor; The source of the sixth PMOS tube and the drain of the seventh PMOS tube are connected to the third end of the transconductor; the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected to the fourth end of the transconductor; A pair of differential voltage signals are connected to the fifth and sixth ends of the transconductor; The transconductance is used to convert the pair of differential voltage signals into two pairs of differential current signals.

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