Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device may include: a first gate structure in a first memory block and including stacked first gate lines, the first gate lines extending from a planar central region to a planar edge region; a second gate structure in a second memory block adjacent to the first memory block and including stacked second gate lines, the second gate lines extending from the planar central region to the planar edge region; an isolation insulation structure located between a) the first gate structure and the second gate structure and located in b) the planar edge region, the isolation insulation structure comprising stacked insulation plates and insulation posts extending through the insulation plates; and a slit structure between a) the first gate structure and the second gate structure and in b) the planar central region, the slit structure being connected to the isolation insulating structure and including an unevenness on a sidewall of the slit structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device for forming a memory cell in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been considered. In addition, in order to improve the operational reliability of such a three-dimensional semiconductor device, various structures and manufacturing methods have been developed. Summary of the invention

[0003] In one embodiment, a semiconductor device may include: a first gate structure, which is in a first storage block and includes a stacked first gate line, the first gate line extending from a planar central region to a planar edge region; a second gate structure, which is in a second storage block adjacent to the first storage block and includes a stacked second gate line, the second gate line extending from a planar central region to a planar edge region; an isolation insulating structure, which is located a) between the first gate structure and the second gate structure and in b) the planar edge region, the isolation insulating structure includes a stacked insulating plate and an insulating column extending through the insulating plate; and a slit structure, which is located a) between the first gate structure and the second gate structure and in b) the planar central region, the slit structure is connected to the isolation insulating structure and includes an irregularity on the side wall of the slit structure.

[0004] In another embodiment, the semiconductor device may include: a dummy stack including sacrificial layers and insulating layers alternately stacked; a first gate structure adjacent to the dummy stack in a first direction and including a stacked first gate line; a second gate structure adjacent to the dummy stack in the first direction and including a stacked second gate line; a first contact structure extending through the first gate structure and connected to the first gate lines, respectively; a second contact structure extending through the second gate structure and connected to the second gate lines, respectively; a slit structure extending between the first gate structure and the second gate structure; and an isolation insulating structure connected to the slit structure and extending between the first gate structure and the second gate structure to protrude into the dummy stack.

[0005] In another embodiment, a method for manufacturing a semiconductor device may include: forming a stack including a first material layer and a second material layer alternately stacked; forming a first opening in a planar edge region of the stack; forming a second opening in a planar central region of the stack; forming an isolation trench by etching the first material layer through the first opening; forming an isolation insulating structure in the isolation trench; forming a slit by enlarging the second opening so that the second openings are connected to each other, the slit exposing the isolation insulating structure; and forming a slit structure in the slit, the slit structure being connected to the isolation insulating structure.

[0006] In yet another embodiment, a method for manufacturing a semiconductor device may include: forming a stack including alternately stacked first material layers and second material layers; forming an isolation insulating structure in a planar edge region of the stack, the isolation insulating structure including stacked insulating plates and insulating pillars extending through the insulating plates and extending in a first direction; forming a slit in a planar central region of the stack, the slit extending in the first direction and exposing the isolation insulating structure; replacing a first material layer located in the planar central region of the first material layer with a third material layer through the slit; and forming a slit structure in the slit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1E is a diagram illustrating a structure of a semiconductor device according to one embodiment.

[0008] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device according to another embodiment.

[0009] Figure 3A and Figure 3B is a diagram illustrating a structure of a semiconductor device according to still another embodiment.

[0010] Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A as well as Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B 2 are diagrams for describing a method for manufacturing a semiconductor device according to various embodiments. DETAILED DESCRIPTION

[0011] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0012] By three-dimensionally stacking memory cells, the integration degree of a semiconductor device can be increased. A semiconductor device having a stable structure and improved reliability can also be provided.

[0013] Hereinafter, embodiments according to the technical scope of the present disclosure will be described with reference to the accompanying drawings.

[0014] Figures 1A to 1E is a diagram illustrating a structure of a semiconductor device according to one embodiment. Figure 1A yes Figure 1C The plan view of the first height LV1, Figure 1B yes Figure 1C The floor plan of the second height LV2, Figure 1C It is along Figure 1A A cross-sectional view taken along line AA' of Figure 1D It is along Figure 1A A cross-sectional view taken along line BB' of Figure 1E It is along Figure 1A A cross-sectional view taken along line CC'.

[0015] Reference Figures 1A to 1E , the semiconductor device may include a plurality of memory planes PL. One wafer may include a plurality of memory planes PL, one memory plane PL may include a plurality of memory blocks MB1 and MB2, and one memory block MB1 or MB2 may include a plurality of pages. As an example, a memory block MB1 or MB2 may be a unit for performing an erase operation, and a page may be a unit for performing a programming operation and / or a read operation. Each memory plane PL may include a plane central region PCE and a plane edge region PEG. The plane central region PCE and the plane edge region PEG may be adjacent to each other in a first direction I. As an example, the plane central region PCE may be located between a pair of plane edge regions PEG.

[0016] The semiconductor device may include at least one of a first gate structure GST1, a second gate structure GST2, a dummy stack DST, an isolation insulating structure ISS and a slit structure SLS, a first channel structure CHA, a second channel structure CHB, a first dummy channel structure DCHA, a second dummy channel structure DCHB, a first support SPA, a second support SPB, and a contact structure CT.

[0017] The first gate structure GST1 may include stacked first gate lines 11A. The first gate lines 11A and the insulating layers 12 may be alternately stacked (eg, Figure 1E). The first gate lines 11A may be word lines, source selection lines, drain selection lines, etc. The first gate lines 11A may each include a conductive material such as, for example, polysilicon or metal. The first gate structure GST1 may belong to the first memory block MB1. The first gate structure GST1 may be located in a plane center region PCE of the memory plane PL and may extend into a plane edge region PEG.

[0018] The second gate structure GST2 may include a stacked second gate line 11B. The second gate line 11B and the insulating layer 12 may be alternately stacked. The second gate line 11B may be a word line, a source selection line, a drain selection line, etc. The second gate lines 11B may each include a conductive material such as, for example, polysilicon or a metal. The second gate structure GST2 may belong to a second memory block MB2. The second gate structure GST2 may be located in a planar central region PCE of the memory plane PL and may extend into a planar edge region PEG.

[0019] The first gate structure GST1 may extend in a first direction I, and the first gate line 11A may extend in the first direction I. The second gate structure GST2 may extend in the first direction I, and the second gate line 11B may extend in the first direction I. The first gate structure GST1 and the second gate structure GST2 may be adjacent to each other in a second direction II crossing the first direction I.

[0020] The first memory block MB1 may include at least one of a first gate structure GST1, a first channel structure CHA, a first dummy channel structure DCHA, a first support member SPA, and a first contact structure CTA. The first gate structure GST1 may include a cell region CR and a contact region CTR (eg, Figure 1E ). The cell region CR may be a region where memory cells are stacked, and the contact region CTR may be a region where an interconnect structure is located. The interconnect structure may include contact plugs, wirings, etc., and may provide a path for transmitting bias to the stacked memory cells.

[0021] Reference Figure 1E , the first channel structure CHA may extend through the cell region CR of the first gate structure GST1. The first channel structure CHA may include a channel layer 14, and may also include at least one of a memory layer 15 and / or an insulating core 16. The memory layer 15 may include at least one or more of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance layer, etc. At least one or more of the first channel structures CHA may be a first dummy channel structure DCHA. Return to reference Figure 1A and Figure 1B, the first dummy channel structure DCHA may be located in the planar edge region PEG, and may have a structure similar to that of the first channel structure CHA.

[0022] The first contact structures CTA may extend through the contact regions CTR of the first gate structure GST1 and may be connected to the first gate lines 11A, respectively. The first contact structures CTA may include first contact plugs 17 and insulating spacers 18 surrounding the sidewalls of the first contact plugs 17. For reference, it may also be as follows: the first gate structure GST1 includes step structures, each of which exposes the first gate line 11A, and the first contact structures CTA are connected to the first gate lines 11A exposed by the step structures.

[0023] The first support member SPA may extend through the contact region CTR of the first gate structure GST1. The first support member SPA may be located around the first contact structure CTA. The first support member SPA may have a structure similar to that of the first channel structure CHA or the first dummy channel structure DCHA. As an example, the first support member SPA may include at least one of a dummy channel layer 14D, a dummy memory layer 15D, and a dummy insulating core 16D (e.g., Figure 1E As shown). The first support members SPA may be arranged in the first direction I and the second direction II, or may be staggered in a zigzag shape. As an example, the first support member SPA may be arranged to surround the first contact structure CTA, and may protrude into the first contact structure CTA (as shown). Figure 1A and Figure 1B shown).

[0024] The second memory block MB2 may have a structure similar to that of the first memory block MB1. The second memory block MB2 may include at least one of a second gate structure GST2, a second channel structure CHB, a second dummy channel structure DCHB, a second support member SPB, and a second contact structure CTB.

[0025] The isolation insulating structure ISS may be located inside the memory plane PL and may be located between the first memory block MB1 and the second memory block MB2 (or at a boundary between the first memory block MB1 and the second memory block MB2) (eg, Figure 1A and Figure 1B The isolation insulating structure ISS may be located between the first memory block MB1 and the second memory block MB2 in the plane edge region PEG. The isolation insulating structure ISS may extend in a first direction I.

[0026] The isolation insulating structure ISS may include stacked insulating plates PT and insulating pillars P (eg Figure 1C and Figure 1D11A and the second gate line 11B. The insulating plate PT and the insulating layer 12 may be alternately stacked. The insulating pillars P may extend through the insulating plate PT in a third direction III. Here, the third direction III may be a direction perpendicular to a plane defined by the first direction I and the second direction II.

[0027] The insulating plate PT may have a line shape extending in the first direction I. The insulating pillars P may be arranged in the first direction and may be spaced apart from each other. The insulating plate PT may extend in the first direction I, and the insulating pillars P may be connected to each other through the insulating plate PT. In the second direction II, the insulating pillars P may have a first width W1, and the insulating plate PT may have a second width W2 (eg, Figure 1D shown).

[0028] In the planar edge region PEG, the insulating layer 12 may be alternately stacked with the insulating plates PT. The insulating layer 12 may extend in the second direction II and may penetrate the isolation insulating structure ISS between the insulating pillars P. The insulating layer 12 may extend between the stacked first gate lines 11A and between the stacked second gate lines 11B.

[0029] The slit structure SLS may be located inside the memory plane PL, and may be located between the first memory block MB1 and the second memory block MB2 (or at the boundary between the first memory block MB1 and the second memory block MB2). The slit structure SLS may be located between the first memory block MB1 and the second memory block MB2 in the plane central area PCE. The slit structure SLS may be connected to the isolation insulating structure ISS, and may be located between the first gate structure GST1 and the second gate structure GST2. The slit structure SLS may include at least one or more of an insulating material, a conductive material, and a semiconductor material. As an example, the slit structure SLS may include a gap filling material such as, for example, an insulating layer or a semiconductor layer. It may also be as follows: the slit structure SLS includes a source contact structure electrically connected to the source layer.

[0030] like Figure 1A and Figure 1BAs shown, the slit structure SLS may extend in the first direction I and may include an uneven portion on its side wall. As used herein, an uneven portion means that the side wall surface is intentionally shaped into a surface wall having a wavy or curved shape, for example, by patterning and / or etching. The side wall of the slit structure SLS may include a convex portion and a concave portion. The isolation insulating structure ISS may be connected to both ends of the slit structure SLS. The first gate structure GST1 and the second gate structure GST2 may be electrically isolated from each other by the isolation insulating structure ISS and the slit structure SLS. The first storage block MB1 and the second storage block MB2 may be electrically isolated from each other by the isolation insulating structure ISS and the slit structure SLS.

[0031] like Figure 1C and Figure 1D As shown, the dummy stack DST may include a stacked sacrificial layer 19. The sacrificial layer 19 may be a layer that is left without being replaced by the gate lines 11A and 11B during the manufacturing process. The dummy stack DST may include sacrificial layers 19 and insulating layers 12 that are alternately stacked. The dummy stack DST may be adjacent to the first gate structure GST1 and the second gate structure GST2 in the first direction I. At least one or more of the first dummy channel structure DCHA and the second dummy channel structure DCHB may extend through the dummy stack DST. A portion of the isolation insulating structure ISS may be located in the dummy stack DST, and the remainder of the isolation insulating structure ISS may be located between the first gate structure GST1 and the second gate structure GST2.

[0032] According to the above structure, the first gate structure GST1 and the second gate structure GST2 can be electrically isolated from each other by the isolation insulating structure ISS and the slit structure SLS. The isolation insulating structure ISS can protrude into the dummy stack DST, and the end of the first gate structure GST1 and the end of the second gate structure GST2 can be isolated from each other by the dummy stack DST and the isolation insulating structure ISS without a separate cutting structure. Through this configuration, the semiconductor device can be driven in units of memory blocks. The first gate structure GST1 and the second gate structure GST2 can be driven separately.

[0033] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device according to another embodiment. Hereinafter, contents overlapping with previously described contents may be omitted.

[0034] Reference Figure 2A and Figure 2BThe semiconductor device may include at least one of a gate structure GST, a channel structure CH, a dummy channel structure DCH, a slit structure SLS, an isolation insulating structure ISS, a support member SP, and a contact structure CT. The gate structure GST may include gate lines 21 and insulating layers 22 alternately stacked. Figure 2A may be a plan view of the gate line 21, and Figure 2B It may be a plan view of the insulating layer 22 .

[0035] The isolation insulating structure ISS may include a stacked insulating plate PT and insulating pillars P. The insulating plate PT may be located at a height corresponding to the gate line 21. In a plane defined by the first direction I and the second direction II, the insulating plate PT may have a line shape extending in a C shape around the dummy channel structure DCH. In a plan view, the insulating pillars P may be arranged in a C shape and may be spaced apart from each other. The insulating pillars P may be connected to each other through the insulating plate PT. For reference, the dummy stack may be located around the isolation insulating structure ISS.

[0036] According to the above structure, the gate structures GST adjacent to each other in the second direction II may be electrically isolated from each other by the isolation insulating structure ISS having a C-shape.

[0037] Figure 3A and Figure 3B is a diagram illustrating a structure of a semiconductor device according to still another embodiment. Hereinafter, contents overlapping with previously described contents may be omitted.

[0038] Reference Figure 3A , the isolation insulating structure ISS and the slit structure SLS may be connected to each other and may have different structures. The slit structure SLS may have a shape in which a plurality of columns are connected to each other. The sidewall of the slit structure SLS may include the above-mentioned uneven portion. The sidewall of the slit structure SLS may include a first convex portion CV1 and a first concave portion CC1. The first convex portion CV1 and the first concave portion CC1 may be arranged alternately.

[0039] The isolation insulating structure ISS may include an insulating column P and an insulating plate PT. The sidewall of the insulating plate PT may include an uneven portion. The sidewall of the insulating plate PT may include a second convex portion CV2 and a second concave portion CC2. The second convex portion CV2 and the second concave portion CC2 may be arranged alternately. In a plan view, the insulating column P may have a circular shape, an elliptical shape, a polygonal shape, etc. The insulating column P may have a circular shape, and the insulating plate PT may have a shape in which circular shapes having a width greater than that of the insulating column P are connected to each other. The second convex portion CV2 may extend along the sidewall of the insulating column P, and the second concave portion CC2 may be located between adjacent insulating columns.

[0040] Reference Figure 3B, the isolation insulating structure ISS and the slit structure SLS may be connected to each other and may have a similar structure. The slit structure SLS may have a shape in which a plurality of columns are connected to each other and may include an uneven portion on its sidewall. The isolation insulating structure ISS may not include an insulating plate, and a plurality of insulating columns P may be directly connected to each other. The sidewall of the isolation insulating structure ISS may include convex portions CV and concave portions CC arranged alternately.

[0041] According to the above structure, the isolation insulating structure ISS and the slit structure SLS can be connected to each other. The isolation insulating structure ISS and the slit structure SLS can have similar or different shapes. As an example, the isolation insulating structure may include an insulating plate PT, and the insulating plate PT may include a second convex portion CV2 and a second concave portion CC2 on its sidewall.

[0042] Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A as well as Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B 2 are diagrams for describing a method for manufacturing a semiconductor device according to various embodiments. Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A is a plan view, and Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B are respectively along Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A Hereinafter, contents overlapping with the previously described contents may be omitted.

[0043] Reference Figure 4A and Figure 4B, a stack ST including alternately stacked first material layers 31 and second material layers 32 may be formed. The first material layers 31 may be used to form gate lines, and the second material layers 32 may be used to insulate the stacked gate lines from each other. The first material layers 31 may each include a material having a high etching selectivity relative to the second material layers 32. As an example, the first material layers 31 may each include a sacrificial material such as, for example, a nitride or a conductive material such as, for example, polysilicon and / or a metal. The second material layers 32 may each include an insulating material such as an oxide or a nitride.

[0044] The stack ST may include a planar central region PCE and a planar edge region PEG. The planar central region PCE and the planar edge region PEG may be adjacent to each other in the first direction I. At least one or more of a channel structure, a dummy channel structure, a support member, and a contact structure may be formed in the planar central region PCE of the stack ST. The contact structures may be connected to the first material layer 31 through the stack ST, respectively. For reference, a contact sacrificial structure may also be formed, and the contact sacrificial structure may be replaced with the contact structure in a subsequent process. When the first material layer 31 is replaced with the third material layer 31A in a subsequent process, the dummy channel structure and the support member may support the stack ST and reduce the bending of the stack ST.

[0045] Subsequently, a first opening OP1 may be formed in a planar edge region PEG of the stack ST. In a plan view, the first opening OP1 may have a circular shape, an elliptical shape, a polygonal shape, etc. The second opening OP2 may be formed in a planar central region PCE of the stack ST. In a plan view, the second opening OP2 may have one or more of a circular shape, an elliptical shape, a polygonal shape, etc. The first opening OP1 and the second opening OP2 may have substantially the same shape or different shapes. As an example, the first opening OP1 and the second opening OP2 may have substantially the same width and may be arranged at substantially the same intervals.

[0046] The first opening OP1 and the second opening OP2 may be arranged in the first direction I. The first opening OP1 and the second opening OP2 may be aligned in the first direction I. The first opening OP1 and the second opening OP2 may be located at a boundary between adjacent memory blocks. When the first opening OP1 is formed, the second opening OP2 may be formed. For reference, the first opening OP1 and the second opening OP2 may also be formed together with the opening for forming the channel structure and / or the contact structure when the opening for forming the channel structure and / or the contact structure is formed.

[0047] Reference Figure 5A and Figure 5B, a first mask pattern 34 may be formed on the stack ST. The first mask pattern 34 may include an opening 34_OP partially exposing the plane edge region PEG. The first mask pattern 34 may cover the second opening OP2 and may expose the first opening OP1.

[0048] For reference, before forming the first mask pattern 34, a sacrificial layer 33 may be formed in the first opening OP1 and the second opening OP2. The sacrificial layers 33 may each include a material having a high etching selectivity with respect to the first material layer 31 and the second material layer 32. When the sacrificial layer 33 is formed, the first opening OP1 may be reopened by removing the sacrificial layer 33 in the first opening OP1 after forming the first mask pattern 34.

[0049] Reference Fig. 6A and Figure 6B , an isolation trench IST may be formed by etching the first material layer 31 through the first opening OP1. The third opening OP3 may be formed by selectively etching the first material layer 31. The first openings OP1 may be connected to each other through the third opening OP3. The first opening OP1 may be enlarged at some heights by etching the first material layer 31, and the enlarged portions of the first opening OP1 may be connected to each other to form the third opening OP3. Thus, the first material layer 31 around the first opening OP1 in the planar edge region PEG may be removed in advance. The first material layer 31 at the boundary between the storage blocks in the planar edge region PEG may be removed in advance.

[0050] When the first opening OP1 is enlarged, the shape of the first opening OP1 can be transferred to the third opening OP3. As an example, when the first opening OP1 has a circular shape, the curved surface of the first opening OP1 can be transferred to the third opening OP3. Therefore, the sidewall of the third opening OP3 may include an uneven portion. As an example, the sidewall of the third opening OP3 may include, for example, a convex portion and a concave portion (such as the convex portion and concave portion described above). Thus, an isolation trench IST including the first opening OP1 and the third opening OP3 can be formed. The isolation trench IST can be located at the boundary between the storage blocks.

[0051] Reference Fig. 7A and Figure 7B, an isolation insulating structure 35 may be formed in the isolation trench IST. The isolation insulating structure 35 may be formed by a thermal atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LP-CVD) method, or the like. The isolation insulating structure 35 may include insulating materials such as, for example, oxides, nitrides, and / or air gaps. Thus, the first material layer 31 around the first opening OP1 in the planar edge region PEG may be replaced with an insulating material. The first material layer 31 located at the boundary between the storage blocks in the planar edge region PEG may be replaced with an insulating material.

[0052] The isolation insulating structure 35 may include a stacked insulating plate 35_PT and an insulating column 35_P extending through the insulating plate 35_PT in the third direction III. The insulating column 35_P may be located in the first opening OP1, and the insulating plate 35_PT may be located in the third opening OP3. The insulating column 35_P and the insulating plate 35_PT may be connected to each other as one layer. The insulating plate 35_PT may include an uneven portion on its sidewall, and may include, for example, a convex portion and a concave portion.

[0053] For reference, the second material layer 32 may be selectively etched before forming the isolation insulating structure 35. In this case, the above reference Figure 3B Described isolation insulation structure ISS.

[0054] Reference Fig. 8A , Figure 8B , Fig.9A and Fig. 9B , the second opening OP2 may be enlarged to form a slit SL. The second opening OP2 may be enlarged so that the second openings OP2 are connected to each other, and the isolation insulating structure 35 may be exposed through the slit SL extending in the first direction I. As an example, the isolation insulating structure 35 may be exposed at both ends of the slit SL. The slit SL may be located at a boundary between memory blocks.

[0055] First, refer to Fig. 8A and Figure 8B , a second mask pattern 36 may be formed on the stack ST. The second mask pattern 36 may include an opening 36_OP that partially exposes the planar central area PCE. The second mask pattern 36 may cover the isolation insulating structure 35 and may expose the second opening OP2. Subsequently, the second opening OP2 may be reopened by removing the sacrificial layer 33 in the second opening OP2. Subsequently, the second material layer 32 may be etched through the second opening OP2. The sidewalls of the isolation insulating structure 35 may be exposed by selectively etching the second material layer 32. The insulating pillar 35_P of the isolation insulating structure 35 may be exposed.

[0056] Then, refer to Fig.9A and Fig. 9B , the first material layer 31 can be etched through the second opening OP2. The sidewall of the isolation insulating structure 35 can be exposed by selectively etching the first material layer 31. The insulating plate 35_PT of the isolation insulating structure 35 can be exposed. Thus, the second opening OP2 can be enlarged and can be connected to each other. When the second opening OP2 is enlarged, the shape of the second opening OP2 can be transferred to the slit SL. As an example, when the second opening OP2 has a circular shape, the curved surface of the second opening OP2 can be transferred to the slit SL. Therefore, the sidewall of the slit SL may include an uneven portion. As an example, the sidewall of the slit SL may include, for example, a convex portion and a concave portion.

[0057] For reference, the order or method of etching the first material layer 31 and the second material layer 32 may be changed. As an example, the second material layer 32 may be etched after etching the first material layer 31, or may be etched simultaneously.

[0058] Reference Fig. 10A and Fig. 10B , the first material layer 31 may be replaced with a third material layer 31A through the slit SL. First, an opening may be formed by selectively etching the first material layer 31 through the slit SL. Subsequently, a third material may be deposited in the opening through the slit SL. Subsequently, the third material deposited in the slit SL may be wet or dry etched to form third material layers 31A respectively located in the openings. The third material layers 31A may each include a metal such as tungsten or molybdenum. Thus, a gate structure GST including alternately stacked third material layers 31A and second material layers 32 may be formed.

[0059] When the first material layer 31 is etched, an etchant may be introduced through the slit SL, and the first material layer 31 within a predetermined range from the slit SL may be etched. Because the slit SL is located in the planar central region PCE, the first material layer 31 in the planar central region PCE may be replaced with the third material layer 31A. Because the slit SL is not located in the planar edge region PEG, only the first material layer 31 in the region close to the slit SL in the planar edge region PEG may be replaced with the third material layer 31A, and the first material layer 31 in the remaining region may remain intact. Therefore, the first material layer 31 may remain in the planar edge region PEG, and the region where the first material layer 31 remains may be defined as a dummy stack DST. The dummy stack DST may include first material layers 31 and second material layers 32 alternately stacked, and may partially surround the isolation insulating structure 35.

[0060] Furthermore, since the first material layer 31 formed at the boundary between the memory blocks is replaced with an insulating material in the process of forming the isolation insulating structure 35 , the third material layer 31A may not be formed at the boundary between the memory blocks in the planar edge region PEG.

[0061] Subsequently, a slit structure 37 may be formed in the slit SL. As an example, the slit structure 37 may be formed by forming an insulating layer, a semiconductor layer, and / or a conductive layer in the slit SL. The sidewall of the slit structure 37 may include an uneven portion, and may include, for example, a convex portion and a concave portion. For reference, it may also be as follows: the slit structure 37 includes a source contact structure connected to the source layer.

[0062] According to the above-described manufacturing method, the gate structures GST can be electrically isolated from each other by the isolation insulating structure 35, the slit structure 37, and the dummy stack DST. Since the isolation insulating structure 35 is formed in the plane edge region PEG and the slit SL is formed in the plane central region PCE, the dummy stack DST can be formed in the plane edge region PEG. Since the dummy stack DST is formed in the process of replacing the first material layer 31 with the third material layer 31A, the gate structures GST can be electrically isolated from each other even if the stack ST is not cut in the plane edge region PEG.

[0063] Although the embodiments according to the technical scope of the present disclosure have been described above with reference to the accompanying drawings, this is only used to explain the embodiments according to the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical scope of the present disclosure, various types of replacements, modifications and changes can be made to the embodiments by ordinary technicians in the field to which the present disclosure belongs, and it should be understood that these replacements, modifications and changes belong to the scope of the present disclosure.

[0064] CROSS-REFERENCE TO RELATED APPLICATIONS

[0065] This application claims priority to Korean Patent Application No. 10-2023-0092448, filed on Jul. 17, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first gate structure in the first memory block and comprising a stacked first gate line extending from a planar central region to a planar edge region; a second gate structure in a second storage block adjacent to the first storage block and comprising a stacked second gate line extending from the planar central region to the planar edge region; an isolation insulating structure, the isolation insulating structure being located a) between the first gate structure and the second gate structure and b) in the planar edge region, the isolation insulating structure comprising stacked insulating plates and insulating pillars extending through the insulating plates; as well as A slit structure is located a) between the first gate structure and the second gate structure and b) in the planar central region, the slit structure is connected to the isolation insulating structure, and includes an uneven portion on a sidewall of the slit structure.

2. The semiconductor device according to claim 1, wherein The planar edge region and the planar central region are adjacent to each other in a first direction, and the first gate line and the second gate line extend in the first direction.

3. The semiconductor device according to claim 2, wherein: The insulating pillars are arranged in the first direction, the insulating plate extends in the first direction, and the insulating pillars are connected to each other through the insulating plate.

4. The semiconductor device according to claim 2, wherein: The insulating plate has a greater width than the insulating pillar in a second direction crossing the first direction. 5 . The semiconductor device according to claim 2 , further comprising an insulating layer which is located in the planar edge region and is alternately stacked with the insulating plates.

6. The semiconductor device according to claim 5, wherein: The insulating layer extends between the stacked first gate lines and between the stacked second gate lines.

7. The semiconductor device according to claim 1, wherein The side wall of the slit structure includes a convex portion and a concave portion.

8. The semiconductor device according to claim 1, wherein A side wall of each of the insulating plates includes a convex portion and a concave portion.

9. The semiconductor device according to claim 1, wherein: The first gate structure and the second gate structure are electrically isolated from each other by the isolation insulating structure and the slit structure.

10. The semiconductor device according to claim 1, further comprising: a first channel structure extending through the first gate structure; as well as First contact structures extend through the first gate structures and are respectively connected to the first gate lines.

11. A semiconductor device, comprising: a dummy stack comprising sacrificial layers and insulating layers alternately stacked; a first gate structure adjacent to the dummy stack in a first direction and comprising a stacked first gate line; a second gate structure adjacent to the dummy stack in the first direction and comprising a stacked second gate line; first contact structures extending through the first gate structures and connected to the first gate lines, respectively; second contact structures extending through the second gate structures and connected to the second gate lines, respectively; a slit structure extending between the first gate structure and the second gate structure; as well as An isolation insulating structure is connected to the slit structure and extends between the first gate structure and the second gate structure to protrude into the dummy stack.

12. The semiconductor device according to claim 11, wherein The first gate structure and the second gate structure are adjacent to each other in a second direction crossing the first direction, and the slit structure and the isolation insulating structure extend in the first direction.

13. The semiconductor device according to claim 11, wherein The first gate structure and the second gate structure are electrically isolated from each other by the slit structure, the isolation insulating structure, and the dummy stack.

14. The semiconductor device according to claim 11, wherein The insulating layer extends between the stacked first gate lines and between the stacked second gate lines.

15. The semiconductor device according to claim 11, wherein The isolation and insulation structure comprises: laminated insulation panels; and An insulating post extends through the stacked insulating plates.

16. The semiconductor device according to claim 15, wherein: The insulating layer extends between the insulating pillars.

17. The semiconductor device according to claim 15, wherein: A side wall of each of the insulating plates includes an irregularity.

18. The semiconductor device according to claim 11, wherein The side wall of the slit structure includes an uneven portion.

19. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a laminate including alternately stacked first material layers and second material layers; forming a first opening in a planar edge region of the stack; forming a second opening in a planar central region of the stack; forming an isolation trench by etching the first material layer through the first opening; forming an isolation insulating structure in the isolation trench; forming a slit by enlarging the second openings so that the second openings are connected to each other, the slit exposing the isolation insulating structure; as well as A slot structure is formed in the slot, the slot structure being connected to the isolation insulating structure.

20. The manufacturing method according to claim 19, wherein: The step of forming the isolation trench comprises the following steps: forming a first mask pattern on the stack, the first mask pattern covering the second opening and exposing the first opening; and A third opening is formed by selectively etching the first material layer through the first opening, the third opening connecting the first openings to each other.

21. The manufacturing method according to claim 20, wherein: A side wall of each of the third openings includes an uneven portion.

22. The manufacturing method according to claim 20, wherein: In the step of forming the isolation insulating structure, the isolation insulating structure including an insulating column located in the first opening and an insulating plate located in the third opening is formed.

23. The manufacturing method according to claim 19, wherein: The step of forming the slit comprises the following steps: forming a second mask pattern on the stack, wherein the second mask pattern covers the isolation insulating structure and exposes the second opening; etching the first material layer through the second opening; and The second material layer is etched through the second opening.

24. The manufacturing method according to claim 19, wherein: The sidewall of the slit includes an uneven portion.

25. The manufacturing method according to claim 19, further comprising the following steps: The first material layer is replaced with a third material layer through the slit.

26. The manufacturing method according to claim 19, wherein: The first opening and the second opening are arranged along a first direction, and the isolation trench and the slit extend along the first direction.

27. The manufacturing method according to claim 19, wherein: The isolation insulating structure and the slit structure are located at boundaries between memory blocks.

28. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a laminate including alternately stacked first material layers and second material layers; forming an isolation insulating structure in a planar edge region of the stack, the isolation insulating structure comprising stacked insulating plates and insulating pillars extending through the insulating plates and extending in a first direction; forming a slit in a planar central region of the stack, the slit extending in the first direction and exposing the isolation insulating structure; replacing the first material layer located in the central area of ​​the plane among the first material layers with a third material layer through the slit; as well as A slit structure is formed in the slit.

29. The manufacturing method according to claim 28, wherein: The steps of forming the isolation insulating structure include the following steps: forming first openings arranged in a first direction in the planar edge region of the stack; forming an isolation trench extending in the first direction by selectively etching the first material layer through the first opening; and The isolation insulating structure is formed in the isolation trench.

30. The manufacturing method according to claim 28, wherein: The step of forming the slit comprises the following steps: forming a second opening in the planar central region of the stack; and The slit is formed by enlarging the second openings so that the second openings are connected to each other.

31. The manufacturing method according to claim 28, wherein: The slit includes irregularities on a sidewall of the slit.

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