Three-dimensional memory, preparation method thereof, memory system and electronic equipment

Abstract

The invention provides a three-dimensional memory and a preparation method thereof, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the programming speed of the three-dimensional memory and reduce reading interference. The invention discloses a three-dimensional memory. The three-dimensional memory comprises a laminated structure and a channel structure, the laminated structure comprises a plurality of gate layers and a plurality of gate dielectric layers which are alternately laminated; and the channel structure penetrates through the laminated structure. The channel structure comprises a barrier layer, a capture layer, a tunneling layer and a channel layer which are stacked in sequence; wherein the dielectric constant of the tunneling layer is smaller than that of the capture layer. The three-dimensional memory is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a three-dimensional memory (3D NAND) with a three-dimensional structure. The three-dimensional memory increases the storage density by arranging the storage cells three-dimensionally on the substrate. Traditional three-dimensional memory has the problems of slow programming speed and slow erasing speed, and the increase in programming speed and erasing speed will bring about serious problems of read disturb. Summary of the invention

[0004] Embodiments of the present disclosure provide a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device, which are used to increase the programming speed of the three-dimensional memory and reduce read disturbance.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a three-dimensional memory is provided, comprising: a stacked structure, including a plurality of gate layers and a plurality of gate dielectric layers alternately stacked; a channel structure running through the stacked structure, the channel structure comprising a blocking layer, a capture layer, a tunneling layer and a channel layer stacked in sequence; wherein the dielectric constant of the tunneling layer is smaller than the dielectric constant of the capture layer.

[0007] The three-dimensional memory provided by the embodiments of the present disclosure includes a stacked structure and a channel structure penetrating the stacked structure. The dielectric constant of the tunneling layer in the channel structure is set to be smaller than the dielectric constant of the capture layer, so that when the three-dimensional memory performs a read, program or erase operation, more voltage is allocated to the tunneling layer among the voltage applied by the gate layer, so that the ability of the charge to pass through the tunneling layer (for example, the charge passes through the tunneling layer to the capture layer, or the charge passes through the tunneling layer to the channel layer) is enhanced, so that the programming and erasing speeds can be improved. Moreover, the increase in voltage distribution on the tunneling layer makes the voltage allocated to the capture layer and the barrier layer relatively small, so that the read interference in the read operation is small, thereby to a certain extent eliminating the restrictive relationship between the size of the programming and erasing speed and the severity of the read interference, and improving the performance of the three-dimensional memory.

[0008] In some embodiments, the material of the tunneling layer includes carbon; the mass percentage of the carbon element in the material of the tunneling layer is α, and α≤50%.

[0009] In some embodiments, the tunneling layer includes at least a first tunneling sublayer and a second tunneling sublayer stacked together; the first tunneling sublayer is closer to the capture layer than the second tunneling sublayer; and the dielectric constant of the first tunneling sublayer is smaller than the dielectric constant of the second tunneling sublayer.

[0010] In some embodiments, a material of the second tunneling sub-layer includes carbon.

[0011] In some embodiments, the tunneling layer further includes a third sub-tunneling layer located at the second sub-tunneling layer and away from the first sub-tunneling layer; a dielectric constant of the third sub-tunneling layer is different from a dielectric constant of the second sub-tunneling layer.

[0012] In some embodiments, the material of the second tunneling sub-layer and the material of the third tunneling sub-layer both include carbon, and the mass percentage of the carbon in the second tunneling sub-layer is different from the mass percentage of the carbon in the third tunneling sub-layer.

[0013] In some embodiments, the material of the tunneling layer further includes silicon oxynitride.

[0014] On the other hand, a method for preparing a three-dimensional memory is provided, comprising: providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate and a stacked structure arranged on one side of the substrate; forming a channel hole penetrating the stacked structure; sequentially forming a blocking layer, a capture layer, a tunneling layer and a channel layer in the channel structure in the channel hole; the dielectric constant of the tunneling layer is smaller than the dielectric constant of the capture layer.

[0015] In some embodiments, forming the tunneling layer includes: using an atomic deposition process to introduce a reaction gas into the channel hole to form the tunneling layer.

[0016] In some embodiments, the composition of the reaction gas includes carbon.

[0017] On the other hand, a storage system is provided, comprising: a controller, and a three-dimensional memory as described in any one of the above embodiments; wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

[0018] On the other hand, an electronic device is provided, comprising: a storage system as described in any of the above embodiments, and a circuit board electrically connected to the storage system.

[0019] It can be understood that the beneficial effects that can be achieved by the method for preparing the three-dimensional memory, the storage system, and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the three-dimensional memory described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0021] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0022] Figure 2 is a structural diagram of a storage system according to some embodiments of the present disclosure;

[0023] Figure 3 is a structural diagram of a three-dimensional memory according to some embodiments of the present disclosure;

[0024] Figure 4 for Figure 3 An enlarged structural diagram of the AA area in the three-dimensional memory shown;

[0025] Figure 5 is a diagram of an energy band structure of a three-dimensional memory according to some embodiments of the present disclosure;

[0026] Figure 6 for Figure 3 Another enlarged structural diagram of the AA region in the three-dimensional memory shown;

[0027] Figure 7 for Figure 3 Another enlarged structural diagram of the AA region in the three-dimensional memory shown;

[0028] Figure 8 is a flow chart of a method for preparing a three-dimensional memory according to some embodiments of the present disclosure;

[0029] Figures 9 to 11 It is a structural diagram corresponding to each step in a method for preparing a three-dimensional memory according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0031] In the description of the present disclosure, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0034] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0035] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0036] like Figure 1 As shown, some embodiments of the present disclosure provide an electronic device 3000, which may include any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, etc. The electronic device 3000 may include a storage system 1000 configured to implement data storage as described below, and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc. to the storage system 1000.

[0037] like Figure 2 As shown, some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 is used in the above electronic device 3000. The storage system 1000 includes a three-dimensional memory 100 and a controller 200. The controller 200 is coupled to the three-dimensional memory 100 and is configured to control the three-dimensional memory 100 to store data.

[0038] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other electronic devices with memory.

[0039] In some examples, the memory system 1000 includes a controller 200 and a three-dimensional memory 100 .

[0040] The storage system 1000 may be integrated into a memory card, for example. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), or a UFS.

[0041] In other examples, such as Figure 2 As shown, the storage system 1000 includes a controller 200 and a plurality of three-dimensional memories 100 .

[0042] Exemplarily, the storage system 1000 includes a controller 200 and four three-dimensional memories 100. The storage system 1000 may be integrated into a solid state drive (SSD).

[0043] In some examples, in storage system 1000, controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0044] In other examples, in the storage system 1000, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage of mobile devices such as smart phones, tablet computers, laptop computers, and enterprise storage arrays.

[0045] In some examples, the controller 200 may be configured to manage data stored in the three-dimensional memory 100 and communicate with an external device (eg, a host).

[0046] In some examples, the controller 200 may also be configured to control operations of the three-dimensional memory 100 , such as read, erase, and program operations.

[0047] In some examples, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 100 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0048] In some examples, the controller 200 is also configured to process an error correction code regarding data read from or written to the three-dimensional memory 100 .

[0049] It is easy to understand that the controller 200 can also perform any other suitable functions, such as formatting the three-dimensional memory 100. For another example, the controller 200 can communicate with an external device (eg, a host) through at least one of various interface protocols.

[0050] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0051] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0052] Some embodiments of the present disclosure provide a three-dimensional memory 100 that can be used in the above storage system. Figure 3 and Figure 4 As shown, the three-dimensional memory 100 includes a substrate 10 , a stacked structure 20 and a channel structure 30 .

[0053] For example, the material of the substrate 10 can be single crystal silicon (Si), single crystal germanium (Ge), germanium silicon (GeSi) or silicon carbide (SiC), etc.; it can also be silicon on insulator (SOI) or germanium on insulator (GOI), etc.; it can also be other materials, such as III-V group compounds such as gallium arsenide.

[0054] Exemplarily, the stacked structure 20 is located on one side of the substrate 10. The stacked structure 20 includes a plurality of gate layers 21 and a plurality of gate dielectric layers 22 that are alternately stacked.

[0055] The material of the gate dielectric layer 22 may be an insulating material, which may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the gate layer 21 may include a conductive material, which may include, for example, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, doped monocrystalline silicon, and silicide.

[0056] In the stacked structure 20, the thicknesses of the multiple gate layers 21 may be approximately equal or unequal. The thicknesses of the multiple gate dielectric layers 22 may be approximately equal or unequal. In addition, in the stacked structure, different numbers of stacked layers correspond to different stacking heights. For example, the number of layers of the stacked structure 20 may be 8 layers, 16 layers, 32 layers, 64 layers, 96 layers, 128 layers, 256 layers, 316 layers, etc. The more stacked layers of the stacked structure 20, the higher the integration, that is, the more storage units are subsequently formed. The number of stacked layers and the stacking height of the stacked structure 20 can be designed according to actual storage requirements, and the present disclosure does not impose specific restrictions on this.

[0057] The channel structure 30 passes through the stacked structure 20, and a portion of the channel structure 30 may also extend into the interior of the substrate 10. The channel structure 30 includes a barrier layer 31, a capture layer 32, a tunnel layer 33, and a channel layer 34 stacked in sequence. The barrier layer 31, the capture layer 32, and the tunnel layer 33 stacked in sequence constitute the storage function layer of the channel structure 30.

[0058] It can be understood that by applying a voltage to the gate layer 21 of the three-dimensional memory 100, the voltage is distributed to the storage functional layer, and charges (electrons or holes) are injected into the capture layer 32 through the tunneling layer 33, or through the tunneling layer 33 to the channel layer 34, so that the three-dimensional memory 100 can realize reading, programming or erasing operations.

[0059] In one implementation, the material of the barrier layer 31 in the storage function layer is generally silicon oxide, the material of the capture layer 32 is generally silicon nitride, and the material of the tunnel layer 33 is generally silicon oxynitride. The mass ratio of silicon (Si), oxygen (O), and nitrogen (N) in each film layer in the storage function layer can be adjusted, the thickness of the barrier layer 31, the capture layer 32, and the tunnel layer 33 can be adjusted, and the preparation temperature of the barrier layer 31, the capture layer 32, and the tunnel layer 33 can be adjusted to improve the programming or erasing speed of the three-dimensional memory 100 and reduce the degree of read disturbance. However, the magnitude of the programming or erasing speed of the three-dimensional memory 100 and the severity of the read disturbance are mutually constrained. When the programming or erasing speed is increased, the read disturbance phenomenon will be aggravated; when the read disturbance is reduced, the programming or erasing speed is lost, and it is impossible to reduce the read disturbance while increasing the programming or erasing speed.

[0060] In some examples of the present disclosure, the dielectric constant of the tunneling layer 33 is smaller than the dielectric constant of the trapping layer 32 .

[0061] Therefore, when the three-dimensional memory 100 is programmed or erased, when a voltage (the voltage is an erase voltage or a programming voltage) is applied to the gate layer 21, the voltages allocated to the tunneling layer 33 and the capture layer 32 are different, and more voltage is allocated to the tunneling layer 33, thereby enhancing the ability of charges to pass through the tunneling layer 33 (for example, charges pass through the tunneling layer 33 to the capture layer 32, or charges pass through the tunneling layer 33 to the channel layer 34), so that the band structures of the tunneling layer 33, the capture layer 32, and the barrier layer 31 match, thereby improving the programming and erasing speeds of the three-dimensional memory 100. When the three-dimensional memory performs a read operation, when the voltage applied to the gate layer 21 is the read voltage, the voltage allocated to the capture layer 32 and the blocking layer 31 is relatively small, and the band structure presented by the tunneling layer 33, the capture layer 32, and the blocking layer 31 is different from the band structure during the above-mentioned programming or erasing operation, so that the read interference in the read operation can be smaller, thereby eliminating the restrictive relationship between the size of the programming and erasing speed and the severity of the read interference to a certain extent, thereby improving the performance of the three-dimensional memory 100.

[0062] Figure 5 The energy band structure diagram of the storage function layer of a three-dimensional memory in the embodiment of the present disclosure when no voltage is applied to the gate layer 21. The energy band of the blocking layer 31 is relatively wide, and the electron movement needs to cross a large energy level difference, which can reduce the ability of electrons to pass through. The energy band of the capture layer 32 is relatively narrow, and the energy band width of each sub-tunneling layer in the tunneling layer 33 (from the first sub-tunneling layer 331 to the second sub-tunneling layer 332, and then to the third sub-tunneling layer 333) increases in sequence in the direction away from the capture layer 32, which is conducive to the movement of electrons from the capture layer 32 to the tunneling layer 33 or from the tunneling layer 33 to the capture layer 32.

[0063] It can be understood that, in the above-mentioned implementation method, the adjustment of the mass ratio relationship of silicon element (Si), oxygen element (O) and nitrogen element (N) in the material of the storage functional layer can no longer bring about changes in the dielectric constants of the blocking layer 31, the capture layer 32 and the tunneling layer 33. Therefore, in some examples of the present disclosure, a new element is introduced into the material of the storage functional layer.

[0064] Specifically, the material of the tunnel layer 33 includes carbon. The introduction of carbon into the material of the tunnel layer 33 can reduce the dielectric constant of the tunnel layer 33, thereby increasing the voltage distributed on the tunnel layer 33 and enhancing the ability of charges to pass through the tunnel layer 33, thereby facilitating the improvement of the speed of programming and erasing operations of the three-dimensional memory 100 and reducing read disturbance.

[0065] In some examples, the material of the tunneling layer 33 also includes silicon oxynitride. For example, the material of the tunneling layer 33 includes silicon, oxygen, nitrogen and carbon, or the material of the tunneling layer 33 is a mixture of silicon carbide, silicon nitride and silicon oxide mixed in a certain mass ratio. Thus, by adjusting the mass percentage of each element, the energy band structure of the tunneling layer 33 can be matched with the energy band structure of the capture layer 32 and the barrier layer 31, thereby realizing the functions of reading, erasing and programming of the three-dimensional memory 100.

[0066] In some examples, the mass percentage of carbon in the material of the tunneling layer 33 is α, and α≤50%.

[0067] Exemplarily, the mass percentage α of the carbon element in the material of the tunneling layer 33 is in the range of α≤20%, or α≤10%, or α≤3%, or α≤2%, or 1%≤α≤2%, or 0<α≤1%.

[0068] For example, the mass percentage α of the carbon element in the material of the tunneling layer 33 may be 1%, 1.5%, 1.8%, 2%, 20%, 32% or 50%.

[0069] By setting the mass percentage of carbon element within the above range, the dielectric constant of the tunneling layer 33 can be lowered, so that more voltage is allocated to the tunneling layer 33, which is beneficial to improving the speed of programming and erasing operations of the three-dimensional memory 100 and reducing read disturbance.

[0070] The tunneling layer 33 may be a single-layer structure, or may include multiple sub-tunneling layers, which is not limited in the present disclosure and may be arranged according to actual needs. When the tunneling layer 33 includes multiple sub-tunneling layers stacked in layers, the dielectric constants of the sub-tunneling layers may be the same or different.

[0071] The following description will be made by taking the tunneling layer 33 including multiple sub-tunneling layers as an example.

[0072] Figure 6 The diagram shows that the tunneling layer 33 includes two sub-tunneling layers, which are a first sub-tunneling layer 331 and a second sub-tunneling layer 332 .

[0073] exist Figure 6 In the embodiment, the first tunneling sub-layer 331 is closer to the capture layer 32 than the second tunneling sub-layer 332. The dielectric constant of the first tunneling sub-layer 331 is smaller than the dielectric constant of the second tunneling sub-layer 332. Thus, the first tunneling sub-layer 331 close to the capture layer 32 can be allocated more voltage, which is beneficial to improve the programming speed and the erasing speed.

[0074] Exemplarily, the material of the first tunneling sub-layer 331 includes carbon.

[0075] For example, the material of the first tunneling sub-layer 331 includes silicon carbide. The material of the first tunneling sub-layer 331 may be a mixture of silicon carbide, silicon nitride, and silicon oxide in a certain proportion. At this time, the material of the second tunneling sub-layer 332 may not include carbon.

[0076] The material of the first tunneling sub-layer 331 includes carbon, which can reduce the dielectric constant of the first tunneling sub-layer 331, so that more voltage is allocated to the first tunneling sub-layer 331, which is beneficial to improving the programming speed and erasing speed of the three-dimensional memory 100, and reducing read interference.

[0077] Figure 7 The tunneling layer 33 includes three sub-tunneling layers, and the tunneling layer 33 includes a first sub-tunneling layer 331, a second sub-tunneling layer 332, and a third sub-tunneling layer 333 stacked in sequence. The third sub-tunneling layer 333 is located on a side of the second sub-tunneling layer 332 away from the first sub-tunneling layer 331. The dielectric constant of the third sub-tunneling layer 333 is different from the dielectric constant of the second sub-tunneling layer 332.

[0078] For example, the dielectric constant of the third sub-tunneling layer 333 is greater than the dielectric constant of the second sub-tunneling layer 332. Among them, the dielectric constants of the first sub-tunneling layer 331, the second sub-tunneling layer 332, and the third sub-tunneling layer 333 increase in sequence, so that the voltages allocated to the first sub-tunneling layer 331, the second sub-tunneling layer 332, and the third sub-tunneling layer 333 in the tunneling layer 33 decrease in sequence, and the first sub-tunneling layer 331 is allocated with more voltage, which is beneficial to reducing the read interference of the three-dimensional memory 100. The dielectric constant of the second sub-tunneling layer 332 is set to be centered, so that the proportion of the voltage allocated to the second sub-tunneling layer 332 in the tunneling layer 33 is larger, which is beneficial to improving the programming speed and erasing speed of the three-dimensional memory 100. As a result, the mutual restriction relationship between read interference and programming and erasing speeds can be broken to a certain extent, and read interference can be reduced while improving programming and erasing speeds.

[0079] For another example, the dielectric constant of the third tunneling sub-layer 333 is smaller than the dielectric constant of the second tunneling sub-layer 332. At this time, the dielectric constant of the third tunneling sub-layer 333 may be equal to or different from the dielectric constant of the first tunneling sub-layer 331. The dielectric constant of the second tunneling sub-layer 332 located in the middle of the tunneling layer 33 is larger, and the dielectric constant of the first tunneling sub-layer 331 is smaller, so that the voltage proportion allocated to the first tunneling sub-layer 331 in the tunneling layer 33 is larger, which is beneficial to reduce the read interference of the three-dimensional memory 100.

[0080] In some other examples, when the tunneling layer 33 includes three sub-tunneling layers, the dielectric constant of the third sub-tunneling layer 333 is equal to the dielectric constant of the second sub-tunneling layer 332. The dielectric constant of the first sub-tunneling layer 331 is smaller than the dielectric constant of the third sub-tunneling layer 333 and the dielectric constant of the second sub-tunneling layer 332, so that the voltage proportion allocated to the first sub-tunneling layer 331 in the tunneling layer 33 is larger, which is beneficial to reduce the read disturbance of the three-dimensional memory 100.

[0081] Exemplarily, the material of the second tunneling sub-layer 332 and the material of the first tunneling sub-layer 331 both include carbon, and the mass percentage of the carbon in the second tunneling sub-layer 332 is less than the mass percentage of the carbon in the first tunneling sub-layer 331 .

[0082] In this case, the material of the third sub-tunneling layer 333 may not include carbon elements, for example, the material of the third sub-tunneling layer 333 may include silicon oxide.

[0083] By adopting the above-mentioned setting method, the mass percentage of carbon element in the first tunneling sub-layer 331 can be larger, and the dielectric constant of the first tunneling sub-layer 331 can be smaller, so that the voltage proportions allocated to each tunneling sub-layer in the tunneling layer are different, and the first tunneling sub-layer 331 is allocated with more voltage, which is beneficial to reduce the read interference of the three-dimensional memory 100.

[0084] In the case where the tunneling layer 33 includes at least three sub-tunneling layers, the multiple sub-tunneling layers are stacked in sequence in a direction away from the capture layer 32. Along the direction from the channel layer 34 to the capture layer 32, the dielectric constants of the various sub-tunneling layers decrease in sequence. Along the direction from the channel layer 34 to the capture layer 32, the dielectric constants of the various sub-tunneling layers may also decrease in a stepwise manner. In each sub-tunneling layer between the channel layer 34 and the capture layer 32, the greater the distance between the sub-tunneling layer and the capture layer 32, the greater the dielectric constant of the sub-tunneling layer, and the less voltage is allocated to the sub-tunneling layer, which is conducive to improving the programming speed and the erasing speed.

[0085] Some embodiments of the present disclosure also provide a method for preparing a three-dimensional memory 100, which is used to prepare the three-dimensional memory 100 in the above embodiments. Figure 8 As shown, the preparation method includes: S100~S300.

[0086] S100, such as Fig. 9 As shown, a three-dimensional array structure 101 is provided; the three-dimensional array structure 101 includes a substrate 10 and a stacked structure 20 arranged on one side of the substrate 10 .

[0087] Exemplarily, the stacked structure 20 includes a plurality of gate layers 21 and a plurality of gate dielectric layers 22 that are alternately stacked. For the features of the gate layers 21 and the gate dielectric layers 22, reference may be made to the description in the above embodiments of the present disclosure, which will not be repeated here.

[0088] S200, such as Fig.10 As shown, a channel hole 35 is formed penetrating the stacked structure 20 .

[0089] For example, the channel hole 35 may be formed by using a dry etching process or a wet etching process.

[0090] For example, the channel hole 35 may extend to the inside of the substrate 10 .

[0091] S300, such as Fig.11 As shown, a barrier layer 31 , a capture layer 32 , a tunnel layer 33 and a channel layer 34 in the channel structure 30 are sequentially formed in the channel hole 35 ; the dielectric constant of the tunnel layer 33 is smaller than the dielectric constant of the capture layer 32 .

[0092] Exemplarily, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any other combination of thin film deposition processes can be used to deposit the material of the storage functional film layer in the channel hole 35 to form a blocking layer 31, a capture layer 32, a tunneling layer 33 and a channel layer 34 in sequence.

[0093] In the three-dimensional memory 100 formed by the above-mentioned preparation method, the dielectric constant of the tunneling layer 33 is smaller than the dielectric constant of the blocking layer 31, so that when the three-dimensional memory 100 is performing a read, program or erase operation, a larger voltage is allocated to the tunneling layer 33, thereby improving its programming or erasing speed and reducing read interference.

[0094] In some embodiments, forming the tunneling layer 33 in the above S300 includes: using an atomic deposition process to introduce a reaction gas into the channel hole 35 to form the tunneling layer 33 .

[0095] Illustratively, the reaction gas may be a mixed gas composed of multiple gases.

[0096] Exemplarily, the component of the reaction gas includes carbon element. The reaction gas containing carbon element can be an organic gas or an inorganic gas, for example, carbon dioxide, carbon monoxide, ethylene, propylene or triethylamine.

[0097] The tunneling layer 33 is formed by the above-mentioned preparation method, so that the texture of the tunneling layer 33 is relatively compact, and the uniformity and consistency of the tunneling layer 33 are relatively good, thereby ensuring that the tunneling layer 33 has a good morphology.

[0098] For example, the reaction gas may include hexachlorodisilane, ammonia, oxygen, carbon monoxide, etc.

[0099] Exemplarily, the preparation process of the barrier layer 31 and the capture layer 32 may also be an atomic deposition process. Therefore, the storage function layer can be formed in the same preparation process, simplifying the preparation process of the three-dimensional memory 100.

[0100] For example, the material of the barrier layer 31 is silicon oxide, the material of the capture layer 32 is silicon nitride, and the material of the tunneling layer 33 is silicon oxynitride and silicon carbide. First, the barrier layer 31 and the capture layer 32 are formed in the channel hole 35. At this time, only hexachlorodisilane, ammonia, oxygen, etc. are introduced to react to form silicon oxide and silicon nitride. After the barrier layer 31 and the capture layer 32 are formed, carbon monoxide gas is introduced at the same time on the basis of the above-mentioned gases to form a tunneling layer 33 containing carbon elements.

[0101] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: The three-dimensional memory comprises: A stacked structure comprising a plurality of gate layers and a plurality of gate dielectric layers stacked alternately; A channel structure running through the stacked structure, the channel structure comprising a barrier layer, a capture layer, a tunnel layer and a channel layer stacked in sequence; Wherein, the dielectric constant of the tunneling layer is smaller than the dielectric constant of the capture layer.

2. The three-dimensional memory according to claim 1, characterized in that: The material of the tunneling layer includes carbon element; the mass percentage of the carbon element in the material of the tunneling layer is α, and α≤50%.

3. The three-dimensional memory according to claim 1, characterized in that: The tunneling layer at least includes a first sub-tunneling layer and a second sub-tunneling layer which are stacked; compared with the second sub-tunneling layer, the first sub-tunneling layer is closer to the capture layer; and the dielectric constant of the first sub-tunneling layer is smaller than the dielectric constant of the second sub-tunneling layer.

4. The three-dimensional memory according to claim 3, characterized in that: The material of the first tunneling sub-layer includes carbon.

5. The three-dimensional memory according to claim 3, characterized in that: The tunneling layer further includes a third sub-tunneling layer located in the second sub-tunneling layer away from the first sub-tunneling layer; The dielectric constant of the third sub-tunneling layer is different from the dielectric constant of the second sub-tunneling layer.

6. The three-dimensional memory according to claim 5, characterized in that: The material of the second tunneling sub-layer and the material of the first tunneling sub-layer both include carbon, and the mass percentage of the carbon in the second tunneling sub-layer is smaller than the mass percentage of the carbon in the first tunneling sub-layer.

7. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: The material of the tunneling layer further includes silicon oxynitride.

8. A method for preparing a three-dimensional memory, characterized in that: include: Providing a three-dimensional array structure; The three-dimensional array structure includes a substrate and a stacked structure arranged on one side of the substrate; forming a channel hole penetrating the stacked structure; A barrier layer, a capture layer, a tunnel layer and a channel layer in a channel structure are sequentially formed in the channel hole; the dielectric constant of the tunnel layer is smaller than the dielectric constant of the capture layer.

9. The preparation method according to claim 8, characterized in that: The forming of the tunneling layer comprises: using an atomic deposition process to introduce a reaction gas into the channel hole to form the tunneling layer.

10. The preparation method according to claim 9, characterized in that: The components of the reaction gas include carbon element.

11. A storage system, characterized in that: The storage system comprises: a controller, and the three-dimensional memory according to any one of claims 1 to 7; wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

12. An electronic device, characterized in that: The electronic device comprises: the memory system as claimed in claim 11, and a circuit board electrically connected to the memory system.

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