Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device structure is provided. The semiconductor device structure includes: a source / drain (S / D) feature disposed over a substrate and between two adjacent semiconductor layers; an internal spacer disposed between the one semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate; and a dielectric layer structure disposed between the S / D feature and the substrate. The dielectric layer structure includes: a first dielectric layer in contact with the internal spacer and the substrate; the second dielectric layer is nested in the first dielectric layer, and the bottom surface and the side wall surface of the second dielectric layer are in contact with the first dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking presents new challenges. For example, it becomes increasingly challenging to reduce parasitic capacitance between source / drain features and gates while maintaining the required K value for the device. Improved structures and methods for making them are needed. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device structure is provided, comprising: a source / drain (S / D) feature, disposed above a substrate and located between two adjacent semiconductor layers; an internal spacer, disposed between a semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate; and a dielectric layer structure, disposed between the S / D feature and the substrate, the dielectric layer structure comprising: a first dielectric layer, in contact with the internal spacer and the substrate; and a second dielectric layer, nested within the first dielectric layer, wherein a bottom surface and a sidewall surface of the second dielectric layer are in contact with the first dielectric layer.

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; forming an internal spacer at an edge of the second semiconductor layer, wherein the internal spacer has a first film property; forming a dielectric layer on the sacrificial gate structure, the internal spacer, the first semiconductor layer of the fin structure, and an exposed surface of the substrate; performing a first processing process so that the dielectric layer over the sidewall surface of the sacrificial gate structure, the first semiconductor layer of the fin structure, and the internal spacer has a second film property different from the first film property of the internal spacer; removing the dielectric layer formed over the sacrificial gate structure, the first semiconductor layer of the fin structure, and the sidewall surface of the internal spacer without affecting the dielectric layer formed over the exposed surface of the substrate; and forming source / drain features over the dielectric layer.

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: depositing a sacrificial gate structure on a portion of a fin structure formed from a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; replacing an edge portion of the second semiconductor layer of each of the first fin structure and the second fin structure with a dielectric material to form an internal spacer; forming a first dielectric layer on the exposed surface of the internal spacer, the sacrificial gate structure, the first semiconductor layer of the fin structure, and the substrate; The present invention relates to a first semiconductor layer of the fin structure and a second dielectric layer formed on the substrate; removing the first dielectric layer and the second dielectric layer from the sidewall surface of the inner spacer, the sacrificial gate structure and the first semiconductor layer of the fin structure; forming a source / drain feature on the first dielectric layer and the second dielectric layer disposed on the exposed surface of the substrate, wherein the bottom surface of the source / drain feature and the first dielectric layer and the second dielectric layer are exposed to air; removing the plurality of second semiconductor layers to expose a portion of the first semiconductor layer of the fin structure; and forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figure 1-Figure 8 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0008] Figures 9A-10A and Figures 15A-21A According to some embodiments, Figure 8 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0009] Figure 9A-1 is a cross-sectional side view of a semiconductor device structure according to an alternative embodiment.

[0010] Figure 9B-Figure 10B and Figure 15B-Figure 21B According to some embodiments, Figure 8 Section BB is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0011] Figure 9C-Figure 10C and Figure 15C - Figure 21C According to some embodiments, Figure 8 Section CC is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0012] Figures 11 to 14 According to some embodiments, Figure 8 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0013] Figure 16-1 to Figure 16-5 According to some embodiments Fig.15A An enlarged view of a portion of a semiconductor device structure.

[0014] Figure 16-1a and Figure 16-1b According to some embodiments Figure 16-1 An enlarged view of a portion of a semiconductor device structure.

[0015] Fig.22A and Fig. 22B is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 23 to 35 According to some alternative embodiments, Figure 8 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0017] Figures 36 to 40 According to some embodiments, Fig.28 An enlarged view of a portion of a semiconductor device structure.

[0018] Figure 36-1 a and Figure 36-1 b shows a diagram according to some embodiments Fig.36 An enlarged view of a portion of a semiconductor device structure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, spatially relative terms such as "below," "beneath," "down," "above," "over," "top," "up," and the like may be used herein to describe the relationship of one element or feature relative to another (one or more) element or (one or more) feature as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] The present disclosure relates generally to semiconductor devices, and more particularly to field effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), gate-all-around (GAA) devices (e.g., horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs, vertical FETs, fork-piece FETs, or complementary FETs (CFETs). Although embodiments of the present disclosure are discussed with respect to GAA devices, implementations of some aspects of the present disclosure may be used in other processes and / or other devices. A person of ordinary skill in the art will readily appreciate that other modifications that may be made are contemplated to be within the scope of the present disclosure.

[0022] Figure 1-Figure 40 An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure is shown. It should be understood that additional embodiments of the method may be Figure 1-Figure 40 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limited and may be interchanged.

[0023] Figure 1-Figure 8 is a perspective view of various stages in fabricating a semiconductor device structure 100 in accordance with some embodiments. Figure 22A-22B A flow chart of a method 1000 for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure is shown. Figure 9A-Figure 40 Semiconductor device 100 is schematically shown at various stages of fabrication according to method 1000. It should be understood that additional steps may be provided before, during, and / or after method 1000, and that some of the steps described may be replaced, eliminated, and / or moved for additional embodiments of method 1000.

[0024] At block 1002 , a semiconductor device structure 100 is provided. The semiconductor device structure 100 includes a semiconductor layer stack 104 formed on a substrate 101 . Figure 1As shown. Substrate 101 can be a semiconductor substrate. Substrate 101 may include crystalline semiconductor materials, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb) and indium phosphide (InP). In one embodiment, substrate 101 is made of silicon. In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0025] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopant may be, for example, boron for a p-type field effect transistor (p-type FET) and phosphorus for an n-type field effect transistor (n-type FET).

[0026] The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices (e.g., nanosheet FETs). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108, and the first and second semiconductor layers 106, 108 are arranged parallel to each other. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. In some embodiments, the first semiconductor layer 106 may be made of SiGe having a first Ge concentration range, and the second semiconductor layer 108 may be made of SiGe having a second Ge concentration range that is less than or greater than the first Ge concentration range. In any case, the second semiconductor layer 108 may have a Ge concentration in a range between about 20 at. % (atomic percent) and 30 at. %.

[0027] The thickness of the first semiconductor layer 106 and the second semiconductor layer 108 can vary depending on the application and / or device performance considerations. In some embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 can have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 has a thickness that can be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each first semiconductor layer 106 has a thickness in a range between about 10 nm and about 30 nm, and each second semiconductor layer 108 has a thickness in a range between about 5 nm and about 20 nm. The second semiconductor layer 108 can eventually be removed and used to define the vertical distance between adjacent channels of the semiconductor device structure 100.

[0028] The first semiconductor layer 106 or a portion thereof may form (one or more) nanosheet channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanosheet" is used herein to refer to any material portion having nanometer-scale, even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to both circular and substantially circular elongated material portions, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The (one or more) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. A nanosheet transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate all around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel.

[0029] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Figure 1 Although shown as alternately arranged, it is understood that, according to the predetermined number of nanosheet channels of each FET, any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104. For example, the number of first semiconductor layers 106 (i.e., the number of channels) can be between 2 and 8.

[0030] At block 1004 , a fin structure 112 is formed from the semiconductor layer stack 104 , such as Figure 2As shown. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from the substrate 101. Before forming the fin structure 112, a mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 may include a liner layer 110a and a hard mask 110b. The liner layer 110a may be an oxygen-containing layer, such as a SiO2 layer. The hard mask 110b may be a nitrogen-containing layer, such as a Si3N4 layer. The mask structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0031] The fin structure 112 may be formed by patterning the mask structure 110 using one or more photolithography processes and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include a double patterning or multiple patterning process. In general, the double patterning or multiple patterning process combines the photolithography process with a self-alignment process, thereby allowing a pattern to be created with, for example, a pitch smaller than that obtainable using a single direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure 112. In any case, one or more etching processes pass through the mask structure 110, through the semiconductor layer stack 104, and into the substrate 101 to form trenches 114 in unprotected areas, leaving a plurality of extended fin structures 112. The width W1 of the fin structure 112 along the Y direction may be in the range of about 1.5 nm to about 44 nm, for example, about 2 nm to about 6 nm. The trench 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

[0032] Figure 2 Also shown are fin structures 112 having substantially vertical sidewalls, such that the widths of the fin structures 112 are substantially similar, and each of the first semiconductor layer 106 and the second semiconductor layer 108 in the fin structure 112 is rectangular. In some embodiments, the fin structure 112 may have tapered sidewalls such that the width of each fin structure 112 increases continuously in a direction toward the substrate 101. In this case, each of the first semiconductor layer 106 and the second semiconductor layer 108 in the fin structure 112 may have different widths and be trapezoidal.

[0033] At block 1006 , after forming the fin structures 112 , an insulating material 118 is formed in the trenches 114 between the fin structures 112 , such as Figure 3As shown. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) process and / or an etch-back process is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0034] Thereafter, the insulating material 118 is recessed to form the isolation region 120. After the recess, a portion of the fin structure 112 (e.g., the semiconductor layer stack 104) may protrude from between adjacent isolation regions 120. The isolation region 120 may have a top surface that is flat, convex, concave, or a combination thereof as shown. The recessing of the insulating material 118 reveals the trench 114 between adjacent fin structures 112. The insulating material 118 may be recessed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. When the recess is completed, the top surface of the insulating material 118 may be flush with or lower than the surface of the second semiconductor layer 108 that contacts the well portion 116 formed from the substrate 101.

[0035] At block 1008 , a cladding layer 117 is formed on the exposed portion of the fin structure 112 by an epitaxial process, such as Figure 4 As shown. In some embodiments, a semiconductor liner (not shown) may be first formed over the fin structure 112, and then a cladding layer 117 may be formed over the semiconductor liner. The semiconductor liner may diffuse into the cladding layer 117 during the formation of the cladding layer 117. In either case, the cladding layer 117 is in contact with the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 include the same material with the same etching selectivity. For example, the cladding layer 117 and the second semiconductor layer 108 may be or include SiGe. The cladding layer 117 and the second semiconductor layer 108 may then be removed to create space for a gate electrode layer that is subsequently formed.

[0036] At block 1010, a liner 119 is formed on the cladding layer 117 and on the top surface of the insulating material 118, such as Figure 5 As shown. The liner 119 may include a material having a k value lower than 7, such as SiO2, SiN, SiCN, SiOC or SiOCN. The liner 119 may be formed by a conformal process such as an ALD process. Then, in the trench 114 ( Figure 4) and a dielectric material 121 is formed on the liner 119. The dielectric material 121 may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a k value less than about 7, such as less than about 3. A planarization process such as a CMP process may be performed to remove the liner 119 and the portion of the dielectric material 121 formed on the fin structure 112. A portion of the cladding layer 117 disposed on the hard mask 110 b is exposed after the planarization process.

[0037] Next, the liner 119 and the dielectric material 121 are recessed to the level of the topmost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the top surface of the liner 119 and the dielectric material 121 may be flush with the top surface of the topmost first semiconductor layer 106. The recessing process may be a selective etching process that does not substantially affect the semiconductor material of the cladding layer 117. As a result of the recessing process, trenches 123 are formed between the fin structures 112.

[0038] At block 1012, in the groove 123 ( Figure 5 ) and forming a dielectric material 125 on the dielectric material 121 and the liner 119, such as Figure 6 As shown. The dielectric material 125 may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO or other suitable dielectric materials. In some embodiments, the dielectric material 125 includes a high-k dielectric material (e.g., a material with a k value greater than 7). The dielectric material 125 may be formed by any suitable process, such as a CVD, PECVD, FCVD or ALD process. A planarization process, such as a CMP process, is performed until the hard mask 110b of the mask structure 110 is exposed. The planarization process removes the dielectric material 125 and the portion of the cladding layer 117 disposed above the mask structure 110. The liner 119, the dielectric material 121 and the dielectric material 125 may be collectively referred to as a dielectric feature 127 or a hybrid fin. The dielectric feature 127 is used to separate the subsequently formed source / drain (S / D) epitaxial features and the adjacent gate electrode layer.

[0039] At block 1014, the cladding layer 117 is recessed and the mask structure 110 is removed, as shown. Figure 7As shown. The recessing of the cladding layer 117 can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process can be controlled so that the remaining cladding layer 117 is substantially at the same level as the top surface of the uppermost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process can be a selective etching process that does not significantly affect the dielectric material 125. The removal of the mask structure 110 can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0040] At block 1016 , one or more sacrificial gate structures 130 (only two are shown) are formed over the semiconductor device structure 100 , such as Figure 8 As shown. A sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, followed by patterning and etching processes. For example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof.

[0041] By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed on the opposite side of the sacrificial gate structure 130. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as the channel region of the semiconductor device structure 100. The fin structure 112 partially exposed on the opposite side of the sacrificial gate structure 130 defines the source / drain (S / D) region of the semiconductor device structure 100. In some cases, some S / D regions can be shared between various transistors. For example, various regions in the S / D region can be connected together and implemented as a multifunctional transistor. Although two sacrificial gate structures 130 are shown, more or fewer sacrificial gate structures 130 can be arranged along the X direction in some embodiments.

[0042] Next, a gate spacer 138 is formed on the sidewalls of the sacrificial gate structure 130. The gate spacer 138 can be formed by first depositing a conformal layer, and then etching back the conformal layer to form a sidewall gate spacer 138. For example, a spacer material layer can be conformally disposed on an exposed surface of the semiconductor device structure 100. The conformal spacer material layer can be formed by an ALD process. Subsequently, an anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer (e.g., the top of the fin structure 112, the cladding layer 117, the dielectric material 125) is removed from the horizontal surface, while the gate spacer 138 is left on the vertical surface (e.g., the sidewall of the sacrificial gate structure 130). The gate spacer 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or a combination thereof.

[0043] In some embodiments where the capping layer 117 and the dielectric features 127 are not present, portions of the sacrificial gate structure 130 and the gate spacers 138 are formed on the insulating material 118 , and gaps are formed between exposed portions of the fin structure 112 .

[0044] Figures 9A-10A and Figures 15A-21A According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section AA. Figure 9B-Figure 10B and Figure 15B-Figure 21B According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section BB. Figure 9C-Figure 10C and Figure 15C - Figure 21C According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section CC. Figures 11 to 14 According to some embodiments, Figure 8 1 and 1 . The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken from the cross-sectional view AA. The cross-sectional view AA is located in the plane of the fin structure 112 along the X direction. The cross-sectional view BB is located in a plane perpendicular to the cross-sectional view AA and is located in the sacrificial gate structure 130. The cross-sectional view CC is located in a plane perpendicular to the cross-sectional view AA and is located in the S / D epitaxial feature 146 along the Y direction ( Fig.15A ).

[0045] At block 1018, the exposed portion of the semiconductor layer stack 104 of the fin structure 112, the exposed portion of the capping layer 117, and a portion of the exposed dielectric material 125 not covered by the sacrificial gate structure 130 and the gate spacer 138 are removed to form a recess 139 for the S / D feature, as shown in FIG. Fig.9A and Fig. 9C As shown. The removal of the layer can be accomplished by using one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. One or more etching processes can be performed until the well portion 116 is exposed. The exposed portion of the fin structure 112 can be recessed so that the top surface 101t of the exposed portion of the fin structure 112 is at the level 101 of the bottom surface of the second semiconductor layer 108 in contact with the well portion 116 of the substrate 101.

[0046] In some embodiments, one or more etching processes are performed so that the top surface 101t of the exposed portion of the fin structure 112 is at a level lower than the interface 113 defined by the bottom surface of the second semiconductor layer 108 and the well portion 116 of the substrate 101. Figure 9A-1 shown.

[0047] At block 1020, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon and / or SiGe having a lower germanium concentration than the second semiconductor layer 108, a wet etchant may be used to selectively etch the second semiconductor layer 108, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0048] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer (or so-called inner spacer) 144, such as Fig. 10A As shown. The internal spacer 144 may be made of SiON, SiCN, SiOC, SiOCN, or SiN. The internal spacer 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing anisotropic etching to remove the portion of the conformal dielectric layer except the internal spacer 144. During the anisotropic etching process, the internal spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the internal spacers 144 along the X direction.

[0049] At block 1022, a first dielectric layer 107a is formed on the exposed surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 and the exposed surface of the substrate 101. Fig.11 As shown. The first dielectric layer 107a can be conformally formed on the top surface and sidewall surface of the sacrificial gate structure 130. In some embodiments, the first dielectric layer 107a is deposited so that the first dielectric layer 107a is located on a horizontal surface of the semiconductor device structure 100, for example, the top surface of the sacrificial gate structure 130 has a rounded head or a curved (e.g., convex) profile. The first dielectric layer 107a serves as a sidewall etch stop layer that protects the inner spacer 144 from downstream etching processes (e.g., removing the second dielectric layer 107b ( Fig.12 )) during the process. The first dielectric layer 107a on the top surface of the substrate 101 becomes a barrier layer for reducing epitaxial source / drain leakage and reducing parasitic capacitance between source / drain features and the gate. The first dielectric layer 107a on the top surface of the sacrificial gate structure 130 may have a thickness H0, and due to the high aspect ratio of the recess 139 between two adjacent sacrificial gate structures 130, the first dielectric layer 107a on the top surface of the substrate 101 has a thickness H1 that is less than the thickness H0.

[0050] The first dielectric layer 107a may be deposited such that the highest point (e.g., the center point) of the first dielectric layer 107a on the top surface of the substrate 101 is at a height higher than, equal to, or lower than the interface 109 defined by the bottommost first semiconductor layer 106 and the bottommost inner spacer 144. Figure 9A-1 In some cases of the embodiments, the highest point of the first dielectric layer 107 a on the top surface of the substrate 101 is at a height between the bottom surface of the bottommost inner spacer 144 and the top surface 101 t of the substrate 101 .

[0051] In some embodiments, the first dielectric layer 107a is deposited such that the highest point (e.g., the center point) of the first dielectric layer 107a on the top surface of the substrate 101 is at substantially the same height as the interface 109 defined by the bottommost first semiconductor layer 106 and the bottommost internal spacer 144.

[0052] The first dielectric layer 107a may include or be formed of an oxide-based material. In some embodiments, the first dielectric layer 107a includes silicon. Exemplary materials for the first dielectric layer 107a may include, but are not limited to, SiO2, SiON, SiOC, etc. The first dielectric layer 107a may be deposited using ALD, CVD, or any suitable conformal deposition technique.

[0053] At block 1024, a second dielectric layer 107b is formed on the first dielectric layer 107a. Fig.12 As shown. The second dielectric layer 107b may be conformally formed on the exposed surface of the first dielectric layer 107a. In some embodiments, the second dielectric layer 107b is deposited so that the second dielectric layer 107b follows the contour of the first dielectric layer 107a. The second dielectric layer 107b may work with the first dielectric layer 107a to help reduce epitaxial source / drain leakage and reduce parasitic capacitance between source / drain features and the gate. In some embodiments, the second dielectric layer 107b above the top surface of the sacrificial gate structure 130 may have a thickness H2, and due to the high aspect ratio of the recess 139 between two adjacent sacrificial gate structures 130, the second dielectric layer 107b above the top surface of the substrate 101 has a thickness H3 that is less than the thickness H2. In some embodiments, the thickness H2 is less than the thickness H0. The thicker first dielectric layer 107a allows the second dielectric layer 107b to be removed without affecting the integrity of the internal spacer 144. In some embodiments, the thickness H2 is substantially equal to the thickness H0. In some embodiments, the thickness H2 is greater than the thickness H0.

[0054] In various embodiments, the second dielectric layer 107b may include a nitride-based material or be formed of a nitride-based material. In some embodiments, the first dielectric layer 107a and the second dielectric layer 107b are formed of materials that are chemically different from each other. For example, the first dielectric layer 107a may be formed of a nitride-based material, and the second dielectric layer 107b may be formed of an oxide-based material. In some embodiments, the second dielectric layer 107b includes silicon. Exemplary materials for the second dielectric layer 107b may include, but are not limited to, SiN, SiON, SiCN, SiOCN, etc. The second dielectric layer 107b may be deposited using ALD, CVD, or any suitable conformal deposition technique.

[0055] The second dielectric layer 107b may be deposited by a plasma-based deposition process. The deposition process may be anisotropic. Due to the high aspect ratio of the recess 139 between adjacent sacrificial gate structures 130, the anisotropic plasma may cause the second dielectric layer 107b to be deposited with different film densities, growth rates, and etching rates, etc. For example, the second dielectric layer 107b above the sacrificial gate structure 130 and the top surface of the substrate 101 may have a first film property, and the second dielectric layer 107b above the sidewall surface of the sacrificial gate structure 130 and the semiconductor layer stack 104 may have a second film property different from the first film property.

[0056] At block 1026, an etching process 175-1 is performed on the semiconductor device structure 100 to remove a portion of the first dielectric layer 107a and the second dielectric layer 107b, such as Fig.13 The etching process 175-1 may be performed in an isotropic or anisotropic manner so that the thickness of the second dielectric layer 107b on the top surface and sidewall surface of the sacrificial gate structure 130 and the second dielectric layer 107b on the top surface of the substrate 101 is reduced. For example, the thickness of the second dielectric layer 107b on the top surface of the sacrificial gate structure 130 may be reduced from a thickness H2( Fig.12 ) is reduced to H2', and the thickness of the second dielectric layer 107b above the top surface of the substrate 101 is increased from H3 ( Fig.12 ) is reduced to H3'. Since the second dielectric layer 107b has different film properties between the top surface of the sacrificial gate structure 130 and the sidewall surface of the sacrificial gate structure 130, the first dielectric layer 107a and the second dielectric layer 107b are removed at different rates. After the etching process 175-1, the second dielectric layer 107b above the sidewall surface of the sacrificial gate structure 130 is completely removed, and the first dielectric layer 107a above the sidewall surface of the sacrificial gate structure 130 has a thickness that can be reduced from H4 ( Fig.12 ) is reduced to H4'. The etching process 175-1 may be performed so that the first dielectric layer 107a and the second dielectric layer 107b above the top surface of the substrate 101 are etched with different profiles, as will be shown in FIG. Figure 16-1 to Figure 16-5 discussed in more detail in .

[0057] During the removal of the second dielectric layer 107b, the first dielectric layer 107a protects the internal spacer 144. If the first dielectric layer 107a is not present, the internal spacer 144 may be damaged and form a dishing profile when the second dielectric layer 107b is removed. The dishing profile of the internal spacer 144 can act as a weak point and allow the etchant used in the subsequent pre-cleaning process (before forming the epitaxial S / D features 146) to further consume the internal spacer 144 and cause air gaps therein. After the epitaxial S / D features 146 are formed, the air gap is confined between the epitaxial S / D features 146 and the internal spacer 144, thereby affecting the yield and performance of the device. The use of the first dielectric layer 107a creates an etching rate difference between the sidewall surfaces of the internal spacer 144 and the first dielectric layer 107a, so as to reduce the dishing phenomenon on the internal spacer 144. As a result, the integrity of the inner spacers 144 is preserved after removal of the second dielectric layer 107b and a subsequent pre-cleaning process.

[0058] The etching process 175-1 may be dry etching, wet etching, or a combination thereof. In some embodiments, the etching process 175-1 is a wet etching process using NH4OH, HF or diluted HF, deionized (DI) water, tetramethylammonium hydroxide (TMAH), other suitable solutions, or a combination thereof. In some embodiments, the etching process 175-1 may be a standard clean 2 (SC2) followed by a standard clean 1 (SC1), wherein SC2 is a mixture of DI water, hydrochloric acid (HCl), and hydrogen peroxide (H2O2), and SC1 is a mixture of DI water, NH4OH, and H2O2. In some embodiments, isopropyl alcohol (IPA) may be used after SC1. Other suitable wet etching processes may also be used, such as: an APM process, including at least water (H2O), ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2); an HPM process, including at least H2O, H2O2 and hydrogen chloride (HCl); an SPM process (also known as piranhaclean), including at least H2O2 and sulfuric acid (H2SO4) or any combination thereof.

[0059] In some embodiments, etching process 175-1 is a dry etching process using plasma or material radicals. For example, etching process 175-1 can use reactive species generated in situ by hydrogen-containing gas in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). In some embodiments, etching process 175-1 is a plasma etching process. Exemplary reactive species may include hydrogen plasma or neutral radical species of hydrogen, such as hydrogen radicals or atomic hydrogen. Other chemicals may also be used, such as fluorine-containing, chlorine-containing or oxygen-containing gases, or combinations thereof. The plasma etching process may be any suitable plasma-based process, such as a decoupled plasma process, a remote plasma process, or a combination thereof. The plasma may be formed by a capacitively coupled plasma (CCP) source or an inductively coupled plasma (ICP) source driven by an RF power generator.

[0060] At block 1028, a pre-cleaning process is performed to remove the first dielectric layer 107a on the sidewall surface of the sacrificial gate structure 130. Fig.14As shown. The pre-cleaning process may use an etchant that selectively removes the first dielectric layer 107a without substantially affecting the internal spacer 144. When the first dielectric layer 107a above the sidewall surface of the sacrificial gate structure 130 is removed, the recess 139 is revealed, and the gate spacer 138, the first semiconductor layer 106, and the internal spacer 144 are exposed. The first dielectric layer 107a and the second dielectric layer 107b above the top surface of the substrate 101 form a dielectric layer structure 107. The pre-cleaning process may be any suitable wet etching process, such as the wet etching discussed above with respect to the etching process 175-1. In some embodiments, the pre-cleaning may use a diluted HF solution. When the first dielectric layer 107a is removed from the sidewall surface of the sacrificial gate structure 130, the first dielectric layer 107a and the second dielectric layer 107b above the top surface of the substrate 101 may be slightly etched. The pre-cleaning process can enhance the etching profile of the first dielectric layer 107a and the second dielectric layer 107b above the top surface of the substrate 101, as will be described in detail in Figure 16-1 to Figure 16-5 discussed in more detail in .

[0061] At block 1030, epitaxial source / drain (S / D) features 146 are formed in the S / D regions, such as Figure 15A-Figure 15C As shown. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial S / D feature 146 by an internal spacer 144. The epitaxial S / D feature 146 may include one or more layers of Si, SiP, SiC and SiCP for n-type FETs or one or more layers of Si, SiGe, Ge for p-type FETs. The epitaxial S / D feature 146 may be formed by using an epitaxial growth method such as selective epitaxial growth (SEG), CVD, ALD or MBE. The epitaxial S / D feature 146 may be an S / D region. For example, one of a pair of epitaxial S / D features 146 located on one side of the sacrificial gate structure 130 may be a source region, and the other of a pair of epitaxial S / D features 146 located on the other side of the sacrificial gate structure 130 may be a drain region. A pair of S / D epitaxial features 146 include a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). The source / drain region(s) may be referred to individually or collectively as a source or a drain, depending on the context. In this separation, source and drain may be used interchangeably and their structures are substantially the same.

[0062] The epitaxial S / D features 146 may be grown laterally from the sidewalls of the first semiconductor layer 106. The epitaxial S / D features 146 of the fin structure may merge with the epitaxial S / D features 146 of the adjacent fin structure and form an integrated body. The epitaxial S / D features 146 may grow in both vertical and horizontal ways to form facets that may correspond to crystal planes of the material used for the first semiconductor layer 106. Since the semiconductor (i.e., the epitaxial S / D features 146) may not grow or may not grow well on the dielectric material (e.g., the first dielectric layer 107a and the second dielectric layer 107b), the bottom portion of the epitaxial S / D features 146 may be separated from the first dielectric layer 107a and the second dielectric layer 107b by the air gap 115. The air gap 115 may effectively reduce the epitaxial source / drain features 146 and subsequent gate electrode layers (e.g., the gate electrode layer 182, Fig. 20A ) between them. In some embodiments, the bottom surface 146 b of each epitaxial S / D feature 146 may have a curved surface, such as a concave shape.

[0063] Figure 16-1 to Figure 16-5 According to some embodiments Fig.15A FIG. 1 is an enlarged view of a portion of a semiconductor device structure 100. Figure 16-1 , an epitaxial S / D feature 146 is disposed above a first dielectric layer 107a and a second dielectric layer 107b. The second dielectric layer 107b is disposed in the first dielectric layer 107a (or nested in the first dielectric layer 107a), and the second dielectric layer 107b has a sidewall surface and a bottom surface in contact with the first dielectric layer 107a. In some embodiments, a top surface 107at of the first dielectric layer 107a and a top surface 107bt of the second dielectric layer 107b are substantially coplanar. The epitaxial S / D feature 146 is disposed between and in contact with two adjacent first semiconductor layers 106 and an internal spacer 144. The bottom surface 146b of the epitaxial S / D feature 146 may have a curved surface that separates the epitaxial S / D feature from the first dielectric layer 107a and the second dielectric layer 107b by an air gap 115. The air gap 115 is defined by the epitaxial S / D features 146, the top surface 107at of the first dielectric layer 107a, and the top surface 107bt of the second dielectric layer 107b.

[0064] In some embodiments, the top surface 107bt of the second dielectric layer 107b is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a vertical distance D1, and the top surface 107at of the first dielectric layer 107a is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a vertical distance D2, and the vertical distance D2 is less than the vertical distance D1.

[0065] In some embodiments, the epitaxial S / D features 146 do not contact the first dielectric layer 107a. In some embodiments, the edge portion of the epitaxial S / D features 146 may slightly contact the first dielectric layer 107a, such as Figure 16-1a In some embodiments, an edge portion of the epitaxial S / D feature 146 contacts the first dielectric layer 107a but does not contact the second dielectric layer 107b. In some embodiments, an edge portion of the epitaxial S / D feature 146 contacts the inner spacer 144 but does not contact the first dielectric layer 107a and the second dielectric layer 107b. Figure 16-1b In this embodiment, the air gap 115 is defined by the epitaxial S / D features 146 , the top surface 107at of the first dielectric layer 107a , the top surface 107bt of the second dielectric layer 107b , and the sidewall surfaces of the inner spacer 144 .

[0066] Figure 16-2 Shown with Figure 16-1 The embodiment is similar to the embodiment of the present invention, except that the top surface 107at of the first dielectric layer 107a and the top surface 107bt of the second dielectric layer 107b are at different heights. For example, the top surface 107at of the first dielectric layer 107a can be at a higher height than the top surface 107bt of the second dielectric layer 107b. In some embodiments, the top surface 107at of the first dielectric layer 107a can be at a lower height than the top surface 107bt of the second dielectric layer 107b.

[0067] Figure 16-3 Shown with Figure 16-2 The embodiment is similar to the embodiment of the embodiment of the present invention, except that the top surface 107bt of the second dielectric layer 107b has a curved surface (e.g., a concave profile), which can be formed due to the isotropic etchant used by the etching process 175-1. In this embodiment, the highest point of the second dielectric layer 107b (e.g., the outer edge of the top surface 107bt of the second dielectric layer 107b) is lower than the top surface 107at of the first dielectric layer 107a.

[0068] Figure 16-4 Shown with Figure 16-3 The embodiment is similar to the embodiment of the present invention, except that the substrate 101 between adjacent replacement gate structures 190 has a curved (e.g., convex) top surface 101t. In this case, the first dielectric layer 107a deposited thereon may have a curved bottom surface that follows the curved contour of the top surface 101t of the substrate 101. Fig.9A), the top surface 101t of the substrate 101 may be etched to have a concave profile. In some cases, a deposition process may be performed to re-deposit a material (e.g., silicon) on the concave top surface so that the top surface 101t of the substrate 101 has a convex profile. Therefore, the first dielectric layer 107a follows the convex profile of the substrate 101. In some embodiments, the top surface 107at of the first dielectric layer 107a may also have a curved profile (e.g., convex). In this case, the top surface 107at of the first dielectric layer 107a may have a first curvature, and the top surface 107bt of the second dielectric layer 107b may have a second curvature different from the first curvature. In some embodiments, the first curvature is greater than the second curvature. In some embodiments, the top surface 107at of the first dielectric layer 107a and the top surface 107bt of the second dielectric layer 107b have a curved profile opposite to the top surface 101t of the substrate 101, such as Figure 16-4 shown.

[0069] Figure 16-5 Shown with Figure 16-4 101, except that the first dielectric layer 107a and the second dielectric layer 107b have a profile that follows the top surface 101t of the substrate 101. In an embodiment where the top surface 101t of the substrate 101 has a curved (e.g., convex) profile, the first dielectric layer 107a and the second dielectric layer 107b are deposited to have a curved (e.g., convex) profile. In some embodiments, the highest point of the second dielectric layer 107b may be at a height lower than the top surface 107at of the first dielectric layer 107a. In some embodiments, the highest point of the second dielectric layer 107b may be at a height higher than the top surface 107at of the first dielectric layer 107a.

[0070] Although in Figure 16-2 to Figure 16-5 Not shown in the embodiments, it is foreseeable that in some embodiments, the top surface 107bt of the second dielectric layer 107b is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a first vertical distance, and the top surface 107at of the first dielectric layer 107a is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a second vertical distance that is less than the first vertical distance.

[0071] At block 1032 , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100 , such as Figure 17A-Figure 17CAs shown. CESL 162 covers the top surface of sacrificial gate structure 130, insulating material 118 and epitaxial S / D feature 146. CESL 162 may include oxygen-containing materials or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc. or a combination thereof, and may be formed by CVD, PECVD, ALD or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162 above semiconductor device structure 100. The material of ILD layer 164 may include compounds containing Si, O, C and / or H, such as silicon oxide, TEOS oxide, SiCOH and SiOC. Organic materials such as polymers may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques.

[0072] At block 1034, after forming the ILD layer 164, a planarization operation such as CMP is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, such as Figures 18A-18C shown.

[0073] At block 1036, the sacrificial gate structure 130 and the second semiconductor layer 108 are sequentially removed, such as Figure 19A-Figure 19C As shown. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the gate spacers 138 and between the adjacent first semiconductor layers 106. The ILD layer 164 protects the epitaxial S / D features 146 during the removal process. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 may be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which may also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0074] The removal of the sacrificial gate structure 130 exposes the first semiconductor layer 106 and the second semiconductor layer 108. An etching process is then performed to remove the second semiconductor layer 108 and expose the internal spacer 144, and the etching process can be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process that removes the second semiconductor layer 108 but does not remove the gate spacer 138, the internal spacer 144, the ILD layer 164, the CESL 162, and the first semiconductor layer 106. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant (such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant (such as a fluorine-based gas (such as F2) or a chlorine-based gas (such as Cl2), or any suitable isotropic etchant. After the etching process, the portion of the first semiconductor layer 106 not covered by the internal spacer 144 is exposed through the opening 166.

[0075] At block 1038, a replacement gate structure 190 is formed, such as Figure 20A-20C As shown. Each replacement gate structure 190 may include an interface layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182. The interface layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106 along the channel region. The IL 178 may include or be made of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.), and / or a dielectric layer (e.g., hafnium silicate) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106. The IL 178 may be formed by CVD, ALD, a cleaning process, or any suitable process. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the IL 178, on the sidewalls of the gate spacer 138, and on the top surface of the first ILD layer 164, the CESL 162, and the inner spacer 144). The gate dielectric layer 180 may include or be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k materials. The gate dielectric layer 180 may be a conformal layer formed by a conformal process such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, or the like, or a combination thereof.

[0076] After forming the IL 178 and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 ( Fig.19A and Fig.19B ) and surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be conformally (and sequentially, if more than one layer) deposited between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier layers and / or capping layers and one or more work function tuning layers. One or more barrier and / or capping layers may include or be nitrides, silicon nitrides, carbon nitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbon nitrides, and / or carbides of tungsten; etc.; or combinations thereof. One or more work function tuning layers may include or be nitrides, silicon nitrides, carbon nitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbon nitrides, and / or carbides of tungsten; cobalt; platinum; etc.; or combinations thereof.

[0077] At block 1040, one or more metal gate etch back (MGEB) processes may be performed on the gate electrode layer 182. The MGEB process is performed such that the top surfaces of the gate electrode layer 182 and the gate dielectric layer 180 are recessed to a level below the top surfaces of the gate spacers 138. In some embodiments, the gate spacers 138 are also recessed to a level below the top surfaces of the ILD layer 164. A self-aligned contact layer 173 is formed between the gate spacers 138, on the gate electrode layer 182 and the gate dielectric layer 180, as shown in FIG. Figure 21A-Figure 21C As shown, the self-aligned contact layer 173 may be a dielectric material having an etching selectivity with respect to the ILD layer 164. In some embodiments, the self-aligned contact layer 173 includes silicon nitride.

[0078] Then, contact openings are formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D features 146. Then, a silicide layer 184 is formed on the S / D epitaxial features 146, and source / drain (S / D) contacts 186 are formed in the contact openings on the silicide layer 184. The S / D contacts 186 may include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The silicide layer 184 may include a metal or metal alloy silicide, and the metal may include a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof. Next, a conductive material is formed in the contact openings and the S / D contacts 186 are formed, such as Fig.21A and Fig. 21B As shown. The conductive material may be made of a material including one or more of the following: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact openings before forming the S / D contacts 186. Then, a planarization process such as CMP is performed to remove excess deposition of the contact material and expose the top surface of the gate electrode layer 182.

[0079] Figure 23-Figure 27 2 shows a semiconductor device 200 at various stages of fabrication according to some alternative embodiments. Fig.23 In the embodiment shown, it is shown that when forming the recess 139 (for example, Fig.9A and 9C ), a dielectric layer 207, such as a first dielectric layer 107a, is formed on the exposed surfaces of the sacrificial gate structure 130, the semiconductor layer stack 104, and the substrate 101 at a stage after the sacrificial gate structure 130. The dielectric layer 207 may be conformally formed on the top surface and the sidewall surface of the sacrificial gate structure 130. Similar to the first dielectric layer 107a, the dielectric layer 207 serves as a protective layer to prevent source / drain leakage and parasitic capacitance between the source / drain features and the gate. The dielectric layer 207 may include the same material as the first dielectric layer 107a and may be formed by the same deposition technique used for the first dielectric layer 107a.

[0080] exist Fig.24, the dielectric layer 207 undergoes a treatment process 177-1 to convert a portion of the dielectric layer 207 into a modified layer. In various embodiments, the treatment process 177-1 may be anisotropic, so that the dielectric layer 207 on the horizontal surface (e.g., the top surface of the sacrificial gate structure 130 and the top surface of the substrate 101) is converted into a first modified layer 207a having a first film property (e.g., a higher film, growth rate, etching rate, etc.), and the dielectric layer 207 on the vertical surface (e.g., the sidewall surface of the sacrificial gate structure 130 and the semiconductor layer stack 104) is converted into a second modified layer 207b having a second film property different from the first film property. In some embodiments, the first modified layer 207a may have a higher film density and a lower etching rate than the second modified layer.

[0081] In some embodiments, the treatment process 177-1 may be a nitridation process using plasma or material radicals. For example, the treatment process 177-1 may use reactive materials generated in situ by nitrogen-containing gas in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). In some embodiments, the treatment process 177-1 is a plasma treatment process. Exemplary reactive materials may include nitrogen plasma or neutral radical materials of nitrogen, such as nitrogen radicals or atomic nitrogen. The plasma treatment may be any suitable plasma process, such as a decoupled plasma process, a remote plasma process, or a combination thereof. The plasma may be formed by a CCP source or an ICP source driven by an RF power generator. In some embodiments, the plasma is a microwave induced plasma with a high frequency or low frequency bias. After the treatment process 177-1, the dielectric layer 207 is nitrided or becomes a nitrided region (i.e., the first modified layer 207a and the second modified layer 207b). In the case where the dielectric layer 207 is formed by silicon oxide, the first modified layer 207a and the second modified layer 207b may be partially or completely converted into silicon oxynitride.

[0082] In the case of using an ICP source, the treatment process 177-1 can be performed in a remote plasma generator. Similarly, the plasma source power can use a continuous wave RF power generator or a pulsed RF power generator operated at a predetermined duty cycle. The source power ionizes the nitrogen-containing gas supplied to the remote plasma generator. Before the generated nitrogen ions are supplied to the processing chamber in which the semiconductor device structure 200 is disposed, the generated nitrogen ions can be filtered to produce neutral radical species (e.g., nitrogen radicals). In an exemplary embodiment, the decoupled plasma process is formed by an ICP source driven by an RF power generator using a tunable frequency from about 2 MHz to about 13.56 MHz, and the processing chamber is operated at a pressure of about 0.5 Torr to about 8 Torr and a temperature of about 300 degrees Celsius to about 600 degrees Celsius for a processing time of about 3 seconds to about 50 seconds. The flow rate of the processing gas (e.g., nitrogen-containing gas) can be provided at about 200 sccm to about 5000 sccm. Suitable nitrogen-containing gases may include, but are not limited to, nitrogen (N2), ammonia (NH3), nitrous oxide (N2O), etc. The RF power generator is operated to provide power between about 50 Watts and about 1000 Watts, and the output of the RF power generator is controlled by a pulse signal having a duty cycle in the range of about 20% to about 80%.

[0083] exist Fig.25 In the embodiment of the present invention, an etching process 175-2, such as etching process 175-1, is performed on the semiconductor device structure 200 to remove a portion of the dielectric layer 207 (e.g., the second modified layer 207b). The etching process 175-2 can be performed in an anisotropic manner so that the first dielectric layer 107a above the sidewall surface of the sacrificial gate structure 130 and the semiconductor layer stack 104 is completely removed. After removing the second modified layer 207b, the internal spacer 144 is exposed. The first modified layer 207a and the second modified layer 207b on the top surface of the substrate 101 form a dielectric layer structure 207c. In some cases, the second modified layer 207b is removed at a faster rate than the first modified layer 207a, and the second modified layer 207b is removed at a faster rate than the internal spacer 144. The etching process 175-2 can continue until the second modified layer 207b is completely removed. The internal spacer 144 remains substantially intact after the etching process 175-2.

[0084] exist Fig.26 In the embodiment, a protective layer 147 is formed on the semiconductor device structure 100. The protective layer 147 may be a polymer, a spin-on carbon material, or other suitable photoresist layer. In one embodiment, the protective layer 147 is a carbon-based polymer. The protective layer 147 protects the first modified layer 207a and the second modified layer 207b from being damaged during a subsequent etch-back process. The protective layer 147 may be deposited until it overfills the recess 139 ( Fig.25 ). The protective layer 147 may be deposited using spin coating or any suitable deposition process. Then, an etch-back process is performed to remove a portion of the protective layer 147. The protective layer 147 may be recessed so that the top surface of the protective layer 147 is at a height between the interface 109 defined by the bottommost first semiconductor layer 106 and the bottommost internal spacer 144 and the interface defined by the gate spacer 138 and the topmost first semiconductor layer 106. In some embodiments, the protective layer 147 is recessed so that the top surface of the protective layer 147 is high enough to cover the first modified layer 207a and the second modified layer 207b. Alternatively, the protective layer 147 may be recessed to any desired height until the first modified layer 207a above the sacrificial gate structure 130 is exposed. The etch-back process may be a wet etch, a dry etch, or a combination thereof. The etch-back process may also remove a portion of the first modified layer 207a above the sacrificial gate structure 130.

[0085] exist Fig. 27 In the embodiment of the present invention, the semiconductor device structure 200 is subjected to an etching process 175-3 to remove the first modified layer 207a not covered by the protective layer 147. The etching process 175-3 may be a dry etching, a wet etching, or a combination thereof. The etching process 175-3 may be performed isotropically or anisotropically. After the etching process 175-3, the top surface of the sacrificial gate structure 130 is exposed. Removing the first modified layer 207a from the top surface of the sacrificial gate structure 130 may be advantageous because it prevents the first modified layer 207a from being undesirably merged on two adjacent sacrificial gate structures 130, or narrowing the opening of the recess 139, which may result in the formation of a seam in a subsequent interlayer dielectric (ILD) layer 164, and thereby causing degradation in the performance of the device.

[0086] exist Fig.28 In the embodiment of the present invention, the protective layer 147 is removed and the epitaxial S / D features 146 are formed. The protective layer 147 can be removed using any suitable process (e.g., an ashing process or any suitable process). The epitaxial S / D features 146 can be formed using the same process as described above. Figure 15A-Figure 15C Since the semiconductor (i.e., epitaxial S / D feature 146) may not grow or grow well on the dielectric material (e.g., first modified layer 207a and second modified layer 207b), the bottom portion of epitaxial S / D feature 146 may be separated from the first modified layer 207a and second modified layer 207b by air gap 215. The semiconductor device structure 200 may undergo further processes, such as those described above with respect to Figure 15A-Figure 15C and Figure 17A-Figure 17C to Figure 21A-Figure 21C The process described.

[0087] Figure 29-Figure 31FIG. 3 shows a semiconductor device structure 300 at various stages of fabrication according to some alternative embodiments. Fig.24 The semiconductor device structure 200 shown in FIG. 1 is substantially the same as that shown in FIG. 1 , except that Fig.29 The sidewall surfaces (eg, Fig.25 ) after removing the second modified layer 207b. It can be seen that the semiconductor device structure 300 undergoes the treatment process 177-2 to further convert the first modified layer 207a above the top surface of the sacrificial gate structure 130 into a third modified layer 207c having a third film property. The treatment process 177-2 allows the third modified layer 207c to be easily removed during a subsequent pre-cleaning process (for the epitaxial S / D feature 146). Due to the high aspect ratio of the recess 139, the first modified layer 207a and the second modified layer 207b at the bottom of the recess 139 (e.g., the first modified layer 207a and the second modified layer 207b above the top surface of the substrate 101) can have minimal impact from the treatment process 177-2. In most cases, the third film property of the third modified layer 207c is different from the film property possessed by the first modified layer 207a and the second modified layer 207b above the top surface of the substrate 101. In some embodiments, the second modified layer 207 b may have a higher etch rate than the first modified layer 207 a , and the etch rate of the first modified layer 207 a may be higher than the etch rate of the inner spacer 144 .

[0088] Treatment process 177-2 can be a plasma treatment or a treatment using a material radical. For example, treatment process 177-2 can use a reactive material generated in situ by an oxygen-containing gas in a reaction chamber or upstream of a reaction chamber (e.g., from a remote plasma generator). Exemplary reactive materials can include oxygen plasma or neutral radical materials of oxygen, such as oxygen radicals or atomic oxygen. In the case of using plasma treatment, the plasma can be formed by a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source driven by an RF power generator, or can be a microwave induced plasma with ion filtration.

[0089] exist Fig.30 In the etching process 175-4, for example, as described above with reference to Fig.13The etching process 175-1 discussed above is performed to remove the third modified layer 207c from the top surface of the sacrificial gate structure 130. Removing the first modified layer 207a from the top surface of the sacrificial gate structure 130 can be advantageous because it prevents the third modified layer 207c from undesirably merging on two adjacent sacrificial gate structures 130, or narrowing the opening of the recess 139, which may result in the formation of a seam in a subsequent interlayer dielectric (ILD) layer 164 and thereby degrade the performance of the device. Due to the high aspect ratio of the recess 139, the first modified layer 207a and the second modified layer 207b at the bottom of the recess 139 (e.g., the first modified layer 207a and the second modified layer 207b on the top surface of the substrate 101) can have minimal impact from the etching process 175-1.

[0090] exist Fig.31 In the embodiment of the present invention, the epitaxial S / D features 146 are formed on the first modified layer 207a and the second modified layer 207b. The epitaxial S / D features 146 can be formed using the same method as described above with respect to Figure 15A-Figure 15C Since the semiconductor (i.e., epitaxial S / D feature 146) may not grow or grow well on the dielectric material (e.g., first modified layer 207a and second modified layer 207b), the bottom portion of epitaxial S / D feature 146 may be separated from the first modified layer 207a and second modified layer 207b by air gap 315. Similarly, semiconductor device structure 300 may undergo further processes, such as those described above with respect to Figure 15A-Figure 15C and Figure 17A-Figure 17C to Figure 21A-Figure 21C Describe the process.

[0091] Figure 32-Figure 35 FIG. 4 shows a semiconductor device structure 400 at various stages of fabrication according to some alternative embodiments. Fig.23 The semiconductor device structure 200 is similar to that shown in FIG. 1 , which shows the formation of the recess 139 (eg, Fig.9A and Fig. 9C ) stage. Fig.32 In the embodiment of the present invention, a dielectric layer 307, such as the first dielectric layer 107a, is formed on the exposed surfaces of the sacrificial gate structure 130, the semiconductor layer stack 104, and the substrate 101 in a manner similar to the first dielectric layer 107a. Likewise, the dielectric layer 307 serves as a protective layer to prevent source / drain leakage and parasitic capacitance between the source / drain features and the gate.

[0092] exist Fig.33In some embodiments, the treatment process 177-3 is performed on the semiconductor device structure 400 so that the dielectric layer 307 has different film properties in different regions. In some embodiments, the treatment process 177-3 is performed so that the dielectric layer 307 above the upper portion of the sacrificial gate structure 130 is converted into a first modified layer 307a having a first film property, and the dielectric layer 307 above the sidewall surface of the semiconductor layer stack 104 and the top surface of the substrate 101 is converted into a second modified layer 307b having a second film property different from the first film property. Therefore, the treatment process 177-3 produces an etching rate difference between the first modified layer 307a and the second modified layer 307b so as to reduce the recess phenomenon on the internal spacer 144, as described above. The treatment process 177-3 also allows the first modified layer 307a ( Fig.34 ). The second modified layer 307b remains substantially intact and protects the internal spacer 144 during the subsequent removal of the first modified layer 307a.

[0093] Treatment process 177-3 can use isotropic plasma or free radical species. For example, treatment process 177-3 can use reactive species produced in situ by oxygen-containing gas in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). Exemplary reactive species can include oxygen plasma or neutral free radical species of oxygen, such as oxygen free radicals or atomic oxygen. Other reactive species, such as fluorine-based or hydrogen-based plasmas, can also be used. In the case of using plasma treatment, the plasma can be formed by a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source driven by an RF power generator, or can be a microwave induced plasma with ion filtering.

[0094] exist Fig.34 In the etching process 175-5, for example, as described above with reference to Fig.25 The etching process 175-2 discussed above is performed to remove the first modified layer 307a from the upper portion of the sacrificial gate structure 130. After the etching process 175-5, a portion of the second modified layer 307b over the sidewall surface of the semiconductor layer stack 104 and the top surface of the substrate 101 may be etched. The second modified layer 307b protects the inner spacer 144 from being damaged during the etching process 175-5.

[0095] exist Fig.35In the embodiment of the present invention, a pre-cleaning process is performed to remove the second modified layer 307b from the sidewall surfaces of the semiconductor layer stack 104. Due to the high aspect ratio of the recess 139, the second modified layer 307b on the top surface of the substrate 101 remains substantially intact. When the second modified layer 307b is removed from the sidewall surfaces of the sacrificial gate structure 130, the recess 139 is revealed and the internal spacer 144 is exposed. The pre-cleaning process may use a diluted HF solution or any suitable etching process. The pre-cleaning process may enhance the etching profile of the second modified layer 307b on the top surface of the substrate 101, as will be seen in FIG. Figure 39-40 After the pre-cleaning process, the epitaxial S / D features 146 are formed on the second modified layer 307b. The epitaxial S / D features 146 may be formed using the same techniques as described above with respect to Figure 15A-Figure 15C Since the semiconductor (i.e., epitaxial S / D feature 146) may not grow or grow poorly on the dielectric material (e.g., second modified layer 307b), the bottom portion of the epitaxial S / D feature 146 may be separated from the second modified layer 307b by the air gap 415. Similarly, the semiconductor device structure 400 may undergo further processes, such as those described above with respect to Figure 15A-Figure 15C and Figure 17A-Figure 17C to Figure 21A-Figure 21C The process described.

[0096] Figure 36-Figure 40 According to some embodiments Fig.28 FIG. 2 is an enlarged view of a portion of the semiconductor device structure 200 shown in FIG. 2 . Although not shown, these embodiments are also applicable to Fig.31 The semiconductor device structure 300 and Fig.35 and 400. exist Fig.36 , the epitaxial S / D feature 146 is disposed above the first modified layer 207a and the second modified layer 207b. In some embodiments, the first modified layer 207a is surrounded by the second modified layer 207b. The top surfaces of the first modified layer 207a and the second modified layer 207b are substantially coplanar. The bottom surfaces of the first modified layer 207a and the second modified layer 207b are in contact with the top surface of the substrate 101. The epitaxial S / D feature 146 is disposed between two adjacent first semiconductor layers 106 and the inner spacer 144 and in contact with the first semiconductor layer 106 and the inner spacer 144. The bottom surface 146b of the epitaxial S / D feature 146 may have a curved surface that separates the epitaxial S / D feature 146 from the first modified layer 207a and the second modified layer 207b by the air gap 215. The air gap 215 is defined by the epitaxial S / D features 146 , the top surface 207at of the first modified layer 207a , and the top surface 207bt of the second modified layer 207b .

[0097] In some embodiments, the epitaxial S / D feature 146 does not contact the first modified layer 207a and the second modified layer 207b. In some embodiments, the edge portion of the epitaxial S / D feature 146 may slightly contact the second modified layer 207b, such as Figure 36-1 In some embodiments, the edge portion of the epitaxial S / D feature 146 contacts the second modified layer 207b but does not contact the first modified layer 207a. In some embodiments, the edge portion of the epitaxial S / D feature 146 contacts the inner spacer 144 but does not contact the first modified layer 207a and the second modified layer 207b. Figure 36-1 In this embodiment, the air gap 215 is defined by the epitaxial S / D features 146, the top surface 207at of the first modified layer 207a, the top surface 207bt of the second modified layer 207b, and the sidewall surfaces of the inner spacer 144.

[0098] In some embodiments, the top surface 207at of the first modified layer 207a is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a vertical distance D3, and the top surface 207bt of the second modified layer 207b is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a vertical distance D4, which is less than the vertical distance D3.

[0099] Fig.37 Shown with Fig.36 The embodiment is similar to the embodiment of the present invention, except that the top surface 207at of the first modified layer 207a and the top surface 207bt of the second modified layer 207b are at different heights. For example, the top surface 207at of the first modified layer 207a can be at a lower height than the top surface 207bt of the second modified layer 207b. In some embodiments, the top surface 207at of the first modified layer 207a can be at a higher height than the top surface 207bt of the second modified layer 207b.

[0100] Fig.38 Shown with Fig.37 The embodiment is similar to the embodiment of the embodiment of the present invention, except that the top surface 207at of the first modified layer 207a has a curved surface (e.g., a concave profile), which can be formed due to the isotropic etchant used in the etching process 175-2. In this embodiment, the highest point of the first modified layer 207a (e.g., the outer edge of the top surface 207at of the first modified layer 207a) is lower than the top surface 207bt of the second modified layer 207b.

[0101] Fig.39 Shown with Fig.38The embodiment is similar to the embodiment of the present invention, except that the substrate 101 between adjacent replacement gate structures 190 has a curved (e.g., convex) top surface 101t. In this case, the first modified layer 207a deposited thereon may have a curved bottom surface that follows the curved profile of the top surface 101t of the substrate 101. In some embodiments, the top surface 207bt of the second modified layer 207b may also have a curved profile (e.g., convex). In this case, the top surface 207at of the first modified layer 207a may have a first curvature, and the top surface 207bt of the second modified layer 207b may have a second curvature less than the first curvature. In some embodiments, the top surface 207at of the first modified layer 207a and the top surface 207bt of the second modified layer 207b have a curved profile opposite to the top surface 101t of the substrate 101.

[0102] Fig.40 Shown with Fig.39 101, except that the first modified layer 207a and the second modified layer 207b have a profile that follows the top surface 101t of the substrate 101. In an embodiment where the top surface 101t of the substrate 101 has a curved (e.g., convex) profile, the first modified layer 207a is deposited to have a curved (e.g., convex) profile. In some embodiments, the highest point of the second modified layer 207b may be at a height lower than the top surface 207at of the first modified layer 207a. In some embodiments, the highest point of the second modified layer 207b may be at a height higher than the top surface 207at of the first modified layer 207a.

[0103] Despite Figure 37-Figure 40 In some embodiments, the top surface 207at of the first modified layer 207a is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a first vertical distance, and the top surface 207bt of the second modified layer 207b is separated from the bottom surface 146b of the epitaxial S / D feature 146 by a second vertical distance that is less than the first vertical distance.

[0104] Various embodiments relate to a novel method of forming a dielectric layer structure over an exposed surface of a sacrificial gate structure and a semiconductor layer stack prior to forming source / drain features. Portions of the dielectric layer structure are etched and retained between the bottom of the source / drain features and the top surface of the substrate for reducing source / drain epitaxial leakage and reducing parasitic capacitance. In various embodiments, an inner dielectric layer of the dielectric layer structure is deposited to create an etch rate difference between an inner spacer and a sidewall surface of an outer dielectric layer of the dielectric layer structure so as to reduce inner spacer recessing during downstream etching processes. As a result, the integrity of the inner spacer is retained, which prevents the formation of air gaps between the inner spacer and the source / drain features and prevents device performance degradation.

[0105] One embodiment is a semiconductor device structure. The semiconductor device structure includes: a source / drain (S / D) feature disposed on a substrate and between two adjacent semiconductor layers; an internal spacer disposed between a semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate; and a dielectric layer structure disposed between the S / D feature and the substrate. The dielectric layer structure includes: a first dielectric layer in contact with the internal spacer and the substrate; and a second dielectric layer nested within the first dielectric layer, wherein the bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.

[0106] Another embodiment is a method for forming a semiconductor device structure. The method includes depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked. The method also includes removing a portion of the fin structure that is not covered by the sacrificial gate structure; forming an internal spacer at an edge of the second semiconductor layer, wherein the internal spacer has a first film property. The method also includes forming a dielectric layer on an exposed surface of the sacrificial gate structure, the internal spacer, the first semiconductor layer of the fin structure, and the substrate. The method also includes performing a first treatment process so that the dielectric layer over the sidewall surface of the sacrificial gate structure, the first semiconductor layer of the fin structure, and the internal spacer has a second film property that is different from the first film property of the internal spacer. The method also includes removing the dielectric layer formed over the sacrificial gate structure, the first semiconductor layer of the fin structure, and the sidewall surface of the internal spacer without affecting the dielectric layer formed over the exposed surface of the substrate. The method also includes forming source / drain features over the dielectric layer.

[0107] Yet another embodiment is a method for forming a semiconductor device structure. The method includes depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked. The method also includes removing a portion of the fin structure that is not covered by the sacrificial gate structure; replacing an edge portion of the second semiconductor layer of each of the first fin structure and the second fin structure with a dielectric material to form an internal spacer; forming a first dielectric layer on the internal spacer, the sacrificial gate structure, the first semiconductor layer of the fin structure, and an exposed surface of the substrate. The method includes forming a second dielectric layer on the first dielectric layer; removing the first dielectric layer and the second dielectric layer from the sidewall surfaces of the internal spacer, the sacrificial gate structure, and the first semiconductor layer of the fin structure; forming a source / drain feature on the first dielectric layer and the second dielectric layer disposed over the exposed surface of the substrate, wherein the bottom surface of the source / drain feature and the first dielectric layer and the second dielectric layer are exposed to air. The method includes removing the plurality of second semiconductor layers to expose a portion of the first semiconductor layer of the fin structure; and forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the fin structure.

[0108] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

[0109] Example 1 is a semiconductor device structure, comprising: a source / drain (S / D) feature, disposed above a substrate and located between two adjacent semiconductor layers; an internal spacer, disposed between a semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate; and a dielectric layer structure, disposed between the S / D feature and the substrate, the dielectric layer structure comprising: a first dielectric layer, in contact with the internal spacer and the substrate; and a second dielectric layer, nested within the first dielectric layer, wherein a bottom surface and a sidewall surface of the second dielectric layer are in contact with the first dielectric layer.

[0110] Example 2 is the semiconductor device structure of Example 1, wherein a top surface of the first dielectric layer and a top surface of the second dielectric layer are substantially coplanar.

[0111] Example 3 is the semiconductor device structure of Example 1, wherein a top surface of the first dielectric layer is at a lower height than a top surface of the second dielectric layer.

[0112] Example 4 is the semiconductor device structure of Example 1, wherein the dielectric layer structure and the S / D features are exposed to air.

[0113] Example 5 is the semiconductor device structure of Example 4, wherein the dielectric layer structure is separated from the S / D feature by an air gap.

[0114] Example 6 is the semiconductor device structure of Example 5, wherein a portion of the S / D feature is also in contact with the inner spacer.

[0115] Example 7 is the semiconductor device structure of Example 4, wherein a portion of the dielectric layer structure contacts a bottom surface of the S / D feature.

[0116] Example 8 is the semiconductor device structure of Example 7, wherein a bottom surface of the S / D feature contacts a portion of the first dielectric layer.

[0117] Example 9 is the semiconductor device structure of Example 1, wherein the S / D feature has a curved bottom surface.

[0118] Example 10 is the semiconductor device structure of Example 1, wherein the first dielectric layer and the second dielectric layer include materials that are chemically different from each other.

[0119] Example 11 is a method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; forming an internal spacer at an edge of the second semiconductor layer, wherein the internal spacer has a first film property; forming a dielectric layer on the sacrificial gate structure, the internal spacer, the first semiconductor layer of the fin structure, and an exposed surface of the substrate; performing a first processing process so that the dielectric layer over the sidewall surface of the sacrificial gate structure, the first semiconductor layer of the fin structure, and the internal spacer has a second film property different from the first film property of the internal spacer; removing the dielectric layer formed over the sacrificial gate structure, the first semiconductor layer of the fin structure, and the sidewall surface of the internal spacer without affecting the dielectric layer formed over the exposed surface of the substrate; and forming source / drain features over the dielectric layer.

[0120] Example 12 is the method of Example 11, wherein after the first treatment process, a dielectric layer formed over a top surface of the sacrificial gate structure and an exposed surface of the substrate has a third film property.

[0121] Example 13 is the method described in Example 12, wherein, after removing the dielectric layer from the sidewall surfaces of the sacrificial gate structure, the first semiconductor layer of the fin structure, and the internal spacer, a second processing process is performed so that the dielectric layer formed above the top surface of the sacrificial gate structure has a fourth film property different from the third film property.

[0122] Example 14 is the method of Example 12, further comprising: before forming the source / drain features, removing a dielectric layer formed over a top surface of the sacrificial gate structure.

[0123] Example 15 is the method of Example 14, further comprising: before removing the dielectric layer formed on the top surface of the sacrificial gate structure, forming a protective layer to cover the dielectric layer formed on the exposed surface of the substrate.

[0124] Example 16 is the method of Example 11, wherein the dielectric layer and the internal spacer are formed of different dielectric materials.

[0125] Example 17 is the method of Example 11, wherein the source / drain features and a dielectric layer formed over the exposed surface of the substrate are exposed to air.

[0126] Example 18 is a method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure on a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; removing a portion of the fin structure that is not covered by the sacrificial gate structure; replacing an edge portion of the second semiconductor layer of each of the first fin structure and the second fin structure with a dielectric material to form an internal spacer; forming a first dielectric layer on the internal spacer, the sacrificial gate structure, the first semiconductor layer of the fin structure, and an exposed surface of the substrate; forming a second dielectric layer on the first dielectric layer; two dielectric layers; removing the first dielectric layer and the second dielectric layer from the sidewall surfaces of the internal spacer, the sacrificial gate structure and the first semiconductor layer of the fin structure; forming source / drain features on the first dielectric layer and the second dielectric layer disposed on the exposed surface of the substrate, wherein the bottom surfaces of the source / drain features and the first dielectric layer and the second dielectric layer are exposed to air; removing the plurality of second semiconductor layers to expose a portion of the first semiconductor layer of the fin structure; and forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the fin structure.

[0127] Example 19 is the method of Example 18, wherein the first dielectric layer is formed of an oxide-based material and the second dielectric layer is formed of a nitride-based material.

[0128] Example 20 is the method described in Example 18, wherein, after removing the first dielectric layer and the second dielectric layer from the sidewall surfaces of the first semiconductor layer of the internal spacer, the sacrificial gate structure, and the fin structure, the first dielectric layer and the second dielectric layer formed above the exposed surface of the substrate are etched so that the top surface of the first dielectric layer and the top surface of the second dielectric layer are at different heights.

Claims

1. A semiconductor device structure, comprising: a source / drain S / D feature disposed on the substrate and between two adjacent semiconductor layers; an internal spacer disposed between and in contact with a semiconductor layer and the substrate; as well as A dielectric layer structure is disposed between the S / D feature and the substrate, the dielectric layer structure comprising: a first dielectric layer in contact with the inner spacer and the substrate; and A second dielectric layer is nested in the first dielectric layer, wherein a bottom surface and a sidewall surface of the second dielectric layer are in contact with the first dielectric layer.

2. The semiconductor device structure according to claim 1, wherein: A top surface of the first dielectric layer and a top surface of the second dielectric layer are substantially coplanar.

3. The semiconductor device structure according to claim 1, wherein: A top surface of the first dielectric layer is at a lower height than a top surface of the second dielectric layer.

4. The semiconductor device structure according to claim 1, wherein: The dielectric layer structure and the S / D features are exposed to air.

5. The semiconductor device structure according to claim 4, wherein: The dielectric layer structure is separated from the S / D features by an air gap.

6. The semiconductor device structure according to claim 5, wherein: A portion of the S / D feature is also in contact with the inner spacer.

7. The semiconductor device structure according to claim 4, wherein: A portion of the dielectric layer structure contacts a bottom surface of the S / D feature.

8. The semiconductor device structure according to claim 7, wherein: A bottom surface of the S / D feature contacts a portion of the first dielectric layer.

9. A method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; forming an inner spacer at an edge of the second semiconductor layer, wherein the inner spacer has a first film property; forming a dielectric layer on the sacrificial gate structure, the inner spacer, the first semiconductor layer of the fin structure, and the exposed surface of the substrate; performing a first treatment process so that the sacrificial gate structure, the first semiconductor layer of the fin structure, and the dielectric layer on the sidewall surface of the inner spacer have a second film property different from the first film property of the inner spacer; removing the dielectric layer formed over the sidewall surfaces of the sacrificial gate structure, the first semiconductor layer of the fin structure, and the inner spacer without affecting the dielectric layer formed over the exposed surface of the substrate; and Source / drain features are formed over the dielectric layer.

10. A method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure over a portion of a fin structure formed from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; replacing an edge portion of the second semiconductor layer of each of the first fin structure and the second fin structure with a dielectric material to form an inner spacer; forming a first dielectric layer on the inner spacer, the sacrificial gate structure, the first semiconductor layer of the fin structure, and the exposed surface of the substrate; forming a second dielectric layer on the first dielectric layer; removing the first dielectric layer and the second dielectric layer from sidewall surfaces of the inner spacer, the sacrificial gate structure, and the first semiconductor layer of the fin structure; forming source / drain features over the first dielectric layer and the second dielectric layer disposed over the exposed surface of the substrate, wherein bottom surfaces of the source / drain features and the first dielectric layer and the second dielectric layer are exposed to air; removing the plurality of second semiconductor layers to expose a portion of the first semiconductor layer of the fin structure; and A gate electrode layer is formed to surround at least an exposed portion of one of the plurality of first semiconductor layers of the fin structure.

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