Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a fin-type active region extending lengthwise in a first horizontal direction on a substrate; a horizontal semiconductor layer on the fin-type active region; a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer; a gate line surrounding the horizontal semiconductor layer and the seed layer on the fin-type active region and extending lengthwise in a second horizontal direction intersecting the first horizontal direction; and a pair of vertical semiconductor layers on the fin-type active region on first and second sides of the horizontal semiconductor layer in the first horizontal direction, respectively, the horizontal semiconductor layer being between the pair of vertical semiconductor layers, in which an inner wall of each of the pair of vertical semiconductor layers contacts the horizontal semiconductor layer, and upper surfaces or lower surfaces of the pair of vertical semiconductor layers are in contact with the seed layer.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0092034 filed on July 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device and more particularly to a semiconductor device including a channel region including a two-dimensional (2D) material. Background Art

[0003] With the rapid size reduction of semiconductor devices, it is desirable to ensure a relatively high operating speed and a relatively high operating accuracy in the semiconductor devices. In addition, with the increased integration and reduced size of semiconductor devices, the possibility of occurrence of process defects during the process of manufacturing nanosheet field effect transistors may increase. Therefore, a semiconductor device having a structure capable of eliminating or reducing the possibility of occurrence of process defects and improving the performance and reliability of nanosheet field effect transistors is being developed. Summary of the invention

[0004] The present disclosure provides a semiconductor device capable of providing more stable performance and improved reliability in a nanosheet field effect transistor.

[0005] According to some aspects of the inventive concept, a semiconductor device is provided, including: a fin-type active area extending in length in a first horizontal direction on a substrate; a horizontal semiconductor layer on the fin-type active area; a seed layer on the fin-type active area and in contact with the horizontal semiconductor layer; a gate line surrounding the horizontal semiconductor layer and the seed layer on the fin-type active area and extending in length in a second horizontal direction intersecting the first horizontal direction; and a pair of vertical semiconductor layers on the fin-type active area on a first side and a second side of the horizontal semiconductor layer in the first horizontal direction, and the horizontal semiconductor layer is between the pair of vertical semiconductor layers, wherein an inner wall of each of the vertical semiconductor layers contacts the horizontal semiconductor layer, and an upper surface or a lower surface of the vertical semiconductor layer contacts the seed layer.

[0006] According to some aspects of the inventive concept, a semiconductor device is provided, comprising: a fin-type active region extending in length in a first horizontal direction on a substrate; a pair of horizontal semiconductor layers on the fin-type active region and facing each other in a vertical direction; a gate line surrounding the horizontal semiconductor layer on the fin-type active region and extending in length in a second horizontal direction intersecting the first horizontal direction; and a pair of vertical semiconductor layers on the fin-type active region on a first side and a second side of the horizontal semiconductor layer in the first horizontal direction, and the horizontal semiconductor layer is between the pair of vertical semiconductor layers, wherein an inner wall of each of the vertical semiconductor layers contacts the horizontal semiconductor layer, an upper surface of the vertical semiconductor layer is coplanar with an upper surface of a horizontal semiconductor layer among the horizontal semiconductor layers that is relatively farther away from the fin-type active region, and a lower surface of the vertical semiconductor layer is coplanar with a lower surface of a horizontal semiconductor layer among the horizontal semiconductor layers that is relatively closer to the fin-type active region.

[0007] According to some aspects of the inventive concept, a semiconductor device is provided, comprising: a fin-type active region extending in length in a first horizontal direction on a substrate; a pair of horizontal semiconductor layers on the fin-type active region and facing each other in a vertical direction; a pair of seed layers on the fin-type active region and respectively contacting the pair of horizontal semiconductor layers; a gate line surrounding the pair of horizontal semiconductor layers and the pair of seed layers on the fin-type active region and extending in length in a second horizontal direction intersecting the first horizontal direction; a pair of vertical semiconductor layers on the fin-type active region, respectively on a first side and a second side of the pair of horizontal semiconductor layers in the first horizontal direction, and the pair of water lines are connected to the gate line. a flat semiconductor layer between the pair of horizontal semiconductor layers; and a pair of source / drain contacts adjacent to a gate line, the gate line being between the pair of source / drain contacts, wherein inner walls of the pair of vertical semiconductor layers respectively contact the pair of horizontal semiconductor layers, upper and lower surfaces of the pair of vertical semiconductor layers contact the pair of seed layers, an upper surface of each of the pair of vertical semiconductor layers is coplanar with an upper surface of a horizontal semiconductor layer located on the relatively upper side among the pair of horizontal semiconductor layers, and a lower surface of each of the pair of vertical semiconductor layers is coplanar with a lower surface of a horizontal semiconductor layer located on the relatively lower side among the pair of horizontal semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic plan view showing a semiconductor device according to some embodiments;

[0010] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0011] Figure 3 is along Figure 1 A cross-sectional view taken along line BB';

[0012] Figure 4 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0013] Figure 5 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0014] Figure 6 is along Figure 1 A cross-sectional view of the semiconductor device taken along line AA';

[0015] Figure 7 is along Figure 1 A cross-sectional view of the semiconductor device taken along line BB';

[0016] Figure 8 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0017] Fig. 9 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0018] Fig.10 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0019] Fig.11 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0020] Fig.12 , Fig.13A , Fig. 13B , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A and Fig.31B is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some embodiments; and

[0021] Figure 32 to Figure 38 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals may be used for the same components in the drawings, and redundant descriptions thereof are omitted here for the sake of brevity.

[0023] Figure 1 is a schematic plan view illustrating a semiconductor device 100 according to some embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 is along Figure 1 A cross-sectional view taken along line BB'.

[0024] Reference Figures 1 to 3 The semiconductor device 100 may include a plurality of fin-type active areas FA protruding upward from the substrate 102 in a vertical direction (Z direction) and extending in length in a first horizontal direction (X direction), and a horizontal semiconductor layer 132 on the plurality of fin-type active areas FA.

[0025] The substrate 102 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. As used herein, the terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" refer to materials including the elements included in these terms, rather than chemical equations representing stoichiometric relationships.

[0026] A device isolation layer (not shown) may cover the first and second sidewalls of each of the plurality of fin type active regions FA and may be on the substrate 102. The device isolation layer may include, for example, an oxide layer, a nitride layer, or a combination thereof.

[0027] The plurality of gate lines 150 may be on the plurality of fin type active areas FA. Each of the plurality of gate lines 150 may extend in length in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction).

[0028] In a region where the plurality of fin type active regions FA and the plurality of gate lines 150 cross each other, a plurality of horizontal semiconductor layers 132 and a plurality of seed layers 134 may be on upper portions of the plurality of fin type active regions FA, respectively.

[0029] The horizontal semiconductor layer 132 may be used as a channel region of the first transistor TR1. On a plane (i.e., an XZ plane) perpendicular to the second horizontal direction (Y direction), the horizontal semiconductor layer 132 may extend relatively longer in the first horizontal direction (X direction) than in the vertical direction (Z direction). The horizontal semiconductor layer 132 may include two layers facing each other in the vertical direction (Z direction) on the plurality of fin-type active regions FA.

[0030] In some embodiments, the two layers of the horizontal semiconductor layer 132 may have substantially the same thickness in the vertical direction (Z direction). In some embodiments, the two layers of the horizontal semiconductor layer 132 may have different thicknesses in the vertical direction (Z direction). For example, in the vertical direction (Z direction), the thickness of the horizontal semiconductor layer 132 located on the relatively upper side among the horizontal semiconductor layers 132 may be greater than the thickness of the horizontal semiconductor layer 132 located on the relatively lower side among the horizontal semiconductor layers 132.

[0031] In some embodiments, the two layers of the horizontal semiconductor layer 132 may have substantially the same size in the first horizontal direction (X direction). In some embodiments, the two layers of the horizontal semiconductor layer 132 may have different sizes in the first horizontal direction (X direction).

[0032] In some embodiments, the horizontal semiconductor layer 132 may include a two-dimensional (2D) material. For example, the horizontal semiconductor layer 132 may include a transition metal dichalcogenide (TMD). For example, the TMD may include MoS 2 , WS 2 and WSe 2 At least one of . Figure 2 and Figure 3 An embodiment in which the horizontal semiconductor layer 132 includes two layers is shown. However, the present disclosure is not limited thereto, and the horizontal semiconductor layer 132 may include at least one layer. For example, when the horizontal semiconductor layer 132 includes one layer, the horizontal semiconductor layer 132 may be any one of the horizontal semiconductor layer 132 located on the relatively upper side and the horizontal semiconductor layer 132 located on the relatively lower side among the above-mentioned horizontal semiconductor layers 132. When the horizontal semiconductor layer 132 includes three or more layers, at least one layer of the horizontal semiconductor layer 132 may be located between the horizontal semiconductor layer 132 located on the relatively upper side among the horizontal semiconductor layers 132 and the horizontal semiconductor layer 132 located on the relatively lower side among the horizontal semiconductor layers 132.

[0033] The seed layer 134 among the plurality of seed layers 134 may contact the corresponding horizontal semiconductor layer 132 of the horizontal semiconductor layer 132. For example, the seed layer 134 (e.g., the first seed layer 134) located on the relatively upper side among the seed layers 134 may be on the upper surface of the horizontal semiconductor layer 132 (e.g., the first horizontal semiconductor layer 132) located on the relatively upper side among the horizontal semiconductor layers 132, and the seed layer 134 (e.g., the second seed layer 134) located on the relatively lower side among the seed layers 134 may be on the lower surface of the horizontal semiconductor layer 132 (e.g., the second horizontal semiconductor layer 132) located on the relatively lower side among the horizontal semiconductor layers 132. The first sidewall and the second sidewall of the seed layer 134 in the first horizontal direction (X direction) may overlap or align with the inner wall of the insulating spacer 116 in the vertical direction (Z direction). In some embodiments, the seed layer 134 may be an oxide of a transition metal included in the TMD of the horizontal semiconductor layer 132 or a catalyst of the transition metal oxide. For example, when the horizontal semiconductor layer 132 includes MoS 2 When the seed layer 134 may include MoO 4 Or Na 2 MoO 4 and K 2 MoO 4 At least one of MoO 4 is included in MoS 2 Oxides of transition metals Mo, Na 2 MoO 4 and K 2 MoO 4 It is a Mo oxide catalyst.

[0034] In some embodiments, in the first horizontal direction (X direction), the horizontal width of the seed layer 134 may be greater than the horizontal width of the horizontal semiconductor layer 132. Therefore, a portion of the seed layer 134 may extend outside the horizontal semiconductor layer 132 in the first horizontal direction (X direction) and may not overlap with the horizontal semiconductor layer 132 in the vertical direction (Z direction). Figure 2 and Figure 3 An embodiment in which the number of seed layers 134 is two is shown. However, the present disclosure is not limited thereto, and the number of seed layers 134 may be at least one. For example, when the number of seed layers 134 is one, the seed layer 134 may be any one of the first seed layer and the second seed layer described above. When the number of seed layers 134 is three or more, at least one of the seed layers 134 may be located between a seed layer located on the relatively upper side among the seed layers 134 and a seed layer located on the relatively lower side among the seed layers 134.

[0035] Each of the plurality of gate lines 150 may include a main gate portion 150M and a plurality of sub-gate portions 150S. The main gate portion 150M may be on the upper side of the horizontal semiconductor layer 132 and the seed layer 134, and may extend in the second horizontal direction (Y direction). The plurality of sub-gate portions 150S may be integrally connected to the main gate portion 150M, and may be between two layers of the horizontal semiconductor layer 132, or between the seed layer 134 located on the relatively lower side among the seed layer 134 and the fin type active area FA. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 150S may be less than the thickness of the main gate portion 150M.

[0036] Each of the plurality of gate lines 150 may include a metal, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal carbide may be TiAlC. However, the material of each of the plurality of gate lines 150 is not limited thereto.

[0037] The first gate dielectric layer 142 may be between the gate line 150 and the horizontal semiconductor layer 132 and between the gate line 150 and the seed layer 134. In some embodiments, the first gate dielectric layer 142 may have a stacked structure of an interface dielectric layer and a high dielectric layer. The interface dielectric layer may include a low dielectric material layer (e.g., a silicon oxide layer, a silicon oxynitride layer, or a combination thereof) having a permittivity or dielectric constant of about 9 or less. In some embodiments, the interface dielectric layer may be omitted. The high dielectric layer may include a material having a dielectric constant higher than that of the silicon oxide layer. For example, the high dielectric layer may have a dielectric constant of about 10 to about 25. The high dielectric layer may include hafnium oxide, but the present disclosure is not limited thereto.

[0038] The second gate dielectric layer 144 may be between the first gate dielectric layer 142 and the gate line 150. The second gate dielectric layer 144 may include a metal nitride layer. The metal nitride layer may include, for example, a titanium nitride layer, a tantalum nitride layer, a molybdenum nitride layer, or a combination of two or more thereof.

[0039] The insulating spacer 116 may be on both sidewalls of the main gate portion 150M and on both sidewalls of the sub-gate portion 150S located at the relatively lower end among the plurality of sub-gate portions 150S. The insulating spacer 116 may be spaced apart from the gate line 150, with a first gate dielectric layer 142 and a second gate dielectric layer 144 between the insulating spacer 116 and the gate line 150. The insulating spacer 116 may include, for example, silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination of two or more thereof.

[0040] A pair of vertical semiconductor layers 136 may be on both sides of the horizontal semiconductor layer 132 in the first horizontal direction (X direction), and the horizontal semiconductor layer 132 is between the pair of (first and second) vertical semiconductor layers 136. On a plane perpendicular to the second horizontal direction (Y direction) (i.e., XZ plane), each vertical semiconductor layer 136 may extend relatively longer in the vertical direction (Z direction) than in the first horizontal direction (X direction). Each of the pair of vertical semiconductor layers 136 may serve as a source / drain region of the first transistor TR1. The upper surface of each of the pair of vertical semiconductor layers 136 may be coplanar with the upper surface of the horizontal semiconductor layer 132 located on the relatively upper side among the horizontal semiconductor layers 132, and the lower surface of each of the pair of vertical semiconductor layers 136 may be coplanar with the lower surface of the horizontal semiconductor layer 132 located on the relatively lower side among the horizontal semiconductor layers 132. The inner sidewalls of a pair of vertical semiconductor layers 136 may contact both sidewalls of the horizontal semiconductor layer 132, and the upper and lower surfaces of the pair of vertical semiconductor layers 136 may contact the seed layer 134. In some embodiments, the sidewalls of the vertical semiconductor layer 136 in contact with the horizontal semiconductor layer 132 may have a vertical length Lg of about 5 nm to about 20 nm in the vertical direction (Z direction). In some embodiments, the vertical semiconductor layer 136 may include a two-dimensional (2D) material doped with impurities. For example, the 2D material may be TMD, and the impurities may be p-type impurities or n-type impurities. The p-type impurities may be, for example, boron, and the n-type impurities may be, for example, phosphorus. In some embodiments, the concentration of the impurities of the vertical semiconductor layer 136 may be about 10 18 / cm 3 to about 10 21 / cm 3 In some embodiments, the vertical semiconductor layer 136 may include a material substantially the same as that of the horizontal semiconductor layer 132. For example, the horizontal semiconductor layer 132 may include MoS 2 , and the vertical semiconductor layer 136 may include MoS doped with impurities 2 .

[0041] In some embodiments, each vertical semiconductor layer 136 may extend in the first horizontal direction (X direction) such that the inner wall of the insulating spacer 116 overlaps (e.g., is aligned) with the outer wall of the vertical semiconductor layer 136 in the vertical direction (Z direction). Therefore, the vertical semiconductor layer 136 may include a portion overlapping the seed layer 134 in the vertical direction (Z direction), and may not include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction). A pair of vertical semiconductor layers 136 may be disposed inside the insulating spacer 116 in the first horizontal direction (X direction).

[0042] The barrier layer 160 and the upper insulating layer 170 may be on the main gate portion 150M. The barrier layer 160 may cover the upper surface of the main gate portion 150M, and the upper insulating layer 170 may cover the upper surface of the barrier layer 160. In some embodiments, the barrier layer 160 may include a metal nitride layer. For example, the metal nitride layer may be TiN. In some embodiments, the upper insulating layer 170 may include a silicon nitride layer, a silicon oxide layer, or a combination thereof.

[0043] The insulating liner 118 may be on both sidewalls of the barrier layer 160 and both sidewalls of the upper insulating layer 170. The insulating liner 118 may cover both sidewalls of the barrier layer 160 and both sidewalls of the upper insulating layer 170. The insulating liner 118 may include, for example, silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination of two or more thereof.

[0044] A pair of source / drain contacts 120 may be on both sides of the gate line 150 in the first horizontal direction (X direction), and one gate line 150 may be between the pair of source / drain contacts 120 on the fin-type active area FA. One of the pair of source / drain contacts 120 may be on the fin-type active area FA between horizontal semiconductor layers 132 that are horizontally adjacent to each other in the first horizontal direction (X direction). The source / drain contact 120 may contact an outer wall of each of the pair of vertical semiconductor layers 136 on one sidewall of the source / drain contact 120.

[0045] In some embodiments, the source / drain contact 120 may include a first metal layer 122 and a second metal layer 124. The first metal layer 122 may cover the sidewalls of the insulating liner 118, the sidewalls of the insulating spacer 116, the sidewalls of the seed layer 134, and the sidewalls of the vertical semiconductor layer 136. A portion of the first metal layer 122 may protrude toward the vertical semiconductor layer 136 in a first horizontal direction (X direction). The protruding portion may overlap with the insulating spacer 116 in a vertical direction (Z direction), and may not overlap with the seed layer 134 in the vertical direction (Z direction). The protruding portion may have a horizontal width substantially the same as that of the insulating spacer 116 in the first horizontal direction (X direction). The protruding portion may contact the outer wall of each of the pair of vertical semiconductor layers 136. The first metal layer 122 may include, for example, Sb, Bi, In, Se, or a combination of two or more thereof. The second metal layer 124 may contact the first metal layer 122. The second metal layer 124 may include, for example, Au, Ni, Pd, Pt, or a combination of two or more thereof. In some embodiments, the first metal layer 122 may be omitted. In this case, the second metal layer 124 may cover the sidewalls of the insulating liner 118, the sidewalls of the insulating spacer 116, the sidewalls of the seed layer 134, and the sidewalls of the vertical semiconductor layer 136.

[0046] like Figure 1 As shown in , a plurality of first transistors TR1 may be formed on a portion of the substrate 102 where a plurality of fin-type active areas FA and a plurality of gate lines 150 intersect each other. The plurality of first transistors TR1 may be, for example, gate-all-around field effect transistors (GAAFETs) or multi-bridge channel field effect transistors (MBCFETs). The plurality of first transistors TR1 may form a logic circuit or a memory device.

[0047] The lower insulating layer 114 may be between the substrate 102 and the first gate dielectric layer 142. The lower insulating layer 114 may include, for example, a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0048] The etch stop layer 112 may be between the lower insulating layer 114 and the substrate 102. For example, the etch stop layer 112 may include a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0049] The semiconductor device 100 according to some embodiments may include a vertical semiconductor layer 136 serving as a source / drain region and contacting a horizontal semiconductor layer 132 serving as a channel region. At this time, a sidewall having a relatively large area of ​​the vertical semiconductor layer 136 may contact the source / drain contact 120, so that the resistance of the source / drain contact 120 may be alleviated or reduced. Therefore, the electrical performance of the semiconductor device 100 including the vertical semiconductor layer 136 may be improved.

[0050] Figure 4is a cross-sectional view illustrating a semiconductor device 100 a according to some embodiments. Figure 5 is a cross-sectional view illustrating a semiconductor device 100 b according to some embodiments. Figure 4 The semiconductor device 100a and Figure 5 Some components of the semiconductor device 100b shown in FIG. Figures 1 to 3 The components of the described semiconductor device 100 are similar, and therefore, the differences are mainly described below.

[0051] Reference Figure 4 In an area where a plurality of fin-type active areas FA and a plurality of gate lines 150 intersect each other, the semiconductor device 100a may include a plurality of horizontal semiconductor layers 132a and a plurality of seed layers 134a respectively on upper portions of the plurality of fin-type active areas FA, and a pair of vertical semiconductor layers 136a on first and second sides of the horizontal semiconductor layer 132a in a first horizontal direction (X direction), and the horizontal semiconductor layer 132a is between the pair of vertical semiconductor layers 136a.

[0052] In some embodiments, the horizontal semiconductor layer 132a may not include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction), and the seed layer 134a may include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction). In some embodiments, the seed layer 134a may contact the insulating spacer 116. For example, the seed layer 134a located on the relatively upper side among the seed layers 134a may contact a portion of the lower surface of the insulating spacer 116 on the sidewall of the main gate portion 150M at a portion of the upper surface of the seed layer 134a.

[0053] In some embodiments, the vertical semiconductor layer 136a may extend in the first horizontal direction (X direction) such that an outer wall of the vertical semiconductor layer 136a is located between an inner wall of the insulating spacer 116 and an outer wall of the insulating spacer 116. Therefore, the vertical semiconductor layer 136a may include a portion overlapping a portion of the insulating spacer 116 in the vertical direction (Z direction).

[0054] A pair of source / drain contacts 120a may be on both sides of the gate line 150 in the first horizontal direction (X direction), and one gate line 150 is between the pair of source / drain contacts 120a on the fin-type active area FA. The source / drain contact 120a may include a first metal layer 122a and a second metal layer 124a. A portion of the first metal layer 122a may protrude toward the vertical semiconductor layer 136a in the first horizontal direction (X direction). The protruding portion may have a horizontal width smaller than the horizontal width of the insulating spacer 116 in the first horizontal direction (X direction).

[0055] Reference Figure 5In the region where the plurality of fin-type active areas FA and the plurality of gate lines 150 intersect each other, the semiconductor device 100b may include a plurality of horizontal semiconductor layers 132b and a plurality of seed layers 134b respectively on the upper portions of the plurality of fin-type active areas FA, and a pair of vertical semiconductor layers 136b on the first side and the second side of the horizontal semiconductor layer 132b in the first horizontal direction (X direction), and the horizontal semiconductor layer 132b is between the pair of vertical semiconductor layers 136b.

[0056] In some embodiments, the horizontal semiconductor layer 132b may not include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction), and the seed layer 134b may include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction). In this case, the insulating spacer 116 may overlap the seed layer 134b in the vertical direction (Z direction) over the entire area or length in the first horizontal direction (X direction). Therefore, both side walls of the seed layer 134b may overlap the outer wall of the insulating spacer 116 in the vertical direction (Z direction). In some embodiments, the seed layer 134b may contact the insulating spacer 116. For example, the seed layer 134b located on the relatively upper side among the seed layers 134b may contact the lower surface of the insulating spacer 116 on the side wall of the main gate portion 150M at a portion of the upper surface of the seed layer 134b.

[0057] In some embodiments, the vertical semiconductor layer 136b may extend in a first horizontal direction (X direction) such that an outer wall of the insulating spacer 116 overlaps or is aligned with an outer wall of the vertical semiconductor layer 136b in a vertical direction (Z direction). Therefore, the vertical semiconductor layer 136b may include a portion that overlaps the entirety of the insulating spacer 116 in the vertical direction (Z direction).

[0058] A pair of source / drain contacts 120b may be on both sides of the gate line 150 in the first horizontal direction (X direction), and one gate line 150 is between the pair of source / drain contacts 120b on the fin-type active area FA. The source / drain contact 120b may include a first metal layer 122b and a second metal layer 124b. The first metal layer 122b may contact an outer wall of the vertical semiconductor layer 136b on a sidewall of the first metal layer 122b. Figures 1 to 3 The first metal layer 122 or Figure 4 Compared with the first metal layer 122a shown in FIG. 1 , the first metal layer 122b may not include the protruding portion.

[0059] Figure 6 is along Figure 1 A cross-sectional view of the semiconductor device 200 taken along line AA′. Figure 7 is along Figure 1 A cross-sectional view of the semiconductor device 200 taken along line BB′. Figure 6 and Figure 7 Some components of the semiconductor device 200 shown in FIG. Figures 1 to 3 The components of the described semiconductor device 100 are similar, and therefore, the differences are mainly described below.

[0060] Reference Figure 6 and Figure 7 , the semiconductor device 200 may include a plurality of fin-type active areas FA and a plurality of horizontal semiconductor layers 232 on the plurality of fin-type active areas FA, and may not include Figure 2 and Figure 3 The plurality of gate lines 150 may be on the plurality of fin type active areas FA, and the plurality of horizontal semiconductor layers 232 may be respectively on upper portions of the plurality of fin type active areas FA in regions where the plurality of fin type active areas FA and the plurality of gate lines 150 cross each other.

[0061] The horizontal semiconductor layer 232 may be used as a channel region of the second transistor TR2. In some embodiments, the upper and lower surfaces of the horizontal semiconductor layer 232 facing each other in the vertical direction (Z direction) and the sidewalls of the horizontal semiconductor layer 232 facing each other in the second horizontal direction (Y direction) may be covered by the first gate dielectric layer 142 between the gate line 150 and the horizontal semiconductor layer 232, and the sidewalls of the horizontal semiconductor layer 232 facing each other in the first horizontal direction (X direction) may be covered by the vertical semiconductor layer 236.

[0062] In some embodiments, the horizontal semiconductor layer 232 may include Figures 1 to 3 The material of the horizontal semiconductor layer 132 of the described semiconductor device 100 is substantially the same or similar material.

[0063] A pair of vertical semiconductor layers 236 may be on a first side and a second side (e.g., corresponding sides) of the horizontal semiconductor layer 232, with the horizontal semiconductor layer 232 between the pair of vertical semiconductor layers 236. Each of the pair of vertical semiconductor layers 236 may serve as a source / drain region of the second transistor TR2. The inner sidewalls of the pair of vertical semiconductor layers 236 may contact the sidewalls of the horizontal semiconductor layer 232, and the upper and lower surfaces of the pair of vertical semiconductor layers 236 may contact the first gate dielectric layer 142. The upper surface of the vertical semiconductor layer 236 may be coplanar with the upper surface of the horizontal semiconductor layer 232 located on the relatively upper side among the horizontal semiconductor layers 232, and the lower surface of the vertical semiconductor layer 236 may be coplanar with the lower surface of the horizontal semiconductor layer 232 located on the relatively lower side among the horizontal semiconductor layers 232. In some embodiments, the vertical semiconductor layer 236 may include a first gate dielectric layer 142 having a first gate dielectric layer 142 and a second gate dielectric layer 142 having a second gate dielectric layer 142. Figures 1 to 3 The vertical semiconductor layers 136 of the semiconductor device 100 are described as being of substantially the same or similar materials.

[0064] In some embodiments, the vertical semiconductor layer 236 may extend in the first horizontal direction (X direction) such that the inner wall of the insulating spacer 116 overlaps or aligns with the outer wall of the vertical semiconductor layer 236 in the vertical direction (Z direction). Therefore, the vertical semiconductor layer 236 may include a portion overlapping the first gate dielectric layer 142 in the vertical direction (Z direction), and may not include a portion overlapping the insulating spacer 116 in the vertical direction (Z direction). A pair of vertical semiconductor layers 236 may be inside the insulating spacer 116 in the first horizontal direction (X direction).

[0065] Figure 8 9 is a cross-sectional view showing a semiconductor device 200a according to some embodiments. Figure 8 The semiconductor device 200a and Fig. 9 Some components of the semiconductor device 200b shown in FIG. Figure 6 and Figure 7 The components of the semiconductor device 200 shown are similar, and therefore, the differences are mainly described below.

[0066] Reference Figure 8 In the region where the plurality of fin-type active areas FA and the plurality of gate lines 150 intersect each other, the semiconductor device 200a may include a plurality of horizontal semiconductor layers 232a respectively on the upper portions of the plurality of fin-type active areas FA, and a pair of vertical semiconductor layers 236a on both sides of the horizontal semiconductor layers 232a in the first horizontal direction (X direction), and the horizontal semiconductor layer 232a is between the pair of vertical semiconductor layers 236a.

[0067] In some embodiments, the vertical semiconductor layer 236a may extend in the first horizontal direction (X direction) such that an outer wall of the vertical semiconductor layer 236a is located between an inner wall of the insulating spacer 116 and an outer wall of the insulating spacer 116. Therefore, the vertical semiconductor layer 236a may include a portion overlapping a portion of the insulating spacer 116 in the vertical direction (Z direction).

[0068] In some embodiments, the upper surface and the lower surface of the vertical semiconductor layer 236a may contact the insulating spacer 116. For example, a portion of the upper surface and a portion of the lower surface of the vertical semiconductor layer 236a located on the relatively inner side may contact the first gate dielectric layer 142, and a remaining portion of the upper surface and a remaining portion of the lower surface of the vertical semiconductor layer 236a located on the relatively outer side may contact the insulating spacer 116.

[0069] A pair of source / drain contacts 120a may be on both sides of the gate line 150, with one gate line 150 between the pair of source / drain contacts 120a on the fin-type active area FA. The source / drain contact 120a may include a first metal layer 122a and a second metal layer 124a. A portion of the first metal layer 122a may protrude toward the vertical semiconductor layer 236a in the first horizontal direction (X direction). The protruding portion may have a horizontal width smaller than the horizontal width of the insulating spacer 116 in the first horizontal direction (X direction).

[0070] Reference Fig. 9 In the region where the plurality of fin-type active areas FA and the plurality of gate lines 150 intersect each other, the semiconductor device 200b may include a plurality of horizontal semiconductor layers 232b respectively on the upper portions of the plurality of fin-type active areas FA and a pair of vertical semiconductor layers 236b on both sides of the horizontal semiconductor layers 232b in the first horizontal direction (X direction), and the horizontal semiconductor layer 232b is disposed between the pair of horizontal semiconductor layers 232b.

[0071] In some embodiments, the vertical semiconductor layer 236b may extend in the first horizontal direction (X direction) so that the outer wall of the insulating spacer 116 overlaps with the outer wall of the vertical semiconductor layer 236b in the vertical direction (Z direction). Therefore, the vertical semiconductor layer 236b may include a portion that overlaps with the entirety of the insulating spacer 116 in the vertical direction (Z direction).

[0072] In some embodiments, the upper surface and the lower surface of the vertical semiconductor layer 236 b may contact the insulating spacer 116. For example, a portion of the upper surface and a portion of the lower surface of the vertical semiconductor layer 236 b located on the relatively inner side may contact the first gate dielectric layer 142, and a remaining portion of the upper surface and a remaining portion of the lower surface of the vertical semiconductor layer 236 b located on the relatively outer side may contact the insulating spacer 116.

[0073] A pair of source / drain contacts 120b may be on both sides of the gate line 150 in the first horizontal direction (X direction), and one gate line 150 is between the pair of source / drain contacts 120b on the fin-type active area FA. The source / drain contact 120b may include a first metal layer 122b and a second metal layer 124b. The first metal layer 122b may contact the outer wall of the vertical semiconductor layer 236b on the sidewall of the first metal layer 122b. The first metal layer 122b may not include a protruding portion.

[0074] Fig.10 is a cross-sectional view illustrating a semiconductor device 300 according to some embodiments.

[0075] Reference Fig.10, the semiconductor device 300 may include a plurality of transistors TR1 and TR2. The plurality of transistors TR1 and TR2 may be formed on a substrate 102. An etch stop layer 112 and a lower insulating layer 114 may be formed between the plurality of transistors TR1 and TR2 and the substrate 102. The plurality of transistors TR1 and TR2 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 and the second transistor TR2 may be arranged in a first horizontal direction (X direction). The first transistor TR1 and the second transistor TR2 may be spaced apart from each other, and an inter-gate insulating layer 310 may be between the first transistor TR1 and the second transistor TR2. The inter-gate insulating layer 310 may include, for example, a silicon nitride layer, a silicon oxide layer, or a combination thereof. The first transistor TR1 may be a reference Figures 1 to 3 The semiconductor device 100 described in reference Figure 4 The semiconductor device 100a described and the reference Figure 5 The second transistor TR2 may be any one of the semiconductor devices 100b described above. Figure 6 and Figure 7 The semiconductor device 200 described in reference Figure 8 The semiconductor device 200a described and the reference Fig. 9 However, the present disclosure is not limited thereto, and each of the first transistor TR1 and the second transistor TR2 may be, for example, Figures 1 to 3 The semiconductor device 100 described in reference Figure 4 The semiconductor device 100a described and the reference Figure 5 Any of the semiconductor devices 100b described.

[0076] Fig.11 is a cross-sectional view illustrating a semiconductor device 400 according to some embodiments.

[0077] Reference Fig.11, the semiconductor device 400 may include a plurality of transistors TR1 and TR2. The plurality of transistors TR1 and TR2 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 may be formed on a substrate 102. An etch stop layer 112 and a lower insulating layer 114 may be formed between the first transistor TR1 and the substrate 102. The second transistor TR2 may be stacked on the first transistor TR1 in a vertical direction (Z direction). The first transistor TR1 and the second transistor TR2 may be spaced apart from each other in the vertical direction (Z direction), and the etch stop layer 112 and the lower insulating layer 114 are disposed between the first transistor TR1 and the second transistor TR2. A source / drain contact 120 extending in length in the vertical direction (Z direction) may be on one side of each of the first transistor TR1 and the second transistor TR2. The source / drain contact 120 extending in length in the vertical direction (Z direction) may contact the first transistor TR1 and the second transistor TR2 at the same time. The first transistor TR1 may be a reference Figures 1 to 3 The semiconductor device 100 described in reference Figure 4 The semiconductor device 100a described and the reference Figure 5 The second transistor TR2 may be any one of the semiconductor devices 100b described above. Figure 6 and Figure 7 The semiconductor device 200 described in reference Figure 8 The semiconductor device 200a described and the reference Fig. 9 However, the present disclosure is not limited thereto, and each of the first transistor TR1 and the second transistor TR2 may be, for example, Figures 1 to 3 The semiconductor device 100 described in reference Figure 4 The semiconductor device 100a described and the reference Figure 5 Any of the semiconductor devices 100b described.

[0078] Fig.12 , Fig.13A , Fig. 13B , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A and Fig.31B is a cross-sectional view for explaining a method of manufacturing a semiconductor device 100 according to some embodiments. Specifically, Fig.12 , Fig.13A , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig.27A , Fig.28A , Fig.29A , Fig. 30A and Fig.31A is shown sequentially along Figure 1 A cross-sectional view of the semiconductor device 100 taken along the line AA′ in FIG. Fig. 13B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B and Fig.31B is shown sequentially along Figure 1 A cross-sectional view of the semiconductor device 100 taken along line BB' in FIG. Figures 12 to 31B In, with Figures 1 to 3 The same reference numerals in the drawings denote the same components, and thus, detailed descriptions thereof may be omitted herein.

[0079] Reference Fig.12 , an etch stop layer 112 and a lower insulating material layer 114S are sequentially formed on the substrate 102. Next, a first sacrificial layer SL1, a first seed material layer SdL1, a second sacrificial layer SL2, and a first oxide layer OX1 may be sequentially formed on the lower insulating material layer 114S. Next, a plurality of fin-type active areas FA may be defined on the substrate 102 by etching a portion of each of the first sacrificial layer SL1, the first seed material layer SdL1, the second sacrificial layer SL2, the etch stop layer 112, the lower insulating material layer 114S, and the substrate 102. Next, a device isolation layer (not shown) may be formed to cover the sidewall of each of the plurality of fin-type active areas FA.

[0080] In some embodiments, the first sacrificial layer SL1 may include a semiconductor material. For example, the first sacrificial layer SL1 may include a Si layer. In some embodiments, the second sacrificial layer SL2 may include a metal oxide layer. For example, the second sacrificial layer SL2 may include an aluminum oxide layer. In some embodiments, the first seed material layer SdL1 may include an oxide of a transition metal or a catalyst of a transition metal oxide. For example, the first seed material layer SdL1 may include an oxide of a transition metal (such as MoO 4 or WO 3 ) or transition metal oxide catalysts (such as Na 2 MoO 4 or K 2 MoO 4 ).

[0081] Reference Fig.13A and Fig. 13B ,exist Fig.12 As a result, a dummy gate layer Py1 may be formed on the first oxide layer OX1, and an insulating material layer 118S covering both sidewalls of the dummy gate layer Py1 and the first oxide layer OX1 may be formed. In some embodiments, the dummy gate layer Py1 may include polysilicon, and the insulating material layer 118S may include a silicon nitride layer.

[0082] Reference Fig.14 ,exist Fig.13A and Fig. 13B As a result, a portion of each of the insulating material layer 118S, the first oxide layer OX1, the first sacrificial layer SL1, the first seed material layer SdL1, and the second sacrificial layer SL2 may be etched by using the dummy gate layer Py1 as an etching mask. Through the etching process, a portion of the insulating material layer 118S covering the upper surface of the first oxide layer OX1 may be removed, and only a portion of the insulating material layer 118S covering both sidewalls of the dummy gate layer Py1 may be retained and defined as the insulating liner 118. The etching process may be performed by using, for example, dry etching, wet etching, or a combination thereof.

[0083] Reference Fig.15 ,exist Fig.14 As a result, the first groove RS1 may be formed by etching a portion of the first sacrificial layer SL1 in a horizontal direction. A portion of the upper surface of the first seed material layer SdL1 located on the relatively upper side among the first seed material layer SdL1 and a portion of the lower surface of the first seed material layer SdL1 located on the relatively lower side among the first seed material layer SdL1 may be exposed by the first groove RS1.

[0084] Reference Fig.16 ,exist Fig.15As a result, an insulating spacer 116 may be formed, and the insulating spacer 116 is formed in the first groove RS1 (see Fig.15 ) and may fill the first groove RS1. The insulating spacer 116 may be formed by forming an insulating material layer, and then removing the remaining portion of the insulating material layer except for the portion filling the first groove RS1, the insulating material layer is in the first groove RS1 and may fill the first groove RS1, and the insulating material layer covers the sidewalls of the first seed material layer SdL1, the sidewalls of the second sacrificial layer SL2, the sidewalls of the first oxide layer OX1, and the sidewalls of the insulating liner 118. Therefore, the length of the insulating spacer 116 in the first horizontal direction (X direction) may be substantially the same as the length of the first groove RS1 in the first horizontal direction (X direction).

[0085] Reference Fig.17 ,exist Fig.16 As a result, a second groove RS2 may be formed by etching a portion of the second sacrificial layer SL2 in a horizontal direction. A portion of a lower surface of the first seed material layer SdL1 located on a relatively upper side among the first seed material layer SdL1 and a portion of an upper surface of the first seed material layer SdL1 located on a relatively lower side among the first seed material layer SdL1 may be exposed by the second groove R2.

[0086] In some embodiments, the length of the second groove RS2 in the first horizontal direction (X direction) may be the same as that of the first groove RS1 (see Fig.15 ) have substantially the same length in the first horizontal direction (X direction).

[0087] In some embodiments, the length of the second groove RS2 in the first horizontal direction (X direction) may be smaller than that of the first groove RS1 (see Fig.15 ) in the first horizontal direction (X direction). In this case, when the length of the second groove RS2 in the first horizontal direction (X direction) is equal to that of the first groove RS1 (see Fig.15 ) in the first horizontal direction (X direction) is the same, the second hole H2 (see Fig. 20A ) may have a larger size in the first horizontal direction (X direction), and by using the second seed material layer SdL2 (see Fig. 20A ) The semiconductor layer 132S formed in the second hole H2 (see Fig.21A ) may also have a larger size in the first horizontal direction (X direction). As a result, the semiconductor device manufactured by the process described below may have a size similar to that of the reference Figure 4 The structure of the semiconductor device 100a described above is basically the same as the structure.

[0088] In some embodiments, reference Fig.17 The process of forming the second groove RS2 described above may be omitted. In this case, when compared with the case of forming the second groove RS2, the second hole H2 (see Fig. 20A ) may have a larger size in the first horizontal direction (X direction), and by using the second seed material layer SdL2 (see Fig. 20A ) The semiconductor layer 132S formed in the second hole H2 (see Fig.21A ) may also have a larger size in the first horizontal direction (X direction). As a result, the semiconductor device manufactured by the process described below may have a size similar to that of the reference Figure 5 The structure of the semiconductor device 100 b described above is basically the same as the structure.

[0089] Reference Fig.18 ,exist Fig.17 As a result, a second seed material layer SdL2 may be formed, the second seed material layer SdL2 is in the second groove RS2 and fills the second groove RS2, and the second seed material layer SdL2 covers the sidewalls of the first seed material layer SdL1, the sidewalls of the insulating spacer 116, the sidewalls of the first oxide layer OX1, the sidewalls of the insulating liner 118, and the upper surface of the lower insulating material layer 114S. Next, a second oxide layer OX2 may be formed, and a third oxide layer OX3 may be formed, the second oxide layer OX2 covers the surface of the second seed material layer SdL2 and conforms to the surface of the second seed material layer SdL2, and the third oxide layer OX3 covers the upper surface of the second oxide layer OX2 and the upper surface of the dummy gate layer Py1.

[0090] In some embodiments, the second oxide layer OX2 and the third oxide layer OX3 may be formed of a silicon oxide layer. In some embodiments, the first seed material layer SdL1 and the second seed material layer SdL2 may include substantially the same material.

[0091] Reference Fig.19A and Fig.19B ,exist Fig.18 In the result of the above, the upper surface of the dummy gate layer Py1 may be exposed by removing a portion of the third oxide layer OX3 overlapping the dummy gate layer Py1 in the vertical direction (Z direction). Next, the first hole H1 may be formed by removing the exposed dummy gate layer Py1. Next, the portion of the lower insulating material layer 114S exposed by the first hole H1 may be removed. At this time, the remaining portion of the lower insulating material layer 114S may be defined as the lower insulating layer 114.

[0092] Reference Fig. 20A and Fig. 20B ,exist Fig.19A and Fig.19BAs a result, the second hole H2 may be formed by removing the second sacrificial layer SL2 exposed through the first hole H1. The first hole H1 and the second hole H2 may be communicatively connected to each other.

[0093] Reference Fig.21A and Fig. 21B ,exist Fig. 20A and 20B As a result, the semiconductor layer 132S may be formed. The semiconductor layer 132S may be formed inside the first seed material layer SdL1 and the second seed material layer SdL2 through an epitaxial growth process using the first seed material layer SdL1 and the second seed material layer SdL2.

[0094] Reference Fig.22A and Fig. 22B ,exist Fig.21A and Fig. 21B As a result, a dielectric material layer 142S1 covering the exposed surface of each of the third oxide layer OX3, the insulating liner 118, the first oxide layer OX1, the first sacrificial layer SL1, the semiconductor layer 132S, the lower insulating layer 114 and the etch stop layer 112 may be formed. In some embodiments, the dielectric material layer 142S1 may be formed by using an atomic layer deposition (ALD) process. Next, a third sacrificial layer SL3 may be formed, which fills the first hole H1 and the second hole H2 and covers the upper surface of the third oxide layer OX3. In some embodiments, the third sacrificial layer SL3 may not cover the upper surface of the third oxide layer OX3. In some embodiments, the third sacrificial layer SL3 may include, for example, a metal oxide. In some embodiments, the third sacrificial layer SL3 may be formed by using an ALD process or a chemical vapor deposition (CVD) process.

[0095] Reference Fig.23 ,exist Fig.22A and Fig. 22B As a result, a portion of the dielectric material layer 142S1, a portion of the third oxide layer OX3, and a portion of the third sacrificial layer SL3 may be removed. Therefore, upper surfaces of the third sacrificial layer SL3, the insulating liner 118, and the second oxide layer OX2 may be coplanar.

[0096] Reference Fig.24 , available from Fig.23 As a result, the second oxide layer OX2 is removed. Next, a third groove RS3 may be formed by sequentially removing the second seed material layer SdL2 and a portion of the first seed material layer SdL1 exposed by removing the second oxide layer OX2. At this time, the remaining portion of the first seed material layer SdL1 that has not been removed may be defined as a seed layer 134. The third groove RS3 may expose a portion of the surface of the semiconductor layer 132S.

[0097] Reference Fig.25 ,exist Fig.24 As a result, the semiconductor layer 132S (see Fig.24 ) is doped with a portion of the substrate exposed by the third recess RS3. In some embodiments, the impurity may be a p-type impurity or an n-type impurity. The p-type impurity may be, for example, boron, and the n-type impurity may be, for example, phosphorus. In some embodiments, the concentration of the doped impurity may be from about 10 18 / cm 3 to about 10 21 / cm 3 In some embodiments, doping with impurities may be performed by using a plasma process. After doping with impurities is performed, a portion of the semiconductor layer 132S that is not doped with impurities may be defined as a horizontal semiconductor layer 132, and a portion of the semiconductor layer 132S that is doped with impurities may be defined as a vertical semiconductor layer 136.

[0098] Reference Fig.26 ,exist Fig.25 As a result, source / drain contacts 120 contacting the vertical semiconductor layer 136 may be formed. The source / drain contacts 120 may be formed by forming a first metal layer 122 conformal to an exposed surface of each of the insulating liner 118, the first oxide layer OX1, the insulating spacer 116, the seed layer 134, the vertical semiconductor layer 136, and the lower insulating layer 114, and then forming a second metal layer 124 covering the exposed surface of the first metal layer 122. The first metal layer 122 and the second metal layer 124 may be formed by using, for example, an ALD process or a CVD process.

[0099] Reference Fig.27A and Fig.27B ,exist Fig.26 As a result, the third hole H3 may be formed by removing a portion of the third sacrificial layer SL3.

[0100] Reference Fig.28A and Fig.28B ,exist Fig.27A and Fig.27B As a result, the portion of the dielectric material layer 142S1 exposed by the third hole H3 may be removed, and the first oxide layer OX1 exposed by the removed portion of the dielectric material layer 142S1 may be removed (see Fig.27A ). The third hole H3 may be expanded by removing the portion of the dielectric material layer 142S1 and the first oxide layer OX1.

[0101] Reference Fig.29A and Fig.29B ,exist Fig.28A and Fig.28BAs a result, the first sacrificial layer SL1 can be removed through the third hole H3 (see Fig.28A ) and the third sacrificial layer SL3. The third hole H3 may be expanded by removing the first sacrificial layer SL1 located on the relatively upper side among the first sacrificial layers SL1. In addition, the fourth hole H4 may be formed by removing the third sacrificial layer SL3, and the fifth hole H5 may be formed by removing the first sacrificial layer SL1 located on the relatively lower side among the first sacrificial layer SL1. The third hole H3, the fourth hole H4, and the fifth hole H5 may be connected to each other.

[0102] Reference Fig. 30A and Fig. 30B ,exist Fig.29A and Fig.29B As a result, a dielectric material layer may be formed, which covers the exposed surface of each of the etch stop layer 112, the lower insulating layer 114, the seed layer 134, and the horizontal semiconductor layer 132. The dielectric material layer together with the remaining dielectric material layer 142S1 may be defined as a first dielectric material layer 142S2. Next, a second dielectric material layer 144S covering the surface of the first dielectric material layer 142S2 may be formed, and a metal material layer 150L filling the third hole H3, the fourth hole H4, and the fifth hole H5 may be formed.

[0103] The first dielectric material layer 142S2 may include a material substantially the same as the dielectric material layer 142S1. For example, the dielectric material layer 142S1 and the first dielectric material layer 142S2 may include silicon oxide. The second dielectric material layer 144S may include a metal nitride layer. The metal material layer 150L may include a metal, a metal carbide, or a combination thereof. The metal material layer 150L may be formed using an ALD process or a CVD process.

[0104] Reference Fig.31A and Fig.31B ,exist Fig. 30A and Fig. 30B As a result, a portion of each of the first dielectric material layer 142S2, the second dielectric material layer 144S, and the metal material layer 150L may be removed. At this time, the remaining first dielectric material layer 142S2, the second dielectric material layer 144S, and the metal material layer 150L may be defined as a first gate dielectric layer 142, a second gate dielectric layer 144, and a gate line 150 (e.g., a main gate portion 150M and a plurality of sub-gate portions 150S), respectively.

[0105] Next, in Fig.31A and Fig.31B As a result, a barrier layer 160 may be formed in the region where the portion of each of the first dielectric material layer 142S2, the second dielectric material layer 144S, and the metal material layer 150L is removed (see Figure 2) and the upper insulating layer 170 (see Figure 2 ), therefore, it is possible to produce Figures 1 to 3 The semiconductor device 100 shown in FIG.

[0106] Figure 32 to Figure 37 is a cross-sectional view for explaining a method of manufacturing a semiconductor device 200 according to some embodiments. Specifically, Figure 32 to Figure 37 is shown sequentially along Figure 1 A cross-sectional view of the semiconductor device 200 taken along the line AA′ in FIG. Figure 32 to Figure 37 It is used to illustrate the execution of reference Figures 12 to 17 A cross-sectional view of a subsequent process following the described process.

[0107] Refer to Fig.17 and Fig.32 ,exist Fig.17 As a result, a second seed material layer SdL2 can be formed, the second seed material layer SdL2 can be in the second groove RS2 and can fill the second groove RS2, and the second seed material layer SdL2 can cover the exposed surface of the first seed material layer SdL1, the sidewalls of the insulating spacer 116, the sidewalls of the first oxide layer OX1, the sidewalls of the insulating liner 118 and the upper surface of the lower insulating material layer 114S.

[0108] Reference Fig.33 ,exist Fig.32 As a result, a portion of the second seed material layer SdL2 may be removed such that only a remaining portion of the second seed material layer SdL2 remains in the second groove RS2.

[0109] Reference Fig.34 ,exist Fig.33 As a result, a second oxide layer OX2 may be formed, and a third oxide layer OX3 may be formed, the second oxide layer OX2 may cover the exposed surface of each of the lower insulating material layer 114S, the insulating spacer 116, the first oxide layer OX1, the insulating liner 118, and the second seed material layer SdL2, and the third oxide layer OX3 may cover the upper surface of the second oxide layer OX2 and the upper surface of the dummy gate layer Py1. That is, compared with the reference Fig.18 The process described is compared to the reference Fig.33 and Fig.34 In the described process, a portion of the second seed material layer SdL2 may be first removed before forming the second oxide layer OX2.

[0110] Reference Fig.35 ,exist Fig.34As a result, the upper surface of the dummy gate layer Py1 may be exposed by removing a portion of the third oxide layer OX3 overlapping the dummy gate layer Py1 in the vertical direction (Z direction). Next, the first hole H1 may be formed by removing the exposed dummy gate layer Py1. Next, the second hole H2 may be formed by removing the second sacrificial layer SL2 exposed by the first hole H1. The first hole H1 and the second hole H2 may be connected to each other.

[0111] Reference Fig.36 ,exist Fig.35 As a result, a semiconductor layer 232S may be formed. The semiconductor layer 232S may be formed using a first seed material layer SdL1 and a second seed material layer SdL2 (see Fig.35 ) is formed by an epitaxial growth process. In some embodiments, both the first seed material layer SdL1 and the second seed material layer SdL2 can be replaced with the semiconductor layer 232S. This can be achieved by using a semiconductor layer including the semiconductor layer 232S of the reference Fig.21A and Fig. 21B The described process is implemented by using a seed material layer of a different material or the same material but changing the conditions of the formation process of the semiconductor layer 232S.

[0112] Reference Fig.37 ,exist Fig.36 As a result, a dielectric material layer 142S1 may be formed, and the dielectric material layer 142S1 may cover the exposed surface of each of the first oxide layer OX1, the first sacrificial layer SL1, the semiconductor layer 232S, the lower insulating layer 114, and the etch stop layer 112. Next, a third sacrificial layer SL3 may be formed, and the third sacrificial layer SL3 may fill the first hole H1 and the second hole H2 and may cover the upper surface of the third oxide layer OX3. Next, a portion of the dielectric material layer 142S1, a portion of the third oxide layer OX3, and a portion of the third sacrificial layer SL3 may be removed.

[0113] Reference Fig.38 , available from Fig.37 As a result, the second oxide layer OX2 is removed. Next, the portion of the semiconductor layer 232S exposed by removing the second oxide layer OX2 may be doped with impurities. As a result, the portion of the semiconductor layer 232S not doped with impurities may be defined as a horizontal semiconductor layer 232, and the portion of the semiconductor layer 232S doped with impurities may be defined as a vertical semiconductor layer 236.

[0114] While the inventive concept has been particularly shown and described with reference to certain examples of embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: a fin-type active region extending in length in a first horizontal direction on the substrate; A horizontal semiconductor layer on the fin-type active region; a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer; a gate line surrounding the horizontal semiconductor layer and the seed layer on the fin-type active region and extending in length in a second horizontal direction intersecting the first horizontal direction; as well as a pair of vertical semiconductor layers, respectively on a first side and a second side of the horizontal semiconductor layer in a first horizontal direction on the fin type active region, and the horizontal semiconductor layer is between the pair of vertical semiconductor layers, The inner wall of each of the pair of vertical semiconductor layers contacts the horizontal semiconductor layer, and the upper surface or the lower surface of the pair of vertical semiconductor layers contacts the seed layer.

2. The semiconductor device according to claim 1, wherein A length of the seed layer in the first horizontal direction is greater than a length of the horizontal semiconductor layer in the first horizontal direction.

3. The semiconductor device according to claim 1, wherein The horizontal semiconductor layer is a first horizontal semiconductor layer, and the semiconductor device further includes a second horizontal semiconductor layer facing the first horizontal semiconductor layer in a vertical direction, and Upper surfaces of the pair of vertical semiconductor layers are coplanar with an upper surface of the first horizontal semiconductor layer, and lower surfaces of the pair of vertical semiconductor layers are coplanar with a lower surface of the second horizontal semiconductor layer.

4. The semiconductor device according to claim 1, wherein The horizontal semiconductor layer includes a two-dimensional semiconductor material, and the two-dimensional semiconductor material includes a transition metal dichalcogenide (TMD).

5. The semiconductor device according to claim 4, wherein: The seed layer includes: An oxide of a transition metal or a catalyst of an oxide of a transition metal included in a TMD.

6. The semiconductor device according to claim 4, wherein The pair of vertical semiconductor layers includes a two-dimensional semiconductor material doped with impurities, and The two-dimensional semiconductor material of the pair of vertical semiconductor layers is the same as the two-dimensional semiconductor material of the horizontal semiconductor layer.

7. The semiconductor device according to claim 1, wherein The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an inner wall of the insulating spacer on the side wall of the main gate portion overlaps an outer wall of one of the pair of vertical semiconductor layers in a vertical direction intersecting the first horizontal direction and the second horizontal direction.

8. The semiconductor device according to claim 1, wherein The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an outer wall of one of the pair of vertical semiconductor layers is located between an inner wall of an insulating spacer on a side wall of the main gate portion and an outer wall of the insulating spacer.

9. The semiconductor device according to claim 1, wherein: The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an outer wall of the insulating spacer on the side wall of the main gate portion overlaps an outer wall of one of the pair of vertical semiconductor layers in a vertical direction intersecting the first horizontal direction and the second horizontal direction.

10. The semiconductor device according to any one of claims 1 to 9, further comprising: A first source / drain contact and a second source / drain contact each contact an outer wall of a corresponding one of the pair of vertical semiconductor layers and are adjacent to a gate line, and the gate line is between the first source / drain contact and the second source / drain contact.

11. The semiconductor device according to claim 10, wherein Each of the first source / drain contact and the second source / drain contact includes: a first metal layer contacting an outer wall of the corresponding vertical semiconductor layer; and The second metal layer covers the surface of the first metal layer.

12. The semiconductor device according to claim 11, wherein The first metal layer includes Sb, Bi, In, Se, or a combination of two or more thereof, and the second metal layer includes Au, Ni, Pd, Pt, or a combination of two or more thereof.

13. A semiconductor device comprising: a fin-type active region extending in length in a first horizontal direction on the substrate; a pair of horizontal semiconductor layers on the fin-type active region and facing each other in a vertical direction; a gate line surrounding the horizontal semiconductor layer on the fin-type active region and extending in length in a second horizontal direction intersecting the first horizontal direction; as well as a pair of vertical semiconductor layers on the fin-type active region on a first side and a second side of the pair of horizontal semiconductor layers in a first horizontal direction, and between the pair of horizontal semiconductor layers, Among them, the inner wall of each of the pair of vertical semiconductor layers contacts the pair of horizontal semiconductor layers, the upper surfaces of the pair of vertical semiconductor layers are coplanar with the upper surface of the horizontal semiconductor layer among the pair of horizontal semiconductor layers that is located relatively farther away from the fin-type active region, and the lower surfaces of the pair of vertical semiconductor layers are coplanar with the lower surface of the horizontal semiconductor layer among the pair of horizontal semiconductor layers that is located relatively closer to the fin-type active region.

14. The semiconductor device according to claim 13, further comprising: A gate dielectric layer is between the gate line and the horizontal semiconductor layer, wherein the upper surface and the lower surface of the pair of vertical semiconductor layers contact the gate dielectric layer.

15. The semiconductor device according to claim 13 or 14, wherein: The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an inner wall of the insulating spacer on a sidewall of the main gate portion overlaps an outer wall of one of the pair of vertical semiconductor layers in a vertical direction.

16. The semiconductor device according to claim 13 or 14, wherein: The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an outer wall of one of the pair of vertical semiconductor layers is located between an inner wall of an insulating spacer on a side wall of the main gate portion and an outer wall of the insulating spacer.

17. The semiconductor device according to claim 16, wherein: An upper surface and a lower surface of the one vertical semiconductor layer contact the insulating spacer.

18. The semiconductor device according to claim 13 or 14, wherein: The gate line includes a main gate portion and a sub-gate portion, and the pair of vertical semiconductor layers extend in a first horizontal direction so that an outer wall of the insulating spacer on the side wall of the main gate portion overlaps an outer wall of one of the pair of vertical semiconductor layers in a vertical direction.

19. The semiconductor device according to claim 18, wherein: An upper surface and a lower surface of the one vertical semiconductor layer contact the insulating spacer.

20. A semiconductor device comprising: a fin-type active region extending in length in a first horizontal direction on the substrate; a pair of horizontal semiconductor layers on the fin-type active region and facing each other in a vertical direction; a pair of seed layers on the fin-type active region and respectively contacting the pair of horizontal semiconductor layers; a gate line surrounding the pair of horizontal semiconductor layers and the pair of seed layers on the fin-type active region and extending in length in a second horizontal direction intersecting the first horizontal direction; a pair of vertical semiconductor layers, on the fin-type active region, respectively on a first side and a second side of the pair of horizontal semiconductor layers in a first horizontal direction, and between the pair of horizontal semiconductor layers; as well as a pair of source / drain contacts adjacent to the gate line, the gate line being between the pair of source / drain contacts, Wherein, inner walls of the pair of vertical semiconductor layers respectively contact the pair of horizontal semiconductor layers, upper surfaces and lower surfaces of the pair of vertical semiconductor layers contact the pair of seed layers, the upper surface of each of the pair of vertical semiconductor layers is coplanar with the upper surface of the horizontal semiconductor layer located on the relatively upper side among the pair of horizontal semiconductor layers, and the lower surface of each of the pair of vertical semiconductor layers is coplanar with the lower surface of the horizontal semiconductor layer located on the relatively lower side among the pair of horizontal semiconductor layers.

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