Semiconductor device and method of manufacturing the same

Abstract

Embodiments relate to a semiconductor device and a method of manufacturing the same. The gate electrode has a first side surface portion facing a region including at least the second semiconductor portion among side surfaces of the mesa portion of the semiconductor layer, a second side surface portion located on the opposite side of the first side surface portion in the second direction, and a bottom portion inclined with respect to the first side surface portion and the second side surface portion and connecting the first side surface portion and the second side surface portion. A first corner between the first side portion and the bottom; and a second corner between the second side portion and the bottom. If a straight line that passes through the first corner and extends in the first direction is a first straight line, and a straight line that passes through the first corner and the second corner is a second straight line, the angle formed by the first straight line and the second straight line is 60 degrees or less.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-115138 (filing date: July 13, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] A semiconductor device having a trench gate structure in which a gate electrode is provided in a trench formed in a semiconductor layer is widely used for power control, for example. Summary of the invention

[0005] According to an embodiment, a semiconductor device comprises: a semiconductor layer having a first semiconductor portion of a first conductivity type, a second semiconductor portion of a second conductivity type provided on the first semiconductor portion, and a third semiconductor portion of the first conductivity type provided on the second semiconductor portion, and having a mesa portion including a part of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion and extending in a first direction; a gate electrode facing a side surface of the mesa portion; and a first insulating portion provided between the gate electrode and the side surface of the mesa portion; the gate electrode having: a first side surface portion facing at least one of the side surfaces of the mesa portion including the second semiconductor portion The conductor portion is disposed in opposite areas; a second side portion, which is located on the opposite side of the first side portion in a second direction orthogonal to the first direction; a bottom portion, which is inclined relative to the first side portion and the second side portion and connects the first side portion and the second side portion; a first corner portion, which is located between the first side portion and the bottom portion; and a second corner portion, which is located between the second side portion and the bottom portion; if a straight line passing through the first corner portion and extending along the first direction is set as a first straight line, and a straight line passing through the first corner portion and the second corner portion is set as a second straight line, then an angle formed by the first straight line and the second straight line is less than 60°.

[0006] According to the embodiment, a semiconductor device capable of reducing the variation in the amount of charge between the gate and the drain and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0008] Figure 2 : is a graph showing the result of simulating the sensitivity of the variation of Qgd with respect to the variation of the position of the first corner portion of the gate electrode.

[0009] Figure 3 to Figure 9 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0010] The following describes the implementation mode with reference to the accompanying drawings. In addition, in each of the drawings, the same reference numerals are used for the same structure. In the following implementation mode, the first conductivity type is described as an n-type and the second conductivity type is described as a p-type, but the first conductivity type may be a p-type and the second conductivity type may be an n-type.

[0011] like Figure 1 As shown, the semiconductor device according to the embodiment includes a semiconductor layer 10 and a trench structure 100 .

[0012] The semiconductor layer 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in a first direction Z. The first direction Z is a direction connecting the first surface 10A and the second surface 10B at the shortest distance. Figure 1 In the diagram, a direction perpendicular to the first direction Z is set as a second direction X. In addition, a direction perpendicular to the first direction Z and the second direction X is set as a third direction Y. In addition, in the first direction Z, a direction toward the first surface 10A is set as an upper direction, and a direction toward the second surface 10B is set as a lower direction.

[0013] As a material of the semiconductor layer 10 , for example, silicon can be used. Alternatively, as a material of the semiconductor layer 10 , for example, silicon carbide, gallium nitride, etc. can also be used.

[0014] The semiconductor layer 10 includes an n-type first semiconductor portion 11, a p-type second semiconductor portion 12 provided on the first semiconductor portion 11, and an n-type third semiconductor portion 13 provided on the second semiconductor portion 12. The n-type impurity concentration of the third semiconductor portion 13 is higher than that of the first semiconductor portion 11.

[0015] In addition, the semiconductor layer 10 includes a mesa portion 10C that includes a portion of the first semiconductor portion 11, the second semiconductor portion 12, and the third semiconductor portion 13 and extends along the first direction Z. The first surface 10A includes the upper surface of the mesa portion 10C. The upper surface of the mesa portion 10C includes the upper surface of the third semiconductor portion 13. The mesa portion 10C extends along the third direction Y. For example, a plurality of mesa portions 10C are arranged in a manner separated from each other in the second direction X. Alternatively, a plurality of columnar mesa portions 10C may be arranged in the second direction X and the third direction Y.

[0016] The trench structure 100 is located in the semiconductor layer 10 on the first surface 10A side. For example, the trench structure 100 extends along the third direction Y. For example, a plurality of trench structures 100 are arranged in the semiconductor layer 10 in a manner separated from each other in the second direction X. Alternatively, a plurality of columnar trench structures 100 may be arranged in the second direction X and the third direction Y.

[0017] For example, the mesa portions 10C of the semiconductor layer 10 and the trench structures 100 are alternately arranged along the second direction X. The trench structures 100 are adjacent to the mesa portions 10C in the second direction X. The trench structures 100 are located between adjacent mesa portions 10C in the second direction X. The mesa portions 10C are located between adjacent trench structures 100 in the second direction X.

[0018] The trench structure 100 includes a gate electrode 30 and an insulating member 40 .

[0019] The gate electrode 30 faces the side surface of the mesa portion 10C in the second direction X. The side surface of the mesa portion 10C includes the side surface of a portion of the first semiconductor portion 11, the side surface of the second semiconductor portion 12, and the side surface of the third semiconductor portion 13. As a material of the gate electrode 30, for example, polycrystalline silicon having conductivity can be used.

[0020] The gate electrode 30 has a first side surface portion 31 , a second side surface portion 32 , a bottom portion 33 , a first corner portion C1 , and a second corner portion C2 .

[0021] The first side surface portion 31 faces a region of the side surface of the mesa portion 10C that includes at least the second semiconductor portion 12. Figure 1 In the illustrated example, the position of the upper end of the first side surface portion 31 in the first direction Z is located closer to the third semiconductor portion 13 than the boundary between the second semiconductor portion 12 and the third semiconductor portion 13 .

[0022] The second side surface portion 32 is located on the opposite side of the first side surface portion 31 in the second direction X. The length of the second side surface portion 32 in the first direction Z is longer than the length of the first side surface portion 31 in the first direction Z.

[0023] The bottom portion 33 is inclined relative to the first side portion 31 and the second side portion 32, and connects the first side portion 31 and the second side portion 32. In cross-section, the shape of the bottom portion 33 is not limited to a straight line, and may be a curved line, a convex shape, a concave shape, or a combination of two or more of these shapes.

[0024] The first corner C1 is located between the first side surface 31 and the bottom 33. For example, the angle formed by the first side surface 31 and the bottom 33 inside the gate electrode 30 (the inner angle of the first corner C1) is greater than 90°.

[0025] The second corner C2 is located between the second side surface 32 and the bottom 33. For example, the angle formed by the second side surface 32 and the bottom 33 on the inner side of the gate electrode 30 (the inner angle of the second corner C2) is less than 90°. The position of the second corner C2 in the first direction Z is located below the position of the first corner C1 in the first direction Z.

[0026] The insulating member 40 includes a first insulating portion 41 provided between the gate electrode 30 and the side surface of the mesa portion 10C of the semiconductor layer 10. The maximum thickness in the second direction X of the first insulating portion 41 between the first side surface portion 31 of the gate electrode 30 and the side surface of the mesa portion 10C is thinner than the maximum thickness in the second direction X of the first insulating portion 41 between the bottom 33 of the gate electrode 30 and the side surface of the mesa portion 10C.

[0027] The trench structure 100 may further include a conductive member 50. The conductive member 50 faces the second side surface 32 of the gate electrode 30 in the second direction X and extends downward from the bottom 33 of the gate electrode 30 in the first direction Z. As a material of the conductive member 50, for example, conductive polysilicon can be used.

[0028] One trench structure 100 has, for example, two gate electrodes 30 provided apart from each other in the second direction X. For example, the conductive member 50 is located between the second side surfaces 32 of the two gate electrodes 30 . The conductive member 50 extends downward from a portion located between the two gate electrodes 30 .

[0029] The conductive member 50 is electrically connected to the first electrode 21 described later. Alternatively, a potential lower than that of the second electrode 22 described later, which is applied with a higher potential than the first electrode 21, may be applied to the conductive member 50. The conductive member 50 can relax the electric field (longitudinal electric field) in the first direction Z, and can improve the withstand voltage.

[0030] The insulating member 40 is located between the gate electrode 30 and the semiconductor layer 10, between the conductive member 50 and the semiconductor layer 10, and between the gate electrode 30 and the conductive member 50. As a material of the insulating member 40, silicon oxide can be used, for example.

[0031] The insulating member 40 includes a second insulating portion 42 , a third insulating portion 43 , and a fourth insulating portion 44 in addition to the above-mentioned first insulating portion 41 .

[0032] The second insulating portion 42 is located in the second direction X between the second side surface portion 32 of the gate electrode 30 and the conductive component 50 .

[0033] The third insulating portion 43 is provided between the conductive member 50 and the first semiconductor portion 11 of the semiconductor layer 10 .

[0034] The fourth insulating portion 44 is located in the first direction X between the gate electrode 30 and the first electrode 21 and between the conductive member 50 and the first electrode 21 .

[0035] The semiconductor device of the embodiment further includes a first electrode 21 provided on the first surface 10A and a second electrode 22 provided on the second surface 10B. The first electrode 21 is in contact with the third semiconductor portion 13 and is electrically connected to the third semiconductor portion 13. In addition, the first electrode 21 is in contact with the second semiconductor portion 12 and is electrically connected to the second semiconductor portion 12.

[0036] The semiconductor layer 10 may further include an n-type fourth semiconductor portion 14 provided between the second electrode 22 and the first semiconductor portion 11. The n-type impurity concentration of the fourth semiconductor portion 14 is higher than the n-type impurity concentration of the first semiconductor portion 11. The fourth semiconductor portion 14 is electrically connected to the second electrode 22.

[0037] The semiconductor device of the embodiment has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. For example, the first electrode 21 functions as a source electrode, the second electrode 22 functions as a drain electrode, the first semiconductor portion 11 functions as a drift layer, the second semiconductor portion 12 functions as a base layer, the third semiconductor portion 13 functions as a source layer, and the fourth semiconductor portion 14 functions as a drain layer.

[0038] When a first potential (for example, a ground potential) is applied to the first electrode 21, a second potential (for example, a positive potential) higher than the first potential is applied to the second electrode 22, and a gate voltage greater than a threshold value is applied to the gate electrode 30, an n-type inversion layer (channel) is formed in the portion of the second semiconductor portion 12 facing the first side surface portion 31 of the gate electrode 30. Then, current flows between the second electrode 22 (drain electrode) and the first electrode 21 (source electrode) via the fourth semiconductor portion 14 (drain layer), the channel, and the third semiconductor portion 13 (source layer).

[0039] According to this embodiment, if a straight line passing through the first corner C1 of the gate electrode 30 and extending in the first direction Z is set as the first straight line L1, and a straight line passing through the first corner C1 and the second corner C2 is set as the second straight line L2, then the angle θ1 formed by the first straight line L1 and the second straight line L2 is less than 60°.

[0040] Figure 2 It is a graph showing the results of simulation of the sensitivity of the variation of Qgd with respect to the variation of the position of the first corner C1 of the gate electrode 30 in the first direction Z when the angle θ1 is changed to 20°, 30°, 40°, 60°, and 80°.

[0041] The horizontal axis represents the position Z in the first direction Z of the first corner C1 of the gate electrode 30. C1 The position Z of the first corner C1 when the on-resistance is the same in each case where the angle θ1 is 20°, 30°, 40°, 60°, and 80° C1 To obtain the same on-resistance, the smaller the angle θ1 is, the smaller the position Z of the first corner C1 is. C1 The closer the first surface 10A is, the closer the first surface 10A is to the first surface 10A.

[0042] The vertical axis represents the deviation of the charge amount Qgd between the gate electrode 30 and the first semiconductor portion 11 (hereinafter also referred to as the gate-drain charge amount). C1 When Qgd is 100%, it is assumed to be 100%.

[0043] Qgd is one of the parameters that affect the characteristics of the semiconductor device, and has an impact on the switching loss when the gate voltage applied to the gate electrode 30 is switched to turn the semiconductor device on and off. Therefore, it is required to keep Qgd within a specified range. In order to reduce the switching loss, the position Z of the first corner C1 is C1 When the deviation is ±10%, the deviation of Qgd is required to be suppressed to less than ±25%.

[0044] Depend on Figure 2 As a result, by setting the angle θ1 between the first straight line L1 and the second straight line L2 to 60° or less, the deviation of Qgd can be set to ±25% or less. In addition, by setting the angle θ1 to 40° or less, the deviation of Qgd can be set to less than ±25%.

[0045] Next, refer to Figure 3 to Figure 9 A method for manufacturing a semiconductor device according to an embodiment will be described.

[0046] like Figure 3 As shown, the method for manufacturing a semiconductor device according to the embodiment includes a step of forming a first trench T1 and a mesa portion 10C in the semiconductor layer 10. The first trench T1 is formed by, for example, RIE (Reactive Ion Etching).

[0047] The first trench T1 extends from the first surface 10A of the semiconductor layer 10 in the first direction Z. The mesa portion 10C is adjacent to the first trench T1 in the second direction X. For example, a plurality of first trenches T1 and a plurality of mesa portions 10C are alternately arranged in the second direction X, respectively.

[0048] Indicates the next process Figures 4 to 9 A portion of the first surface 10A side of a portion where the first trench T1 is adjacent to the mesa portion 10C is shown in an enlarged manner.

[0049] The method for manufacturing a semiconductor device according to the embodiment includes a step of forming an insulating member 40 in the first trench T1. Figure 4 As shown, the insulating member 40 covers the side surfaces of the mesa portion 10C (the side walls of the first trench T1) and the first surface 10A. In addition, the insulating member 40 covers the bottom wall of the first trench T1. The insulating member 40 is formed along the two side walls and the bottom wall of the first trench T1 that are opposite to each other in the second direction X. In the case of a semiconductor device having a conductive member 50, a space is left between the insulating members 40 located on the two side walls of the first trench T1, and the conductive member 50 is formed in the space.

[0050] like Figure 5 As shown, the method for manufacturing a semiconductor device of the embodiment includes a step of forming a second trench T2 on the insulating member 40. The second trench T2 is formed by dry etching. The second trench T2 is formed, for example, by RIE. During the RIE, the sputtered material is easily deposited on the sidewall of the second trench T2. Thus, the sidewall of the second trench T2 is inclined relative to the first direction Z in such a manner that the width in the second direction X is smaller as it approaches the lower side of the second trench T2.

[0051] The second trench T2 includes a first side wall T2a located on the side of the mesa portion 10C in the second direction X, a second side wall T2b located on the opposite side of the first side wall T2a in the second direction X, and a bottom wall T2c connecting the first side wall T2a and the second side wall T2b. The deviation of the depth of the first side wall T2a when the second trench T2 is formed is related to the position Z in the first direction Z of the first corner C1 of the gate electrode 30 described above. C1 The deviation corresponds to the deviation of Qgd.

[0052] The second side wall T2b is located closer to the interface between the conductive component 50 and the insulating component 40 than the first side wall T2a in the second direction X. Figure 4 In the state shown in FIG. 1 , the thickness of the insulating member 40 in the first direction Z on the mesa portion 10C side is thicker than the thickness of the insulating member 40 in the first direction Z on the conductive member 50 side. Figure 5 As shown, at the second trench T2, the depth in the first direction Z on the mesa portion 10C side is shallower than the depth in the first direction Z on the conductive component 50 side. That is, the position in the first direction Z of the lower end of the second side wall T2b is located below the position in the first direction Z of the lower end of the first side wall T2a.

[0053] Therefore, the bottom wall T2c is inclined relative to the first side wall T2a and the second side wall T2b. The second trench T2 has a third corner C3 located between the first side wall T2a and the bottom wall T2c and a fourth corner C4 located between the second side wall T2b and the bottom wall T2c. The position of the first direction Z of the fourth corner C4 is located below the position of the first direction Z of the third corner C3.

[0054] If a straight line passing through the third corner C3 of the second trench T2 and extending in the first direction Z is set as a third straight line L3, and a straight line passing through the third corner C3 and the fourth corner C4 is set as a fourth straight line L4, then an angle θ2 formed by the third straight line L3 and the fourth straight line L4 is less than 60°. In the second trench T2, a gate electrode 30 is formed as described later, so the angle θ2 of the second trench T2 corresponds to the angle θ1 of the gate electrode 30 described above.

[0055] like Figure 8 As shown in FIG. 1 , the method for manufacturing a semiconductor device of the embodiment includes a step of forming a gate electrode 30 in the second trench T2. The gate electrode 30 is formed, for example, by a CVD (Chemical Vapor Deposition) method. The gate electrode 30 is also deposited on the first surface 10A in the first direction Z, and then etched back, for example, by a CDE (Chemical Dry Etching) method. Thus, as shown in FIG. Fig. 9 As shown, the upper surface of the gate electrode 30 retreats to a predetermined position in the second trench T2.

[0056] In the aforementioned process of forming the second trench T2, Figure 5 As shown in FIG. 1 , a portion 40a of the insulating member 40 remains between the first side wall T2a and the side surface of the mesa portion 10C. Furthermore, the method for manufacturing a semiconductor device of the embodiment may include removing a portion 40a of the insulating member 40 between the first side wall T2a and the side surface of the mesa portion 10C after forming the second trench T2, so as to Figure 6 The method for manufacturing a semiconductor device of the embodiment may further include a step of exposing the side surface of the mesa portion 10C at the first side wall T2a as shown in FIG. Figure 7 Thus, the first insulating portion 41 which is not destroyed by RIE can be used as a gate insulating film instead of using the portion 40a of the insulating member 40 destroyed by RIE when forming the second trench T2 as a gate insulating film.

[0057] For example, a portion 40a of the insulating member 40 between the first side wall T2a and the side surface of the mesa portion 10C can be removed by wet etching. Thus, damage to the semiconductor layer 10 can be reduced compared to the case where a portion 40a of the insulating member 40 is removed by dry etching. In addition, the first insulating portion 41 can be formed by thermally oxidizing the exposed side surface of the mesa portion 10C.

[0058] Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor layer having a first semiconductor portion of a first conductivity type, a second semiconductor portion of a second conductivity type provided on the first semiconductor portion, and a third semiconductor portion of the first conductivity type provided on the second semiconductor portion, and having a mesa portion including a part of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion and extending in a first direction; a gate electrode facing a side surface of the mesa portion; and a first insulating portion provided between the gate electrode and the side surface of the mesa portion; The gate electrode has: a first side surface portion facing a region of the side surface of the mesa portion that includes at least the second semiconductor portion; a second side surface portion located on an opposite side of the first side surface portion in a second direction orthogonal to the first direction; a bottom portion, which is inclined relative to the first side portion and the second side portion and connects the first side portion and the second side portion; a first corner portion located between the first side portion and the bottom portion; and a second corner portion, located between the second side portion and the bottom portion; If a straight line passing through the first corner and extending in the first direction is set as a first straight line, and a straight line passing through the first corner and the second corner is set as a second straight line, Then the angle formed by the first straight line and the second straight line is less than 60°.

2. The semiconductor device according to claim 1, wherein: An angle formed by the first straight line and the second straight line is less than 40°.

3. The semiconductor device according to claim 1, wherein: Also available: a conductive member that is opposed to the second side surface portion of the gate electrode in the second direction and extends downward in the first direction relative to the bottom portion of the gate electrode; as well as The second insulating portion is located between the conductive component and the second side portion.

4. The semiconductor device according to claim 3, wherein: The semiconductor device further includes a first electrode provided on the mesa portion and electrically connected to the third semiconductor portion. The conductive component is electrically connected to the first electrode.

5. The semiconductor device according to claim 1, wherein: The position of the upper end of the first side surface portion in the first direction is located on the third semiconductor portion side relative to a boundary between the second semiconductor portion and the third semiconductor portion.

6. The semiconductor device according to claim 1, wherein: A length of the second side surface portion in the first direction is longer than a length of the first side surface portion in the first direction.

7. The semiconductor device according to claim 1, wherein: An angle formed by the first side surface portion and the bottom portion on the inner side of the gate electrode is greater than 90°.

8. The semiconductor device according to claim 1, wherein: An angle formed between the second side surface portion and the bottom portion on the inner side of the gate electrode is smaller than 90°.

9. The semiconductor device according to claim 1, wherein: The maximum thickness of the first insulating portion in the second direction between the first side surface portion of the gate electrode and the side surface of the mesa portion is thinner than the maximum thickness of the first insulating portion in the second direction between the bottom portion of the gate electrode and the side surface of the mesa portion.

10. A method for manufacturing a semiconductor device, characterized in that: have: A step of forming a first trench extending in the first direction from the first surface of a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in the first direction, and a mesa portion of the semiconductor layer adjacent to the first trench in a second direction orthogonal to the first direction; forming an insulating member in the first trench; a step of forming a second groove, which is a step of forming the second groove on the insulating member by dry etching, the second groove having a first side wall opposite to the side of the mesa portion in the second direction, a second side wall located on the opposite side of the first side wall in the second direction, a bottom wall inclined relative to the first side wall and the second side wall and connecting the first side wall and the second side wall, a third corner located between the first side wall and the bottom wall, and a fourth corner located between the second side wall and the bottom wall, wherein if a straight line passing through the third corner and extending in the first direction is set as a third straight line, and a straight line passing through the third corner and the fourth corner is set as a fourth straight line, an angle formed by the third straight line and the fourth straight line is 60 degrees or less; and The step of forming a gate electrode in the second trench.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In the step of forming the second trench, a portion of the insulating member remains between the first side wall and the side surface of the mesa portion. The method for manufacturing a semiconductor device further comprises: After forming the second trench, removing the portion of the insulating member between the first side wall and the side surface of the mesa portion to expose the side surface of the mesa portion at the first side wall; and and forming a first insulating portion on the exposed side surface of the mesa portion.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The portion of the insulating member between the first side wall and the side surface of the mesa portion is removed by wet etching.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The first insulating portion is formed by thermally oxidizing the exposed side surface of the mesa portion.

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