Method of fabricating stacked transistors, stacked transistors, devices, and apparatus

Abstract

The application provides a preparation method of a stacked transistor, a stacked transistor, a device and equipment, the method comprising: forming a fin structure on a substrate; performing a thermal oxidation treatment on the fin structure and the substrate to form an input / output oxidation insulating layer; depositing a first insulating material on the input / output oxidation insulating layer to form an insulating isolation layer; forming a first transistor based on the first fin structure; flipping and thinning the substrate until a first surface of a second fin structure and a part of the input / output oxidation insulating layer are exposed; etching the second fin structure to a preset height to form a first recess; removing the exposed input / output oxidation insulating layer and the input / output oxidation insulating layer located on the sidewall of the first recess to expose the insulating isolation layer; depositing the first insulating material in the first recess to form an insulating isolation structure; and forming a second transistor based on the second fin structure.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a method for fabricating a stacked transistor, a stacked transistor, a device, and an apparatus. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] Currently, the high thermal budget generated during the fabrication of stacked transistors remains a problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a method for fabricating stacked transistors, stacked transistors, devices, and apparatus to reduce the thermal budget generated during the fabrication of stacked transistors.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a stacked transistor, the stacked transistor comprising a first transistor and a second transistor stacked together; the method comprising: forming a fin structure on a substrate; the fin structure comprising a first fin structure and a second fin structure; performing thermal oxidation treatment on the fin structure and the substrate to form an input / output oxide insulating layer; the input / output oxide insulating layer covering the surface of the fin structure and the surface of the substrate; depositing a first insulating material on the input / output oxide insulating layer to form an insulating isolation layer; the insulating isolation layer covering the surface of the input / output oxide insulating layer; and forming a first transistor based on the first fin structure. The substrate is flipped and thinned until a first surface of the second fin structure and a portion of the input / output oxide insulating layer are exposed; the first surface is the surface of the second fin structure that is away from the first fin structure; the second fin structure is etched to a predetermined height to form a first groove; the exposed input / output oxide insulating layer and the input / output oxide insulating layer located on the sidewall of the first groove are removed to expose an insulating isolation layer; a first insulating material is deposited in the first groove to form an insulating isolation structure; the insulating isolation structure and the insulating isolation layer located on the sidewall of the second fin structure are integrated and cover the first surface; a second transistor is formed based on the second fin structure.

[0006] In some possible implementations, prior to forming the first transistor based on the first fin structure, the method further includes: depositing a second insulating material on the input / output oxide insulating layer to form a shallow trench isolation structure; the shallow trench isolation structure enclosing the fin structure; and removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the first fin structure.

[0007] In some possible implementations, before forming the second transistor based on the second fin structure, the method further includes: removing a second portion of the shallow trench isolation structure to expose the insulating isolation layer and the insulating isolation structure enclosing the second fin structure, and forming a shallow trench isolation layer; the shallow trench isolation layer is located between the first transistor and the second transistor for isolating the first transistor and the second transistor.

[0008] In some possible implementations, depositing a first insulating material in a first groove to form an insulating isolation structure includes: depositing the first insulating material in the first groove and on the insulating isolation layer to form the first insulating isolation structure; the first insulating isolation structure being integral with the insulating isolation layer; and removing the first insulating isolation structure and the insulating isolation layer to a predetermined height until a shallow groove isolation structure is exposed to form the insulating isolation structure.

[0009] In some possible implementations, after removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the first fin structure, the method further includes: depositing semiconductor material in the first gate region of the first transistor to form a first dummy gate structure;

[0010] After removing the second portion of the shallow trench isolation structure to expose the insulating isolation layer and the insulating isolation structure enclosing the second fin structure, the method further includes depositing semiconductor material in the second gate region of the second transistor to form a second dummy gate structure.

[0011] In some possible implementations, the above method further includes, during the formation of the first transistor, performing a gate cut-off process on the first dummy gate structure to form a first gate cut-off structure.

[0012] In some possible implementations, the above method further includes, during the formation of the second transistor, performing a gate cut-off process on the second dummy gate structure to form a second gate cut-off structure.

[0013] In a second aspect, embodiments of this application provide a stacked transistor, fabricated using the method described in the first aspect above. The stacked transistor includes: a first transistor; a second transistor; the first transistor and the second transistor stacked together; and a shallow trench isolation layer located between the first transistor and the second transistor for isolating the first transistor and the second transistor. The fin-like structures of the first transistor and the second transistor are formed in the same process. The surface of the fin-like structure located in the shallow trench isolation layer is covered by an input / output oxide insulating layer, and the surface of the input / output oxide insulating layer is covered by an insulating isolation layer. The input / output oxide insulating layer is formed by thermal oxidation treatment on the surface of the fin-like structure, and the insulating isolation layer is formed by depositing a first insulating material on the input / output oxide insulating layer.

[0014] Thirdly, embodiments of this application provide a semiconductor device comprising: stacked transistors as described in the second aspect above.

[0015] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is disposed on the circuit board.

[0016] In this application, an input / output oxide insulating layer and an insulating isolation layer are formed on the outside of the first fin structure and the second fin structure. The input / output oxide insulating layer and the insulating isolation layer on the surface of the first fin structure and the second fin structure are integrally formed. This can avoid the re-formation of the input / output oxide insulating layer on the surface of the second fin structure during the fabrication of the second transistor, and solve the problem of excessively high thermal budget caused by forming the input / output oxide insulating layer multiple times in stacked transistors.

[0017] Furthermore, the input / output oxide insulating layer and insulating isolation layer formed outside the first fin structure and the second fin structure can effectively protect the first fin structure and the second fin structure during the fabrication of stacked transistors.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram of an implementation process of the method for fabricating stacked transistors in this application.

[0021] Figure 2 This is a schematic diagram of a stacked transistor structure in an embodiment of this application;

[0022] Figures 3A to 3I This is a schematic diagram of the stacked crystal preparation process in an embodiment of this application;

[0023] Figure 4 This is a design layout of the gate cutoff structure in the embodiments of this application;

[0024] The above images:

[0025] 10. Stacked transistor; 11. First transistor; 111. First fin structure; 112. First spacer; 113. First interlayer dielectric layer; 114. First gate cut-off structure; 115. First source / drain structure; 116. First gate dielectric layer; 117. First gate structure; 118. First source / drain metal; 119. First metal interconnect layer; 12. Second transistor; 121. Second fin structure; 122. Second spacer; 123. Second interlayer dielectric layer; 124. Second gate cut-off structure; 125. Second source / drain structure; 126, Second gate dielectric layer; 127, Second gate structure; 128, Second source / drain metal; 129, Second metal interconnect layer; 13, Shallow trench isolation layer; 14, Insulating layer; 15, Carrier wafer; 21, Substrate; 22, Shallow trench isolation structure; 231, First dummy gate structure; 232, Second dummy gate structure; 241, First gate cut-off groove; 31, Input / output oxide insulating layer; 32, Insulating isolation layer; 33, First groove; 34, First insulating isolation structure; 35, Insulating isolation structure. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0027] With Moore's Law continuously evolving, and beyond the technology node of gate-all-around FETs (GAA), further miniaturizing transistor size is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. They are considered one of the key technologies for continuing the miniaturization of integrated circuits. Currently, the high thermal budget generated during the fabrication of stacked transistors remains a problem that urgently needs to be solved.

[0028] To address the aforementioned technical problems, this application provides a method for fabricating stacked transistors to reduce the thermal budget generated during the fabrication of stacked transistors.

[0029] In the embodiments of this application, the stacked transistors described above can be applied to semiconductor devices such as memory and processors.

[0030] In some embodiments, the stacked transistors include: a first transistor; a second transistor; a stacked arrangement of the first and second transistors; and a shallow trench isolation layer located between the first and second transistors for isolating the first and second transistors, wherein the fin structure of the first transistor and the fin structure of the second transistor are formed in the same process, the surface of the fin structure located in the shallow trench isolation layer is covered by an input / output (I / O) oxide insulating layer, and the surface of the input / output oxide insulating layer is covered by an insulating isolation layer; the input / output oxide insulating layer is formed by thermal oxidation treatment on the surface of the fin structure, and the insulating isolation layer is formed by depositing a first insulating material on the input / output oxide insulating layer.

[0031] In some embodiments, since the first fin structure (i.e., the fin structure of the first transistor) and the second fin structure (i.e., the fin structure of the second transistor) are formed through the same process, the first transistor formed based on the first fin structure and the second transistor formed based on the second fin structure are self-aligned in the direction of the active region.

[0032] In the embodiments of this application, the active region is a collective term for the source region, the drain region, and the channel region.

[0033] In the embodiments of this application, the first transistor and the second transistor in the stacked transistors can be transistors of the same type, such as fin field-effect transistors.

[0034] Figure 2 This refers to stacked transistors composed of fin field-effect transistors, which will be discussed below. Figure 2 The structure of the stacked transistor shown illustrates the fabrication method of the stacked transistor provided in the embodiments of this application.

[0035] Figure 1 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application. See also... Figure 1 As shown, the fabrication method of the above-mentioned stacked transistors may include:

[0036] S101, a fin-like structure is formed on the substrate; wherein the fin-like structure includes a first fin-like structure and a second fin-like structure.

[0037] Understandably, a substrate is provided, fin structures are patterned on the substrate, and then multiple fin structures are formed by etching.

[0038] It should be noted that, in Figure 2 The number of fin structures in this example is only one example. The number of fin structures can be designed according to actual needs, and this application does not specifically limit this.

[0039] In some embodiments, since the fin structures in the two transistors (i.e., the first fin structure and the second fin structure) are formed in the same etching process, a larger etching depth can be selected during the etching process, making the height of the fin structure sufficient to fabricate two transistors. In one example, the height of the fin structure can be greater than 100 nanometers (nm).

[0040] It should be noted that during the process of forming the fin structure through etching, a substrate of a predetermined height needs to be retained. The retained substrate can serve to support the fin structure.

[0041] S102, thermal oxidation treatment is performed on the fin structure and the substrate to form an input / output oxide insulating layer; wherein the input / output oxide insulating layer covers the surface of the fin structure and the surface of the substrate.

[0042] Understandably, thermal oxidation of the fin structure and the unetched substrate can form an input / output oxide (I / O oxide) covering the surfaces of both the fin structure and the substrate. This I / O oxide forms an input / output oxide insulating layer. This insulating layer can protect the fin structure in subsequent processes.

[0043] In some embodiments, the input / output oxides forming the input / output oxide insulating layer may include any of the following: silicon monoxide (SiO), silicon dioxide (SiO2), etc., but are not limited to the input / output oxides listed above. Other input / output oxides may also be selected according to actual needs. This application embodiment does not specifically limit this.

[0044] In some embodiments, the integrally formed input / output oxide insulating layer can effectively protect the fin structure in subsequent fabrication processes.

[0045] S103, a first insulating material is deposited on the input / output oxide insulating layer to form an insulating isolation layer. The insulating isolation layer covers the surface of the input / output oxide insulating layer.

[0046] Understandably, an insulating material (i.e., a first insulating material) is deposited on the surface of the input / output oxide insulating layer to form an insulating isolation layer that covers the surface of the input / output oxide insulating layer. This insulating isolation layer serves to protect the fin structure and the input / output oxide insulating layer in subsequent processes.

[0047] In some embodiments, the first insulating material forming the insulating isolation layer may be silicon nitride (SiN) or other insulating materials, and the embodiments of this application do not specifically limit this.

[0048] In some embodiments, the integrally formed insulating layer can work together with the input / output oxide insulating layer to protect the fin structure in subsequent fabrication processes.

[0049] In some embodiments, during the fabrication of conventional stacked transistors, the input / output insulating oxide layers in the first transistor and the second transistor are formed separately. That is, the input / output insulating oxide layer in the first transistor is formed during the formation of the first transistor, and the input / output insulating oxide layer in the second transistor is formed during the formation of the second transistor. This means that the high temperatures generated during the formation of the input / output insulating oxide layer in the second transistor may damage the first transistor. In the embodiments of this application, the integrally formed input / output insulating oxide layer avoids the above-mentioned problem, that is, it avoids the thermal damage to the stacked transistors that may occur during the formation of the input / output insulating oxide layer in the second transistor.

[0050] In some possible implementations, after S103 and before S104, the method may further include: depositing a second insulating material on the input / output oxide insulating layer to form a shallow trench isolation structure (STI); the shallow trench isolation structure enclosing the fin structure; and removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the first fin structure.

[0051] Understandably, after forming the input / output oxide insulating layer, a second insulating material of a predetermined height is deposited on the input / output oxide insulating layer to form a shallow trench isolation structure. The height of the shallow trench isolation structure is greater than the height of the fin structure, and the shallow trench isolation structure can enclose the insulating isolation layer. Next, the portion of the shallow trench isolation structure enclosing the first insulating isolation layer (i.e., the first part) is removed by a chemical-mechanical planarization (CMP) process until the first insulating isolation layer is exposed; wherein, the first insulating isolation layer is the portion of the insulating isolation layer corresponding to the first fin structure, and correspondingly, the second insulating isolation layer is the portion of the insulating isolation layer corresponding to the second fin structure.

[0052] In some embodiments, the second insulating material may include any of the following: silicon nitride (SiN, Si3N4), SiO2, or silicon oxycarbide (SiCO), etc. The second insulating material is not limited to the materials listed above, and other insulating materials may be selected according to actual needs; this application does not specifically limit this.

[0053] S104, based on the first fin structure, forms the first transistor.

[0054] Understandably, other structures in the first transistor, such as the first source / drain structure, the first gate structure, and the first metal interconnect layer, can be fabricated based on the first fin structure using standard transistor fabrication processes.

[0055] S105, the substrate is flipped and thinned until the first surface of the second fin structure and a portion of the input / output oxide insulating layer are exposed; wherein the first surface is the surface of the second fin structure that is away from the first fin structure.

[0056] Understandably, after the first transistor is formed, it is flipped so that the substrate is facing upwards, and then the substrate is thinned until the first surface of the second fin structure and the input / output oxide insulating layer previously covering the substrate are exposed.

[0057] In some embodiments, the substrate can be thinned using a chemical mechanical planarization process.

[0058] In some possible implementations, prior to S105 above, the method for fabricating the stacked transistor may further include: depositing an insulating material on the surface of the first transistor away from the second fin structure to form an insulating layer; and bonding the insulating layer to a carrier wafer.

[0059] In this embodiment, the bonded carrier wafer can provide physical support for the flipped first transistor after the wafer is flipped, effectively preventing the first transistor from being broken by external force during the fabrication of the second transistor.

[0060] It should be noted that the insulating material forming the insulating layer can be selected according to actual needs, and the embodiments of this application do not impose specific limitations on it.

[0061] S106, etch a second fin-like structure at a predetermined height to form a first groove.

[0062] Understandably, after exposing the first surface of the second fin structure, a portion of the second fin structure can be removed by selective etching, and the groove formed by the etching is the first groove.

[0063] S107, Remove the exposed input / output oxide insulation layer and the input / output oxide insulation layer located on the sidewall of the first groove to expose the insulation isolation layer.

[0064] Understandably, after the first groove is formed, the sidewall of the first groove is part of the input / output oxide insulating layer. Then, the input / output oxide insulating layer on the sidewall of the first groove and the input / output oxide insulating layer exposed after the wafer is flipped and the substrate is thinned are removed, so that the insulating isolation structure located above the shallow trench isolation structure is exposed.

[0065] S108, a first insulating material is deposited in the first groove to form an insulating isolation structure; the insulating isolation structure and the insulating isolation layer located on the sidewall of the second fin structure are integrated and cover the first surface.

[0066] Understandably, depositing the same first insulating material as the insulating layer in the first groove can form an insulating isolation structure. Because the same material is used, the insulating isolation structure and the insulating layer can be integrated, and the insulating isolation structure covers the first surface of the second fin structure.

[0067] In some possible implementations, S108 may include: depositing a first insulating material in the first groove and on the insulating isolation layer to form a first insulating isolation structure; the first insulating isolation structure being integral with the insulating isolation layer; removing the first insulating isolation structure and the insulating isolation layer at a predetermined height until the shallow groove isolation structure is exposed to form an insulating isolation structure.

[0068] Understandably, depositing a first insulating material in the first groove and on the exposed insulating layer can form a first insulating isolation structure. This first insulating isolation structure not only fills the first groove but also covers the exposed insulating layer, becoming integral with it. Next, selective etching removes the first insulating isolation structure and the exposed insulating layer to a predetermined height until a shallow trench isolation structure below the insulating layer is exposed. The unetched first insulating material inside the first groove forms the insulating isolation structure.

[0069] In some possible implementations, after S108 and before S109, the method may further include: removing a second portion of the shallow trench isolation structure to expose the insulating isolation layer and the insulating isolation structure that enclose the second fin structure, and forming a shallow trench isolation layer; the shallow trench isolation layer is located between the first transistor and the second transistor for isolating the first transistor and the second transistor.

[0070] Understandably, after the insulating isolation structure is formed, the portion of the shallow trench isolation structure that encloses the second insulating isolation layer (i.e., the second part) can be removed by selective etching until the second insulating isolation layer and the insulating isolation structure are exposed. During the etching process of the shallow trench isolation structure, the shallow trench isolation structure with a preset height is retained. The unetched shallow trench isolation structure is the shallow trench isolation layer, which is located between the first transistor and the second transistor and can be used to isolate the first transistor and the second transistor.

[0071] S109, based on the second fin structure, forms the second transistor.

[0072] Understandably, after forming the insulating isolation structure, a second transistor can be formed based on the second fin structure according to the standard process for manufacturing transistors.

[0073] In some embodiments, since the second transistor is formed based on the second fin structure after the first transistor is flipped, the second transistor and the first transistor are stacked back to back and self-aligned.

[0074] In some possible implementations, after removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the first fin structure, the method may further include: depositing semiconductor material in the first gate region of the first transistor to form a first dummy gate structure; after removing a second portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the second fin structure and the insulating isolation structure, the method may further include: depositing semiconductor material in the second gate region of the second transistor to form a second dummy gate structure.

[0075] Understandably, photolithography opens the first gate region of the first transistor, and depositing semiconductor material (such as polysilicon) in the first gate region can form the first dummy gate structure of the first transistor. Correspondingly, after wafer flipping and removing the second portion of the shallow trench isolation structure, photolithography opens the second gate region of the second transistor, and depositing semiconductor material (such as polysilicon) in the second gate region can form the second dummy gate structure of the second transistor.

[0076] In some possible implementations, the above method may further include, during the formation of the first transistor, performing a gate cut-off process on the first pseudo-gate structure of the first transistor to form a first gate cut-off structure.

[0077] Understandably, during the fabrication of the first transistor, after forming the first dummy gate structure in the first transistor, the first dummy gate structure can be subjected to gate cutting treatment to form a first gate cutting groove, and then insulating material can be filled into the first gate cutting groove to form a first gate cutting structure.

[0078] In some possible implementations, the above method may further include: performing a gate cut-off process on the second pseudo-gate structure of the second transistor to form a second gate cut-off structure.

[0079] Understandably, during the fabrication of the second transistor, after forming the second dummy gate structure in the second transistor, the second dummy gate structure can be subjected to gate cut-off processing to form a second gate cut-off groove. Then, insulating material is filled into the second gate cut-off groove to form a second gate cut-off structure.

[0080] In some possible implementations, S104 may include: photolithographically opening the first gate region of the first transistor; depositing polysilicon in the first gate region to form a first dummy gate structure; depositing insulating material on the sidewalls of the first dummy gate structure to form a first spacer wall; depositing dielectric material in other regions of the first transistor besides the first gate region to form a first interlayer dielectric layer; performing a gate cut-off process on the first dummy gate structure to form a first gate cut-off structure; removing the first interlayer dielectric layer; performing source-drain epitaxial growth in the first source-drain region of the first transistor to form a first source-drain structure; redepositing dielectric material to form the first interlayer dielectric layer; removing the first dummy gate structure and the input / output oxide insulating layer and isolation layer covering the surface of the first fin structure to expose the first fin structure; forming a first gate dielectric layer and a first gate structure in the first gate region; forming a first source-drain metal over the first source-drain structure; and performing back-end processes over the first gate structure and the first source-drain metal to form a first metal interconnect layer.

[0081] In some possible implementations, S109 may include: photolithographically opening the second gate region of the second transistor; depositing polysilicon in the second gate region to form a second dummy gate structure; depositing insulating material on the sidewalls of the second dummy gate structure to form a second spacer wall; depositing dielectric material in other regions of the second transistor besides the second gate region to form a second interlayer dielectric layer; performing a gate cut-off process on the second dummy gate structure to form a second gate cut-off structure; removing the second interlayer dielectric layer; performing source-drain epitaxial growth in the second source-drain region of the second transistor to form a second source-drain structure; redepositing dielectric material to form a second interlayer dielectric layer; removing the second dummy gate structure and the insulating isolation structure, insulating isolation layer, and input / output oxide insulating layer surrounding the second fin structure to expose the second fin structure; forming a second gate dielectric layer and a second gate structure in the second gate region; forming a second source-drain metal over the second source-drain structure; and performing a back-end process over the second gate structure and the second source-drain metal to form a second metal interconnect layer.

[0082] In the embodiments of this application, the first source-drain structure represents the source and / or drain in the first transistor. Correspondingly, other expressions related to "source-drain" in the embodiments of this application are used to represent "source and / or drain", such as: second source-drain structure, first source-drain metal and second source-drain metal, etc.

[0083] The stacked transistors provided in the embodiments of this application will be described below, taking the first transistor and the second transistor as fin field-effect transistors as examples. Figure 2 This is a schematic diagram of one structure of stacked transistors in an embodiment of this application. Figure 2(a) is the design layout of the stacked transistor. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the stacked transistor along the tangential direction of the gate structure (i.e., the AA' direction); (c) is a cross-sectional view of the stacked transistor along the tangential direction of the source-drain structure (i.e., the BB' direction); and (d) is a cross-sectional view of the stacked transistor along the tangential direction of the fin structure (i.e., the CC' direction).

[0084] See Figure 2 As shown, the stacked transistor 10 includes a first transistor 11, a second transistor 12, and a shallow trench isolation layer 13. The first transistor 11 and the second transistor 12 are stacked back-to-back. The shallow trench isolation layer 13 is located between the first transistor 11 and the second transistor 12 to isolate the first transistor 11 and the second transistor 12. The fin structure of the first transistor 11 and the fin structure of the second transistor 12 are formed in the same process. The surface of the fin structure in the shallow trench isolation layer 13 is covered by an input / output oxide insulating layer 31, and the surface of the input / output oxide insulating layer 31 is covered by an insulating isolation layer 32. The input / output oxide insulating layer 31 is formed by thermally oxidizing the fin structure, and the insulating isolation layer 32 is formed by depositing a first insulating material on the input / output oxide insulating layer 31.

[0085] Figure 2 The stacked transistor 10 shown can be used Figures 3A to 3I The process shown is used for preparation. Figures 3A to 3I This is a schematic diagram of the stacked crystal preparation process in an embodiment of this application.

[0086] In one example, the fabrication process of the stacked transistor 10 may include the following steps:

[0087] Step 1: Provide a substrate 21 (see...) Figure 3A (a)). The substrate can be a silicon (Si) substrate.

[0088] Step 2: Etch substrate 21 to form first fin structure 111 and second fin structure 121 (see...) Figure 3A (b) in the middle.

[0089] Step 3: Perform thermal oxidation on the unetched substrate 21 and the surfaces of the first fin structure 111 and the second fin structure 121 to form the input / output oxide insulating layer 31 (see...). Figure 3A (c) in the middle.

[0090] Step 4: Deposit a first insulating material on the input / output oxide insulating layer 31 to form an insulating isolation layer 32 (see...) Figure 3B (a) in the middle.

[0091] Step 5: A second insulating material is deposited on the insulating isolation layer 32, and a chemical mechanical planarization treatment is performed to form a shallow trench isolation structure 22. The height of the shallow trench isolation structure 22 is greater than the height of the fin structure (see [link to documentation]). Figure 3B (b) in the middle.

[0092] Step 6: By etching, remove the portion of the shallow trench isolation structure 22 that encloses the first fin structure 111 until the portion of the insulating isolation layer 32 corresponding to the first fin structure 111 is exposed; then, photolithography is used to open the first gate region of the first transistor 11, and polysilicon is deposited in the first gate region to form the first dummy gate structure 231 (see...). Figure 3B (c) in the middle.

[0093] Step 7: Deposit insulating material on the sidewalls of the first dummy gate structure 231 to form a first spacer wall 112; deposit interlayer dielectric in the region of the first transistor 11 other than the first gate region to form a first interlayer dielectric layer 113 (see...). Figure 3C (a) in the middle.

[0094] Step 8: Perform gate cut-off processing on the first pseudo-gate structure 231 to form the first gate cut-off groove 241 (see...) Figure 3C (b) in the middle.

[0095] Step 9: Deposit insulating material in the first gate cut-off groove 241 to form the first gate cut-off structure 114 (see...) Figure 3C (c) in the middle.

[0096] Step 10: Remove the first interlayer dielectric layer 113 (see...) Figure 3D (a) in the middle.

[0097] Step 11: Etch the first fin structure 111 to form a first source / drain trench; perform epitaxial growth of the source / drain in the first source / drain trench to form a first source / drain structure 115; redeposit interlayer dielectric in the first transistor 11, except for the first gate region, to form a first interlayer dielectric layer 113 (see...). Figure 3D (b) in the middle.

[0098] Step 12: Remove the portions of the first dummy gate structure 231, the insulating isolation layer 32 corresponding to the first fin structure 111, and the input / output oxide insulating layer 31 corresponding to the first fin structure 111 (i.e., the portions covering the surface of the first fin structure 111) to expose the first fin structure 111; then, deposit insulating material on the surface of the first fin structure 111 in the first gate region to form the first gate dielectric layer 116; fill the first gate region with metal material to form the first gate structure 117 (see...). Figure 3D (c) in the middle.

[0099] Step 13: Form a first source / drain metal 118 above the first source / drain structure 115; perform subsequent processes above the first gate structure 117 and the first source / drain metal 118 to form a first metal interconnect layer 119 (see...). Figure 3E (a) in the middle.

[0100] Step 14: Deposit insulating material on the first metal interconnect layer 119 to form an insulating layer 14. Bond the insulating layer 14 to the carrier wafer 15. Then, perform a flipping process on the first transistor 11 so that the substrate 21 faces upward (see...). Figure 3E (b) in the middle.

[0101] Step 15: Thinning and chemical mechanical planarization are performed on substrate 21 to expose the first surface of the input / output oxide insulating layer 31 and the second fin structure 121 (see...). Figure 3E (c) in the middle.

[0102] Step 16: Etch a portion of the second fin structure 121 to form the first groove 33 (see...) Figure 3F (a) in the middle.

[0103] Step 17: Remove the exposed input / output oxide insulating layer 31 by anisotropic etching until the insulating isolation layer 32 (i.e., the input / output oxide insulating layer 31 on the sidewall of the first groove 33 and the input / output oxide insulating layer 31 above the shallow trench isolation structure 22) is exposed (see...). Figure 3F (b) in the middle.

[0104] Step 18: Deposit a first insulating material in the first groove 33 and on the insulating layer 32 to form a first insulating structure 34 (see...) Figure 3F (c) in the middle.

[0105] Step 19: Using a chemical mechanical planarization process, a portion of the first insulating isolation structure 34 is removed, leaving only the first insulating material filling the first groove 33, forming the insulating isolation structure 35; and exposing the shallow groove isolation structure 22 (see...). Figure 3G (a)). In this case, the insulating isolation structure 35 and the insulating isolation layer 32 are integrated and together cover the first surface of the input / output oxide insulating layer 31 and the second fin structure 121.

[0106] Step 20: Remove the portion of the shallow trench isolation structure 22 that encloses the second fin structure 121, exposing the portion of the insulating isolation layer 32 that is connected to the second fin structure 121 and the insulating isolation structure 35, while retaining the shallow trench isolation structure 22 at a predetermined height. The retained shallow trench isolation structure 22 is the shallow trench isolation layer 13 (see...). Figure 3G (b) in the middle.

[0107] Step 21: Photolithography opens the second gate region of the second transistor 12, and polysilicon is deposited in the second gate region to form the second pseudo-gate structure 232 (see...). Figure 3G (c) in the middle.

[0108] Step 22: Deposit insulating material on the sidewalls of the second pseudo-gate structure 232 to form the second spacer wall 122; deposit interlayer dielectric in the region of the second transistor 12 other than the second gate region to form the second interlayer dielectric layer 123 (see...). Figure 3H (a) in the middle.

[0109] Step 23: Form the second gate cutoff structure 124 in the second transistor 12 (for specific process details, please refer to steps 8 and 9) (see...) Figure 3H (b) in the middle.

[0110] It should be noted that, in the process of fabricating stacked transistors, the gate cutting process of the dummy gate structure (i.e., the first dummy gate structure and the second dummy gate structure) to form the first gate cutting structure and the second gate cutting structure is only one example. It is also possible to omit the first gate cutting structure and the second gate cutting structure in the stacked transistor according to actual needs, that is, no gate cutting process is performed during the fabrication process. The embodiments of this application do not specifically limit this.

[0111] Step 24: Form the second source / drain structure 125 in the second transistor 12 (for specific process details, please refer to steps 10 and 11) (see...) Figure 3H (c) in the middle.

[0112] Step 25: Remove the portions of the second dummy gate structure 232, the insulating isolation structure 35, and the insulating isolation layer 32 corresponding to the second fin structure 121, as well as the portion of the input / output oxide insulating layer 31 covering the surface of the second fin structure 121. Deposit insulating material on the surface of the second fin structure 121 in the second gate region to form the second gate dielectric layer 126. Fill the second gate region with metal material to form the second gate structure 127 (see...). Figure 3I (a) in the middle.

[0113] Step 26: Form a second source / drain metal 128 above the second source / drain structure 125; perform subsequent processes above the second gate structure 127 and the second source / drain metal 128 to form a second metal interconnect layer 129 (see...). Figure 3I (b) in the middle.

[0114] Thus, the stacked transistor 10 was successfully fabricated using the method described above.

[0115] In some embodiments, the gate cut-off structure (i.e., the first gate cut-off structure and the second gate cut-off structure) can be designed as a gate cut-off hole or a gate cut-off line according to actual needs, and this application embodiment does not specifically limit this. In one example, different forms of the first gate cut-off structure and the second gate cut-off structure can be formed according to different design layouts; Figure 4 This is a design layout of the gate cutoff structure in the embodiments of this application; Figure 4 Image (a) shows a gate cut-off structure in the form of a gate cut-off hole. Figure 4 (b) shows a gate cut-off structure in the form of a gate cut-off line.

[0116] In some embodiments, a semiconductor device may include multiple stacked transistors, which play different roles within the device. Based on these functional differences, the stacked transistors in a semiconductor device can be categorized into logic transistors and input / output transistors. Logic transistors are primarily used to construct digital logic circuits and are distributed within the internal logic region of the semiconductor device; input / output transistors are used for the input and output interfaces of integrated circuits and are mainly distributed at the edges or peripheral areas of the semiconductor device.

[0117] In some embodiments, when the stacked transistors are logic transistors, the structure of the stacked transistors is as follows: Figure 2 As shown, there is no input / output oxide insulating layer or insulating isolation layer formed by input / output oxides on the surfaces of the first fin structure and the second fin structure; however, the surface of the fin structure located in the shallow trench isolation layer is covered with the input / output oxide insulating layer and the insulating isolation layer.

[0118] In some embodiments, when the stacked transistors are input / output transistors, since a high withstand voltage is required, it is not necessary to remove the input / output oxide insulating layer during the fabrication of the first and second transistors. In the final stacked transistor, the surface of the first fin structure is covered with input / output oxide, i.e., the input / output oxide insulating layer; the sidewalls of the second fin structure are covered with input / output oxide, i.e., the input / output oxide insulating layer (not shown in the figure). It should be noted that, since the first surface of the second fin structure is not covered by the input / output oxide insulating layer during the fabrication process, there is no input / output oxide on the first surface of the second fin structure in the final stacked transistor. The surface of the fin structure located in the shallow trench isolation layer is covered with the input / output oxide insulating layer and the insulating isolation layer.

[0119] It should be noted that the difference between stacked transistors as logic transistors and stacked transistors as input / output transistors can be reflected in the setting of the input / output oxide insulating layer, or in other aspects, such as differences in function and structure. This application will not elaborate on these differences in the embodiments.

[0120] In this embodiment, an input / output oxide insulating layer and an insulating isolation layer are formed on the outside of the first fin structure and the second fin structure. The input / output oxide insulating layer and the insulating isolation layer on the surface of the first fin structure and the second fin structure are integrally formed. This can avoid the re-formation of the input / output oxide insulating layer on the surface of the second fin structure during the fabrication of the second transistor, and solve the problem of excessively high thermal budget caused by forming the input / output oxide insulating layer multiple times in stacked transistors.

[0121] Furthermore, the input / output oxide insulating layer and insulating isolation layer formed outside the first fin structure and the second fin structure can effectively protect the first fin structure and the second fin structure during the fabrication of stacked transistors.

[0122] Furthermore, the stacked transistor fabrication method described in this application is an organic integration of current sequential and monolithic stacked transistor solutions. It boasts high reusability of mature technologies, avoiding extensive and costly process development to save costs, and is highly feasible. In this application embodiment, the stacked transistors employ a self-aligned "back-to-back" active region and metal gate design. The front and back transistors (i.e., the first and second transistors) have independent signal and power supply networks, interconnected through local interconnects. Without altering the ultra-miniaturized 4T track cell design, it significantly frees up metal wiring resources (improving efficiency by over 60%), offering enormous potential for collaborative optimization in process design. Finally, the stacked transistor fabrication method is compatible with existing mainstream device architectures, enabling the front and back stacking of planar transistors, fin field-effect transistors, nanosheet field-effect transistors, and even vertical field-effect transistors (VTFETs) without requiring special process development for specific device architectures. This provides high flexibility and strong scalability from the perspective of semiconductor process node iteration. Flip-chip stacked transistors are conceptually very advanced, possess significant industrial value, and are highly practical with broad expansion prospects.

[0123] Furthermore, the structure of the stacked transistors provided in this application embodiment can be inspected using analytical instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the stacked transistors provided in this application embodiment can be inspected using TEM slicing. For example, the input / output oxide insulating layer and insulating isolation layer located on the sidewalls of the fin structure can be observed in the shallow trench isolation layer.

[0124] This application provides a semiconductor device, including a stacked transistor as described in the above embodiments. Specific limitations of the stacked transistor can be found above. Figure 2 The stacked transistors shown will not be described in detail here.

[0125] This application provides an electronic device, including a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the stacked transistors described above. Specific limitations of the stacked transistors can be found above. Figure 2 This will not be elaborated upon here.

[0126] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0127] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, The stacked transistors include a first transistor and a second transistor stacked together; the method includes: A fin-like structure is formed on a substrate; the fin-like structure includes a first fin-like structure and a second fin-like structure; The fin structure and the substrate are subjected to thermal oxidation to form an input / output oxide insulating layer; the input / output oxide insulating layer covers the surface of the fin structure and the surface of the substrate. A first insulating material is deposited on the input / output oxide insulating layer to form an insulating isolation layer; the insulating isolation layer covers the surface of the input / output oxide insulating layer. The first transistor is formed based on the first fin structure; The substrate is flipped and thinned until a first surface of the second fin structure and a portion of the input / output oxide insulating layer are exposed; the first surface is the surface of the second fin structure that is away from the first fin structure. The second fin-like structure at a predetermined height is etched to form a first groove; Remove the exposed input / output oxide insulation layer and the input / output oxide insulation layer located on the sidewall of the first groove to expose the insulating isolation layer; The first insulating material is deposited in the first groove to form an insulating isolation structure; the insulating isolation structure and the insulating isolation layer located on the sidewall of the second fin structure are integrated and cover the first surface; The second transistor is formed based on the second fin structure.

2. The method according to claim 1, characterized in that, Prior to forming the first transistor based on the first fin structure, the method further includes: A second insulating material is deposited on the input / output oxide insulating layer to form a shallow trench isolation structure; the shallow trench isolation structure encloses the fin structure; Remove a first portion of the shallow trench isolation structure to expose the insulating isolation layer that encloses the first fin structure.

3. The method according to claim 2, characterized in that, Prior to forming the second transistor based on the second fin structure, the method further includes: The second portion of the shallow trench isolation structure is removed to expose the insulating isolation layer enclosing the second fin structure and the insulating isolation structure, and a shallow trench isolation layer is formed; the shallow trench isolation layer is located between the first transistor and the second transistor for isolating the first transistor and the second transistor.

4. The method according to claim 3, characterized in that, The step of depositing the first insulating material in the first groove to form an insulating isolation structure includes: The first insulating material is deposited in the first groove and on the insulating isolation layer to form a first insulating isolation structure; the first insulating isolation structure is integral with the insulating isolation layer. Remove the first insulating isolation structure and the insulating isolation layer at a predetermined height until the shallow groove isolation structure is exposed to form the insulating isolation structure.

5. The method according to claim 3, characterized in that, After removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the first fin structure, the method further includes: depositing semiconductor material in the first gate region of the first transistor to form a first dummy gate structure; After removing the second portion of the shallow trench isolation structure to expose the insulating isolation layer enclosing the second fin structure and the insulating isolation structure, the method further includes depositing semiconductor material in the second gate region of the second transistor to form a second dummy gate structure.

6. The method according to claim 5, characterized in that, In the process of forming the first transistor, the method further includes: performing a gate cut-off process on the first pseudo-gate structure to form a first gate cut-off structure.

7. The method according to claim 5, characterized in that, In the process of forming the second transistor, the method further includes: performing a gate cut-off process on the second pseudo-gate structure to form a second gate cut-off structure.

8. A stacked transistor, characterized in that, The stacked transistor is prepared by the method according to any one of claims 1 to 7, wherein the stacked transistor comprises: First transistor; The second transistor; the first transistor and the second transistor are stacked; A shallow trench isolation layer is located between the first transistor and the second transistor to isolate the first transistor and the second transistor. The fin structure of the first transistor and the fin structure of the second transistor are formed in the same process. The surface of the fin structure located in the shallow trench isolation layer is covered by an input / output oxide insulating layer. The surface of the input / output oxide insulating layer is covered by an insulating isolation layer. The input / output oxide insulating layer is formed by thermal oxidation treatment on the surface of the fin structure. The insulating isolation layer is formed by depositing a first insulating material on the input / output oxide insulating layer.

9. A semiconductor device, characterized in that, include: The stacked transistor as described in claim 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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