Preparation method of semiconductor structure, chip module, backlight module and display module

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the following steps of: forming a glass substrate which is provided with at least M first grooves which are sunken relative to a first surface, filling red fluorescent powder or green fluorescent powder or yellow fluorescent powder in each groove, arranging a water-oxygen isolation layer and a glue bonding layer on the fluorescent powder, and arranging a rough surface on a second surface; forming M chips on the growth substrate, wherein first surfaces of the M chips are provided with a first electrode and a second electrode; bonding the surfaces, on which the electrodes are prepared, of the M chips with the temporary substrate, and removing the growth substrate; the M chips are rearranged into an array of I * J groups of chip modules, and each group of chip modules comprises N chips; transferring the rearranged array into a first groove in the glass substrate and solidifying the rearranged array; a first insulating layer is formed on the surface of a chip on a glass substrate, holes are formed in a first electrode and a second electrode corresponding to the first insulating layer, a conductive interconnection structure is manufactured, the first electrode or the second electrode forms a common electrode, each common electrode corresponds to one chip module, and if the second electrode forms the common electrode, the conductive interconnection structure is manufactured. The common electrode and each first electrode are mutually independent; and cutting the glass substrate to form I * J groups of chip modules.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a preparation method of semiconductor structure, chip module, backlight module and display module BACKGROUND

[0002] Micro-LED packaging has the following several packaging technology routes:

[0003] The first is single-chip integrated packaging, which has the characteristics of ultra-high resolution and ultra-high brightness, but it cannot solve the problem of colorization.

[0004] The second route is the optical synthesis of Micro array lens, which has a relatively complex structure, and cannot meet the requirements of high resolution and high brightness.

[0005] The third is a full-color scheme of UV / B Micro LED array plus RGB quantum dot color conversion. It can be seen that in addition to the poor stability of quantum dot materials, there are some difficulties to be overcome in the scheme of spraying, photolithography or color film.

[0006] The fourth is the MiP full-color packaging based on RGB Micro-LED, which can balance yield and cost, and is most feasible for mass production. The core is to solve the problem of reducing the use threshold of Micro-LED, and to realize full testing and sorting.

[0007] MIP (Micro LED in Package) is essentially the organic combination of Micro LED and discrete devices, that is, the whole display panel is packaged separately, so that the yield control will be greatly improved in smaller area, and the testing link is moved from the chip to the packaging section, which will effectively reduce the cost and improve the speed.

[0008] MiP is the combination of Micro-LED chip and high-precision carrier board, so as to realize fan-out packaging, which can reduce the difficulty of testing and the difficulty of downstream mounting. MiP device can realize full testing, sorting and mixing Bin of RGB Micro pixels, and can make the display consistency of the panel high. MiP scheme can filter out the defective products while separating light and color, which can ensure the yield before delivery and reduce the repair cost of downstream, which also has certain advantages compared with traditional scheme. At the same time, MiP has better adaptability, and a MiP device can meet the application of products with different dot pitches.

[0009] The MIP packaging technology can not greatly increase the equipment, and the current equipment can be used for production, so that the high production line equipment investment of the enterprise is greatly reduced. Meanwhile, the MIP technology moves the test originally required on the chip end to the packaging end, changes the chip test to the pin test, greatly improves the efficiency, further reduces the cost, and guarantees that the downstream customers can produce the Micro LED display screen by using the existing equipment. SUMMARY

[0010] The technical problem solved by the present application is the low die bonding efficiency and high cost of the backlight display device prepared by the traditional backlight display device manufacturing method, and the small light transmission distance of light in the growth substrate, low light emission uniformity and small light emission angle. A semiconductor structure preparation method, chip module, backlight module and display module are provided to solve the problems of low die bonding efficiency and high cost caused by the preparation method of the backlight display device, and the small light transmission distance of light in the growth substrate, low light emission uniformity and small light emission angle.

[0011] In addition, by packaging quantum dot fluorescent powder in a glass substrate, the combination of GaN blue light chips or violet light chips and quantum dot materials is realized through a mass transfer technology, and the problem of water and oxygen resistance of quantum dot fluorescent powder materials is solved. This major technical breakthrough will fully speed up the commercialization process of Micro LED display technology.

[0012] To solve the above technical problems, an embodiment of the present application provides a semiconductor structure preparation method, comprising:

[0013] A glass substrate is formed, the glass substrate includes a first surface and a second surface opposite to the first surface, the glass substrate has at least M first grooves recessed relative to the first surface, and a rough surface is formed on the second surface;

[0014] M chips are formed on the growth substrate, and a first electrode and a second electrode are formed on the first surface of each of the M chips;

[0015] One surface of the M chips on which the electrodes are prepared is bonded to a temporary substrate, and the growth substrate is removed;

[0016] The M chips on the temporary substrate are rearranged, and the rearrangement mode is to divide the M chips into I*J chip module array groups, and each chip module group includes N chips;

[0017] The I*J chip module array groups after rearrangement are transferred to the first grooves in the glass substrate and are solidified;

[0018] A first insulating layer is formed on the first grooves, the first surface and the chip surface.

[0019] forming a conductive interconnection structure on the first insulating layer corresponding to the first electrode, the conductive interconnection structure being electrically connected with the first electrode;

[0020] forming a common electrode, each common electrode corresponding to a group of chip modules, a plurality of second electrodes being electrically connected with the pads to form the common electrode, the common electrode being independent of each first electrode;

[0021] cutting the glass substrate to form I*J groups of independent chip modules.

[0022] Optionally, the glass substrate has a light transmittance greater than 90% in the blue light band.

[0023] Optionally, the width of the first groove bottom parallel to the first surface direction is greater than 0.01 mm.

[0024] Optionally, the spacing between the top of the first groove is greater than 0.1 mm.

[0025] Optionally, the included angle between the first groove sidewall and the first groove bottom is greater than 30°.

[0026] Optionally, the method of arraying the I*J groups of chip modules on the glass substrate includes glue bonding.

[0027] Optionally, the pad is a column structure, and its height is greater than or equal to the height of the second electrode of the N chips corresponding thereto.

[0028] Optionally, the arrangement of the N chips in each group of chip modules is that the N chips are uniformly distributed along the circumferential direction, and the pad is located in the area surrounded by the N chips.

[0029] Optionally, before transferring a plurality of the chips into the first groove, further comprising: forming a plurality of first reflective layers on the first surface.

[0030] Optionally, the reflectivity of the first reflective layer is 90 to 100%.

[0031] Optionally, the method of forming a plurality of the first reflective layers includes:

[0032] forming a first reflective material on the first surface;

[0033] etching the first reflective material by a wet etching process to form a plurality of the first reflective layers on the first surface.

[0034] Optionally, the glass substrate further has a plurality of second grooves recessed with respect to the second surface, and the second grooves are located between adjacent first grooves.

[0035] Optionally, the width of the second groove bottom parallel to the second surface direction is greater than 0.01mm.

[0036] Optionally, the spacing between the second groove top is greater than 0.005mm.

[0037] Optionally, the included angle between the second groove side wall and the second groove bottom is greater than 30°.

[0038] Optionally, the spacing between the adjacent first groove and the second groove parallel to the second surface direction is greater than 0.05mm.

[0039] Optionally, the forming method of the second groove comprises:

[0040] forming a plurality of second grooves recessed relative to the second surface in the glass substrate by a wet etching process, the second grooves being located between adjacent first grooves.

[0041] Optionally, before fixing the chip in the first groove, further comprising: forming a plurality of second reflective layers on the second surface.

[0042] Optionally, the light transmittance of the second reflective layer is 10% to 90%, and the reflectivity is 10% to 90%.

[0043] Optionally, the method for forming the glass substrate comprises:

[0044] providing a first glass substrate, the first glass substrate comprising a first surface;

[0045] forming a plurality of first grooves recessed relative to the first surface in the first glass substrate by a wet etching process.

[0046] Optionally, the first electrode is a P electrode, and the second electrode is an N electrode; or the first electrode is an N electrode, and the second electrode is a P electrode.

[0047] An embodiment of the present application also provides a chip module prepared based on the preparation method of the semiconductor structure described in the foregoing embodiments, which comprises:

[0048] a glass substrate comprising a first surface and a second surface opposite to the first surface, the glass substrate having at least N first grooves recessed relative to the first surface, and a rough surface formed on the second surface;

[0049] N chips and a pad, each chip is provided with a first electrode and a second electrode; the second electrode of the N chips is electrically connected with the pad; and the second surface of the N chips is respectively fixed in each of the first grooves in the glass substrate; wherein N is a positive integer, and N≥2;

[0050] A first insulating layer is located on the first groove, the first surface and the chip surface.

[0051] A conductive interconnection structure is located in the first insulating layer.

[0052] An embodiment of the present application also provides a backlight module, which comprises H chip modules as described in the foregoing embodiments; wherein the second surface of the H chip modules is fixed on the bottom surface of the first groove; the circuit board is provided with H sub-zones corresponding to the H chip modules; each chip module is electrically connected with the circuit board by bonding with the corresponding sub-zone; wherein H is a positive integer, and H≥2.

[0053] Optionally, each sub-zone is further provided with a second connector and N first connectors;

[0054] The N first connectors are bonded with the first electrodes of the N chips of the corresponding chip module through the corresponding conductive interconnection structure, and the second connector is bonded with the common electrode, so as to realize the electrical connection between the single chip module and the circuit board.

[0055] An embodiment of the present application also provides a display module, which comprises the backlight module as described in the foregoing embodiments.

[0056] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0057] By transferring M chips to a temporary substrate and rearranging them into chip modules with N chips in each group, the chips are fixed in the corresponding first grooves in the form of modules at one time, which improves the chip transfer and fixation efficiency compared with the one-by-one transfer mode, and improves the bonding efficiency with the circuit board compared with the original single chip bonding with the circuit board, thereby reducing the process cost. Further, by taking the glass substrate with the first grooves as the substrate of the chip module, the chips are directly fixed in the first grooves of the glass substrate, which reduces the OD distance of the semiconductor structure. At the same time, the glass substrate with the first grooves and the rough surface on the second surface increases the light output angle of the chips. Secondly, based on the glass substrate with the first grooves, the chip packaging can be realized only by filling the first insulating layer in the first grooves, thereby further reducing the product cost. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figures 1 to 17 Fig. is a structural schematic diagram of different process stages prepared according to the preparation method of the semiconductor structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] As described in the background, the backlight display device prepared by using the preparation method of the conventional backlight display device has low die bonding efficiency and high cost, and meanwhile, the prepared backlight display device has the problems of small light transmission path of light in the growth substrate, low light uniformity and small light emitting angle.

[0060] In the preparation scheme of the conventional backlight display device, the die bonding is performed by fixing single sapphire chips on the substrate one by one. With the increasing demand for yield in the industry, the production efficiency of the die bonding one by one is low and the cost is high. Moreover, in the structure of the conventional sapphire chip formed on the substrate, the light emitted in the sapphire chip has a small light transmission path in the growth substrate and a small light emitting angle.

[0061] Moreover, due to the limitation of the conventional substrate structure design, the sapphire chips are all made and packaged on the surface of the flat substrate, so it is very difficult to design a structure for increasing the light emitting angle on the flat surface, and the process and structure are very complex and the packaging and manufacturing cost is very high.

[0062] To solve the above problems, an embodiment of the present application provides a preparation method of a semiconductor structure, Figure 1 Fig. is a flowchart of the preparation method of a semiconductor structure in an embodiment of the present application. The preparation method comprises:

[0063] forming a glass substrate, the glass substrate comprising a first surface and a second surface opposite to the first surface, the glass substrate having at least M first grooves recessed relative to the first surface, and a rough surface formed on the second surface.

[0064] forming M chips on the growth substrate, and a first electrode and a second electrode formed on the first surface of each of the M chips.

[0065] bonding the side of the M chips on which the electrodes are prepared to a temporary substrate, and removing the growth substrate.

[0066] rearranging the M chips on the temporary substrate, and the rearrangement mode is to divide the M chips into I*J chip module array groups, and each chip module group comprises N chips.

[0067] transferring the I*J chip module array groups after the rearrangement into the first grooves in the glass substrate and solidifying.

[0068] A first insulating layer is formed on the first groove, the first surface and the chip surface.

[0069] A hole is formed on the first insulating layer corresponding to the first electrode, and a conductive interconnection structure is made, which is electrically connected with the first electrode.

[0070] A common electrode is formed, each corresponding to a group of chip modules, and a plurality of second electrodes are electrically connected with the pads to form the common electrode, which is independent of each first electrode.

[0071] The glass substrate is cut to form I*J groups of independent chip modules.

[0072] The cut independent chip modules are bonded with the circuit board to realize electrical connection of the chip modules and the circuit board.

[0073] By transferring M chips to a temporary substrate and rearranging them into chip modules with N chips in each group, the chips are fixed in the corresponding first grooves in the form of modules, which improves the chip transfer and curing efficiency compared to the individual transfer mode, and improves the bonding efficiency with the circuit board compared to the original single chip bonding with the circuit board, thereby reducing the process cost. Further, by using the glass substrate with a plurality of first grooves as the substrate of the chip module, the chips are directly fixed in the first grooves of the glass substrate, which reduces the OD distance of the semiconductor structure. At the same time, the glass substrate with first grooves and a rough surface on the second surface increases the light output angle of the chips. Secondly, based on the glass substrate with first grooves, only the first insulating layer needs to be filled in the first grooves to realize chip packaging, thereby further reducing the product cost.

[0074] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0075] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0076] Figures 1 to 17 is a structure schematic diagram of different process stages of the preparation method of the semiconductor structure according to the embodiment of the present application.

[0077] The preparation method of the semiconductor structure provided by the present application comprises: forming a glass substrate, the glass substrate comprising a first surface, and the glass substrate having a plurality of first grooves recessed relative to the first surface. The process of forming the glass substrate is as shown in Figures 1 to 2 .

[0078] Please refer toFigure 1 The first glass substrate 101 includes a first surface 1011, and a rough surface 107 is formed on the second surface.

[0079] The first glass substrate 101 has a light transmittance greater than 90% in the blue light band.

[0080] The thickness d1 of the first glass substrate 101 is greater than 0.1 mm.

[0081] Please refer to Figure 2 A plurality of first grooves 10111 recessed relative to the first surface 1011 are formed in the first glass substrate 101 by a wet etching process, thereby preparing a glass substrate for manufacturing chips in the first grooves.

[0082] The etching solution used in the wet etching process is hydrofluoric acid.

[0083] The width d2 of the first groove 10111 bottom parallel to the direction of the first surface 1011 is greater than 0.01 mm.

[0084] The distance d3 between the first grooves 10111 is an integer multiple of the width of the chip bottom. The chip can be an LED chip or a mini LED chip. The width of the chip bottom is a value known to those skilled in the art, which is not described here.

[0085] The included angle between the first groove sidewall and the first groove 10111 bottom is greater than 30°.

[0086] The spacing d4 between the tops of the plurality of first grooves 10111 is greater than 0.1 mm.

[0087] The included angle between the first groove sidewall and the first groove bottom is used to increase the light emission angle of the chip. By adjusting the size of the included angle in the range of greater than 0.1 mm, the light emission angle can be adjusted.

[0088] In some embodiments of the present application, only a plurality of first grooves recessed relative to the first surface of the glass substrate are provided, and the chips can be manufactured in the first grooves.

[0089] In other embodiments of the present application, before fixing a plurality of chips in the first grooves, a plurality of first reflective layers are formed on the surface of the first surface to improve the light emission efficiency of the semiconductor structure and improve the light emission brightness of the semiconductor structure.

[0090] The process of forming the first grooves and a plurality of reflective layers on the glass substrate is described in detail below, and the specific preparation process is shown in Figures 3 to 5 .

[0091] Please refer to Figure 3 The first reflective material 103 is formed on the first surface 1011 of the first glass substrate 101.

[0092] The reflectivity of the first reflective material 103 is 90-100%.

[0093] In some typical examples, the first reflective material 103 is a DBR mirror layer or a metal mirror

[0094] Please refer to Figure 4 The first reflective material is etched by a wet etching process to form a plurality of first mirror layers 1031 on the first surface 1011 of the first glass substrate 101.

[0095] When etching the first reflective material 103, the etching solution used in the wet etching process is hydrofluoric acid.

[0096] Please refer to Figure 5 A plurality of first recesses 10111 are formed in the first glass substrate 101 by a wet etching process, which are recessed relative to the first surface 1011 and located between adjacent first mirror layers 1031, thereby forming a glass substrate 101 with first recesses on the first surface 1011.

[0097] The following describes the subsequent processes of the semiconductor manufacturing method with an example of forming a plurality of first mirror layers and a plurality of first recesses recessed relative to the first surface on the first surface of the glass substrate. The preparation method of only forming first recesses without first mirror layers is the same as this, which will not be described here. The subsequent steps are as follows Figures 6 to 17 The.

[0098] M chips are formed on the growth substrate, and the first surface of each of the M chips is formed with a first electrode and a second electrode.

[0099] In one typical example, the chip is an LED chip 102.

[0100] Please refer to Figure 6 , Figure 6The LED chip 102 includes, but is not limited to, an N-GaN layer 1021, a quantum well layer 1022, a P-GaN layer 1023, a chip mirror layer 1024, an insulating layer 1025, a P-PAD layer 1026, and an N-PAD layer 1027. The quantum well layer 1022, the P-GaN layer 1023, the chip mirror layer 1024, and the insulating layer 1025 are sequentially stacked on the N-GaN layer 1021. The insulating layer 102 exposes part of the surface of the chip mirror layer 1024, and the P-PAD layer 1026 and the N-PAD layer 1027 penetrate the aforementioned structure layers and respectively contact the P-GaN layer 1023 and the N-GaN layer 1021.

[0101] In some specific examples, the LED chip includes any one of a single-color short-wavelength LED chip, a blue LED, a near-ultraviolet LED, and a QD-LED.

[0102] Bond the side with the electrodes prepared on the M chips to the temporary substrate, and remove the growth substrate.

[0103] The temporary substrate is specifically an elastic film, and the transferring process is specifically a film tearing machine. Specifically, the electrode side of the array of LED chips 102 is placed on the operation table of the film tearing machine with the electrode side facing up, the bottom of the array of LED chips 102 is vacuum adsorbed, the elastic film is covered on the electrode side of the array of LED chips 102, pressure is applied by using a roller, so that the elastic film and the array of LED chips 102 are tightly bonded together, and finally the elastic film is torn off to realize transferring the array of LED chips 102 to the elastic film. Of course, it should be realized that the film tearing machine is only an example of transferring the array of LED chips 102 after the substrate is peeled off to the elastic film, and the present application is not limited thereto, and any other way of transferring the array of LED chips 102 after the substrate is peeled off to the elastic film is within the protection scope of the present application.

[0104] The growth substrate is peeled off by a chemical peeling process. Compared with a traditional laser peeling process for peeling off the growth substrate, the chemical peeling process can avoid damaging the epitaxial light-emitting structure, so as to reduce the manufacturing cost of the LED chip 102 and improve the chip quality.

[0105] The M chips on the temporary substrate are rearranged. The rearrangement mode is to divide the M chips into I*J chip module arrays, and each chip module includes N chips.

[0106] The arrangement mode is to divide the M LED chips 101 into I*J groups of LED chip module arrays, each group of chip modules includes N LED chips 102, and the N LED chips 102 are uniformly distributed in the circumferential direction; wherein M, N, I, and J are positive integers, and 2≤N<M, I, J<M; operating the LED chip module as a whole by N LED chips 102 can improve the operation efficiency and reduce the operation cost compared with operating M LED chips 102 separately.

[0107] As a specific implementation, the specific operation of the film expanding is to directly wrap the elastic film on the primary and secondary rings of the film expander, and directly expand the film with the film expander. The film expander can adopt a conventional film expander of the prior art, and will not be described here.

[0108] Please refer to Figure 7 The I*J groups of chip module arrays after rearrangement are transferred to the first grooves in the glass substrate 101 and solidified. The arrangement of the first grooves in the glass substrate 101 corresponds to the arrangement of the plurality of chips 102, so that N first grooves correspond to a group of chip modules, and then after transfer and fixation, a plurality of chip modules are formed in the glass substrate. The arrangement form of the chip module here can refer to the structure in Figure 17 .

[0109] The process of transferring the chip module array from the elastic film to the glass substrate is as follows: after the chip module array after film expansion and the glass substrate to be bonded are adhered together by bonding glue, they are placed in a graphite carrier, and bonding is performed under the high pressure and high temperature environment provided by the bonding machine to transfer the chip module array after film expansion to the glass substrate. After the transfer is completed, the elastic film can be torn off.

[0110] The bonding machine and the bonding operation are conventional techniques in the art, and will not be described here; wherein the glass substrate is any one of a glass substrate, a ceramic substrate, or a transparent glue. Of course, it should be realized that bonding is only an example of the present application, and the present application is not limited thereto, and other ways of transferring the chip array from the elastic film to the glass substrate are also within the protection scope of the present application.

[0111] The way of solidifying the I*J groups of chip module arrays on the glass substrate includes glue bonding.

[0112] The LED chip module can be directly fixed to the glass substrate 101, and no other intermediate layer is needed, thereby facilitating the reduction of the OD pitch.

[0113] In an embodiment, only chips are fixed in the first grooves, as shown in Figure 7 .

[0114] Please refer to Figure 8 In another embodiment of the present application, the first recess can further comprise fluorescent powder or quantum dots 1021, so that the chip emits white light.

[0115] The fluorescent powder or quantum dots 1021 are bonded in the first recess.

[0116] The fluorescent powder or quantum dots 1021 can also be made in the first recess by sintering.

[0117] There are red fluorescent powder or green fluorescent powder or yellow fluorescent powder in each recess, and the fluorescent powder has a water oxygen isolation layer and a glue bonding layer.

[0118] In one embodiment, rare earth fluorescent powder can be selected. White light is synthesized by exciting the fluorescent powder by a single-color short-wavelength LED chip. In a specific example, the chip is a blue light LED, and the fluorescent powder is selected to be yellow-green fluorescent powder; or the chip is a near-ultraviolet LED, and the fluorescent powder is selected to be three-primary-color fluorescent powder.

[0119] In another preferred embodiment, quantum dots can use red-green quantum dots. In a specific example, the chip selects QD-LED. Since the wavelength of QD-LED is adjustable, high color gamut under NTSC, DCI-P3, BT2020, etc. standard system can be realized according to requirements, wherein the NTSC color gamut can reach 115%, and the DCI-P3 color gamut can reach 100%.

[0120] Please refer to Figure 10 A first insulating layer 104 is formed in the first recess, on the surface of the first face 1011, and on the surface of the chip 102

[0121] In some specific examples, the material of the first insulating layer 104 includes silicon oxide, silicon nitride, silica gel, and PI glue.

[0122] Since the glass substrate of the semiconductor structure based on the structure of the first recess is prepared, only the first insulating layer needs to be filled in the first recess to realize chip packaging, without the need for complex preparation of packaging structure, thereby simplifying the packaging process and improving production efficiency. Please refer to Figure 11 A conductive interconnection structure 105 is made by opening holes on the first insulating layer 104 corresponding to the first electrode 1026, and the conductive interconnection structure 105 is electrically connected to the first electrode 1026.

[0123] Please refer to Figure 9 , Figure 9For the top view of the chip module after transfer, a common electrode is formed, each common electrode corresponds to a group of chip modules, and a plurality of second electrodes 1027 are electrically connected to the pads 1013 to form a common electrode, and the common electrode is independent of each first electrode 1026;

[0124] The pad 1013 is a column structure, and its height is greater than or equal to the height of the second electrode 1027 of the N chips corresponding thereto.

[0125] The arrangement of the N chips 102 in each group of chip modules is that the N chips 102 are uniformly distributed along the circumferential direction, and the pad 1013 is located in the area surrounded by the N chips 102.

[0126] The pad 1013 is a common negative electrode, the first electrode 1026 is a P electrode, and the second electrode 1027 is an N electrode. Alternatively, the common electrode is a common positive electrode, the first electrode is an N electrode, and the second electrode is a P electrode.

[0127] Please refer to Figure 12 The glass substrate is cut to form I*J groups of independent chip modules, and the top view after cutting can be as shown in Figure 9 .

[0128] Please refer to Figure 13 , a plurality of circuit boards 106 are provided, and a second connecting body 1062 and a first connecting body 1061 are arranged.

[0129] Please refer to Figure 14 The independent chip module after cutting is bonded with the circuit board 106 to realize the electrical connection between the chip module and the circuit board 106.

[0130] The first connecting body 1061 is bonded with the first electrode 1026 of the N chips 102 of the corresponding chip module through the corresponding conductive interconnection structure 105, and the second connecting body 1062 is bonded with the pad 1013 to realize the electrical connection between the single chip module and the circuit board 106.

[0131] To sum up, the method for manufacturing the semiconductor structure provided by the application improves the chip transfer and curing efficiency compared with the one-by-one transfer mode, and improves the efficiency of bonding with the circuit board compared with the original single chip bonding with the circuit board, thereby reducing the process cost. Further, the glass substrate with the first grooves is used as the substrate of the chip module, and the chip is directly fixed in the first groove of the glass substrate, thereby reducing the OD distance of the semiconductor structure. Meanwhile, the glass substrate with the first grooves and the rough surface on the second surface increases the light output angle of the chip. In addition, based on the glass substrate with the first grooves, the chip packaging can be realized by only filling the first insulating layer in the first groove, thereby further reducing the product cost.

[0132] The embodiment of the application further provides another method for manufacturing a semiconductor structure. The glass substrate further comprises a second surface opposite to the first surface. The difference between the preparation method and the preparation method of the foregoing embodiment is that in the embodiment, a plurality of second grooves recessed relative to the second surface are further manufactured on the second surface of the first glass substrate.

[0133] Figures 15 to 17 is a structure schematic diagram of different process stages of the semiconductor structure prepared by the preparation method of another embodiment of the application.

[0134] Please refer to Figure 15 The glass substrate 101 is formed, and the glass substrate 101 comprises a first surface 1011, and the glass substrate 101 has a plurality of first grooves 10111 recessed relative to the first surface 1011.

[0135] After the first grooves 10111 are formed, a plurality of second grooves 10121 recessed relative to the second surface 1012 are further arranged on the second surface 1012 of the glass substrate 101, the plurality of second grooves 10121 are recessed relative to the second surface 1012, and the second grooves 10121 are located between adjacent first grooves 10111.

[0136] The second grooves 10121 are arranged on the surface opposite to the chip, thereby forming a glass substrate with a concave-convex structure, which is used for further changing the light output angle of the semiconductor structure.

[0137] The width of the second grooves 10121 in the direction parallel to the second surface is greater than 0.01 mm.

[0138] The spacing between the top of the plurality of second grooves 10121 is greater than 0.005 mm.

[0139] The included angle between the sidewall of the second groove 10121 and the bottom of the second groove 10121 is greater than 30°.

[0140] The included angle between the sidewall of the second groove 10121 and the bottom of the second groove 10121 can be adjusted to further adjust the light emitting angle.

[0141] The distance between the adjacent first groove and the second groove 10121 in the direction parallel to the second surface is greater than 0.05 mm.

[0142] The forming method of the second groove 10121 includes forming a plurality of second grooves 10121 recessed relative to the second surface in the glass substrate by using a wet etching process, and the second grooves 10121 are located between adjacent first grooves.

[0143] In other embodiments of the present application, before fixing the plurality of chips in the first grooves, a plurality of first reflective layers 1031 are formed on the first surface. The preparation method and material of the first grooves and the first reflective layers 1031 are the same as those in the foregoing embodiments, and will not be repeated here. Similarly, after forming the first grooves, a plurality of second grooves recessed relative to the second surface are arranged on the second surface of the glass substrate, the plurality of second grooves are recessed relative to the second surface, and the second grooves are located between adjacent first grooves.

[0144] The preparation method of the semiconductor structure provided in the present embodiment will be described in detail below, taking the formation of the first reflective layer on the first surface as an example.

[0145] Please refer to Figure 16 The other subsequent specific manufacturing processes and material of the structure layer after forming the second grooves 10121 and the first reflective layer 1031 are the same as those in the foregoing embodiments, so as to form the semiconductor structure, and will not be repeated here.

[0146] Please refer to Figure 17 In further improved embodiments of the present application, before fixing the chips 102 in the first grooves, a plurality of second reflective layers 109 are formed on the surface of the second surface 1012, so as to form the semiconductor structure. The surface of the second surface refers to the surface that has not been recessed.

[0147] The material and thickness of the second reflective layer can be the same as or different from those of the first reflective layer.

[0148] The second reflective layer is used to improve the utilization rate of the light beam of the chip, so as to further improve the luminous brightness.

[0149] In summary, in the embodiment, the chip transfer curing efficiency is improved, and compared with the original single chip bonding with the circuit board respectively, the efficiency of bonding with the circuit board is improved, thereby reducing the process cost. In addition to increasing the light output angle. Since the second groove is also arranged on the second surface, the light output angle of the semiconductor structure can be further increased.

[0150] Please refer to Figure 14 and Figure 9 An embodiment of the present application also provides a chip module prepared based on the preparation method of the semiconductor structure described in the foregoing embodiment, which comprises:

[0151] A glass substrate 101 comprising a first surface 1011 and a second surface 1012 opposite to the first surface 1011, wherein the glass substrate 101 has at least N first grooves recessed relative to the first surface 1011, and a rough surface 107 is formed on the second surface 1012.

[0152] N chips 102 and a pad 1013, each chip 102 is provided with a first electrode 1025 and a second electrode 1027; the second electrodes 1027 of the N chips 102 are electrically connected with the pad 1013; and the second surfaces 1012 of the N chips 102 are respectively cured in the corresponding first grooves in the glass substrate 102, and the first electrodes 1026 and the pad 1013 are bonded with a circuit board 106 to realize electrical connection with the circuit board 106; wherein N is a positive integer, and N≥2.

[0153] A first insulating layer 104 located on the first groove, the surface of the first surface 1011 and the surface of the chip 102.

[0154] A conductive interconnection structure 105 located in the first insulating layer 104, and the first electrode 1026 and the circuit board 106 are electrically connected through the conductive interconnection structure 105.

[0155] Please refer to Figure 16 In another embodiment of the present application, a second groove recessed relative to the second surface is further formed on the second surface of the glass substrate.

[0156] Please refer to Figure 17 In other embodiments of the present application, a second groove recessed relative to the second surface is further formed on the second surface of the glass substrate, and a second mirror layer 108 located between the second grooves is further formed on the second surface.

[0157] An embodiment of the present application further provides a backlight module, comprising H chip modules as described in the foregoing embodiments; wherein the second surfaces of the H chip modules are all fixed on the bottom surfaces of the first grooves; the circuit board is provided with H partitions corresponding to the H chip modules; each chip module is bonded with the corresponding partition to realize electrical connection with the circuit board; wherein H is a positive integer and H is greater than or equal to 2.

[0158] Each partition is further provided with a second connecting body and N first connecting bodies.

[0159] The N first connecting bodies are bonded with the first electrodes of the N chips of the corresponding chip module through the corresponding conductive interconnection structures, and the second connecting body is bonded with the common electrode, so as to realize electrical connection of a single chip module with the circuit board.

[0160] An embodiment of the present application further provides a display module, comprising the backlight module as described in the foregoing embodiments.

[0161] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A glass substrate is formed, the glass substrate including a first surface and a second surface opposite to the first surface, the glass substrate having at least M first grooves recessed relative to the first surface, and a rough surface formed on the second surface; M chips are formed on a growth substrate, and a first electrode and a second electrode are formed on the first surface of each of the M chips; The side of the M chips with electrodes is bonded to a temporary substrate, and the growth substrate is removed. The M chips on the temporary substrate are rearranged in such a way that the M chips are divided into I*J chip module arrays, each chip module including N chips; The rearranged I*J group chip module array is transferred into the first groove in the glass substrate and cured. A first insulating layer is formed on the first groove, the first surface, and the chip surface; An opening is made on the first insulating layer corresponding to the first electrode to create a conductive interconnect structure, which is electrically connected to the first electrode. A common electrode is formed, each common electrode corresponds to a set of chip modules, and several second electrodes are electrically connected to the pads to form a common electrode. The common electrode is independent of each first electrode. The glass substrate is cut to form I*J independent chip modules.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The glass substrate has a transmittance of more than 90% in the blue light band.

3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The width of the bottom of the first groove in the direction parallel to the first surface is greater than 0.01 mm.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that, The spacing between the tops of several of the first grooves is greater than 0.1 mm.

5. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The included angle between the sidewall of the first groove and the bottom of the first groove is greater than 30°.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method of bonding the I*J group chip module array onto the glass substrate includes adhesive bonding.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The pad has a cylindrical structure, and its height is greater than or equal to the height of the second electrodes of the N corresponding chips.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The N chips in each chip module are arranged as follows: the N chips are evenly distributed along the circumference, and the pads are located in the area surrounded by the N chips.

9. The method for preparing a semiconductor structure as described in claim 1, characterized in that, Before transferring the plurality of chips into the first groove, the method further includes forming a plurality of first reflective layers on the surface of the first surface.

10. The method for preparing the semiconductor structure according to claim 9, characterized in that, The reflectivity of the first reflective mirror layer is 90% to 100%.

11. The method for preparing the semiconductor structure as described in claim 9, characterized in that, Several methods for forming the first reflective layer include: A first reflective material is formed on the first surface; The first reflective material is etched using a wet etching process to form several first reflective mirror layers on the first surface.

12. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The glass substrate also has a plurality of second grooves recessed relative to the second surface, and the second grooves are located between adjacent first grooves.

13. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The width of the bottom of the second groove in the direction parallel to the second surface is greater than 0.01 mm.

14. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The spacing between the tops of several second grooves is greater than 0.005 mm.

15. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The included angle between the sidewall of the second groove and the bottom of the second groove is greater than 30°.

16. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The distance between adjacent first and second grooves in the direction parallel to the second surface is >0.05mm.

17. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The method for forming the second groove includes: A plurality of second grooves are formed in the glass substrate by a wet etching process, which are recessed relative to the second surface. The second grooves are located between adjacent first grooves.

18. The method for preparing a semiconductor structure as described in claim 12, characterized in that, Before fixing the chip in the first groove, the method further includes forming a plurality of second reflective layers on the second surface.

19. The method for preparing a semiconductor structure as described in claim 18, characterized in that, The second reflective mirror layer has a light transmittance of 10% to 90% and a reflectance of 10% to 90%.

20. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The method for forming the glass substrate includes: A first glass substrate is provided, the first glass substrate including a first surface; A plurality of first grooves are formed in the first glass substrate by means of a wet etching process, which are recessed relative to the first surface.

21. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The first electrode is a P electrode, and the second electrode is an N electrode; or the first electrode is an N electrode, and the second electrode is a P electrode.

22. A chip module, prepared according to the semiconductor structure preparation method described in claims 1 to 21, characterized in that, The chip module includes: A glass substrate, the glass substrate including a first surface and a second surface opposite to the first surface, the glass substrate having at least N first grooves recessed relative to the first surface, and a rough surface formed on the second surface; N chips and one pad, each chip having a first electrode and a second electrode; the second electrodes of all N chips are electrically connected to the pad; and the second surfaces of the N chips are respectively solidified in several first grooves within the glass substrate; where N is a positive integer and N≥2; A first insulating layer located in the first groove, the first surface, and the chip surface; The conductive interconnect structure located in the first insulating layer.

23. A backlight module, characterized in that, The circuit includes H chip modules as described in claim 22; wherein the second surface of each of the H chip modules is solidified on the bottom surface of the first groove; the circuit board is provided with H partitions corresponding to the H chip modules; each chip module is electrically connected to the circuit board by bonding with the corresponding partition; wherein H is a positive integer and H≥2.

24. The backlight module according to claim 23, characterized in that, Each of the aforementioned partitions is further provided with a second connector and N first connectors; N first connectors are bonded to the first electrodes of the N chips of the corresponding chip module through the corresponding conductive interconnect structure, and the second connectors are bonded to the common electrode to realize the electrical connection between a single chip module and the circuit board.

25. A display module, characterized in that, Includes the backlight module as described in claim 23 or 24.

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