An integrated high voltage semiconductor device structure and manufacturing method thereof

Abstract

The present invention relates to an integrated high-voltage semiconductor device structure and a manufacturing method thereof. The present invention comprises an N-type epitaxial layer on an N-type substrate, a drain metal is arranged on the back, and the structure is divided into an M1 device area, an M2 device area and an isolation area. A P-type column is arranged in the N-type epitaxial layer, and a P-type body area is arranged above it, connecting N-type and P-type sources with different doping; a threshold adjustment area is provided in the M2 device area, and the device surface is covered with a gate oxide layer and a polysilicon gate; dielectric layers are respectively distributed in each area, and the M1 source metal and the M2 source metal are connected to the source of the P-type body area; a diode is configured in the isolation area, the anode metal is connected to the N-type source, the cathode metal is connected to the P-type source, or a second gate polysilicon is arranged, which is respectively connected to heavily doped N-type and P-type polysilicon and anode and cathode metals. The present invention reduces the loss of circuit topology and improves system efficiency and integration.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an integrated high-voltage semiconductor device structure and a manufacturing method thereof. Background Art

[0002] The superjunction structure introduces the ordinary PN junction into the voltage-resistant layer of the power device, and introduces a significant two-dimensional field effect inside the voltage-resistant layer. This complex field modulation can greatly reduce the peak electric field on the surface of the device and optimize the field distribution inside the body. The rated voltage of superjunction MOSFET devices is generally above 650V, and is widely used in various high-voltage fields such as automotive electronics, photovoltaic new energy, artificial intelligence, servers, computers, industrial power supplies, and household appliances.

[0003] AC-DC chips are switching power chips specially designed to convert alternating current (AC) into direct current (DC). They are commonly used in various electronic devices such as automotive electronics, photovoltaic new energy, artificial intelligence, servers, computers, industrial power supplies, household appliances, etc. to provide the required low-voltage DC power. AC-DC chips contain functional modules such as input power filter circuit, rectifier circuit, switching power control circuit and output voltage stabilization circuit to achieve efficient AC to DC conversion.

[0004] Figure 1 It is a common flyback AC-DC circuit topology, which includes AC-DC chip, super junction power MOSFET (M1) device, transformer, rectifier and output filter. The AC-DC chip can periodically open and close the super junction power MOSFET (M1) device to generate high-frequency pulse signals. These pulse signals are transmitted to the output end through the transformer, and then converted into a smooth DC output voltage through the rectifier and filter.

[0005] For traditional AC-DC chips, VDD is connected to the input stage through resistor R1. When the chip is powered on, the input stage supplies power to the chip's VDD through resistor R1. When the potential of C1 reaches the minimum startup voltage of the chip, the chip starts to work. When the chip is started, VDD draws power through the inductor winding coupled to the output end and supplies power to the chip. Therefore, once the chip is started, the AC-DC chip does not need to be powered through resistor R1, but the path is always in the on state, which increases the loss of the system and reduces the AC-DC conversion efficiency.

[0006] In addition, in this circuit topology, it is necessary to additionally set up a super junction power MOSFET device as a switching device, which increases the complexity of the system. Moreover, due to the introduction of additional devices, higher stray inductance and stray capacitance will be brought about, affecting the reliability of the system. Summary of the invention

[0007] To this end, the present invention provides an integrated high-voltage semiconductor device structure and a manufacturing method thereof, which overcomes the shortcomings of the prior art such as high loss, low efficiency, and high system complexity of the switching power supply startup circuit, reduces the loss of the circuit topology, and improves the system efficiency and integration.

[0008] In order to solve the above technical problems, the present invention provides an integrated high-voltage semiconductor device structure, including an M1 device region, an M2 device region, and an isolation region arranged between the M1 device region and the M2 device region; the semiconductor device structure includes:

[0009] N-type substrate;

[0010] An N-type epitaxial layer is disposed on the surface of the N-type substrate;

[0011] A drain metal is disposed on the back side of the N-type substrate;

[0012] P-type columns are arranged at intervals in the N-type epitaxial layer, including first P-type columns located in the M1 device region and the M2 device region, and second P-type columns located in the isolation region;

[0013] A P-type body region is arranged in the N-type epitaxial layer and is located above each of the P-type pillars, and the P-type body region is connected to one or more of the P-type pillars below it; the P-type body region includes a first P-type body region located in the M1 device region and the M2 device region, and a second P-type body region located in the isolation region; wherein a first heavily doped N-type source and a first heavily doped P-type source are arranged in the first P-type body region, and the first heavily doped N-type source is located on both sides of the first heavily doped P-type source;

[0014] A threshold adjustment region, located on the surface of the N-type epitaxial layer in the M2 device region;

[0015] A gate oxide layer, disposed on the surface of the N-type epitaxial layer;

[0016] A first gate polysilicon is disposed on the surface of the gate oxide layer located in the M1 device region and the M2 device region;

[0017] A dielectric layer, disposed on the surface of the N-type epitaxial layer, including a first dielectric layer located in the M1 device region and the M2 device region, and a second dielectric layer located in the isolation region;

[0018] M1 source metal and M2 source metal, respectively corresponding to the surface of the first dielectric layer located in the M1 device region and the M2 device region, wherein the M1 source metal is connected to the first heavily doped N-type source and the first heavily doped P-type source in each of the first P-type body regions in the M1 device region, and the M1 source metal is connected to the first heavily doped N-type source and the first heavily doped P-type source in each of the first P-type body regions in the M2 device region;

[0019] A diode device, including an anode metal and a cathode metal, both of which are located on the surface of the second dielectric layer;

[0020] Wherein, a second heavily doped N-type source and a second heavily doped P-type source are respectively disposed in the second P-type body region, the anode metal is connected to the second heavily doped N-type source, and the cathode metal is connected to the second heavily doped P-type source;

[0021] Alternatively, a second gate polysilicon is arranged in the second dielectric layer, and heavily doped N-type polysilicon and heavily doped P-type polysilicon are respectively arranged on both sides of the second gate polysilicon, the heavily doped N-type polysilicon is connected to the cathode metal, and the heavily doped P-type polysilicon is connected to the anode metal.

[0022] In one embodiment of the present invention, the first dielectric layer is provided with a first contact hole filled with a first metal;

[0023] A first metal is in contact with the M1 source metal and the M2 source metal respectively, and the first metal is in contact with the corresponding first heavily doped N-type source and the first heavily doped P-type source; the first dielectric layer isolates the first gate polysilicon and the first metal.

[0024] In one embodiment of the present invention, the second dielectric layer is provided with a second contact hole for filling the second metal;

[0025] Wherein, the anode metal is connected to the second heavily doped N-type source through the second metal, and the cathode metal is connected to the second heavily doped P-type source through the second metal; or,

[0026] The heavily doped N-type polysilicon is connected to the cathode metal through the second metal, and the heavily doped P-type polysilicon is connected to the anode metal through the second metal.

[0027] In one embodiment of the present invention, in the isolation region, a plurality of the second P-type columns are disposed below each of the second P-type body regions.

[0028] In one embodiment of the present invention, the number of the second P-type columns under each of the second P-type body regions is 2 to 5.

[0029] In one embodiment of the present invention, in the M2 device region, a plurality of the first P-type pillars are disposed under each of the first P-type body regions.

[0030] In one embodiment of the present invention, 2 to 5 first P-type columns are disposed under each of the first P-type body regions.

[0031] In one embodiment of the present invention, the threshold adjustment region is provided on the surface of the N-type epitaxial layer in the M2 device region; or, the threshold adjustment region is provided only on the surface of the first P-type body region in the M2 device region.

[0032] In one embodiment of the present invention, an enhancement-mode super junction power MOSFET device is formed in the M1 device region, a depletion-mode super junction power MOSFET device is formed in the M2 device region, an isolation structure and the diode device are formed in the isolation region, and the drain of the enhancement-mode super junction power MOSFET device is connected to the drain of the depletion-mode super junction power MOSFET device; the semiconductor device structure further includes:

[0033] A first gate pad connected to the first gate polysilicon in the M1 device region through a metal or polysilicon lead;

[0034] A first source pad connected to the M1 source metal through a metal or polysilicon lead;

[0035] A second gate pad connected to the first gate polysilicon in the M2 device region through a metal or polysilicon lead;

[0036] The second source pad is connected to the M2 source metal through a metal or polysilicon lead.

[0037] The present invention also provides a method for manufacturing an integrated high-voltage semiconductor device structure, the manufacturing method comprising:

[0038] Step 1: providing an N-type substrate, and growing an N-type epitaxial layer on the surface of the N-type substrate;

[0039] Step 2: selectively etching a deep groove on the surface of the N-type epitaxial layer;

[0040] Step 3: Filling the deep trenches with P-type silicon material to form P-type pillars, and removing excess P-type silicon material on the surface of the N-type epitaxial layer;

[0041] Step 4: using a mask window, by means of ion implantation, implanting P-type impurities on the surface of the N-type epitaxial layer and thermally annealing to form a P-type body region, wherein the P-type body region is connected to one or more P-type columns therebelow; forming an M1 device region, an M2 device region, and an isolation region disposed between the M1 device region and the M2 device region on the device, wherein the P-type columns are disposed at intervals in the N-type epitaxial layer, including a first P-type column located in the M1 device region and the M2 device region and a second P-type column located in the isolation region, and the P-type body region includes a first P-type body region located in the M1 device region and the M2 device region and a second P-type body region located in the isolation region;

[0042] Step 5: Using a mask window and ion implantation, N-type impurities are implanted on the surface of the N-type epitaxial layer to form a threshold adjustment region;

[0043] Step 6: growing a gate oxide layer on the surface of the N-type epitaxial layer, depositing gate polysilicon on the surface of the gate oxide layer, and etching away the excess gate oxide layer and the gate polysilicon thereon using a mask window;

[0044] Step 7: Using a mask, inject N-type impurities to form a heavily doped N-type source, and using a mask, inject P-type impurities to form a heavily doped P-type source, followed by high temperature annealing to activate the doped ions;

[0045] Step 8: deposit a dielectric layer on the device surface, and use a mask window to etch the dielectric layer to form a contact hole;

[0046] Step nine: depositing metal on the dielectric layer, the metal filling the contact hole and connecting the heavily doped N-type source, the heavily doped P-type source and the surface metal, etching the surface metal using a mask window to form M1 source metal, M2 source metal, cathode metal and anode metal;

[0047] Step 10: Thinning the N-type substrate and depositing metal on the back side thereof to form a drain metal.

[0048] The above technical solution of the present invention has the following advantages compared with the prior art:

[0049] The present invention describes an integrated high-voltage semiconductor device structure and a method for manufacturing the same. From the perspective of device structure, the channel length of the integrated depletion-type superjunction power MOSFET device M2 of the present invention is adjustable, which can ensure more reliable shutdown of the device and reduce device leakage during shutdown.

[0050] The isolation structure of the present invention has an adjustable size, and the isolation structure area can be adjusted according to application requirements to isolate voltages of different magnitudes. In addition, the diode device D1 is directly integrated in the isolation structure, which can further reduce the area of ​​the power device of the present invention.

[0051] The temperature measuring diode device D1 of the present invention is arranged in the body silicon, which can give full play to the advantage of the stable temperature coefficient of the silicon diode, and the diode device D1 is only turned on when the drain metal is connected to high voltage. At this time, the P-type body region and the N-type epitaxial layer are reverse biased, which effectively prevents the leakage of the diode D1 from entering the N-type epitaxial layer, thereby improving the temperature measurement accuracy of the diode device D1.

[0052] From the application point of view, the integrated high-voltage semiconductor device and the control circuit part of the present invention are integrated into the same switching power supply chip, which has the following advantages:

[0053] By integrating the switch device, i.e., the enhanced super junction power MOSFET device M1, into the chip, the complexity of the flyback circuit topology is reduced. In addition, by integrating the diode device D1 into the chip, the AC-DC chip has a temperature detection function, which automatically cuts off the power to the chip when the chip temperature is too high, thereby improving the safety and reliability of the system.

[0054] By integrating the depletion-type super junction power MOSFET device M2, when the chip is powered on, since the depletion-type MOSFET device is naturally turned on, the chip VCC can be powered by the depletion-type super junction power MOSFET device M2. After the power-on is completed, the depletion-type super junction power MOSFET device M2 is turned off, thereby reducing the loss of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0056] Figure 1 It is a traditional flyback AC-DC circuit topology.

[0057] Figure 2 The schematic diagram of the circuit of the integrated high-voltage semiconductor device structure of the present invention is shown in FIG.

[0058] Figure 3 It is a schematic diagram of the layout of the integrated high-voltage semiconductor device structure of the present invention.

[0059] Figure 4 It is a schematic diagram of the cross-sectional structure of the enhancement mode super junction power MOSFET device of the present invention.

[0060] Figure 5 It is a schematic diagram of the cross-sectional structure of the depletion-mode super junction power MOSFET device of the present invention.

[0061] Figure 6 It is a schematic diagram of the cross-sectional structure of the isolation structure and the diode device of the present invention.

[0062] Figure 7It is a schematic diagram of the cross-sectional structure of the isolation structure and the diode device according to Example 2 of the present invention.

[0063] Figure 8 Transfer characteristic curves of depletion-type devices under different channel lengths.

[0064] Fig. 9 It is a schematic diagram of the cross-sectional structure after the epitaxial layer is formed in the present invention.

[0065] Fig.10 This is a schematic diagram of the cross-sectional structure after deep trench etching is completed in the present invention.

[0066] Fig.11 The figure is a schematic diagram of the cross-sectional structure after the deposition of the P-type silicon material is completed in the present invention.

[0067] Fig.12 It is a schematic diagram of the cross-sectional structure after the P-type body region is formed in the present invention.

[0068] Fig.13 It is a schematic diagram of the cross-sectional structure after the threshold adjustment area is formed in the present invention.

[0069] Fig.14 It is a schematic diagram of the cross-sectional structure after the gate oxide layer and gate polysilicon are formed in the present invention.

[0070] Fig.15 The cross-sectional structure diagram is a schematic diagram of the present invention after forming a heavily doped N-type source and a heavily doped P-type source.

[0071] Fig.16 This is a schematic diagram of the cross-sectional structure after the dielectric deposition is completed in the present invention.

[0072] Fig.17 It is a schematic diagram of the cross-sectional structure after the M1 source metal, the M2 source metal, the anode metal and the cathode metal are formed in the present invention.

[0073] Description of the Figures in the Specification:

[0074] 001, drain metal; 002, N-type substrate; 003, N-type epitaxial layer; 004, P-type column; 004a, first P-type column; 004b, second P-type column; 005, P-type body region; 005a, first P-type body region; 005b, second P-type body region; 006, heavily doped P-type source; 006a, first heavily doped P-type source; 006b, second heavily doped P-type source; 007, heavily doped N-type source; 007a, first heavily doped N-type source; 007b, second heavily doped N-type source; 008, gate oxide layer; 009, threshold adjustment region; 010, gate polysilicon; 010a, first gate polysilicon; 010b, second gate polysilicon; 011, dielectric layer; 011a, first dielectric layer; 011b, second dielectric layer; 012, contact hole; 012a, first contact hole; 012b, second contact hole; 013, M2 source metal; 014, M1 source metal; 015, heavily doped N-type polysilicon; 016, heavily doped P-type polysilicon; 017, cathode metal; 018, anode metal; 019, deep trench;

[0075] 100, integrated high-voltage semiconductor device; 200, isolation structure; 300, M1 device region; 500, M2 device region; 600, isolation region;

[0076] M1, enhancement mode super junction power MOSFET device; D1, diode device; M2, depletion mode super junction power MOSFET device;

[0077] 1. First gate pad; 2. Second gate pad; 3. First source pad; 4. Second source pad; 5. Anode pad; 6. Cathode pad. DETAILED DESCRIPTION

[0078] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0079] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0080] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0081] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0082] Example 1

[0083] Reference Figure 2 As shown, this embodiment provides an integrated high-voltage semiconductor device 100 structure, including an M1 device region 300, an M2 device region 500, and an isolation region 600 disposed between the M1 device region 300 and the M2 device region 500; the semiconductor device structure includes:

[0084] N-type substrate 002;

[0085] An N-type epitaxial layer 003 is disposed on the surface of the N-type substrate 002;

[0086] The drain metal 001 is disposed on the back side of the N-type substrate 002;

[0087] P-type columns 004 are arranged at intervals in the N-type epitaxial layer 003, including a first P-type column 004a located in the M1 device region 300 and the M2 device region 500, and a second P-type column 004b located in the isolation region 600;

[0088] A P-type body region 005 is disposed in the N-type epitaxial layer 003 and is located above each of the P-type pillars 004, and the P-type body region 005 is connected to one or more of the P-type pillars 004 thereunder; the P-type body region 005 includes a first P-type body region 005a located in the M1 device region 300 and the M2 device region 500, and a second P-type body region 005b located in the isolation region 600; wherein a first heavily doped N-type source 007a and a first heavily doped P-type source 006a are disposed in the first P-type body region 005a, and the first heavily doped N-type source 007a is located on both sides of the first heavily doped P-type source 006a;

[0089] A threshold adjustment region 009 located on the surface of the N-type epitaxial layer 003 in the M2 device region 500;

[0090] A gate oxide layer 008 is disposed on the surface of the N-type epitaxial layer 003;

[0091] A first gate polysilicon 010a is disposed on the surface of the gate oxide layer 008 located in the M1 device region 300 and the M2 device region 500;

[0092] The dielectric layer 011 is disposed on the surface of the N-type epitaxial layer 003, including a first dielectric layer 011a located in the M1 device region 300 and the M2 device region 500, and a second dielectric layer 011b located in the isolation region 600;

[0093] The M1 source metal 014 and the M2 source metal 013 correspond to the surfaces of the first dielectric layer 011a located in the M1 device region 300 and the M2 device region 500, respectively, wherein the M1 source metal 014 is connected to the first heavily doped N-type source 007a and the first heavily doped P-type source 006a in each of the first P-type body regions 005a in the M1 device region 300, and the M1 source metal 014 is connected to the first heavily doped N-type source 007a and the first heavily doped P-type source 006a in each of the first P-type body regions 005a in the M2 device region 500;

[0094] The diode device D1 includes an anode metal 018 and a cathode metal 017, both of which are located on the surface of the second dielectric layer 011b;

[0095] The second heavily doped N-type source 007b and the second heavily doped P-type source 006b are respectively disposed in the second P-type body region 005b, the anode metal 018 is connected to the second heavily doped N-type source 007b, and the cathode metal 017 is connected to the second heavily doped P-type source 006b.

[0096] Specifically, the first dielectric layer 011a is provided with a first contact hole 012a filled with a first metal; the first metal is in contact with the M1 source metal 014 and the M2 source metal 013 below, and the first metal is in contact with the corresponding first heavily doped N-type source 007a and the first heavily doped P-type source 006a respectively; the first dielectric layer 011a isolates the first gate polysilicon 010a and the first metal.

[0097] Specifically, the second dielectric layer 011b is provided with a second contact hole 012b for filling the second metal; wherein the anode metal 018 is connected to the second heavily doped N-type source 007b through the second metal, and the cathode metal 017 is connected to the second heavily doped P-type source 006b through the second metal;

[0098] Specifically, for the convenience of design, the threshold adjustment region 009 is provided on the surface of the N-type epitaxial layer 003 in the M2 device region 500. Since the doping concentration of the heavily doped N-type source and the heavily doped P-type source is much higher than the threshold adjustment region 009, the threshold adjustment region 009 in the source region can be ignored. In addition, since the threshold adjustment region 009 mainly adjusts the threshold voltage of the channel region, the threshold adjustment region 009 can also be provided only on the surface of the first P-type body region 005a in the M2 device region 500.

[0099] It can be understood that an enhancement-type super junction power MOSFET device M1 is formed in the M1 device region 300, a depletion-type super junction power MOSFET device M2 is formed in the M2 device region 500, an isolation structure 200 and the diode device D1 are formed in the isolation region 600, and the drain of the enhancement-type super junction power MOSFET device M1 is connected to the drain of the depletion-type super junction power MOSFET device M2; in addition, it also includes a first gate pad 1, a first source pad 3, a second gate pad 2 and a second source pad 4; wherein:

[0100] The first gate pad 1 is connected to the first gate polysilicon 010a in the M1 device region 300 through a metal or polysilicon lead;

[0101] The first source pad 3 is connected to the M1 source metal 014 through a metal or polysilicon lead;

[0102] The second gate pad 2 is connected to the first gate polysilicon 010a in the M2 device region 500 through a metal or polysilicon lead;

[0103] The second source pad 4 is connected to the M2 source metal 013 through a metal or polysilicon lead.

[0104] Reference Figure 2 As shown, the drain of the enhancement-type super junction power MOSFET device M1 is connected to the drain of the depletion-type super junction power MOSFET device M2, and an isolation structure 200 is further provided between the enhancement-type super junction power MOSFET device M1 and the depletion-type super junction power MOSFET device M2, and the diode device D1 is provided in the isolation structure 200. The cross-sectional structure of the enhancement-type super junction power MOSFET device M1 is shown in FIG. Figure 4 As shown, the cross-sectional structure of the depletion-type super-junction power MOSFET device M2 is shown in FIG. Figure 5 shown.

[0105] Reference Figure 3 As shown, there are a first gate pad 1, a second gate pad 2, a first source pad 3, a second source pad 4, an anode pad 5, and a cathode pad 6, and the pads correspond to Figure 2 The various pins in the circuit schematic shown.

[0106] It should be noted that in order to save chip area, the depletion-mode super junction power MOSFET device M2 is arranged inside the enhancement-mode super junction power MOSFET device M1, and an isolation structure 200 of different sizes is provided between the depletion-mode super junction power MOSFET device M2 and the enhancement-mode super junction power MOSFET device M1 depending on different isolation requirements. Not only that, the diode device D1 is also arranged in the isolation structure 200.

[0107] Figure 3 The heavily doped N-type source and the heavily doped P-type source located in the isolation structure 200 are schematically shown, which respectively constitute the cathode and anode of the diode device D1 and are respectively connected to the cathode pad 6 and the anode pad 5 through metal.

[0108] It should be noted that the depletion-mode super junction power MOSFET device M2 and the diode device D1 may also be arranged outside the enhancement-mode super junction power MOSFET device M1.

[0109] Reference Figure 6 As shown, in the enhancement-mode super junction power MOSFET device M1 and the depletion-mode super junction power MOSFET device M2 adjacent to the isolation structure 200, the gate oxide layer 008 and the first gate polysilicon 010a thereon are not provided. Meanwhile, the threshold adjustment region 009 is not provided on the side adjacent to the isolation structure 200 of the depletion-mode super junction power MOSFET device M2. The main purpose of the above measures is to avoid the existence of leakage channels on the surface of the first P-type body region 005a on both sides of the isolation structure 200, thereby affecting the isolation effect.

[0110] Specifically, in order to ensure that the depletion-type super junction power MOSFET device M2 has lower leakage when turned off, in the M2 device region 500, two first P-type pillars 004a are exemplarily provided under each of the first P-type body regions 005a, which makes the channel length of the device longer, while not affecting the original charge balance of the super junction device. The increase of the first P-type pillars 004a in the M2 device region 500 further increases the channel length, and the increase in the channel length can further reduce the leakage of the device in the off state.

[0111] Reference Figure 8 As shown in the figure, it is the transfer characteristic curve of the depletion-type device under different channel length conditions. Under the condition of Vgs=0V, the device is in the on state, and under the condition of Vgs=-3V, the device is in the off state. However, for different channel lengths, the leakage of the device in the off state is not the same. When the channel is longer (L=5μm), the leakage of the device in the off state is at the pA level, and when the channel is shorter, the leakage of the device in the off state is about 0.1mA, which is nearly 7 orders of magnitude different. Therefore, increasing the channel length can effectively reduce the leakage level of the device, thereby reducing the power consumption of the system and improving the system efficiency.

[0112] When designing a device, a trade-off needs to be made between the leakage level of the device and the device area. Therefore, in the M2 device region 500, 2 to 5 first P-type pillars 004a are provided under each first P-type body region 005a.

[0113] Specifically, in the isolation region 600, two second P-type columns 004b are exemplarily provided below each second P-type body region 005b. The above arrangement improves the isolation withstand voltage between the enhancement-type super junction power MOSFET device M1 and the depletion-type super junction power MOSFET device M2. Generally speaking, the larger the area of ​​the isolation structure 200, the better the isolation effect. Therefore, depending on the different isolation withstand voltage requirements between the enhancement-type super junction power MOSFET device M1 and the depletion-type super junction power MOSFET device M2, the area of ​​the isolation structure 200 is also different, and the number of the second P-type columns 004b below each second P-type body region 005b is 2 to 5.

[0114] When the above-mentioned integrated high-voltage semiconductor device 100 is used, it will be integrated with the control circuit in the same AC-DC chip. When the AC-DC chip is powered on, since the depletion-type super-junction power MOSFET device M2 is naturally turned on, a current path can be formed to supply power to the chip. After the chip is started, the depletion-type super-junction power MOSFET device M2 is turned off by the control circuit, and the above-mentioned charging path through the depletion-type super-junction power MOSFET device M2 is also disconnected, thereby avoiding power loss in this charging circuit after the chip is started.

[0115] In addition, a diode device D1 is also provided in the power semiconductor device. Since the diode device D1 has a natural temperature characteristic, that is, the forward conduction voltage drop of the diode will decrease with the increase of temperature, the forward voltage drop of the diode can be used to monitor the operating temperature of the chip. When the temperature is too high, the control circuit will give a signal to shut down the enhanced super junction power MOSFET device M1 to prevent the temperature from further increasing and causing chip failure.

[0116] Example 2

[0117] This embodiment provides an integrated high-voltage semiconductor device 100 structure. The difference from the first embodiment is that Figure 7 As shown, a second gate polysilicon 010b is provided in the second dielectric layer 011b, and heavily doped N-type polysilicon 015 and heavily doped P-type polysilicon 016 are respectively provided on both sides of the second gate polysilicon 010b, the heavily doped N-type polysilicon 015 is connected to the cathode metal 017, and the heavily doped P-type polysilicon 016 is connected to the anode metal 018. The heavily doped N-type polysilicon 015 is connected to the cathode metal 017 through the second metal, and the heavily doped P-type polysilicon 016 is connected to the anode metal 018 through the second metal. The rest of the structure is the same as that of Embodiment 1.

[0118] Embodiment 2 provides a new diode implementation method, that is, using polysilicon to implement the diode. Since a dielectric layer 011 is provided between the polysilicon and the bulk silicon for isolation, the diode device D1 formed using polysilicon can effectively avoid the leakage problem of the polysilicon diode in the bulk silicon.

[0119] Example 3

[0120] This embodiment provides a method for manufacturing an integrated high-voltage semiconductor device 100 structure. Figure 6 Taking the cross-sectional structure shown as an example, the following steps are included:

[0121] Step S1: Fig. 9 As shown, an N-type substrate 002 material is selected and an N-type epitaxial layer 003 is epitaxially grown. Each region in the figure only shows the basic structure of the device and does not represent the actual area size of each region;

[0122] Step S2: Fig.10 As shown, a deep trench 019 is selectively etched on the surface of the N-type epitaxial layer 003. The deep trench 019 is generally deep, reaching a depth of more than 2 / 3 of the epitaxial layer, and a typical depth of more than 20 μm;

[0123] Step S3: Fig.11As shown, P-type silicon material is deposited to fill the above-mentioned deep trench 019 to form a P-type column 004, and the excess P-type silicon material on the surface of the N-type epitaxial layer 003 is removed to form a basic N / P spacing distribution structure of the super junction structure. It should be noted that the industry usually uses deep trench 019 or multiple epitaxial process methods to achieve a super junction N / P spacing distribution structure. The power semiconductor device can also use multiple epitaxial process methods to achieve an N / P spacing super junction structure;

[0124] Step S4: Fig.12 As shown, a mask window is used, and the mask window is generally a photoresist, and its function is to transfer the pattern on the layout to the actual device, that is, on the silicon wafer. Through chemical and optical treatment, the area opened by the photoresist can form a corresponding doped area or remove the medium in this area. In this step, by means of ion implantation, P-type impurities are implanted on the surface of the N-type epitaxial layer 003 and thermally annealed to form a P-type body region 005, and the P-type body region 005 is connected to one or more P-type pillars 004 thereunder;

[0125] Step S5: Fig.13 As shown, by using a mask window and ion implantation, N-type impurities are implanted on the surface of the N-type epitaxial layer 003 to form a threshold adjustment region 009. The threshold adjustment region 009 is only arranged in the M2 device region 500. Its main purpose is to enable the device to be turned on when the gate voltage is 0.

[0126] Step S6: Fig.14 As shown, a gate oxide layer 008 is grown on the surface of the N-type epitaxial layer 003, and gate polysilicon 010 is deposited on the surface of the gate oxide layer 008 and the surface of the dielectric layer 011, and the excess gate oxide layer 008 and the gate polysilicon 010 thereon are etched away using a mask window;

[0127] Step S7: Fig.15 As shown, using a mask, N-type impurities are injected to form a heavily doped N-type source, and then using another mask, P-type impurities are injected to form a heavily doped P-type source. The gate polysilicon will block the injection of N-type impurities or P-type impurities into the N-type epitaxial layer 003. After high-temperature annealing, the N-type impurities and P-type impurities are activated. Due to the high temperature, the N-type impurities will further diffuse into the dielectric layer 011 and the N-type epitaxial layer 003 under the gate oxide layer. The high temperature here is usually around 1000°C, and it can also be achieved by laser annealing or rapid thermal annealing.

[0128] Step S8: Fig.16 As shown, a dielectric layer 011 is deposited, and a mask window is used to etch the dielectric layer 011 to form a contact hole 012;

[0129] Step S9: Fig.17As shown, metal is deposited on the dielectric layer 011, the metal fills the contact hole 012 and connects the heavily doped N-type source, the heavily doped P-type source and the surface metal, and the surface metal is etched using a mask window to form an M1 source metal 014, an M2 source metal 013, a cathode metal 017 and an anode metal 018;

[0130] Step S10: Figure 6 As shown, the N-type substrate 002 is thinned, usually to 100 μm to 200 μm, and a metal is deposited on the back side thereof to form a drain metal 001 .

[0131] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. An integrated high-voltage semiconductor device structure, characterized in that: It includes an M1 device region, an M2 device region, and an isolation region arranged between the M1 device region and the M2 device region; The semiconductor device structure comprises: N-type substrate; An N-type epitaxial layer is disposed on the surface of the N-type substrate; A drain metal is disposed on the back side of the N-type substrate; P-type columns are arranged at intervals in the N-type epitaxial layer, including first P-type columns located in the M1 device region and the M2 device region, and second P-type columns located in the isolation region; A P-type body region is arranged in the N-type epitaxial layer and is located above each of the P-type pillars, and the P-type body region is connected to one or more of the P-type pillars below it; the P-type body region includes a first P-type body region located in the M1 device region and the M2 device region, and a second P-type body region located in the isolation region; wherein a first heavily doped N-type source and a first heavily doped P-type source are arranged in the first P-type body region, and the first heavily doped N-type source is located on both sides of the first heavily doped P-type source; A threshold adjustment region, located on the surface of the N-type epitaxial layer in the M2 device region; A gate oxide layer, disposed on the surface of the N-type epitaxial layer; A first gate polysilicon is disposed on the surface of the gate oxide layer located in the M1 device region and the M2 device region; A dielectric layer, disposed on the surface of the N-type epitaxial layer, including a first dielectric layer located in the M1 device region and the M2 device region, and a second dielectric layer located in the isolation region; M1 source metal and M2 source metal correspond to the surfaces of the first dielectric layer located in the M1 device region and the M2 device region, respectively, wherein the M1 source metal is connected to the first heavily doped N-type source and the first heavily doped P-type source in each of the first P-type body regions in the M1 device region, and the M1 source metal is connected to the first heavily doped N-type source and the first heavily doped P-type source in each of the first P-type body regions in the M2 device region; a depletion-type super junction power MOSFET device is formed in the M2 device region; A diode device, including an anode metal and a cathode metal, both of which are located on the surface of the second dielectric layer; Wherein, a second heavily doped N-type source and a second heavily doped P-type source are respectively disposed in the second P-type body region, the anode metal is connected to the second heavily doped N-type source, and the cathode metal is connected to the second heavily doped P-type source; Alternatively, a second gate polysilicon is arranged in the second dielectric layer, and heavily doped N-type polysilicon and heavily doped P-type polysilicon are respectively arranged on both sides of the second gate polysilicon, the heavily doped N-type polysilicon is connected to the cathode metal, and the heavily doped P-type polysilicon is connected to the anode metal.

2. An integrated high-voltage semiconductor device structure according to claim 1, characterized in that: The first dielectric layer is provided with a first contact hole filled with a first metal; A first metal is in contact with the M1 source metal and the M2 source metal respectively, and the first metal is in contact with the corresponding first heavily doped N-type source and the first heavily doped P-type source; The first dielectric layer isolates the first gate polysilicon from the first metal.

3. The integrated high-voltage semiconductor device structure according to claim 1, characterized in that: The second dielectric layer is provided with a second contact hole for filling a second metal; Wherein, the anode metal is connected to the second heavily doped N-type source through the second metal, and the cathode metal is connected to the second heavily doped P-type source through the second metal; or, The heavily doped N-type polysilicon is connected to the cathode metal through the second metal, and the heavily doped P-type polysilicon is connected to the anode metal through the second metal.

4. The integrated high-voltage semiconductor device structure according to claim 1, characterized in that: In the isolation region, a plurality of the second P-type columns are disposed below each of the second P-type body regions.

5. The integrated high-voltage semiconductor device structure according to claim 4, characterized in that: The number of the second P-type columns under each of the second P-type body regions is 2 to 5.

6. The integrated high-voltage semiconductor device structure according to claim 1, characterized in that: In the M2 device region, a plurality of the first P-type pillars are disposed below each of the first P-type body regions.

7. The integrated high-voltage semiconductor device structure according to claim 6, characterized in that: Two to five first P-type columns are disposed below each of the first P-type body regions.

8. The integrated high-voltage semiconductor device structure according to claim 1, characterized in that: The threshold adjustment region is disposed on the surface of the N-type epitaxial layer in the M2 device region; or, the threshold adjustment region is disposed only on the surface of the first P-type body region in the M2 device region.

9. The integrated high-voltage semiconductor device structure according to claim 1, characterized in that: An enhancement-mode super junction power MOSFET device is formed in the M1 device region, an isolation structure and the diode device are formed in the isolation region, and the drain of the enhancement-mode super junction power MOSFET device is connected to the drain of the depletion-mode super junction power MOSFET device; the semiconductor device structure further includes: A first gate pad connected to the first gate polysilicon in the M1 device region through a metal or polysilicon lead; A first source pad connected to the M1 source metal through a metal or polysilicon lead; A second gate pad connected to the first gate polysilicon in the M2 device region through a metal or polysilicon lead; The second source pad is connected to the M2 source metal through a metal or polysilicon lead.

10. A method for manufacturing an integrated high-voltage semiconductor device structure, characterized in that: The production method comprises: Step 1: providing an N-type substrate, and growing an N-type epitaxial layer on the surface of the N-type substrate; Step 2: selectively etching a deep groove on the surface of the N-type epitaxial layer; Step 3: Filling the deep trenches with P-type silicon material to form P-type pillars, and removing excess P-type silicon material on the surface of the N-type epitaxial layer; Step 4: using a mask window, by means of ion implantation, implanting P-type impurities on the surface of the N-type epitaxial layer and thermally annealing to form a P-type body region, wherein the P-type body region is connected to one or more P-type columns therebelow; forming an M1 device region, an M2 device region, and an isolation region disposed between the M1 device region and the M2 device region on the device, wherein the P-type columns are disposed at intervals in the N-type epitaxial layer, including a first P-type column located in the M1 device region and the M2 device region and a second P-type column located in the isolation region, and the P-type body region includes a first P-type body region located in the M1 device region and the M2 device region and a second P-type body region located in the isolation region; Step 5: Using a mask window and ion implantation, N-type impurities are implanted on the surface of the N-type epitaxial layer to form a threshold adjustment region; Step 6: growing a gate oxide layer on the surface of the N-type epitaxial layer, depositing gate polysilicon on the surface of the gate oxide layer, and etching away the excess gate oxide layer and the gate polysilicon thereon using a mask window; Step 7: Using a mask, inject N-type impurities to form a heavily doped N-type source, and using a mask, inject P-type impurities to form a heavily doped P-type source, followed by high temperature annealing to activate the doped ions; Step 8: deposit a dielectric layer on the device surface, and use a mask window to etch the dielectric layer to form a contact hole; Step nine: depositing metal on the dielectric layer, the metal filling the contact hole and connecting the heavily doped N-type source, the heavily doped P-type source and the surface metal, etching the surface metal using a mask window to form M1 source metal, M2 source metal, cathode metal and anode metal; forming a depletion-type super junction power MOSFET device in the M2 device area; Step 10: Thinning the N-type substrate and depositing metal on the back side thereof to form a drain metal.

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