Three-dimensional semiconductor device and manufacturing method thereof

Abstract

The invention relates to a three-dimensional semiconductor device and a manufacturing method thereof. An example three-dimensional semiconductor device includes: a backside metal layer; a lower active region on the back metal layer, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; an interlayer insulating layer surrounding the lower source / drain pattern and the upper source / drain pattern; a penetrating conductive pattern extending through the interlayer insulating layer in a vertical direction; and an inhibitor covering a side surface penetrating a lower portion of the conductive pattern. The inhibitor includes a carbon atom.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same, the semiconductor device including a three-dimensional semiconductor device with improved electrical characteristics and a three-dimensional semiconductor device with improved productivity. Background Art

[0002] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOS-FETs). In order to meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. The scaling down of MOS-FETs may cause degradation in the operating characteristics of semiconductor devices. Various studies are being conducted to overcome the technical limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the invention

[0003] In some implementations, a three-dimensional semiconductor device includes: a back metal layer; a lower active region on the back metal layer, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; an interlayer insulating layer surrounding the lower source / drain pattern and the upper source / drain pattern; a penetrating conductive pattern penetrating the interlayer insulating layer in a vertical direction; and an inhibitor covering a side surface of a lower portion of the penetrating conductive pattern. The inhibitor includes carbon atoms.

[0004] In some implementations, a three-dimensional semiconductor device includes: a back metal layer; a lower active region on the back metal layer, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; an interlayer insulating layer surrounding the lower source / drain pattern and the upper source / drain pattern; and a penetrating conductive pattern penetrating the interlayer insulating layer in a vertical direction. The penetrating conductive pattern includes a seed layer and a main layer on the seed layer. The width of the bottom surface of the main layer is greater than the width of the top surface of the seed layer.

[0005] In some implementations, a three-dimensional semiconductor device includes: a metal layer; an interlayer insulating layer on the metal layer; a penetrating conductive pattern penetrating the interlayer insulating layer in a vertical direction, the penetrating conductive pattern including a seed layer and a main layer on the seed layer; and an inhibitor covering a side surface of the seed layer. The penetrating conductive pattern is electrically connected to the metal layer. The side surface of the inhibitor is aligned with the side surface of the main layer.

[0006] In some implementations, a method for manufacturing a three-dimensional semiconductor device includes: forming a penetration hole penetrating an interlayer insulating layer on a device isolation layer; forming an inhibitor on an inner surface of the penetration hole to expose a top surface of the device isolation layer to the penetration hole; forming a seed layer to cover the exposed top surface of the device isolation layer; removing an upper portion of the inhibitor; and using the seed layer as a seed growth main layer to fill the penetration hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a conceptual diagram illustrating a logic unit of an example of a semiconductor device.

[0008] Figure 2 is a conceptual diagram of a logic unit showing another example of a semiconductor device.

[0009] Figure 3 is a top view illustrating an example of a three-dimensional semiconductor device.

[0010] FIG. 4A to FIG. 4C Along Figure 3 Example cross-sectional views taken along lines AA', BB' and CC'.

[0011] Figures 5 to 8 is corresponding to Figure 4B An example enlarged view of a portion P1.

[0012] Fig. 9 is along Figure 3 An example cross-sectional view taken along line BB'.

[0013] Fig.10 is corresponding to Fig. 9 An example enlarged view of portion P2.

[0014] FIG. 11A to FIG. 20 is a diagram illustrating an example of a method of manufacturing a three-dimensional semiconductor device.

[0015] Figure 21 to Figure 25 is a diagram illustrating another example of a method of manufacturing a three-dimensional semiconductor device. DETAILED DESCRIPTION

[0016] Example implementations will now be described more fully with reference to the accompanying drawings, in which exemplary implementations are shown.

[0017] Figure 1 is a conceptual diagram showing a logic unit of an example of a semiconductor device. In detail, Figure 1 A logic cell of a two-dimensional device according to a comparative example is shown.

[0018] Reference Figure 1, a single height cell SHC' may be provided. In detail, a first power line POR1 and a second power line POR2 may be provided on a substrate 100. A drain voltage VDD (e.g., a power supply voltage) may be applied to one of the first power line POR1 and the second power line POR2. A source voltage VSS (e.g., a ground voltage) may be applied to the other of the first power line POR1 and the second power line POR2. In some implementations, a source voltage VSS may be applied to the first power line POR1, and a drain voltage VDD may be applied to the second power line POR2.

[0019] A single height cell SHC' may be defined between the first power line POR1 and the second power line POR2. The single height cell SHC' may include a first active area AR1 and a second active area AR2. One of the first active area AR1 and the second active area AR2 may be a PMOSFET area, and the other of the first active area AR1 and the second active area AR2 may be an NMOSFET area. For example, the first active area AR1 may be an NMOSFET area, and the second active area AR2 may be a PMOSFET area. That is, the single height cell SHC' may include a CMOS structure provided between the first power line POR1 and the second power line POR2.

[0020] The semiconductor device according to the comparative example may be a two-dimensional device in which transistors of a front end of line (FEOL) layer are two-dimensionally arranged. For example, an NMOSFET of the first active area AR1 may be spaced apart from a PMOSFET of the second active area AR2 in the first direction D1.

[0021] Each of the first active region AR1 and the second active region AR2 may have a first width AW1 in the first direction D1. In a comparative example, a length of the single height cell SHC' in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to a distance (eg, a pitch) between the first power line POR1 and the second power line POR2.

[0022] The single height cell SHC' may constitute a single logic unit. In this specification, a logic unit may mean a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic unit may include transistors constituting the logic device and interconnection lines connecting the transistors to each other.

[0023] In the comparative example, since the single height cell SHC' includes a two-dimensional device, the first active area AR1 and the second active area AR2 may not overlap with each other and may be spaced apart from each other in the first direction D1. Therefore, the first height HE1 of the single height cell SHC' should be defined as spanning both the first active area AR1 and the second active area AR2 spaced apart from each other in the first direction D1. Therefore, the first height HE1 of the single height cell SHC' may be given to be greater than at least twice the first width AW1. As a result, the first height HE1 of the single height cell SHC' in the comparative example is greater than the second height HE2 of the single height cell SHC to be described below. That is, the single height cell SHC' in the comparative example may have a relatively large area.

[0024] Figure 2 is a conceptual diagram of a logic unit showing another example of a semiconductor device. Figure 2 A logic cell of a three-dimensional device is shown.

[0025] Reference Figure 2 , a single height cell SHC including a three-dimensional device having stacked transistors may be provided. In detail, a first power line POR1 and a second power line POR2 may be provided on the substrate 100. The single height cell SHC may be defined between the first power line POR1 and the second power line POR2.

[0026] The single height cell SHC may include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region.

[0027] In some implementations, the semiconductor device may be a three-dimensional device in which transistors of the FEOL layer are stacked vertically. A lower active region LAR serving as a bottom layer may be provided on a substrate 100, and an upper active region UAR serving as a top layer may be stacked on the lower active region LAR. For example, an NMOSFET of the lower active region LAR may be provided on the substrate 100, and a PMOSFET of the upper active region UAR may be stacked on the NMOSFET. The lower active region LAR and the upper active region UAR may be spaced apart from each other in a vertical direction (e.g., in a third direction D3).

[0028] Each of the lower active region LAR and the upper active region UAR may have a second width AW2 in the first direction D1. In some implementations, a length of the single height cell SHC in the first direction D1 may be defined as a second height HE2.

[0029] Since the single height cell SHC includes a three-dimensional device (i.e., a stacked transistor), the lower active region LAR and the upper active region UAR may overlap each other. Therefore, the second height HE2 of the single height cell SHC may have a size spanning a single active region, or may be greater than the second width AW2. As a result, the second height HE2 of the single height cell SHC may be less than the above Figure 1 The single height cell SHC′ has a first height HE1. That is, the single height cell SHC may have a relatively small area. In a three-dimensional semiconductor device, the integration density of the device may be increased by reducing the area of ​​the logic cell.

[0030] Figure 3 is a top view illustrating an example of a three-dimensional semiconductor device. FIG. 4A to FIG. 4C is along Figure 3 Example cross-sectional views taken along lines AA', BB' and CC'. Figure 3 and FIG. 4A to FIG. 4C The three-dimensional semiconductor device can be Figure 2 Detailed example of a single-height unit.

[0031] Reference Figure 3 and FIG. 4A to FIG. 4C , a single height unit SHC may be provided on the substrate 100. The substrate 100 may include a first surface 100A and a second surface 100B opposite to each other. The first surface 100A may be a front surface of the substrate 100, and the second surface 100B may be a rear surface of the substrate 100. In some implementations, the substrate 100 may be an insulating substrate formed of or including a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). In some implementations, the substrate 100 may be a semiconductor substrate made of silicon, germanium, or silicon germanium.

[0032] In some implementations, the substrate 100 may include a first lower insulating layer LIL1 and a second lower insulating layer LIL2. The first lower insulating layer LIL1 may be provided on the second lower insulating layer LIL2. The first lower insulating layer LIL1 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (Si or SiGe). The second lower insulating layer LIL2 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0033] A device isolation layer ST may be provided in the substrate 100. The device isolation layer ST may define a single height cell SHC. When viewed in a top view, the single height cell SHC may be defined between device isolation layers ST adjacent to each other in the first direction D1. The device isolation layer ST may be interposed between a back metal layer BSM and a through conductive pattern TC to be described below. In some implementations, the device isolation layer ST may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0034] In some implementations, each single height cell SHC may be a logic cell constituting a logic circuit. Each single height cell SHC may be a logic cell including the previously referenced Figure 2 The described three-dimensional device. The single height cells SHC may be arranged in a first direction D1.

[0035] Each single height cell SHC may include a lower active region LAR and an upper active region UAR stacked sequentially on the substrate 100. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region. The lower active region LAR may be provided as a bottom layer of the FEOL layer, and the upper active region UAR may be provided as a top layer of the FEOL layer. The NMOSFET and PMOSFET of the lower active region LAR and the upper active region UAR may be stacked vertically to form a three-dimensional stacked transistor. In some implementations, the lower active region LAR may be an NMOSFET region, and the upper active region UAR may be a PMOSFET region. Each of the lower active region LAR and the upper active region UAR may be a strip or line region extending in the second direction D2.

[0036] The lower active region LAR may include a lower channel pattern LCH and a lower source / drain pattern LSD. The lower channel pattern LCH may be interposed between a pair of lower source / drain patterns LSD. The lower channel pattern LCH may connect the pair of lower source / drain patterns LSD to each other.

[0037] The lower channel pattern LCH may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked and spaced apart from each other. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). In some implementations, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be a nanosheet. As an example, the lower channel pattern LCH may further include one or more semiconductor patterns stacked and spaced apart from the second semiconductor pattern SP2.

[0038] Lower source / drain patterns LSD may be provided on the substrate 100. Each lower source / drain pattern LSD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In some implementations, a top surface of the lower source / drain pattern LSD may be higher than a top surface of the second semiconductor pattern SP2 of the lower channel pattern LCH.

[0039] The lower source / drain pattern LSD may be doped with impurities to have a first conductivity type. The first conductivity type may be an n-type or a p-type. In some implementations, the first conductivity type may be an n-type. The lower source / drain pattern LSD may be formed of or include silicon (Si) and / or silicon germanium (SiGe).

[0040] A first interlayer insulating layer 110 may be provided on the lower source / drain pattern LSD. The first interlayer insulating layer 110 may cover the lower source / drain pattern LSD.

[0041] A lower active contact LAC may be provided below the lower source / drain pattern LSD. The lower active contact LAC may be electrically connected to the lower source / drain pattern LSD. The lower active contact LAC may be buried in the substrate 100. The lower active contact LAC may extend vertically from the second surface 100B of the substrate 100 to the first surface 100A. The lower active contact LAC may be formed of or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0042] The upper active region UAR may be provided on the first interlayer insulating layer 110. The upper active region UAR may include an upper channel pattern UCH and an upper source / drain pattern USD. The upper channel pattern UCH may vertically overlap with the lower channel pattern LCH, respectively. The upper source / drain pattern USD may vertically overlap with the lower source / drain pattern LSD, respectively. The upper channel pattern UCH may be interposed between a pair of upper source / drain patterns USD. The upper channel pattern UCH may connect the paired upper source / drain patterns USD to each other.

[0043] The upper channel pattern UCH may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked to be spaced apart from each other. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be a nanosheet. As an example, the upper channel pattern UCH may further include one or more semiconductor patterns stacked and spaced apart from the fourth semiconductor pattern SP4.

[0044] At least one dummy channel pattern DSP may be interposed between the lower channel pattern LCH and the upper channel pattern UCH thereon. A seed layer SDL may be interposed between the dummy channel pattern DSP and the upper channel pattern UCH.

[0045] The dummy channel pattern DSP may be spaced apart from the lower source / drain pattern LSD and the upper source / drain pattern USD. In other words, the dummy channel pattern DSP may not be connected to any source / drain pattern. The dummy channel pattern DSP may be formed of at least one of a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride), or include at least one of a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride). In some implementations, the dummy channel pattern DSP may be formed of at least one of a silicon-based insulating material or include at least one of a silicon-based insulating material.

[0046] The upper source / drain pattern USD may be provided on the top surface of the first interlayer insulating layer 110. Each of the upper source / drain patterns USD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In some implementations, the top surface of the upper source / drain pattern USD may be higher than the top surface of the fourth semiconductor pattern SP4 of the upper channel pattern UCH.

[0047] The upper source / drain pattern USD may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern LSD. The second conductivity type may be a p-type. The upper source / drain pattern USD may be formed of or include at least one of silicon germanium (SiGe) and / or silicon (Si).

[0048] A plurality of gate electrodes GE may be provided on the single height cell SHC. In detail, the gate electrode GE may be provided on the stacked lower channel pattern LCH and the upper channel pattern UCH. When viewed in a top view, the gate electrode GE may be a stripe pattern extending in the first direction D1. The gate electrode GE may vertically overlap the stacked lower channel pattern LCH and the upper channel pattern UCH.

[0049] The gate electrode GE may extend from the first surface 100A of the substrate 100 to the gate cap pattern GP in a vertical direction (i.e., a third direction D3). The gate electrode GE may extend from the lower channel pattern LCH of the lower active region LAR to the upper channel pattern UCH of the upper active region UAR in the third direction D3. The gate electrode GE may extend from the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4 in the third direction D3.

[0050] The gate electrode GE may be provided on top, bottom and opposite side surfaces of each of the first to fourth semiconductor patterns SP1 to SP4. That is, the transistor may include a three-dimensional field effect transistor (eg, MBCFET or GAAFET) in which the gate electrode GE is provided to three-dimensionally surround a channel pattern.

[0051] The gate electrode GE may include a lower gate electrode LGE provided in the bottom layer of the FEOL layer (i.e., the lower active region LAR) and an upper gate electrode UGE provided in the top layer of the FEOL layer (i.e., the upper active region UAR). The lower gate electrode LGE and the upper gate electrode UGE may overlap each other vertically. In some implementations, the lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. That is, the gate electrode GE may be a common gate electrode, wherein the lower gate electrode LGE on the lower channel pattern LCH and the upper gate electrode UGE on the upper channel pattern UCH are connected to each other.

[0052] The lower gate electrode LGE may include a first internal electrode PO1 interposed between the substrate 100 and the first semiconductor pattern SP1 , a second internal electrode PO2 interposed between the first and second semiconductor patterns SP1 and a third internal electrode PO3 interposed between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0053] The upper gate electrode UGE may include a fourth internal electrode PO4 interposed between the dummy channel pattern DSP (or seed layer SDL) and the third semiconductor pattern SP3 , a fifth internal electrode PO5 interposed between the third and fourth semiconductor patterns SP3 and SP4 , and an external electrode PO6 on the fourth semiconductor pattern SP4 .

[0054] A pair of gate spacers GS may be respectively disposed on opposite side surfaces of the gate electrode GE. A pair of gate spacers GS may be respectively disposed on opposite side surfaces of the external electrode PO6. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the second interlayer insulating layer 120. The gate spacer GS may be formed of or include at least one of SiCN, SiCON, or SiN. In some implementations, the gate spacer GS may be a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0055] The gate capping pattern GP may be provided on the top surface of the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE or in the first direction D1. For example, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0056] The gate insulating layer GI may be interposed between the gate electrode GE and the first to fourth semiconductor patterns SP1 to SP4 and between the gate electrode GE and the gate spacer GS. The gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. In some implementations, the gate insulating layer GI may include a silicon oxide layer and a high-k dielectric layer, the silicon oxide layer being formed to directly cover the semiconductor patterns SP1 to SP4, and the high-k dielectric layer being formed on the silicon oxide layer. In other words, the gate insulating layer GI may be a multilayer structure including a silicon oxide layer and a high-k dielectric layer.

[0057] The high-k dielectric layer may be formed of or include at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0058] The second interlayer insulating layer 120 may be provided on the upper source / drain pattern USD and the gate electrode GE. The second interlayer insulating layer 120 may cover the upper source / drain pattern USD. The third interlayer insulating layer 130 may be provided to cover the second interlayer insulating layer 120.

[0059] An upper active contact UAC may be provided to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130 and may be electrically connected to the upper source / drain pattern USD, respectively. A top surface of the upper active contact UAC may be coplanar with a top surface of the third interlayer insulating layer 130 .

[0060] The upper gate contact UGC may be provided to penetrate the third interlayer insulating layer 130 and the gate cap pattern GP, ​​and may be electrically connected to the upper gate electrode UGE. Each of the upper active contact UAC and the upper gate contact UGC may be formed of a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0061] The cutting pattern CT may be provided between the gate electrodes GE adjacent to each other in the first direction D1. The cutting pattern CT may separate adjacent gate electrodes GE from each other among the gate electrodes GE. Adjacent gate electrodes GE among the gate electrodes GE may be spaced apart from each other in the first direction D1 by the cutting pattern CT. The cutting pattern CT may be a strip or line pattern extending in the second direction D2. The cutting pattern CT may be formed of or include at least one of an insulating material (e.g., silicon oxide and silicon nitride).

[0062] A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. A first metal layer M1 may be provided in the fourth interlayer insulating layer 140. The first metal layer M1 may include an upper interconnect line UMI. The first metal layer M1 may further include an upper via UVI. The upper via UVI may electrically connect the upper interconnect line UMI to the upper active contact UAC or the upper gate contact UGC. Each of the upper interconnect line UMI and the upper via UVI may be formed of a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0063] Additional metal layers (e.g., M2, M3, M4, etc.) may be stacked on the first metal layer M1. The first metal layer M1 and the additional metal layers (e.g., M2, M3, M4, etc.) thereon may constitute back-end-of-line (BEOL) layers of a semiconductor device. The additional metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may include routing lines for connecting logic cells to each other.

[0064] A lower interlayer insulating layer 210 may be provided below the second surface 100B of the substrate 100. A back metal layer BSM may be provided in the lower interlayer insulating layer 210. The back metal layer BSM may include a lower interconnect line LMI. The back metal layer BSM may further include a lower via LVI. The lower via LVI may electrically connect the lower interconnect line LMI to the lower active contact LAC, the lower gate contact LGC, or the lower contact pattern LCP (which will be referred to as Figure 5 is described).

[0065] Each of the lower interconnect line LMI and the lower via LVI may be formed of a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W) and molybdenum (Mo), or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W) and molybdenum (Mo).

[0066] The lower metal layer may be further stacked below the back metal layer BSM. In some implementations, the lower metal layer may include a power delivery network. The power delivery network may include a wiring network for applying a source voltage VSS and a drain voltage VDD to the back metal layer BSM.

[0067] The source voltage VSS and the drain voltage VDD can be applied to the back metal layer BSM through the power delivery network. Figure 4A , one of the source voltage VSS and the drain voltage VDD may be applied to the lower source / drain pattern LSD through the lower interconnect line LMI, the lower via LVI, and the lower active contact LAC. The other of the source voltage VSS and the drain voltage VDD may be applied to the first metal layer M1 from the back metal layer BSM through a power tap cell. The voltage applied to the first metal layer M1 through the power tap cell may be applied to the upper source / drain pattern USD through the upper interconnect line UMI, the upper via UVI, and the upper active contact UAC. The power tap cell may be interposed between the single height cells SHC adjacent to each other.

[0068] The through conductive pattern TC may be provided to penetrate the interlayer insulating layers 110, 120, and 130 in the vertical direction (ie, the third direction D3). The through conductive pattern TC may be provided in a through hole TH formed to penetrate the interlayer insulating layers 110, 120, and 130 in the vertical direction. In some implementations, the plurality of through conductive patterns TC may be arranged in various shapes when viewed in a top view. Figure 3 An example in which the penetration conductive patterns TC are two-dimensionally arranged in the first direction D1 and the second direction D2 is shown, but the concept is not limited to this example.

[0069] The through conductive pattern TC may be provided to penetrate the interlayer insulating layers 110, 120, and 130 and electrically connect the first metal layer M1 to the back metal layer BSM. The through conductive pattern TC may be electrically connected to the first metal layer M1 through the upper via UVI and may be electrically connected to the back metal layer BSM through the upper via UVI. Figures 5 to 8 The lower contact pattern LCP is electrically connected to the back metal layer BSM.

[0070] The through conductive pattern TC may include a seed layer SL and a main layer ML on the seed layer SL. The main layer ML may be provided without a seam therein. An inhibitor IN may be provided on a side surface of the seed layer SL of the through conductive pattern TC. A through spacer TS may be provided on a side surface of the through conductive pattern TC.

[0071] Figures 5 to 8 is corresponding to Figure 4B In the following, reference will be made to Figure 4B , Figure 5 , Figure 6 , Figure 7 and Figure 8 The penetrating conductive pattern is described in more detail.

[0072] Reference Figure 4B and Figures 5 to 8 , the penetrating conductive pattern TC may include a seed layer SL on the device isolation layer ST and a main layer ML on the seed layer SL. In some implementations, the seed layer SL and the main layer ML may be provided without an observable interface therebetween and may be two parts classified based on the first level t1. The first level LV1 may be a vertical level of the top surface INb of the inhibitor IN. Optionally, the seed layer SL and the main layer ML may be distinguished from each other based on an interface therebetween. The top surface SLb of the seed layer SL and the bottom surface of the main layer ML may contact each other at the first level LV1, but the concept is not limited to this example. At the first level LV1, the top surface SLb of the seed layer SL may have a first width W1 in the first direction D1, and the bottom surface MLa of the main layer ML may have a second width W2 in the first direction D1. The second width W2 may be greater than the first width W1.

[0073] The side surface MLc of the main layer ML may deviate from the side surface SLc of the seed layer SL in the first direction D1 or the opposite direction. The side surface MLc of the main layer ML may not be aligned with the side surface SLc of the seed layer SL. Therefore, near the first level LV1, the side surfaces SLc and MLc of the through conductive pattern TC may have a stepped profile.

[0074] The penetration conductive pattern TC may be formed of a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). As an example, each of the seed layer SL and the main layer ML may be formed of a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). The seed layer SL and the main layer ML may be formed of the same material or different materials, or include the same material or different materials. As an example, each of the seed layer SL and the main layer ML may be formed of molybdenum (Mo) or include molybdenum (Mo). As another example, the seed layer SL may be formed of or include ruthenium (Ru), and the main layer ML may be formed of or include molybdenum (Mo).

[0075] The inhibitor IN may cover the side surface SLc of the seed layer SL of the through conductive pattern TC. The inhibitor IN may be provided to surround the side surface SLc of the seed layer SL. The inhibitor IN may be provided to expose at least a portion of the bottom surface of the through conductive pattern TC (e.g., the bottom surface SLa of the seed layer SL). The exposed bottom surface of the through conductive pattern TC may contact the device isolation layer ST and / or the lower contact pattern LCP to be described below.

[0076] The inhibitor IN may be formed of or include a material that is easily deposited on the through spacer TS but difficult to deposit on the device isolation layer ST in the manufacturing process to be described below. As an example, the inhibitor may be formed of or include a carbon-containing material (e.g., cyclohexanecarbaldehyde (CHAD)).

[0077] The bottom surface INa of the inhibitor IN may be located at substantially the same level as the bottom surface of the through conductive pattern TC (e.g., the bottom surface SLa of the seed layer SL); for example, the bottom surfaces INa and SLa may be substantially coplanar with each other. The top surface INb of the inhibitor IN may be located at substantially the same level as the top surface SLb of the seed layer SL (e.g., the first level LV1); for example, the top surfaces INb and SLb may be substantially coplanar with each other. The top surface INb of the inhibitor IN may contact a portion of the bottom surface MLa of the main layer ML. The outer side surface INc1 of the inhibitor IN may be aligned with the side surface MLc of the main layer ML. The inner side surface INc2 of the inhibitor IN may contact the side surface SLc of the seed layer SL.

[0078] A penetration spacer TS may be provided on the side surfaces SLc and MLc of the penetration conductive pattern TC. The penetration spacer TS may cover the inner side surface of the penetration hole TH. The penetration spacer TS may vertically extend in a region between the penetration conductive pattern TC and the interlayer insulating layers 110, 120, and 130. The penetration spacer TS may separate the penetration conductive pattern TC from the interlayer insulating layers 110, 120, and 130.

[0079] The penetration spacer TS may be spaced apart from the side surface SLc of the seed layer SL by the inhibitor IN. The penetration spacer TS may be in contact with the side surface MLc of the main layer ML and the outer side surface INc1 of the inhibitor IN. The penetration spacer TS may not cover at least a portion of the bottom surface of the penetration conductive pattern TC (e.g., the bottom surface SLa of the seed layer SL) and at least a portion of the bottom surface INa of the inhibitor IN. In some implementations, the penetration spacer TS may be formed of or include silicon nitride.

[0080] The lower contact pattern LCP may be interposed between the back metal layer BSM and the penetration conductive pattern TC. The lower contact pattern LCP may be surrounded by the device isolation layer ST. The lower contact pattern LCP may be provided below the penetration conductive pattern TC to electrically connect the penetration conductive pattern TC to the back metal layer BSM. The width of the lower contact pattern LCP in the first direction D1 or the second direction D2 may increase in the downward direction, but the concept is not limited to this example. As an example, when viewed in a cross-sectional view, the lower contact pattern LCP may have a trapezoidal shape having a greater width at its bottom surface than at its top surface.

[0081] The lower contact pattern LCP may be in contact with the bottom surface SLa of the seed layer SL. Figure 5 The lower contact pattern LCP may cover the bottom surface of the seed layer SL. The lower contact pattern LCP may be in contact with the bottom surface INa of the inhibitor IN. The top surface of the lower contact pattern LCP may be located at substantially the same level as or different from the top surface of the device isolation layer ST.

[0082] The lower contact pattern LCP may extend into the through hole TH, as shown in FIG. Figure 6 As shown. In the manufacturing method to be described below, when the lower contact pattern LCP is formed, the area below the through-conductive pattern TC may be etched, and the lower portion of the through-conductive pattern TC may also be etched during this step. Therefore, the through-conductive pattern TC may be recessed in a downward direction. In some implementations, the inhibitor IN and the seed layer SL of the through-conductive pattern TC may be etched together, and the lower contact pattern LCP may be in contact with the main layer ML of the through-conductive pattern TC. The top surface of the lower contact pattern LCP may be located at a level higher than the top surface of the device isolation layer ST.

[0083] The lower contact pattern LCP may vertically overlap a portion of the penetrating conductive pattern TC and may be horizontally offset from the penetrating conductive pattern TC. Figure 7 and Figure 8 As shown. The seed layer SL does not remain in the region overlapping with the lower contact pattern LCP because it is etched during the formation of the lower contact pattern LCP. In the region not vertically overlapping with the lower contact pattern LCP, the seed layer SL may not be etched but may remain, and the bottom surface SLa of the seed layer SL may contact the device isolation layer ST. However, when there is a difference between the offset direction and the profile direction, the entire seed layer SL may appear to be retained, as shown in FIG. Figure 8 shown.

[0084] Fig. 9 is along Figure 3 An example cross-sectional view taken along line BB'. Fig.10 is corresponding to Fig. 9 Hereinafter, reference will be made to Fig. 9 and Fig.10 Describes penetrating conductive patterns.

[0085] Reference Fig. 9 and Fig.10 , the through spacer TS may not be provided on the inner side surface of the through hole TH. On the inner side surface of the through hole TH, the side surface MLc of the main layer ML and the outer side surface INc1 of the inhibitor IN may be aligned with each other. The through conductive pattern TC and the inhibitor IN may be in contact with the interlayer insulating layers 110, 120, and 130. As an example, the main layer ML may be in contact with the interlayer insulating layers 110, 120, and 130, and the seed layer SL may be spaced apart from the interlayer insulating layers 110, 120, and 130 with the inhibitor IN interposed therebetween.

[0086] Fig.10 The lower contact pattern LCP is shown to have Figure 5, but the penetrating conductive pattern TC and the lower contact pattern LCP may be provided to have the same Figures 6 to 8 The structural features in are basically the same or similar structural features.

[0087] FIG. 11A to FIG. 20 is a diagram showing an example of a method for manufacturing a three-dimensional semiconductor device. More specifically, Fig.11A , Fig. 12A , Fig.13A and Fig.14A is along Figure 3 A cross-sectional view taken along line AA'. Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig.17 and Fig.19 is along Figure 3 A cross-sectional view taken along line BB'. Fig. 12C and Fig. 14C is along Figure 3 A cross-sectional view taken along line CC'. Fig.15 , Fig.18 and Fig. 20 is corresponding to Fig. 14B , Fig.17 and Fig.19 An enlarged cross-sectional view of portion P1. Fig.16 is corresponding to Fig. 14B An enlarged cross-sectional view of portion P3.

[0088] In the following, reference will be made to FIG. 11A to FIG. 20 Describe the manufacturing in more detail Figures 3 to 4C For the sake of brevity of description, previously described elements may be identified with the same reference numerals without repeating their overlapping descriptions.

[0089] Reference Fig.11A and Fig. 11B , a semiconductor substrate 105 may be provided. The semiconductor substrate 105 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the semiconductor substrate 105 may be a single crystal silicon wafer.

[0090] A first lower insulating layer LIL1 may be formed on the semiconductor substrate 105. The first lower insulating layer LIL1 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (e.g., Si or SiGe).

[0091] The first sacrificial layer SAL1 and the first active layer ACL1 may be alternately formed on the first lower insulating layer LIL1. The first sacrificial layer SAL1 and the first active layer ACL1 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), and may be formed of materials different from each other. For example, the first sacrificial layer SAL1 may be formed of or include silicon germanium (SiGe), and the first active layer ACL1 may be formed of or include silicon (Si). The concentration of germanium (Ge) in each first sacrificial layer SAL1 may be in the range of 10 at % to 30 at %.

[0092] A separation layer DSL may be formed on the uppermost first sacrificial layer among the first sacrificial layers SAL1. In some implementations, the thickness of the separation layer DSL may be greater than the thickness of the first sacrificial layer SAL1. The separation layer DSL may be formed of or include silicon (Si) or silicon germanium (SiGe). In the case where the separation layer DSL includes silicon germanium (SiGe), the germanium concentration of the separation layer DSL may be higher than the germanium concentration of the first sacrificial layer SAL1. For example, the germanium concentration of the separation layer DSL may be in the range of 40 at % to 90 at %.

[0093] A seed layer SDL may be formed on the separation layer DSL. The seed layer SDL may be formed of or include the same material as the first active layer ACL1. Second sacrificial layers SAL2 and second active layers ACL2 may be alternately stacked on the seed layer SDL. Each second sacrificial layer SAL2 may be formed of or include the same material as the first sacrificial layer SAL1, and each second active layer ACL2 may be formed of or include the same material as the first active layer ACL1. The separation layer DSL may be interposed between the first sacrificial layer SAL1 and the seed layer SDL.

[0094] The stack pattern STP may be formed by patterning the stacked first and second sacrificial layers SAL1 and SAL2, the first and second active layers ACL1 and ACL2, and the separation layer DSL. The formation of the stack pattern STP may include forming a hard mask pattern on the uppermost second active layer in the second active layer ACL2, and etching the layers SAL1, SAL2, ACL1, ACL2, SDL, and DSL stacked on the semiconductor substrate 105 using the hard mask pattern as an etching mask. During the formation of the stack pattern STP, the upper portion of the semiconductor substrate 105 may be patterned to form a trench TR defining a single height cell SHC. The stack pattern STP may be a stripe or line pattern extending in the second direction D2.

[0095] The stack pattern STP may include a lower stack pattern STP1 on the first lower insulating layer LIL1, an upper stack pattern STP2 on the lower stack pattern STP1, and a separation layer DSL between the lower stack pattern STP1 and the upper stack pattern STP2. The lower stack pattern STP1 may include a first sacrificial layer SAL1 and a first active layer ACL1 that are alternately stacked. The upper stack pattern STP2 may include a seed layer SDL and a second sacrificial layer SAL2 and a second active layer ACL2 that are alternately stacked on the seed layer SDL. A device isolation layer ST may be formed on the semiconductor substrate 105 to fill the trench TR.

[0096] Reference FIG. 12A to FIG. 12C , a plurality of sacrificial patterns PP may be formed to intersect the stacked patterns STP. Each sacrificial pattern PP may be formed to have a line shape extending in the first direction D1. In detail, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the semiconductor substrate 105, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may be formed of amorphous silicon and / or polycrystalline silicon, or include amorphous silicon and / or polycrystalline silicon.

[0097] A pair of gate spacers GS may be formed on opposite side surfaces of the sacrificial pattern PP, respectively. In detail, a spacer layer may be conformally formed on the semiconductor substrate 105. The spacer layer may cover the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. The gate spacer GS may be formed by anisotropically etching the spacer layer.

[0098] An etching process may be performed on the stack pattern STP using the gate spacer GS and the hard mask pattern MP as an etching mask. As a result of the etching process, a recess RS may be formed between adjacent sacrificial patterns in the sacrificial pattern PP. Due to the recess RS, the stack pattern STP may be formed to have a bar shape.

[0099] A sacrificial contact pattern PLH may be formed in the semiconductor substrate 105 exposed by the recess RS. The sacrificial contact pattern PLH may be formed in the form of a contact plug. The sacrificial contact pattern PLH may be arranged in the second direction D2. The sacrificial contact pattern PLH may be formed of a material having an etching selectivity relative to the semiconductor substrate 105 (e.g., silicon germanium (SiGe)), or include a material having an etching selectivity relative to the semiconductor substrate 105 (e.g., silicon germanium (SiGe)). The sacrificial contact pattern PLH may be formed by an epitaxial growth process. The recess RS may be formed to expose the sacrificial contact pattern PLH. That is, the recess RS may overlap with the sacrificial contact pattern PLH.

[0100] In the case where the separation layer DSL includes silicon germanium (SiGe), the separation layer DSL may be replaced by a silicon-based insulating material. For example, the separation layer DSL exposed by the recess RS may be selectively removed to form an empty region, and then a silicon-based insulating material (eg, silicon nitride) may be formed to fill the empty region.

[0101] Reference Fig.13A and Fig. 13B , a lower source / drain pattern LSD may be formed in the recess RS. In detail, the lower source / drain pattern LSD may be formed by performing a first SEG process using a side surface of the lower stack pattern STP1 exposed through the recess RS as a seed layer. The lower source / drain pattern LSD may be grown using the first active layer ACL1 exposed through the recess RS as a seed layer. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0102] As an example, during the first SEG process, impurities may be implanted into the lower source / drain pattern LSD in an in-situ manner. As another example, after forming the lower source / drain pattern LSD, impurities may be implanted into the lower source / drain pattern LSD. The lower source / drain pattern LSD may be doped to have a first conductivity type (e.g., n-type).

[0103] The first active layer ACL1 interposed between the pair of lower source / drain patterns LSD may constitute a lower channel pattern LCH. That is, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH may be formed of the first active layer ACL1. The lower channel pattern LCH and the lower source / drain pattern LSD may constitute a lower active region LAR serving as a bottom layer of a three-dimensional device.

[0104] The lower source / drain pattern LSD may be formed to completely fill the space between the pair of lower channel patterns LCH. That is, the first SEG process may be performed for a sufficiently long time until the lower source / drain pattern LSD grows to fill the space between the pair of lower channel patterns LCH and connect the pair of lower channel patterns LCH to each other.

[0105] The first interlayer insulating layer 110 may be formed to cover the lower source / drain pattern LSD. In some implementations, before forming the first interlayer insulating layer 110, an etch stop layer may be additionally formed to conformally cover the lower source / drain pattern LSD. In some implementations, a portion of the first interlayer insulating layer 110 may be formed under the lower source / drain pattern LSD before forming the lower source / drain pattern LSD, and another portion of the first interlayer insulating layer 110 may be further formed after forming the lower source / drain pattern LSD.

[0106] In the recess RS, the first interlayer insulating layer 110 may cover the side surface of the upper stack pattern STP2. Next, the upper portion of the first interlayer insulating layer 110 may be removed to expose the side surface of the upper stack pattern STP2 in the recess RS again. The upper source / drain pattern USD may be formed on the exposed side surface of the upper stack pattern STP2. In detail, the upper source / drain pattern USD may be formed by a second SEG process, in which the side surface of the upper stack pattern STP2 exposed by the recess RS is used as a seed layer. The upper source / drain pattern USD may be grown using the second active layer ACL2 exposed by the recess RS as a seed layer. The upper source / drain pattern USD may be doped to have a second conductivity type (e.g., p-type) different from the first conductivity type.

[0107] The second active layer ACL2 interposed between a pair of upper source / drain patterns USD may be used as an upper channel pattern UCH. That is, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may be formed by the second active layer ACL2. The upper channel pattern UCH and the upper source / drain pattern USD may constitute an upper active region UAR, which is a top layer of a three-dimensional device. The second SEG process may also be performed for a sufficiently long time so that the upper source / drain pattern USD completely fills the space between the pair of upper channel patterns UCH.

[0108] The second interlayer insulating layer 120 may be formed to cover the upper source / drain pattern USD. In some implementations, before forming the second interlayer insulating layer 120, an etch stop layer may be further formed to conformally cover the upper source / drain pattern USD.

[0109] Thereafter, the second interlayer insulating layer 120 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the second interlayer insulating layer 120 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. All hard mask patterns MP on the sacrificial pattern PP may be removed during the planarization process. As a result, the top surface of the second interlayer insulating layer 120 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0110] Reference FIG. 14A to FIG. 16 , the exposed sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may include a wet etching process using an etching solution capable of selectively etching polysilicon. As a result of removing the sacrificial pattern PP, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be exposed.

[0111] An etching process selected for selectively etching the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be performed to leave the first to fourth semiconductor patterns SP1 to SP4 and the dummy channel pattern DSP and remove only the first sacrificial layer SAL1 and the second sacrificial layer SAL2. The etching process may be selected to have a high etching rate for silicon germanium. For example, the etching process may be selected to have a high etching rate for a silicon germanium layer having a germanium concentration higher than 10 at%.

[0112] The gate insulating layer GI may be conformally formed in an empty space formed by removing the sacrificial pattern PP and the first and second sacrificial layers SAL1 and SAL2. The gate electrode GE may be formed on the gate insulating layer GI. The formation of the gate electrode GE may include forming first to fifth internal electrodes PO1 to PO5 between the substrate 100 and the first semiconductor pattern SP1 and between the first to fourth semiconductor patterns SP1 to SP4 and forming an external electrode PO6 in a region formed by removing the sacrificial pattern PP. Before or after forming the gate electrode GE, a cutting pattern CT may be additionally formed in a region formed by removing the sacrificial pattern PP.

[0113] The gate electrode GE may be recessed to have a reduced height. A gate capping pattern GP may be formed on the recessed gate electrode GE. A planarization process may be performed on the gate capping pattern GP so that a top surface of the gate capping pattern GP is coplanar with a top surface of the second interlayer insulating layer 120. A third interlayer insulating layer 130 may be formed to cover the gate electrode GE and the second interlayer insulating layer 120.

[0114] The through hole TH may be formed to penetrate the interlayer insulating layers 110, 120, and 130. The through hole TH may be formed by an anisotropic etching process. The etching process may be performed until the device isolation layer ST is exposed through the through hole TH. The width of the through hole TH may decrease as the height decreases.

[0115] The through spacer TS may be formed to cover the inner surface of the through hole TH and the third interlayer insulating layer 130. The through spacer TS may be formed on the entire top surface of the semiconductor substrate 105. As an example, the through spacer TS may conformally cover the entire top surface of the semiconductor substrate 105. The through spacer TS may cover the top surface of the device isolation layer ST exposed by the inner bottom surface of the through hole TH.

[0116] In some implementations, an auxiliary deposition layer AD may be formed on the top surface of the third interlayer insulating layer 130 to cover the through spacers TS (eg, see Fig.16 ). The auxiliary deposition layer AD may not be formed on the inner bottom surface of the through hole TH. The through spacer TS may have a first thickness T1 (eg, see Fig.15 The sum of the thicknesses of the through spacer TS and the auxiliary deposition layer AD on the third interlayer insulating layer 130 may be a second thickness T2 (eg, see Fig.16 ). The second thickness T2 may be greater than the first thickness T1. In some implementations, the auxiliary deposition layer AD may be formed by a physical vapor deposition (PVD) process. Due to the poor step coverage characteristics of the PVD process, the auxiliary deposition layer AD may not be deposited on the inner bottom surface of the penetration hole TH. The auxiliary deposition layer AD may be formed of or include the same material as the penetration spacer TS.

[0117] Reference Fig.17 and Fig.18 , the penetration spacer TS may be removed from the inner bottom surface of the penetration hole TH. Therefore, the top surface of the device isolation layer ST may be reopened through the inner bottom surface of the penetration hole TH. The removal process may be performed by an anisotropic etching process on the penetration spacer TS, and thus the penetration spacer TS may remain on the inner side surface of the penetration hole TH. The auxiliary deposition layer AD may protect the penetration spacer TS on the third interlayer insulating layer 130, and thus the penetration spacer TS may remain on the third interlayer insulating layer 130 even after the etching process.

[0118] The inhibitor IN may be formed to cover the penetration spacer TS. The inhibitor IN may be selectively deposited on the surface of the penetration spacer TS. In other words, the inhibitor IN may not be formed on the inner bottom surface of the penetration hole TH. Therefore, even after the inhibitor IN is formed, the top surface of the device isolation layer ST may still be exposed through the inner bottom surface of the penetration hole TH. The inhibitor IN may be formed on the inner side surface of the penetration hole TH and the top surface of the third interlayer insulating layer 130.

[0119] Reference Fig.19 and Fig. 20, a seed layer SL may be formed on the inner bottom surface of the penetration hole TH. The seed layer SL may be selectively deposited on the exposed top surface of the device isolation layer ST. More specifically, the seed layer SL may not be directly formed on the surface of the inhibitor during the process of forming the seed layer SL. The inhibitor IN may prevent or inhibit the seed layer SL from being formed on the penetration spacer TS, and the seed layer SL may not be deposited on the inner side surface of the penetration hole TH and the top surface of the third interlayer insulating layer 130. The seed layer SL may fill the lower portion of the penetration hole TH and cover the exposed top surface of the device isolation layer ST. Although the seed layer SL is not directly formed on the surface of the inhibitor IN, the seed layer SL may be in contact with the lower portion of the inhibitor IN because the seed layer SL is formed on the device isolation layer ST in the lower portion of the penetration hole TH. The lower portion of the inhibitor IN may surround the seed layer SL. In some implementations, the seed layer SL may be formed by an atomic layer deposition (ALD) process. The process of forming the seed layer SL may be formed at a first temperature.

[0120] Next, a removal process may be performed on the inhibitor IN. The inhibitor may be removed by an annealing process. The annealing process may be performed at a second temperature. The second temperature may be higher than the first temperature at which the seed layer SL is formed. Therefore, during the formation of the seed layer SL (ie, at the first temperature), the inhibitor IN may not be removed.

[0121] A removal process may be performed to remove the upper portion of the inhibitor IN, and the lower portion of the inhibitor IN may remain between the seed layer SL and the penetration spacer TS. The lower portion of the inhibitor IN may remain on the side surface of the seed layer SL and may surround the seed layer SL. Since the upper portion of the inhibitor IN is removed, the penetration spacer TS may be exposed to the outside.

[0122] Reference Figures 3 to 8 , the main layer ML may be formed to fill the upper portion of the through hole TH. The main layer ML may be formed by a selective growth process using the seed layer SL as a seed. Therefore, in the through hole TH, the main layer ML may gradually grow from the seed layer SL toward the top of the through hole TH (ie, in a bottom-up growth manner).

[0123] In the growth process, the penetration spacer TS may not be used as a seed crystal. Therefore, unlike a conformal deposition process in which deposition is performed on the side surface of the penetration hole TH, the main layer ML may be formed without a seam therein, and in some implementations, the main layer ML may be formed of a single grain or several grains. In this case, the penetration conductive pattern TC may have a reduced resistance, which allows the electrical characteristics of the three-dimensional semiconductor device to be improved, and further, the occurrence of failures due to seams in subsequent processes may be reduced.

[0124] In addition, the bottom-up growth process can reduce the processing time compared to the conformal deposition process. As a result, the productivity in the process of manufacturing three-dimensional semiconductor devices can be improved.

[0125] The upper active contact UAC may be formed to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130, and may be connected to the upper source / drain pattern USD, respectively. The upper gate contact UGC may be formed to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130, and may be connected to the gate electrode GE. The upper active contact UAC and the upper gate contact UGC may be formed during the process of forming the penetration conductive pattern TC or by another process different from the process of forming the penetration conductive pattern TC. The penetration spacer TS may be removed from the top surface of the third interlayer insulating layer 130, and may remain on the inner side surface of the penetration hole TH.

[0126] A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A first metal layer M1 including an upper interconnect line UMI may be formed in the fourth interlayer insulating layer 140. An upper via UVI may be formed to electrically connect the first metal layer M1 to an upper gate contact UGC and an upper active contact UAC. A BEOL layer including additional metal layers (e.g., M2, M3, M4, etc.) may be formed on the first metal layer M1.

[0127] Thereafter, the semiconductor substrate 105 may be turned upside down so that the rear surface of the semiconductor substrate 105 is exposed to the outside. The exposed semiconductor substrate 105 may be selectively removed. Thus, the sacrificial contact pattern PLH and the first lower insulating layer LIL1 may be exposed.

[0128] A second lower insulating layer LIL2 may be formed on the exposed sacrificial contact pattern PLH and the exposed first lower insulating layer LIL1. For example, the second lower insulating layer LIL2 may be formed of or include at least one of silicon-based insulating materials (e.g., silicon oxide, silicon oxynitride, or silicon nitride). In some implementations, the second lower insulating layer LIL2 may be formed of or include the same material as the device isolation layer ST.

[0129] The first lower insulating layer LIL1 and the second lower insulating layer LIL2 may constitute a substrate 100. The substrate 100 may include a first surface 100A and a second surface 100B. A planarization process may be performed on the second surface 100B of the substrate 100 to expose top surfaces of the sacrificial contact patterns PLH.

[0130] The sacrificial contact pattern PLH may be replaced by the lower active contact LAC. In detail, the sacrificial contact pattern PLH may be selectively removed. An etching process may be further performed on the area formed by removing the sacrificial contact pattern PLH to expose the lower source / drain pattern LSD. The lower active contact LAC may be formed to be connected to the exposed lower source / drain pattern LSD. The lower active contact LAC may be formed in a self-aligned manner using the sacrificial contact pattern PLH.

[0131] The lower gate contact LGC may be formed to penetrate the substrate 100 and may be coupled to the gate electrode GE. Figures 5 to 8 The lower contact pattern LCP of the substrate 100 may be further formed by a process of forming the lower gate contact LGC or by an additional process. The formation of the lower contact pattern LCP may include etching a portion of the substrate 100 vertically overlapping the penetration conductive pattern TC and filling the etched area with the lower contact pattern LCP. Here, depending on the alignment and depth of the etched area, Figures 5 to 8 The lower contact pattern LCP may be formed in various shapes.

[0132] A lower interlayer insulating layer 210 may be formed on the second surface 100B of the substrate 100. A back metal layer BSM may be formed in the lower interlayer insulating layer 210. The back metal layer BSM may include a lower interconnect line LMI. In addition, a lower via LVI may be formed to electrically connect the back metal layer BSM to the lower active contact LAC and the lower gate contact LGC. In some implementations, the lower via LVI may be formed to connect the lower active contact LAC to the lower interconnect line LMI. A lower metal layer may be additionally formed on the back metal layer BSM. In some implementations, the lower metal layer may include a power delivery network.

[0133] Figure 21 to Figure 25 is a diagram showing another example of a method for manufacturing a three-dimensional semiconductor device. More specifically, Fig.21 and Fig.24 is along Figure 3 A cross-sectional view taken along line BB'. Fig. 22 and Fig.25 is corresponding to Fig.21 and Fig.24 An enlarged cross-sectional view of portion P2. Fig.23 is corresponding to Fig.21 An enlarged view of part P4.

[0134] In the following, reference will be made to Figure 21 to Figure 25 Describe the manufacturing in more detail Fig. 9 For the sake of brevity of description, previously described elements may be identified with the same reference numerals without repeating their overlapping descriptions.

[0135] Reference Figure 21 to Figure 23 ,and FIG. 14A to FIG. 14C In a different implementation method, the inhibitor IN may be formed after forming the through hole TH without forming the through spacer TS. In the case where the inhibitor IN is formed by a method having a poor step coverage characteristic, the inhibitor IN may not be substantially formed on the lower portion of the through hole TH. As an example, the inhibitor IN may be formed on the inner side surface of the through hole TH and the top surface of the third interlayer insulating layer 130, but may not be formed on the inner bottom surface of the through hole TH. Therefore, after the inhibitor IN is formed, the top surface of the device isolation layer ST may be exposed through the inner bottom surface of the through hole TH.

[0136] The inhibitor IN may have a third thickness T3 at the bottommost of the inner side surface of the through hole TH and may have a fourth thickness T4 on the top surface of the third interlayer insulating layer 130. The fourth thickness T4 may be greater than the third thickness T3 due to the step coverage property of the inhibitor IN.

[0137] Next, a seed layer SL may be formed on the inner bottom surface of the through hole TH. The seed layer SL may be selectively deposited on the exposed top surface of the device isolation layer ST. The seed layer SL may not be deposited on the inner side surface of the through hole TH and the top surface of the third interlayer insulating layer 130.

[0138] Reference Fig.24 and Fig.25 , a removal process may be performed on the inhibitor IN. The removal process may be performed to remove an upper portion of the inhibitor IN, and a lower portion of the inhibitor IN may remain between the seed layer SL and the first interlayer insulating layer 110 .

[0139] Thereafter, the above method can be used to produce Fig. 9 three-dimensional semiconductor devices.

[0140] In some implementations, the penetrating conductive pattern can be formed as a seamless structure and can be formed by a single grain or a plurality of grains. Therefore, the resistance of the penetrating conductive pattern can be reduced, which can improve the electrical characteristics of the three-dimensional semiconductor device. In addition, failures that may occur in subsequent processes due to the seams can be reduced.

[0141] In addition, the penetrating conductive pattern can be formed by a bottom-up growth process, which can shorten the processing time compared to a conformal deposition process. As a result, the productivity in the process of manufacturing a three-dimensional semiconductor device can be improved.

[0142] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what may be claimed, but rather, should be interpreted as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in the following circumstances, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0143] While example implementations of the concepts described herein have been particularly shown and described, those skilled in the art will understand that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0144] This application claims the priority of Korean Patent Application No. 10-2023-0091587 filed in the Korean Intellectual Property Office on July 14, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor device, comprising: Back metal layer; a lower active region on the back metal layer, the lower active region comprising a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region comprising an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; an interlayer insulating layer, surrounding the lower source / drain pattern and the upper source / drain pattern; A penetrating conductive pattern extending through the interlayer insulating layer in a vertical direction; as well as An inhibitor covers a side surface of a lower portion of the penetrating conductive pattern, wherein the inhibitor includes carbon atoms. 2 . The three-dimensional semiconductor device according to claim 1 , wherein a bottom surface of the inhibitor is coplanar with a bottom surface of the penetrating conductive pattern.

3. The three-dimensional semiconductor device according to claim 1, comprising a device isolation layer between the back metal layer and the penetrating conductive pattern, The penetrating conductive pattern is in contact with the device isolation layer.

4. The three-dimensional semiconductor device according to claim 1, comprising a lower contact pattern between the back metal layer and the penetrating conductive pattern, The penetrating conductive pattern contacts the lower contact pattern. 5 . The three-dimensional semiconductor device according to claim 1 , comprising a through spacer extending between the through conductive pattern and the interlayer insulating layer. 6 . The three-dimensional semiconductor device according to claim 5 , wherein the through spacer separates the through conductive pattern from the interlayer insulating layer. 7 . The three-dimensional semiconductor device according to claim 5 , wherein the inhibitor is disposed between the lower portion of the penetrating conductive pattern and the penetrating spacer. 8 . The three-dimensional semiconductor device according to claim 1 , wherein the penetrating conductive pattern comprises at least one of Mo, Ru, Cu, Al, or W. 9 . The three-dimensional semiconductor device according to claim 1 , wherein a side surface of the penetrating conductive pattern is in contact with the interlayer insulating layer. 10 . The three-dimensional semiconductor device according to claim 1 , wherein a side surface of the inhibitor is in contact with the interlayer insulating layer.

11. A three-dimensional semiconductor device, comprising: Back metal layer; a lower active region on the back metal layer, the lower active region comprising a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region comprising an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; an interlayer insulating layer surrounding the lower source / drain pattern and the upper source / drain pattern; as well as A penetrating conductive pattern extending through the interlayer insulating layer in a vertical direction, The penetrating conductive pattern includes a seed layer and a main layer, the main layer is on the seed layer, and The width of the bottom surface of the main layer is greater than the width of the top surface of the seed layer. 12 . The three-dimensional semiconductor device according to claim 11 , wherein the seed layer and the main layer comprise different metal materials. 13 . The three-dimensional semiconductor device according to claim 11 , wherein the seed layer and the main layer comprise a same metal material.

14. The three-dimensional semiconductor device according to claim 11, comprising a device isolation layer between the back metal layer and the penetrating conductive pattern, The seed layer is in contact with the device isolation layer.

15. The three-dimensional semiconductor device according to claim 11, comprising a penetration spacer on a side surface of the penetration conductive pattern, The penetrating spacer is spaced apart from a side surface of the seed layer and is in contact with a side surface of the main layer.

16. The three-dimensional semiconductor device according to claim 11, comprising an inhibitor covering a side surface of the seed layer, The side surface of the inhibitor is aligned with the side surface of the main layer.

17. A three-dimensional semiconductor device, comprising: Metal layer; an interlayer insulating layer on the metal layer; A penetrating conductive pattern extending through the interlayer insulating layer in a vertical direction, wherein the penetrating conductive pattern comprises a seed layer and a main layer, wherein the main layer is on the seed layer; as well as an inhibitor covering a side surface of the seed layer, wherein the penetrating conductive pattern is electrically connected to the metal layer, and The side surface of the inhibitor is aligned with the side surface of the main layer. The three-dimensional semiconductor device according to claim 17 , wherein the inhibitor comprises carbon atoms. 19 . The three-dimensional semiconductor device according to claim 17 , wherein a width of a bottom surface of the main layer is greater than a width of a top surface of the seed layer.

20. The three-dimensional semiconductor device according to claim 17, comprising a device isolation layer between the metal layer and the penetrating conductive pattern, The seed layer is in contact with the device isolation layer.

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