Semiconductor device and forming method thereof

Abstract

Various embodiments of the present disclosure relate to a phase change material (PCM) radio frequency (RF) switch having a PCM recess. The PCM structure overlies the heater, and the first electrode and the second electrode are located on opposite sides of the PCM structure, respectively, and are electrically coupled thereto. The PCM recess is located at the top of the PCM structure and overlies the heater over an active portion of the PCM structure. Further, the width of the PCM recess is the same or substantially the same as the active portion. The active portion is configured to vary between a crystalline phase and an amorphous phase while the remainder of the PCM structure (e.g., the passive portion) is in the crystalline phase. Because the PCM is recessed, the thickness of the PCM structure in the active portion is smaller than the thickness of the PCM structure in the passive portion. The embodiment of the invention also provides a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Radio frequency (RF) switches are devices used to route high-frequency signals and are often used in wireless communication systems. For example, RF switches can be found in mobile phones, WiFi routers, etc. RF switches typically have higher power handling capabilities, better linearity, and a wider operating frequency band than complementary metal oxide semiconductor (CMOS) switches. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a heater located above a substrate; a phase change material (PCM) structure located above the heater; and a first electrode and a second electrode, respectively located on opposite sides of the heater and electrically coupled to the PCM structure on the opposite sides; wherein the top of the PCM structure has a recess, the recess overlies the heater and has a width smaller than the width of the heater.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a heater located above a substrate; a phase change material (PCM) structure overlying the heater; and a first electrode and a second electrode, respectively located on opposite sides of the heater and electrically coupled to the PCM structure on the opposite sides; wherein the PCM structure has a first thickness overlying the heater, and also has a second thickness laterally offset from the heater, and wherein the first thickness is different from the second thickness.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a heater above a substrate; forming a pair of electrodes on opposite sides of the heater; depositing a passivation layer overlying the heater; forming a phase change material (PCM) structure overlying the passivation layer and the heater; and etching the PCM structure to form a recess overlying the heater. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of a phase change material (PCM) radio frequency (RF) switch having a PCM recess are shown.

[0008] Figure 2 Shows Figure 1Magnified cross-sectional views of some more detailed embodiments of PCM RF switches.

[0009] Figure 3 Shows Figure 2 Top layout diagram of some embodiments of PCM RF switches.

[0010] Figure 4 Shows Figure 3 The dimensions of the PCM RF switch are shown in the top layout diagram for some alternative embodiments of the variations.

[0011] Figure 5A-5F Shows Figure 2 Cross-sectional views of some alternative embodiments of PCM RF switches.

[0012] Figure 6 Shown include Figure 2 Cross-sectional views of some embodiments of integrated chips of PCM RF switches.

[0013] Figure 7 Shows Figure 6 Cross-sectional views of some alternative embodiments of integrated chips.

[0014] Figure 8-Figure 21 A series of cross-sectional views illustrating some embodiments of methods of forming a PCM RF switch having a PCM recess.

[0015] Fig. 22 Shows Figure 8-Figure 21 A block diagram of some embodiments of the method.

[0016] Figure 23-Figure 27 Shows Figure 8-Figure 21 A series of cross-sectional views of some first alternative embodiments of the method.

[0017] Figure 28-Figure 42 Shows Figure 8-Figure 21 A series of cross-sectional views of some second alternative embodiments of the method.

[0018] Fig.43 Shows Figure 28-Figure 42 A block diagram of some embodiments of the method.

[0019] Figure 44-Figure 47 A series of cross-sectional views illustrating some embodiments of a method of forming an integrated chip including a PCM RF switch having a PCM recess. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] A radio frequency (RF) switch is a phase change material (PCM) RF switch, which includes a heater, a PCM structure, and a pair of electrodes. The electrodes are adjacent to the PCM structure at opposite sides of the PCM structure. The PCM structure overlies the heater and has a uniform thickness. In addition, the PCM structure has a pair of active parts and passive parts, and the active part is arranged between the pair of active parts and passive parts.

[0023] The passive portion is in a crystalline phase and extends from the active portion to the electrodes, respectively. Because the passive portion is in a crystalline phase, the passive portion has a low resistance. The active portion overlies the heater and is configured to selectively change between a crystalline phase and an amorphous phase by selective heating of the heater. When in the amorphous phase, the active portion is in a high resistance state (HRS) that electrically isolates the electrodes from each other. When in the crystalline phase, the active portion is in a low resistance state (LRS) that electrically couples the electrodes together. The HRS may correspond to the OFF state of the PCM RF switch, and the LRS may correspond to the ON state of the PCM RF switch.

[0024] The performance of a PCM RF switch can be evaluated based on on-resistance and heat resistance. The lower the on-resistance, the lower the insertion loss. Increasing the thickness of the PCM structure reduces the on-resistance. However, increasing the thickness of the PCM structure also causes voids in the PCM structure due to thermal stress when cycling the PCM RF switch. These voids are mainly formed at the active portion where the thermal stress is highest and reduce the heat resistance of the PCM RF switch. Therefore, there is a trade-off between on-resistance and heat resistance.

[0025] The present invention relates to a PCM RF switch with a PCM recess. The PCM recess is located on top of a PCM structure and overlies a heater at an active portion of the PCM structure. Due to the PCM recess, the thickness of the PCM RF structure may be smaller at the active portion. The small thickness prevents the formation of voids in the active portion under the thermal stress generated by the PCM RF switch cycle. This makes the PCM RF switch highly heat resistant. Note that voids are mainly formed in the active portion where the thermal stress is highest, so voids are not a problem in the passive portion. In addition, due to the PCM recess, the thickness of the PCM RF structure may be larger in the passive portion. The large thickness reduces the resistance of the passive portion, resulting in low on-resistance and low insertion loss. Therefore, the PCM recess allows the PCM RF switch to obtain the advantages of small PCM thickness and large PCM thickness.

[0026] refer to Figure 1 , a cross-sectional view 100 of some embodiments of a PCM RF switch 102 having a PCM recess 104 is provided. The PCM RF switch 102 may also be referred to as a semiconductor device, a PCM device, etc. The PCM recess 104 is located on top of a PCM structure 106 and overlies a heater 108 at an active portion 106a of the PCM structure 106. The width W of the PCM recess 104 is r Smaller than the width W of the heater 108 h .

[0027] The width W of the active portion 106a is a Smaller than the width W of the heater 108 h , and the active portion 106a is configured to selectively change between the amorphous phase and the crystalline phase by selective heating of the heater 108. For example, the active portion 106b may be set to the amorphous phase by heating the active portion 106a to a temperature exceeding the melting temperature for a first time period and quenching (e.g., rapidly cooling) the active portion 106a. As another example, the active portion 106b may be set to the crystalline phase by heating the active portion 106a to a temperature above the crystallization temperature and below the melting temperature for a second time period longer than the first time period.

[0028] When in the amorphous phase, the active portion 106a is in HRS. When in the crystalline phase, the passive portion 106a is in LRS. HRS may correspond to the OFF state of the PCM RF switch 102, while LRS may correspond to the ON state of the PCM RF switch 102. The active portion 106a will be contrasted with the rest of the PCM structure 106, which corresponds to the pair of passive portions 106ia.

[0029] The pair of passive portions 106ia are located at opposite sides of the active portion 106a, respectively, and extend from the active portion 106a to the first electrode 110a and the second electrode 110b, respectively. As a result, the passive portion 106ia separates the first and second electrodes 110a, 110b from the active portion 106a. In addition, the passive portion 106ia is in a crystalline phase and remains in the crystalline phase during the cycle (e.g., ON / OFF cycle) of the PCM RF switch 102. Because the passive portion 106ia is in a crystalline phase, the passive portion 106ia has a low resistance and provides a low resistance electrical path from the active portion 106a to the first and second electrodes 110a, 110b, respectively.

[0030] Due to the PCM recess 104, the active thickness T at the active portion 106a a and the passive thickness T at the passive portion 106ia ia Specifically, the active and passive thicknesses T a , T ia Relatively small and large.

[0031] The small thickness T at the active portion 106a a Preventing voids from forming at the active portion 106a under thermal stress of the PCM RF switch 102 cycle. a can result in faster heat dissipation, which reduces thermal stress and reduces voiding. By preventing voiding, a small thickness T a This results in high heat resistance of the PCM RF switch 102. Note that voids are mainly formed at the active portion 106a where the thermal stress is highest, while voids are not a problem at the passive portion 106ia. The large thickness T at the passive portion 106ia ia The PCM recess 104 results in a low resistance at the passive portion 106ia. The low resistance results in a low on-resistance of the PCM RF switch 102. Therefore, the PCM recess 104 allows the PCM RF switch 102 to have a small thickness (eg, T a ) and large thickness (such as T ia ) benefits.

[0032] With the active thickness T a With passive thickness T ia The ratio (e.g. T a / T ia ), the on-resistance of the PCM RF switch 102 decreases. For example, a ratio of 1 may produce an on-resistance of X, a ratio of 0.77 may produce an on-resistance of 0.84*X, and a ratio of 0.67 may produce an off-resistance of 0.77*X. In some embodiments, the ratio is greater than or equal to 0.5 and less than 1. If the ratio is outside this range, the on-resistance of the PCM RF switch 102 may be high, for example, and / or the heat resistance of the PCM RF switch 102 may be low, for example.

[0033] Continue to refer Figure 1 , each passive portion 106ia can be divided into a portion A and a portion B. The portion A is laterally offset from the heater 108 at the periphery of the PCM structure 106. Therefore, the portion A is away from the heater 108 and is not heated by the heater 108 or is minimally heated by the heater 108 during the cycle of the PCM RF switch 102. Therefore, the portion A does not undergo a phase change during the cycle. The portion B overlies the heater 108 and separates the portion A from the active portion 106a. Similar to the active portion 106a, during the cycle of the PCM RF switch 102, the portion B is heated by the heater 108 and may exceed the melting temperature when the PCM RF switch 102 is set to the amorphous phase. However, due to the increased thickness of the portion B, the heat dissipation of the portion B may be poor. Therefore, the portion B may not undergo quenching and may return to the crystalline phase. Therefore, the portion B also does not undergo a phase change during the cycle.

[0034] The first and second electrodes 110a, 110b are flush with the heater 108 and are laterally separated from the heater 108 by the first dielectric layer 112a and the spacing S. In some embodiments, the spacing S is 0.15 microns or some other suitable value or value range. In addition, the first electrode 110a and the second electrode 110b are respectively located below the PCM structure 106 on opposite sides of the PCM structure 106 and directly contact the PCM structure 106.

[0035] The passivation layer 114 overlies the heater 108 and the first dielectric layer 112a to separate the heater 108 from the PCM structure 106. In addition, the passivation layer 114 is recessed into the bottom of the PCM structure 106 so that the passivation layer 114 and the PCM structure 106 have corresponding bottom surfaces flush with each other.

[0036] During use of the PCM RF switch 102, the first and second electrodes 110a, 110b function as RF transmission lines or are otherwise electrically coupled to an RF transmission line. A signal is input into the first electrode 110a and selectively transmitted to the second electrode 110b according to the ON / OFF state of the PCM RF switch 102. In addition, the heater 108 is controlled to change the PCM RF switch 102 between an ON state and an OFF state. Compared to a complementary metal oxide semiconductor (CMOS) switch, the PCM RF switch 102 has higher power handling capability, better linearity, and a wider operating frequency band.

[0037] In some embodiments, when the PCM RF switch 102 is in the ON state, the PCM structure 106 is fully crystalline. In addition, in some embodiments, when the PCM RF switch 102 is in the OFF state, the active portion 106a (bounded by the dashed line) is fully amorphous and the rest of the PCM structure 106 is fully crystalline.

[0038] In some embodiments, the first and second electrodes 110a, 110b are or include tungsten and / or some other suitable material with low electrical resistance and high heat resistance. In some embodiments, the heater 108 is or includes tungsten and / or some other suitable material with low electrical resistance and high heat resistance. In some embodiments, the PCM structure 106 is or includes germanium telluride and / or some other suitable phase change material. In some embodiments, the first dielectric layer 112a is or includes silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In some embodiments, the passivation layer 114 is or includes silicon nitride and / or some other suitable dielectric.

[0039] In some embodiments, the active thickness T a is about 500-1000 angstroms, about 500-750 angstroms, about 750-1000 angstroms, or some other suitable value or range of values. a If the active thickness T is too large (e.g., greater than 1000 angstroms), voids may be formed at the active portion 106a under thermal stress generated by cycling of the PCM RF switch 102. Therefore, the thermal resistance of the PCM RF switch 102 may be low. a Too small (eg, less than 500 angstroms), the maximum current of the PCM RF switch 102 may be low and / or the on-resistance of the PCM RF switch 102 may be high.

[0040] In some embodiments, the passive thickness T ia is about 750-1500 angstroms, about 750-1125 angstroms, about 1125-1500 angstroms, or some other suitable value or range of values. iaIf the passive thickness T is too small (eg, less than 750 angstroms), the maximum current of the PCM RF switch 102 may be low and / or the on-resistance of the PCM RF switch may be high. ia If the height of the PCM RF switch 102 is too large (e.g., greater than 1500), the height of the PCM RF switch 102 may be high and may cause a large amount of topographic variation at the PCM RF switch 102. Such topographic variation may destroy the uniformity of the semiconductor process and may cause a low manufacturing yield of the PCM RF switch 102.

[0041] In some embodiments, the width W of the PCM recess 104 is r is or includes 0.4 micrometers, 0.35-0.45 micrometers, or some other suitable value or value range. In addition, in some embodiments, the width W of the active portion 106a is a is or includes 0.4 micrometers, 0.35-0.45 micrometers, or some other suitable value or value range. In some embodiments, the width W of the PCM recess 104 is r and the width W of the active portion 106a a In other embodiments, the width W of the PCM recess 104 is r Greater than the width W of the active portion 106a a .

[0042] In some embodiments, the width W of the active portion 106a is a The width W of the PCM recess 104 r The ratio (e.g. W a / W r ) is greater than or equal to 0.9 and less than or equal to 1. If the ratio is too small (e.g., less than 0.9), the PCM recess 104 may extend largely into the inactive portion 106ia and may severely reduce the on-resistance. If the ratio is too large (e.g., greater than 1), the PCM recess 104 may not cover a large amount of the active portion 106a. Therefore, voids may be formed and heat resistance may be severely reduced.

[0043] In some embodiments, the width W of the heater 108 is h is or includes 1 micron, 0.875-1.125 microns, or some other suitable value or value range. In some embodiments, the width W of the active portion 106a is a The width W of the heater 108 h The ratio (e.g. W a / W h ) is approximately 0.4 and / or some other suitable value.

[0044] refer to Figure 2 , provides Figure 1FIG. 2 is an enlarged cross-sectional view 200 of some more detailed embodiments of the PCM RF switch 102 .

[0045] The hard mask 202 overlies the PCM structure 106 outside the PCM recess 104, and the PCM recess 104 extends through the hard mask 202. In addition, the hard mask 202 includes a first hard mask layer 202a and a second hard mask layer 202b overlying the first hard mask layer 202a. In alternative embodiments, the first hard mask layer 202a or the second hard mask layer 202b is omitted. The first hard mask layer 202a may be, for example, or include silicon nitride and / or some other suitable dielectric, and the second hard mask layer 202b may be, for example, or include silicon oxide and / or some other suitable dielectric, or vice versa.

[0046] The first capping layer 204 overlies the hard mask 202 outside the PCM recess 104, and the PCM recess 104 extends through the first capping layer 204. In addition, the first capping layer 204 extends to the first and second electrodes 110a, 110b along the pair of first common sidewalls, which are formed by the PCM structure 106 and the hard mask 202 and are respectively facing away from each other on opposite sides of the PCM structure 106. The first capping layer 204 can be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the first capping layer 204 is the same material as the first hard mask layer 202a.

[0047] The second capping layer 206 overlies the first capping layer 204 and lines the first capping layer 204, and further lines the PCM recess 104. In addition, the first capping layer 204, the hard mask 202, and the PCM structure 106 form a pair of second common sidewalls, which are opposite to each other in the PCM recess 104 and lined by the second capping layer 206. The second capping layer 206 can be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the second capping layer 206 is the same material as the first hard mask layer 202a and / or the first capping layer 204.

[0048] The passivation layer 114 includes three segments that are laterally spaced apart from each other, respectively overlying the heater 108 and the first and second electrodes 110a, 110b. In addition, these segments are located below the first and second cap layers 204, 206. The passivation layer 114 can be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the passivation layer 114 is the same material as at least one or more of the first hard mask layer 202a, the first cap layer 204, or the second cap layer 206.

[0049] The first dielectric layer 112a extends below the first and second electrodes 110a, 110b and the heater 108. Thus, the first dielectric layer 112a separates the first and second electrodes 110a, 110b and the heater 108 from the first etch stop layer 208a, which is located below the first dielectric layer 112a. In an alternative embodiment, the first etch stop layer 208a is omitted. The first etch stop layer 208a is a different dielectric material than the first dielectric layer 112a, and may be, for example, or include silicon carbide and / or some other suitable dielectric.

[0050] The second dielectric layer 112b overlies the PCM RF switch 102. The second dielectric layer 112b may be or include, for example, silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In some embodiments, the second dielectric layer 112b is the same dielectric material as the first dielectric layer 112a.

[0051] The first through hole 210a and the second through hole 210b are respectively located on opposite sides of the PCM RF switch 102. In addition, the first through hole 210a and the second through hole 210b respectively overlie the first electrode 110a and the second electrode 110b and extend from the first electrode 110a and the second electrode 110b to the top of the second dielectric layer 112b. The first through hole 210a and the second through hole 210b can be, for example, or include aluminum, copper, aluminum copper, some other suitable metal, or any combination of the above metals.

[0052] refer to Figure 3 , provides Figure 2 The top layout diagram 300 of some embodiments of the PCM RF switch 102. For example, Figure 2 The cross-sectional view 200 may be along Figure 3 Furthermore, the PCM structure 106 and the PCM recess 104 are shown in dashed lines, and the PCM recess 94 extends the entire length of the PCM structure 106 .

[0053] The heater 108 includes a pair of a central portion 108c and a pad portion 108p. The central portion 108c has a columnar shape that is elongated between the pad portions 108p in a first dimension, and the PCM recess 104 and the PCM structure 106 are also elongated along the first dimension. In addition, the central portion 108c is laterally located between the first and second electrodes 110a, 110b and adjacent to the first and second electrodes 110a, 110b in a second dimension orthogonal to the first dimension. The pad portions 108p are respectively located at opposite ends of the central portion 108c and have a rectangular shape. In some embodiments, the heater 108 has an I-shape. In alternative embodiments, at least one or more of the central portion 108c or the pad portions 108p have some other suitable shapes.

[0054] refer to Figure 4 , provides Figure 3 A top layout diagram 400 of some alternative embodiments of dimensional variations of the PCM RF switch 102 is shown.

[0055] refer to Figure 5A-5F , provides Figure 2 Cross-sectional views 500A-500F of some alternative embodiments of the PCM RF switch 102 are shown.

[0056] exist Figure 5A In the embodiment, the bottom surface 104bs of the PCM recess 104 has a concave profile such that the edge of the bottom surface 104bs is farther from the heater 108 than the lateral center of the bottom surface 104bs. In alternative embodiments, the bottom surface 104bs has a convex profile or some other suitable profile.

[0057] exist Figure 5B In the embodiment, the hard mask 202 extends along the outer sidewalls of the PCM structure 106 and overlies the portion of the passivation layer 114 overlying the first and second electrodes 110a, 110b. In addition, the first cap layer 204 is omitted, and the second cap layer 206 lines the hard mask 202 laterally beyond the PCM structure 106.

[0058] exist Figure 5C , the hard mask 202 and the first capping layer 204 are omitted.

[0059] exist Figure 5D In the embodiment, the hard mask 202 and the first cap layer 204 are omitted, and the passivation layer 114 is continuous. In addition, the first and second electrodes 110a, 110b overlie the passivation layer 114 and the PCM structure 106 and extend along the outer sidewall of the PCM structure 106. This can reduce the height of the first through hole 210a and the second through hole 210b, which can shorten the connection distance to the first electrode 110a and the second electrode 110b. The reduced connection distance can reduce the on-resistance of the PCM RF switch 102.

[0060] exist Figure 5E In the embodiment, the hard mask 202 is omitted and the passivation layer 114 is continuous. In addition, the planarization dielectric layer 502 fills the PCM recess 104 on the second cap layer 206 and further overlies the first and second cap layers 204, 206 that are laterally offset from the PCM structure 106. As shown below, in forming Figure 5E The planarization dielectric layer 502 can assist in the planarization process when the PCM RF switch 102 is constructed. The first and second cap layers 204, 206, the PCM structure 106, and the planarization dielectric layer 502 have corresponding top surfaces that are flush with each other and together form a planar surface.

[0061] The first and second electrodes 110a, 110b, the third capping layer 504 and the second dielectric layer 112b overlie the flat surface. The first electrode 110a and the second electrode 110b have planar profiles overlying the PCM structure 106 on opposite sides of the PCM structure 106, respectively. The third capping layer 504 overlies the first and second electrodes 110a, 110b and pads the first and second electrodes 110a, 110b, and the second dielectric layer 112b overlies the third capping layer 504.

[0062] like Figure 5D As shown, placing the first and second electrodes 110a, 110b above the PCM structure 106 can reduce the height of the first and second vias 210a, 210b. This in turn can shorten the connection distance to the first and second electrodes 110a, 110b, which can reduce the on-resistance of the PCM RF switch 102.

[0063] In some embodiments, the planarization dielectric layer 502 is or includes silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In some embodiments, the planarization dielectric layer 502 is the same material as the first dielectric layer 112a and / or the same material as the second dielectric layer 112b. In some embodiments, the third cap layer 504 is or includes silicon nitride and / or some other suitable dielectric. In some embodiments, the third cap layer 504 is the same material as one or more of the first cap layer 204, the second cap layer 206, or the passivation layer 114.

[0064] exist Figure 5E In the PCM RF switch 102 and Figure 5E However, the spacing between the first electrode 110a and the second electrode 110b has been increased.

[0065] refer to Figure 6 , provides Figure 2 A cross-sectional view 600 of some embodiments of an integrated chip of a PCM RF switch 102 is shown. In an alternative embodiment, the PCM RF switch 102 is as shown in FIG. Figure 5A-5F Any one of the following is shown.

[0066] The interconnect structure 602 overlies the semiconductor substrate 604 and includes a plurality of wirings 606 and a plurality of vias 210. The plurality of wirings 606 are divided into a plurality of wiring levels, and the plurality of vias 210 are divided into a plurality of via levels alternately stacked with the plurality of wiring levels.

[0067] From the bottom to the top of the interconnect structure 602, the wiring levels are labeled M1, M2, etc. to M9. In addition, the wiring 606 at the wiring levels M8 and M9 have a greater height than their counterparts at the lower wiring levels. From the bottom to the top of the interconnect structure 602, the via levels are labeled V0, V1, etc. to V8. In addition, the vias 210 at the via levels V0, V7, and V8 have a greater height than their counterparts at the other via levels.

[0068] In alternative embodiments, the interconnect structure 602 has more or fewer wiring levels and / or more or fewer via levels. In addition, in alternative embodiments, the interconnect structure 602 also includes a middle end process (MEOL) located below the via level V0. The MEOL includes a pair of contact levels, which may also be referred to as CA and CB.

[0069] The dielectric structure surrounds the interconnect structure 602 and includes a plurality of interconnect dielectric layers 112 and a plurality of etch stop layers 208. The interconnect dielectric layers 112 and etch stop layers 208 are alternately stacked from the bottom of the interconnect structure 602 to the top of the interconnect structure 602. The etch stop layers 208 enhance the control of etching to form various wiring and via levels.

[0070] In some embodiments, etch stop layer 208 is or includes silicon carbide and / or some other suitable dielectric. In some embodiments, multiple interconnect dielectric layers 112 are or include undoped silicate glass (USG), borosilicate glass (BSG), silicon oxide, some other suitable dielectric, or any combination thereof.

[0071] The PCM RF switch 102 is located in the interconnect structure 602, vertically between the wiring level M7 and the wiring level M8. In an alternative embodiment, the PCM RF switch 102 is vertically located between two other vertically adjacent wiring levels in the interconnect structure 602. The interconnect structure 602 is electrically coupled to the PCM RF switch 102 to facilitate the electrical routing of the RF signal to and from the first and second electrodes 110a, 110b, respectively, and further facilitate the control of the heater 108.

[0072] As described above, the PCM RF switch 102 is Figure 2 In an alternative embodiment, the PCM RF switch 102 is as shown. Figure 5A-5F In addition, it should be understood that Figure 2 The first etch stop layer 208a in the embodiment may correspond to one of the plurality of etch stop layers 208, Figure 2 The first and second dielectric layers 112a, 112b in may correspond to two of the interconnect dielectric layers 112. Similarly, Figure 2The first and second through holes 210 a , 210 b in FIG. 2 may correspond to two of the through holes 210 .

[0073] A heat sink 608 is located below the heater 108 in the interconnect structure 602. The heat sink 608 is formed by the wiring at the wiring level M7 and the wiring level M6 and the vias at the via level V6. The heat sink 608 helps to dissipate heat while cycling the PCM RF switch 102. For example, the heat sink 608 can help quench the active portion 106a of the PCM structure 106 (see Figure 2 ), and at the same time, the PCM RF switch 102 is switched to the OFF state.

[0074] Between the interconnect structure 602 and the semiconductor substrate 604, a pair of logic devices 610 are located below the interconnect structure 602 and are electrically coupled to the interconnect structure 602. In addition, the logic device 610 is partially formed in the semiconductor substrate 604. In alternative embodiments, there may be more or fewer logic devices 610 and / or there may be devices other than logic devices in addition or alternatively. In some embodiments, the semiconductor substrate 604 is or includes silicon or the like.

[0075] Logic devices 610 are separated from each other by isolation structures 612. Isolation structures 612 may be, for example, or include shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, local oxidation of silicon (LOCOS) isolation structures, some other suitable type of isolation structures, or any combination of the above structures. Logic devices 610 are shown as planar field effect transistors (planar FETs). However, logic devices 610 may alternatively be fin field effect transistors (FinFETs), gate-all-around (GAA) field effect transistors, some other suitable type of logic devices and / or transistors, or any combination of the above.

[0076] The logic device 610 includes a corresponding gate electrode 614, a corresponding gate dielectric layer 616, a corresponding pair of source / drain regions 618, and a corresponding well 620. The pair of source / drain regions 618 is inserted into the top of the semiconductor substrate 604. The gate electrodes 614 are respectively overlying the gate dielectric layer 616 and are respectively located between the pair of source / drain regions 618. The well 620 corresponds to a doped region of the semiconductor substrate 604 and is respectively located under the pair of source / drain regions 618 and the gate electrode 614. In an alternative embodiment, the well 620 is omitted.

[0077] refer to Figure 7 , provides Figure 6 A cross-sectional view 700 of some alternative embodiments of an integrated chip, wherein the PCM RF switch 102 is as shown Figure 5E In an alternative embodiment, the PCM RF switch 102 is as shown. Figure 5A-5D or Fig. 5FAny one of the following is shown.

[0078] refer to Figure 8-Figure 21 , a series of cross-sectional views 800-2100 of some embodiments of a method of forming an integrated chip including a PCM RF switch having a PCM recess are provided. For example, the method may be used to form Figure 2 The PCM RF switch 102 or some other suitable PCM RF switch.

[0079] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a conductive layer 802 is deposited over the first dielectric layer 112 a. The first dielectric layer 112 a overlies the first etch stop layer 208 a, which overlies the substrate (not shown). In an alternative embodiment, the first etch stop layer 208 a is omitted. As described below, the first dielectric layer 112 a may correspond to, for example, an interconnect dielectric layer, etc.

[0080] In some embodiments, the conductive layer 802 is or includes tungsten and / or some other suitable material with low electrical resistance and high heat resistance. In some embodiments, the first dielectric layer 112a is or includes silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In some embodiments, the first etch stop layer 208a is or includes silicon carbide and / or some other suitable dielectric.

[0081] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 8 , the conductive layer 802 is patterned to form the first electrode 110a, the second electrode 110b, and the heater 108 spaced apart between the first and second electrodes 110a, 110b. For example, the conductive layer 802 may be patterned so that the first and second electrodes 110a, 110b and the heater 108 have the following characteristics: Figure 3 or Figure 4 The corresponding top layout shown. For example, patterning can be performed by or using a photolithography / etching process or some other suitable patterning process. In addition, patterning can, for example, include etching the conductive layer 802 while the mask 902 covers the conductive layer 802, and then removing the mask 902.

[0082] like Fig.10 As shown in the cross-sectional view 1000 of , a dielectric material is deposited over and around the first and second electrodes 110a, 110b and the heater 108 to extend the first dielectric layer 112a.

[0083] like Fig.11As shown in the cross-sectional view 1100 of , the first dielectric layer 112a is planarized so that the top surface of the first dielectric layer 112a is flush with the corresponding top surfaces of the first and second electrodes 110a, 110b and the heater 108. For example, the planarization can be performed by chemical mechanical planarization (CMP) and / or some other suitable planarization.

[0084] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the passivation layer 114 is deposited on the first dielectric layer 112a, and on the first and second electrodes 110a, 110b and the heater 108. In some embodiments, the passivation layer 114 is or includes silicon nitride and / or some other suitable dielectric.

[0085] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the passivation layer 114 is patterned to form a pair of openings 1302, the pair of openings 1302 being laterally offset from the heater 108 and overlying the first and second electrodes 110a, 110b, respectively. For example, the patterning may be performed by or using a photolithography / etching process or some other suitable patterning process. In addition, the patterning may, for example, include etching the passivation layer 114 while the mask 1304 covers the passivation layer 114, and then removing the mask 1304.

[0086] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , the PCM layer 1061 is deposited over the passivation layer 114 and fills the opening 1302 (see FIG. 1 ). Fig.13 In some embodiments, the PCM layer 1061 is or includes germanium telluride and / or some other suitable phase change material.

[0087] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a first hard mask layer 202a and a second hard mask layer 202b are deposited over the PCM layer 1061. The first hard mask layer 202a is deposited first, and then the second hard mask layer 202b is deposited overlying the first hard mask layer 202a. The second hard mask layer 202b is a different material from the first hard mask layer 202a. The first hard mask layer 202a may be, for example, or include silicon nitride and / or some other suitable dielectric. The second hard mask layer 202b may be, for example, or include silicon oxide and / or some other suitable dielectric.

[0088] like Fig.16As shown in the cross-sectional view 1600 of FIG. 1 , the PCM layer 1061, the first hard mask layer 202a and the second hard mask layer 202b are patterned. The patterning forms the PCM structure 106 and the hard mask 202 overlying the PCM structure 106. The PCM structure 106 covers the heater 108 and has a pair of outer sidewalls overlying the first and second electrodes 110a, 110b, respectively. The first and second electrodes 110a, 110b, the heater 108 and the PCM structure 106 together form the PCM RF switch 102.

[0089] For example, patterning can be performed by or using a photolithography / etching process or some other suitable patterning process. In addition, patterning can, for example, include etching the PCM layer 1061, the first hard mask layer 202a, and the second hard mask layer 202b while the mask 1602 overlies these layers (e.g., the second hard mask layer 202b), and then removing the mask 1602.

[0090] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , the first capping layer 204 is deposited over the passivation layer 114 and the hard mask 202, and further extends along the outer sidewalls of the PCM structure 106. The first capping layer 204 may be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the first capping layer 204 is the same material as the first hard mask layer 202a and / or the passivation layer 114.

[0091] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , the first cap layer 204, the hard mask 202, and the PCM structure 106 are patterned to form a PCM recess 104 overlying the heater 108 at the active portion 106a of the PCM structure 106. For example, the patterning may be performed by or using a photolithography / etching process or some other suitable patterning process. In addition, the patterning may, for example, include etching the first cap layer 204, the hard mask 202, and the PCM structure 106 while the mask 1802 covers these layers (e.g., the first cap layer 204), and then removing the mask 1802. The mask 1802 may, for example, be or include a photoresist and / or some other suitable material.

[0092] The active portion 106a is configured to selectively change between an amorphous phase and a crystalline phase by selective heating of the heater 108. For example, the active portion 106b may be set to an amorphous phase by heating the active portion 106a to a temperature exceeding a melting temperature for a first time period and quenching (e.g., rapidly cooling) the active portion 106a. As another example, the active portion 106b may be set to a crystalline phase by heating the active portion 106a to a temperature above a crystallization temperature and below a melting temperature for a second time period greater than the first time period.

[0093] When in the amorphous phase, the active portion 106a is in HRS. When in the crystalline phase, the active portion 106a is in LRS. HRS may correspond to the OFF state of the PCM RF switch 102, while LRS may correspond to the ON state of the PCM RF switch 102. The active portion 106a will be contrasted with the rest of the PCM structure 106, which corresponds to the pair of passive portions 106ia. In some embodiments, the PCM recess 104, the active portion 106a, and the passive portion 106ia have the following configurations: Figure 1 The dimensions (e.g., width, thickness, etc.)

[0094] The pair of passive portions 106ia are located at opposite sides of the active portion 106a, respectively, and extend from the active portion 106a to the first electrode 110a and the second electrode 110b, respectively. As a result, the passive portion 106ia separates the first and second electrodes 110a, 110b from the active portion 106a. In addition, the passive portion 106ia is in a crystalline phase and remains in the crystalline phase during the cycle (e.g., ON / OFF cycle) of the PCM RF switch 102. Because the passive portion 106ia is in a crystalline phase, the passive portion 106ia has a low resistance and provides a low resistance electrical path from the active portion 106a to the first and second electrodes 110a, 110b, respectively.

[0095] Due to the PCM recess 104, the active thickness T at the active portion 106a a and the passive thickness T at the passive portion 106ia ia Specifically, the active thickness and passive thickness T a , T ia Relatively small and large.

[0096] The small thickness T at the active portion 106a a Preventing voids from forming at the active portion 106a under thermal stress of the PCM RF switch 102 cycle. a This can lead to faster heat dissipation, which reduces thermal stress and reduces voiding. By preventing voiding, a small thickness T a This results in high thermal tolerance of the PCM RF switch 102. Note that voids are mainly formed at the active portion 106a where thermal stress is highest, so voids are not a problem at the passive portion 106ia. The large thickness T at the passive portion 106ia ia The PCM recess 104 results in a low resistance at the passive portion 106ia. The low resistance results in a low on-resistance of the PCM RF switch 102. Therefore, the PCM recess 104 allows the PCM RF switch 102 to have a small thickness (eg, T a ) and large thickness (such as T ia ) benefits.

[0097] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the second capping layer 206 is deposited over the first capping layer 204 and lines the PCM recess 104. The second capping layer 206 can be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the second capping layer 206 is the same material as at least one of the first hard mask layer 202a, the passivation layer 114, or the first capping layer 204.

[0098] like Fig. 20 As shown in the cross-sectional view 2000 of , a second dielectric layer 112b is deposited overlying the second cap layer 206 and filling the PCM recess 104. In some embodiments, the second dielectric layer 112b is or includes silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In addition, in some embodiments, the top of the second dielectric layer 112b is planarized to make it flat. For example, the planarization can be performed by CMP and / or some other suitable planarization.

[0099] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 1 , the first through hole 210a and the second through hole 210b are formed above the first and second electrodes 110a and 110b, respectively, and extend from the first and second electrodes 110a and 110b. In some embodiments, Fig.21 In addition to the cross-sectional view 2100 of FIG. 21, an additional through hole is formed overlying the heater 108 and extending from the heater 108. For example, in the case where the heater 108 has a Figure 3 or Figure 4 In the case of the top layout shown, these additional vias may be formed above and extend from the pad portions 108p, respectively.

[0100] Although Figure 8-Figure 21 is described with reference to one method, but it should be understood that Figure 8-Figure 21 The structure shown in is not limited to this method, but can be independent of this method. Figure 8-Figure 21 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 8-Figure 21 A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0101] refer to Fig. 22 , provides Figure 8-Figure 21 Block diagram 2200 of some embodiments of the method.

[0102] At block 2202, a pair of electrodes and a heater are formed interposed on top of a first dielectric layer, wherein the heater is located between and spaced apart from the electrodes. Figure 8-Figure 11 .

[0103] At block 2204, a passivation layer is deposited over the electrode pair, the heater, and the first dielectric layer. Fig.12 .

[0104] At block 2206, the passivation layer is patterned to form a pair of openings that expose the electrodes and are laterally offset from the heater, respectively. Fig.13 .

[0105] At block 2208, a PCM layer is deposited filling the opening and overlying the passivation layer. Fig.14 .

[0106] At block 2210, a hard mask layer is deposited overlying the PCM layer. Fig.15 .

[0107] At block 2212, the PCM layer and the hard mask layer are patterned into a PCM structure and a hard mask on top of the PCM structure, respectively, wherein the PCM structure has a pair of outer sidewalls respectively in the opening. Fig.16 .

[0108] At block 2214, a first capping layer is deposited, the first capping layer overlying the hard mask and lining the outer sidewalls. Fig.17 .

[0109] At block 2216, the first cap layer, the hard mask, and the PCM structure are patterned to form a PCM recess overlying the heater in the active portion of the PCM structure. Fig.18 .

[0110] At block 2218, a second cap layer is deposited, the second cap layer overlying the first cap layer and lining the PCM recess. Fig.19 .

[0111] At block 2220, a second dielectric layer is deposited overlying the second cap layer. Fig. 20 .

[0112] At block 2222, vias are formed in the second dielectric layer and extending from the electrodes, respectively. Fig.21 .

[0113] Although Fig. 22The block diagram 2200 is shown and described herein as a series of actions or events, but it should be understood that the order shown in these actions or events should not be interpreted as limiting. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0114] refer to Figure 23-Figure 27 , provides Figure 8-Figure 21 A series of cross-sectional views 2300-2700 of some first alternative embodiments of the method.

[0115] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 1 , the first dielectric layer 112a is patterned to form a plurality of openings 2302, which correspond to the pairs of electrodes and heaters to be formed thereafter. In addition, the first dielectric layer 112a overlies the first etch stop layer 208a, which overlies the substrate (not shown). In an alternative embodiment, the first etch stop layer 208a is omitted.

[0116] For example, patterning may be performed by or using a photolithography / etching process or some other suitable patterning process. In addition, patterning may, for example, include etching the first dielectric layer 112a while the mask 2304 is overlying the first dielectric layer 112a, and then removing the mask 2304.

[0117] like Fig.24 As shown in the cross-sectional view 2400 , a conductive layer 802 is deposited, and the conductive layer 802 covers the first dielectric layer 112 a and fills the opening 2302 .

[0118] like Fig.25 As shown in the cross-sectional view 2500 of , the conductive layer 802 is planarized to remove the conductive layer 802 from the top of the first dielectric layer 112a. The planarization forms the first electrode 110a, the second electrode 110b and the heater 108 in the opening 2302, respectively. For example, the planarization can be performed by CMP and / or some other suitable planarization.

[0119] like Fig.26 As shown in the cross-sectional view 2600, the above-described implementation of Figure 12-Figure 20 The above-described operations are performed to form the PCM RF switch 102 below the second dielectric layer 112 b.

[0120] like Fig. 27 As shown in the cross-sectional view 2700, Fig.21As described above, the first through hole 210a and the second through hole 210b are formed above the first and second electrodes 110a and 110b, respectively, and extend from the first and second electrodes 110a and 110b.

[0121] Although Figure 23-Figure 27 is described with reference to one method, but it should be understood that Figure 23-Figure 27 The structure shown in is not limited to this method, but can be independent of this method. Figure 23-Figure 27 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 23-Figure 27 A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0122] refer to Figure 28-Figure 42 , provides Figure 8-Figure 21 A series of cross-sectional views 2800-4200 of some second alternative embodiments of the method. For example, the method can be used to form Figure 5E , Fig. 5F The PCM RF switch 102, or some other suitable PCM RF switch.

[0123] like Fig.28 As shown in the cross-sectional view 2800, the execution of Figure 8-Figure 11 The operations described above are performed to form the heater 108 inserted into the top of the first dielectric layer 112a. These operations are performed as described above, except that the first and second electrodes 110a, 110b are omitted (eg, not formed). Figure 8-Figure 11 In an alternative embodiment, instead of performing Figure 23-Figure 25 The actions described above are used to form the heater 108. In this alternative embodiment, except that the first and second electrodes 110a, 110b are omitted, other actions are as described above. Figure 23-Figure 25 described.

[0124] like Fig.29 As shown in the cross-sectional view 2900 of FIG. 1 , the passivation layer 114 is deposited on the first dielectric layer 112a and the heater 108. In addition, the PCM layer 1061 is deposited on the passivation layer 114. For example, the passivation layer 114 may be as follows: Fig.12 The PCM layer 1061 may be deposited as described above and / or the PCM layer 1061 may be deposited as described above. Fig.14 Deposition is performed as described.

[0125] like Figure 30-Figure 34 As described in the cross-sectional views 3000-3400, Figure 15-19 The actions are performed as described above. For example, Fig.30 Shows about Fig.15 The actions described, Fig.31Shows about Fig.16 The actions described, Fig.32 Shows about Fig.17 The above-mentioned actions are repeated in this way, and the PCM structure 106 having the PCM recess 104 is formed, and the hard mask 202 , the first capping layer 204 and the second capping layer 206 are further formed.

[0126] like Fig.35 As shown in the cross-sectional view 3500 of FIG. 35A , a planarization dielectric layer 502 is deposited over the second cap layer 206 and fills the PCM recess 104. In some embodiments, the planarization dielectric layer 502 is or includes silicon oxide, some other suitable oxide and / or dielectric, or any combination thereof. In some embodiments, the planarization dielectric layer 502 is the same material as the first dielectric layer 112 a and / or the same material as the second dielectric layer 112 b.

[0127] like Fig.36 As shown in the cross-sectional view 3600 of FIG. 36 , the planarization dielectric layer 502, the first cap layer 204, the second cap layer 206, and the hard mask 202 are planarized. The planarization removes the hard mask 202 and flushes the corresponding top surfaces of the planarization dielectric layer 502, the first cap layer 204, the second cap layer 206, and the PCM structure 106 to form a planar or substantially planar surface. For example, the planarization may be performed by CMP and / or some suitable planarization process.

[0128] like Fig.37 As shown in the cross-sectional view 3700 of FIG. 37 , a mask 3702 is formed, and the mask 3702 overlies the planarization dielectric layer 502 and the PCM structure 106. The mask 3702 covers the PCM recess 104 and has a pair of openings 3704, and the pair of openings 3704 expose the PCM structure 106 at opposite sides of the PCM structure 106, respectively. The mask 3702 can be or include, for example, photoresist and / or some other suitable material. The mask 3702 can be formed, for example, by photolithography and / or by some other suitable process.

[0129] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 38A , a conductive layer 3802 is deposited over the mask 3702 and in the opening 3704. In addition, the conductive layer 3802 is deposited so that the material of the conductive layer 3802 accumulates vertically without lateral accumulation from the sidewalls of the mask 3702 in the opening 3704, or with minimal lateral accumulation. In some embodiments, the conductive layer 3802 is or includes tungsten and / or some other suitable material with low electrical resistance and high heat resistance. In some embodiments, the conductive layer 3802 is the same material as the heater 108.

[0130] In some embodiments, conductive layer 3802 is deposited by an anisotropic deposition process. For example, conductive layer 3802 can be deposited by an evaporative deposition process and / or some other suitable deposition process. In addition, in some embodiments, the sidewalls of mask 3702 in opening 3704 are formed to be inclined so that the corresponding width of opening 3704 increases from top to bottom. The inclined sidewalls can minimize lateral accumulation from the inclined sidewalls.

[0131] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 3702 , the mask 3702 is removed, thereby peeling off the portion of the conductive layer 3802 covering the mask 3702, and forming the first and second electrodes 110a and 110b. Figure 37-Figure 39 An example of a metal lift-off process for forming the first and second electrodes 110 a , 110 b is shown, but other suitable processes may also be used to form the first and second electrodes 110 a , 110 b .

[0132] like Fig.40 As shown in the cross-sectional view 4000 of FIG. 4000 , the third capping layer 504 is deposited over the first and second electrodes 110 a, 110 b and lines the first and second electrodes 110 a, 110 b. The third capping layer 504 can be or include, for example, silicon nitride and / or some other suitable dielectric. In some embodiments, the third capping layer 504 is the same material as the first capping layer 204 and / or the second capping layer 206.

[0133] like Fig.41 As shown in the cross-sectional view 4100, the above Fig. 20 The described actions are performed to form the second dielectric layer 112b.

[0134] like Fig.42 As shown in the cross-sectional view 4200, the above Fig.21 The described actions are performed to form first and second through holes 210a, 210b respectively overlying the first and second electrodes 110a, 110b and extending from the first and second electrodes 110a, 110b.

[0135] Although Figure 28-Figure 42 is described with reference to one method, but it is understood that Figure 28-Figure 42 The structure shown in is not limited to this method, but can be independent of this method. Figure 28-Figure 42 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 28-Figure 42 A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0136] refer to Fig.43 , provides Figure 28-Figure 42 Block diagram 4300 of some embodiments of the method.

[0137] At block 4302, a heater is formed inserted into the top of the first dielectric layer. For example, see Fig.28 .

[0138] At block 4304, a passivation layer, a PCM layer, and a hard mask layer are vertically stacked and formed overlying the heater and the first dielectric layer. Fig.29 and Fig.30 .

[0139] At block 4306, the PCM layer and the hard mask layer are patterned into a PCM structure and a hard mask on top of the PCM structure, respectively. Fig.31 .

[0140] At block 4308, a first capping layer is deposited, the first capping layer overlying the hard mask and lining the sidewalls of the PCM structure. Fig.32 .

[0141] At block 4310, the first cap layer, the hard mask, and the PCM structure are patterned to form a PCM recess overlying the heater at an active portion of the PCM structure. Fig.33 .

[0142] At block 4312, a second cap layer is deposited, the second cap layer overlying the first cap layer and lining the PCM recess. Fig.34 .

[0143] At block 4314, a planarizing dielectric layer is deposited overlying the second cap layer. Fig.35 .

[0144] At block 4316, the planarization dielectric layer, the first and second capping layers, and the hard mask are planarized to expose the top surface of the PCM structure. Fig.36 .

[0145] At block 4318, a pair of electrodes overlying the PCM structure and the planarized dielectric layer are formed on opposite sides of the PCM structure, respectively. Figure 37-Figure 39 .

[0146] At block 4320, a third capping layer is deposited, the third capping layer overlying and lining the electrode. Fig.40 .

[0147] At block 4322, a second dielectric layer is deposited overlying the third cap layer. Fig.41 .

[0148] At block 4324, vias are formed in the second dielectric layer, the vias extending from the electrodes, respectively. Fig.42 .

[0149] Although Fig.43 Block diagram 4300 is shown and described herein as a series of actions or events, but it should be understood that the order of these actions or events shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0150] refer to Figure 44-Figure 47 , a series of cross-sectional views 4400-4700 of some embodiments of a method of forming an integrated chip including a PCM RF switch having a PCM recess are provided. For example, the method may be used to form Figure 6 integrated chip or other suitable integrated chip.

[0151] like Fig.44 As shown in cross-sectional view 4400 of FIG. 44 , a pair of logic devices 610 are formed on semiconductor substrate 604, separated from each other by isolation structure 612. Logic device 610 is shown as a planar FET. However, logic device 610 may alternatively be a FinFET, a GAA-FET, some other suitable type of logic device and / or transistor, or any combination of the foregoing. In alternative embodiments, more or fewer logic devices 610 may be formed on semiconductor substrate 604 and / or devices other than logic devices may be formed in addition or in lieu thereof.

[0152] Logic device 610 includes a corresponding gate electrode 614, a corresponding gate dielectric layer 616, a corresponding pair of source / drain regions 618, and a corresponding well 620. In an alternative embodiment, well 620 is omitted.

[0153] like Fig.45 As shown in the cross-sectional view 4500 of FIG. 45, the interconnect structure 602 is partially formed above the logic device 610 and electrically coupled to the logic device 610. The interconnect structure 602 includes a plurality of wirings 606 and a plurality of vias 210. The plurality of wirings 606 are divided into a plurality of wiring levels, and the plurality of vias 210 are divided into a plurality of via levels alternately stacked with the plurality of wiring levels. From the bottom to the top of the interconnect structure 602, the wiring levels are labeled M1, M2, etc. to M7. From the bottom to the top of the interconnect structure 602, the via levels are labeled V0, V1, etc. to V6.

[0154] The interconnect structure 602 is formed so that the wiring at the wiring levels M6 and M7 and the vias at the via level V6 form a heat sink 608 on top of the interconnect structure 602. In an alternative embodiment, the heat sink 608 is omitted. The heat sink 608 helps dissipate the heat generated by the heater formed later. In addition, in an alternative embodiment, the interconnect structure 602 is formed with more or fewer wiring levels and / or more or fewer via levels. In addition, in an alternative embodiment, the interconnect structure 602 is formed with a MEOL between the via level V0 and the logic device 610.

[0155] like Fig.45 As shown in the cross-sectional view 4500 of , a lower dielectric structure is formed around the interconnect structure 602. The lower dielectric structure includes a plurality of interconnect dielectric layers 112 and a plurality of etch stop layers 208 alternately stacked from the bottom of the interconnect structure 602 to the top of the interconnect structure 602. The plurality of etch stop layers 208 include a first etch stop layer 208a located at the top of the interconnect structure 602, and the plurality of interconnect dielectric layers 112 include a first dielectric layer 112a covering the first etch stop layer 208a.

[0156] like Fig.46 As shown in the cross-sectional view 4600, the execution of Figure 8-Figure 20 The actions described above are used to form the PCM RF switch 102. In an alternative embodiment, the execution of Figure 23-Figure 26 The actions described above are used to form the PCM RF switch 102. In other alternative embodiments, the execution of Figure 28-Figure 41 The actions described above are performed to form the PCM RF switch 102. For example, such other alternative embodiments may form Figure 7 The PCM RF switch 102 and integrated chip are shown.

[0157] like Fig.47 As shown in the cross-sectional view 4700 of FIG. 47 , the interconnect structure 602 is completed above the PCM RF switch 102 and electrically coupled to the PCM RF switch 102. The completed interconnect structure 602 includes additional via levels V7, V8, and V9 alternately stacked on the PCM RF switch 102 and additional routing levels M8 and M9.

[0158] like Fig.47 As shown in the cross-sectional view 4700 of , an upper dielectric structure is formed around the additional via levels V7, V8 and V9 and the additional wiring levels M8 and M9. The upper dielectric structure includes a plurality of additional interconnect dielectric layers 112 and a plurality of additional etch stop layers 208 alternately stacked with the additional interconnect dielectric layers 112. The plurality of additional interconnect dielectric layers 112 include a second dielectric layer 112b on top of the PCMRF switch 102.

[0159] Although Figure 44-Figure 47is described with reference to one method, but it is understood that Figure 44-Figure 47 The structure shown in is not limited to this method, but can be independent of this method. Figure 44-Figure 47 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 44-Figure 47 A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0160] In some embodiments, the present disclosure provides a semiconductor device, comprising: a heater, located above a substrate; a phase change material (PCM) structure, located above the heater; and a first electrode and a second electrode, respectively located on opposite sides of the heater and electrically coupled to the PCM structure on opposite sides; wherein the top of the PCM structure has a recess, the recess overlies the heater and has a width less than the width of the heater. In some embodiments, the width of the PCM structure is greater than the width of the heater. In some embodiments, the first electrode and the second electrode are located below the PCM structure and are flush with the heater. In some embodiments, the first electrode and the second electrode overlie the PCM structure and extend along corresponding sidewalls of the PCM structure. In some embodiments, the first electrode and the second electrode have corresponding bottommost surfaces overlying the top surface of the PCM structure. In some embodiments, the heater is laterally located between the first electrode and the second electrode in a first dimension, and wherein the heater has a pair of pads that are laterally spaced apart from each other in a second dimension orthogonal to the first dimension, and the first electrode and the second electrode are laterally arranged between the pads. In some embodiments, the semiconductor device further includes: a hard mask overlying the PCM structure, wherein the hard mask and the PCM structure form a first common sidewall overlying the heater in the recess, and further form a second common sidewall overlying the first electrode outside the recess; a first cap layer overlying the hard mask, wherein the first cap layer also forms the first common sidewall and lines the second common sidewall; and a second cap layer overlying the first cap layer and lines the first common sidewall and the second common sidewall.

[0161] In some embodiments, the present disclosure provides another semiconductor device, comprising: a heater located above a substrate; a phase change material (PCM) structure overlying the heater; and a first electrode and a second electrode, respectively located on opposite sides of the heater and electrically coupled to the PCM structure on opposite sides; wherein the PCM structure has a first thickness overlying the heater and also has a second thickness laterally offset from the heater, and wherein the first thickness is different from the second thickness. In some embodiments, the PCM structure has a central portion, the central portion overlying the heater and having a first thickness throughout the entire portion, and wherein the remaining portion of the phase change material structure is thicker than the central portion. In some embodiments, the width of the central portion is less than the width of the heater, and the width of the heater is less than the width of the PCM structure. In some embodiments, the remaining portion of the PCM structure partially covers the heater. In some embodiments, the semiconductor device further comprises a passivation layer, located below the PCM structure between the PCM structure and the heater, for separating the PCM structure from the heater. In some embodiments, the passivation layer has a bottom surface flush with a bottom surface of the PCM structure, and also has a sidewall facing the PCM structure.

[0162] In some embodiments, the present invention provides a method of forming a semiconductor device, comprising: forming a heater above a substrate; forming a pair of electrodes respectively located on opposite sides of the heater; depositing a passivation layer overlying the heater; forming a phase change material (PCM) structure overlying the passivation layer and the heater; and etching the PCM structure to form a recess overlying the heater. In some embodiments, a portion of the PCM structure located below the recess has a first thickness and spans the entire width of the recess, and wherein the remaining portion of the PCM structure is thicker than the portion. In some embodiments, the passivation layer is deposited overlying the pair of electrodes, and wherein the method further comprises: patterning the passivation layer to form a pair of openings, the pair of openings respectively exposing the pair of electrodes and laterally offset from the heater, wherein the PCM structure is formed in the pair of openings. In some embodiments, the formation of the PCM structure comprises: depositing a PCM layer overlying the passivation layer; and patterning the PCM layer into the PCM structure so that the PCM structure has a pair of corresponding sidewalls respectively overlying the pair of electrodes, the pair of electrodes being located in the pair of openings. In some embodiments, the method further comprises: depositing a dielectric layer overlying the PCM structure and filling the recess; and performing planarization on the dielectric layer until the top surface of the dielectric layer is flush with the top surface of the PCM structure. In some embodiments, the formation of the PCM structure comprises: depositing a PCM layer overlying the passivation layer; forming a hard mask layer overlying the PCM layer; and performing additional etching of the PCM layer and the hard mask layer with a common mask in place to form the PCM structure and a hard mask located on top of the PCM structure, respectively, wherein the planarization removes the hard mask. In some embodiments, the method further comprises depositing a conductive layer over the substrate, wherein the pair of heaters and electrodes is formed by the conductive layer.

[0163] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a heater positioned above the substrate; a phase change material structure located above the heater; as well as A first electrode and a second electrode, respectively located on opposite sides of the heater and respectively electrically coupled to the phase change material structure on the opposite sides; The top of the phase change material structure has a recess, and the recess covers the heater and has a width smaller than a width of the heater.

2. The semiconductor device according to claim 1, wherein The width of the phase change material structure is greater than the width of the heater.

3. The semiconductor device according to claim 1, wherein The first electrode and the second electrode are located below the phase change material structure and are flush with the heater.

4. The semiconductor device according to claim 1, wherein: The first electrode and the second electrode overlie the phase-change material structure and extend along corresponding side walls of the phase-change material structure.

5. The semiconductor device according to claim 1, wherein The heater is laterally located between the first electrode and the second electrode in a first dimension, and wherein the heater has a pair of pads laterally spaced apart from each other in a second dimension orthogonal to the first dimension, and the first electrode and the second electrode are laterally arranged between the pads.

6. The semiconductor device according to claim 1, further comprising: a hard mask overlying the phase change material structure, wherein the hard mask and the phase change material structure are formed in the recess overlying a first common sidewall of the heater, and further formed outside the recess overlying a second common sidewall of the first electrode; a first capping layer overlying the hard mask, wherein the first capping layer also forms the first common sidewall and lines the second common sidewall; and The second cover layer covers the first cover layer and lines the first common side wall and the second common side wall.

7. A semiconductor device comprising: a heater positioned above the substrate; a phase change material structure overlying the heater; as well as a first electrode and a second electrode, respectively disposed on opposite sides of the heater and respectively electrically coupled to the phase change material structure on the opposite sides; The phase change material structure has a first thickness overlying the heater and also has a second thickness laterally offset from the heater, and wherein the first thickness is different from the second thickness.

8. The semiconductor device according to claim 7, wherein: The phase change material structure has a central portion overlying the heater and having the first thickness throughout its entirety, and wherein a remaining portion of the phase change material structure is thicker than the central portion.

9. The semiconductor device according to claim 7, further comprising: A passivation layer is located below the phase-change material structure between the phase-change material structure and the heater to separate the phase-change material structure from the heater.

10. A method of forming a semiconductor device, comprising: forming a heater over the substrate; forming a pair of electrodes respectively located on opposite sides of the heater; depositing a passivation layer overlying the heater; forming a phase change material structure overlying the passivation layer and the heater; as well as The phase change material structure is etched to form a recess overlying the heater.

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