System comprising semiconductor chip and method of manufacturing the system

Abstract

The invention relates to a system (110) comprising an input projection layer (111), at least one second digital artificial neural network (50) and at least one semiconductor chip (40) having an analog artificial neural network (10) mapped from a trained first digital artificial neural network (17), the analog circuit comprises at least one input (20) configured to receive at least one input signal, and at least one output (26) configured to provide at least one analog output signal, where the analog artificial neural network (10) electrically connects the input (20) to the output (26), where the semiconductor chip (40) is recursively coupled to a second digital artificial neural network (50), where the semiconductor chip (40) is coupled to the second digital artificial neural network (50). The input projection layer (111) is electrically connected to the semiconductor chip (40) such that the output of the semiconductor chip (40) is provided to the at least one hidden layer of the second digital artificial neural network (50), and wherein the input (20) of the semiconductor chip (40) and the input layer of the second digital artificial neural network (50) are electrically connected to the input projection layer (111). A fast processing artificial neural network (10) is provided that operates faster than a second digital artificial neural network. Thus, before the second digital artificial neural network provides the output, the analog artificial neural network provides the output to affect operation of the second digital artificial neural network.

Description

Technical Field

[0001] The present invention relates to a system including a semiconductor chip and a method of manufacturing the system. Background Art

[0002] Artificial intelligence can be used to recognize patterns in technical applications such as image recognition or machine parameter monitoring. Artificial neural networks that mimic the function of biological neurons can provide artificial intelligence. These neural networks can be trained with training data, wherein the training adapts the neural networks, thereby improving their ability to perform tasks.

[0003] Different artificial neural networks can be coupled to assign subtasks of a task to be performed, for example, if the task is image recognition, the first subtask may be a rough classification of image elements and the second subtask may be the recognition of image elements. For example, in the human brain, the first part of the brain roughly classifies image elements, such as dangerous elements or harmless elements, wherein the second part of the brain recognizes image elements of the same image. The first part of the brain can influence the second part of the brain, for example, to speed up the recognition of dangerous image elements.

[0004] The structure can be formed by a first and a second artificial neural network, wherein the first artificial neural network is recursively coupled to the second artificial neural network. Both artificial neural networks receive the same input based on the same data. The first artificial neural network can affect the results of the second artificial neural network, wherein the second artificial neural network does not affect the first artificial neural network. Such an architecture is known from WO 2020 / 233850A1.

[0005] Since the first artificial neural network affects the second artificial neural network, the first artificial neural network must provide output before the second artificial neural network. If the complexity of the first artificial neural network is lower than that of the second artificial neural network, or if the input data of the first artificial neural network is sub-sampled, or if the second artificial neural network is started after the first artificial neural network generates output to affect the second artificial neural network, the first artificial neural network can provide output before the second artificial neural network.

[0006] There is a need to provide a fast processing artificial neural network that can contain the same complexity as another artificial neural network, can use the same input data samples as another artificial neural network, and can complete operations during the operation of another artificial neural network. Summary of the invention

[0007] The objects of the invention are solved by the subject-matter of the independent claims. Further embodiments are incorporated in the dependent claims and in the following description.

[0008] According to the present invention, a system is provided, which includes an input projection layer, at least one second digital artificial neural network, and at least one semiconductor chip, obtained by at least the following steps: providing a first trained digital artificial neural network; determining a state of the first trained digital artificial neural network, the state including at least information about digital nodes of the first trained digital artificial neural network and information about a digital connection architecture between digital nodes of the first trained digital artificial neural network; manufacturing a semiconductor chip, the semiconductor chip including an analog circuit having an analog artificial neural network designed according to the state of the first trained digital artificial neural network, wherein the analog circuit includes at least one input configured to receive at least one input signal and at least one output configured to provide at least one analog output signal, wherein the analog artificial neural network electrically connects the input to the output, wherein the semiconductor chip, in particular the analog artificial neural network, is recursively coupled to the second digital artificial neural network, and wherein the input of the semiconductor chip and the input layer of the second digital artificial neural network are electrically connected to the input projection layer.

[0009] The term "digital artificial neural network" as used herein encompasses software-based artificial neural networks, wherein the software runs on an information technology (IT) platform or in a microprocessor. Thus, the digital artificial neural network exists only on a digital electronic circuit platform, such as in a random access memory. Therefore, the nodes and connections between nodes exist only virtually and can be deleted. Due to the architecture of the software-based artificial neural network, the IT platform or microprocessor processes each node of the digital artificial neural network sequentially.

[0010] The term "simulated artificial neural network" as used herein includes artificial neural networks formed on analog hardware (e.g., hard-wired microchips). The simulated artificial neural network physically exists in the form of simulated circuits. The simulated wires and components of the semiconductor chip itself constitute the simulated artificial neural network. Therefore, the nodes of the simulated artificial neural network and the connections between the nodes cannot be completely deleted. The nodes of each layer of the simulated artificial neural network process the input data simultaneously.

[0011] These steps provide a semiconductor chip containing analog circuits. These analog circuits are non-programmable and form an analog artificial neural network. The analog artificial neural network operates in an analog manner so that the electrical signal at the input layer of the analog artificial neural network propagates through all the nodes of the layer of the artificial neural network at the same time. Therefore, the number of layers determines the processing speed of the electrical signal. In a digital artificial neural network, the nodes of the layer process the signal in sequence. Therefore, the number of nodes determines the processing speed of the electrical signal in the digital artificial neural network. Since the number of nodes is generally greater than the number of layers, the digital artificial neural network is slower than the analog artificial neural network with the same complexity. Therefore, if the analog artificial neural network has the same number of nodes and the same number of layers as the digital artificial neural network, the analog artificial neural network on the semiconductor chip is faster than the corresponding digital artificial neural network running on an IT platform or a microprocessor. The two artificial neural networks may have the same sampling of input data and may have the same complexity.

[0012] In order to manufacture a semiconductor chip, it is usually necessary to train a first digital artificial neural network. The first trained digital artificial neural network can also be called a digital master artificial neural network. Then, the state of the first trained digital artificial neural network is determined. The state can be read from the program running the first trained digital artificial neural network. The state includes information about at least the digital nodes of the first trained digital artificial neural network and the digital connections between the digital nodes, i.e., the so-called digital connection architecture. At least the information about the digital nodes can, for example, include biases, weights, transfer functions, and activation functions. The information about the digital nodes and the digital connection architecture completely determines the first digital artificial neural network. An analog artificial neural network is designed based on this information. The designed analog artificial neural network is provided as an analog circuit on a semiconductor chip. Of course, the semiconductor chip manufactured by this method may include more than one analog artificial neural network. Each of the more than one analog artificial neural networks can be based on a different trained digital artificial neural network. Some of the more than one analog artificial neural networks can be based on the same trained digital artificial neural network.

[0013] Thus, the semiconductor chip includes an analog circuit having an analog artificial neural network designed according to the state of the first trained digital artificial neural network.

[0014] As described above, the simulated artificial neural network runs much faster than the first trained digital artificial neural network. Therefore, the present invention provides a fast processing artificial neural network that can include the same complexity as another artificial neural network, and can use the same input data samples as another artificial neural network, and can complete operations during the operation of another artificial neural network.

[0015] The input may, for example, include an electrical connector configured to receive a signal. The signal may be an electrical signal, an optical signal, an acoustic signal, an olfactory signal, etc. In addition, the output may, for example, include an electrical connector configured to provide an electrical signal. The input may be electrically connected to an input layer of a simulated artificial neural network. Alternatively, the input may be an input layer of a simulated artificial neural network. The output may be electrically connected to an output layer of a simulated artificial neural network. Alternatively, the output may be an output layer of a simulated artificial neural network.

[0016] The semiconductor chip is recursively coupled to a second digital artificial neural network having the same complexity and sampled using the same input data. The coupling can be performed, for example, via an analog-digital interface. Then, when the second digital artificial neural network is running, the analog artificial neural network can output an electrical signal to affect the operation of the second digital artificial neural network.

[0017] The analog artificial neural network and the second digital artificial neural network operate using the same input data of the input projection layer. The input projection layer can provide input data to the input layer of the analog artificial neural network at the same time, wherein the digital nodes of the input layer of the second digital artificial neural network can receive the input data sequentially. Therefore, the analog artificial neural network and the second digital artificial neural network both receive input data with the same sampling. In addition, the operation speed of the analog artificial neural network is faster than that of the second digital artificial neural network. Therefore, the analog artificial neural network provides output before the second digital artificial neural network provides output to affect the operation of the second digital neural network.

[0018] Since the simulated artificial neural network is implemented on a hard-wired analog circuit, any basic rules of ethics of artificial intelligence can be permanently implemented in the simulated artificial neural network. These rules can only be changed within a known range, or even unchangeable.

[0019] Furthermore, since simulated ANNs run on semiconductor chips and do not require any external access connections, it is impossible to hack simulated ANNs.

[0020] In one example, the simulated artificial neural network may include simulated electronic nodes and simulated connection architectures between the simulated electronic nodes, wherein, in the step of manufacturing a semiconductor chip, the analog electronic nodes and the analog connection architectures are manufactured to correspond to digital nodes and digital connection architectures of a first trained digital artificial neural network.

[0021] The analog electronic components can form analog electronic nodes and analog connection architectures between these analog electronic nodes. The biases, weights, transfer functions, and activation functions of the analog electronic nodes correspond to the biases, weights, transfer functions, and activation functions of the digital nodes of the first trained digital artificial neural network. In addition, the wires between the analog electronic nodes forming the analog connection architecture correspond to the digital connections between the digital nodes.

[0022] In one example, the analog artificial neural network of the semiconductor chip may include analog electronic nodes and analog connection architectures between the analog electronic nodes, wherein the analog electronic nodes and the analog connection architecture correspond to digital nodes and digital connection architectures of the first trained digital artificial neural network, respectively.

[0023] In a further example, the simulated artificial neural network may include at least one simulated electronic switch and / or at least one simulated electronic node.

[0024] The analog electronic switches can be configured to interrupt or establish electrical connections between analog nodes of different layers of the simulated artificial neural network. For example, a switch array can be arranged between the input layer and the first hidden layer of the simulated artificial neural network. This means that the electrical connection between each node of the input layer and each node of the first hidden layer includes an analog electronic switch. The switch array can then control the propagation of electrical signals through the simulated artificial neural network. The simulated artificial neural network processes electrical signals only when the switch array does not interrupt the electrical connection between the input layer and the first hidden layer. Therefore, the switch array can control the start of the operation of the simulated artificial neural network. Of course, any electrical connection of the simulated artificial neural network can include an analog electronic switch to control the propagation of electrical signals.

[0025] The analog electronic switch may include, for example, a transistor and / or a field effect transistor. In addition, a controller providing a control signal may control the analog electronic switch. The semiconductor chip may include, for example, the controller. Alternatively, the controller and the semiconductor chip may be separate components.

[0026] Also, for example, the input may include a sensor array configured to simultaneously provide a sensor data signal from each sensor of the sensor array to the simulated artificial neural network.

[0027] All sensors of the sensor array can provide corresponding sensor signals simultaneously. For example, the sensor array can include a pixel array. The pixel array can include, for example, active pixel sensors. In addition, the sensors in the sensor array can, for example, provide corresponding sensor signals in sequence. Then, the sensor array can be used as input to the analog artificial neural network and the second digital artificial neural network simultaneously. In another example, the sensor array can include an olfactory sensor array, a pressure sensor array, an ultrasonic sensor array, a temperature sensor array, and / or an acoustic sensor array.

[0028] In another example, the analog circuit may include only electronic components with fixed characteristics such that the analog artificial neural network cannot be trained.

[0029] In this example, the simulated artificial neural network is fixed and cannot be trained. This example provides a semiconductor chip with a simulated artificial neural network that is simple and cost-effective to manufacture, so that the simulated artificial neural network can be trained.

[0030] In another example, an analog circuit may include at least one electronic component having a variable characteristic.

[0031] In this example, the simulated artificial neural network can be trained by changing the characteristics of at least one electronic component. The at least one electronic component with a variable characteristic can be, for example, an adjustable resistor or an analog electronic switch. The adjustable resistor can, for example, electrically connect two nodes to adjust the weight of the electrical connection between these nodes. The analog electronic switch can, for example, connect and disconnect the electrical connection between two nodes. The fewer electronic components with variable characteristics in the simulated artificial neural network, the lower the training ability of the simulated artificial neural network.

[0032] According to a third aspect of the present invention, there is provided a device comprising at least one semiconductor chip according to the above description and at least one controller, wherein the controller is configured to provide at least one control signal to the semiconductor chip, the control signal is preferably a start signal of a sensor array of the semiconductor chip, the controller preferably comprises at least one of the following groups: an analog electronic control circuit, a digital electronic control circuit, a control program and a processor, wherein the semiconductor chip preferably also comprises a control input, the control input is configured to receive the start signal, wherein further preferably, the sensor array is also configured to provide a sensor data signal when the start signal is received.

[0033] In an example, the controller may be further configured to provide a reset signal for resetting the analog circuit.

[0034] In an example, the system may further include at least one interface for controlling and transmitting data, the interface being configured to recursively couple the semiconductor chip to the second digital artificial neural network, wherein the interface is preferably configured to provide at least one analog control signal for simulating the artificial neural network, wherein the interface is further preferably configured to receive an analog output signal from the semiconductor chip, generate a digital control signal from the analog output signal, and provide the at least one digital control signal to at least one digital node in at least one hidden layer of the second digital artificial neural network, so that the interface recursively couples the semiconductor chip to the second digital artificial neural network.

[0035] The interface can convert the analog output signal of the simulated artificial neural network into a digital control signal. At least one digital node of the hidden layer of the second trained artificial neural network receives the digital control signal. Then, the digital signal affects the operation of these digital nodes, thereby affecting the output of these digital nodes. Therefore, the simulated artificial neural network affects the operation of the second trained artificial neural network.

[0036] The advantages and effects of the system and further developments are derived from the advantages and effects of the above-mentioned semiconductor chip and device and further developments. In this regard, reference is made to the previous description. In another example, the input projection layer may include at least one of the following groups: a pixel array, an olfactory sensor array, a pressure sensor array, an ultrasound sensor array, a temperature sensor array, and an acoustic sensor array.

[0037] According to another aspect of the present invention, a method for manufacturing a system according to the above description is provided, wherein the method comprises at least the following steps: separately training a second digital artificial neural network without providing the second digital artificial neural network with an output from the analog artificial neural network; providing a semiconductor chip having a separately trained analog artificial neural network, wherein training of the analog artificial neural network is performed without providing the second digital artificial neural network with the output of the analog artificial neural network; recursively connecting the semiconductor chip to the separately trained second digital artificial neural network so that the output of the analog artificial neural network is provided to at least one hidden layer of the second digital artificial neural network; and training the analog artificial neural network of the recursively connected semiconductor chip and the separately trained second digital artificial neural network together.

[0038] The recursive connection of the semiconductor chip to the separately trained second digital artificial neural network includes the recursive connection of the analog artificial neural network to the separately trained second digital artificial neural network.

[0039] In the step of training the simulated artificial neural network of the recursively connected semiconductor chip and the separately trained second digital artificial neural network together, the simulated artificial neural network may remain fixed. The training then includes the training of the separately trained second digital artificial neural network, while the simulated artificial neural network influences the separately trained second digital artificial neural network. Alternatively, the simulated artificial neural network may be trainable so that the training also includes the training of the simulated artificial neural network.

[0040] Advantages and effects of the method of manufacturing a system and further developments derive from the advantages and effects of the semiconductor chip, the device, the system and the method of manufacturing a semiconductor chip described above and further developments. In this respect, reference is made to the previous description.

[0041] In one example, the step of providing a semiconductor chip having a separately trained analog artificial neural network may include at least the following sub-steps: separately training the first digital artificial neural network.

[0042] Therefore, before manufacturing the analog artificial neural network, the first digital artificial neural network is trained. Then, according to the above method for manufacturing a semiconductor, the first trained digital artificial neural network is used to manufacture a semiconductor chip.

[0043] Alternatively or additionally, a simulated artificial neural network may be trained on a simulated circuit comprising simulated electronic components having adjustable characteristics.

[0044] In addition, for example, the first training data set can be used to provide a separately trained analog artificial neural network for the semiconductor chip, wherein, preferably, the second digital artificial neural network is trained with the second training data set, and further preferably, the third training data set is used to train the analog artificial neural network and the separately trained second digital artificial neural network together.

[0045] The first training data set may be applicable to training the analog artificial neural network. The second training data set may be applicable to training the second digital artificial neural network. The third training data set may be applicable to training the analog artificial neural network and the second digital artificial neural network together. Therefore, training may be performed with higher efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The present invention will be described below by way of exemplary embodiments using the accompanying drawings.

[0047] Figure 1a , b shows a schematic diagram of the simulated artificial neural network.

[0048] Figure 2a , b show schematic diagrams of digital (a) and analog (b) artificial neural networks.

[0049] Figure 3a, b shows a schematic diagram of the sensor array.

[0050] Figure 4 A schematic diagram showing an example of a control circuit for a sensor element is shown.

[0051] Figure 5 A flow chart representing the nodes of a neural network is shown.

[0052] Figure 6a -h shows a schematic diagram of the simulation circuit used to simulate the electronic node.

[0053] Figure 7a -g shows a schematic diagram of an analog circuit for providing alternative schemes for biasing and different functional progressions.

[0054] Figure 8 A schematic diagram showing an electronic component with variable characteristics.

[0055] Figure 9a , b shows a schematic diagram of a switchable electrical connection.

[0056] Fig.10 A schematic diagram of a system with an analog artificial neural network on a semiconductor recursively coupled to a trained digital artificial neural network is shown.

[0057] Fig.11 A flow chart of a method for manufacturing a semiconductor chip is shown.

[0058] Fig.12 A flow chart of a method for manufacturing a system is shown. DETAILED DESCRIPTION

[0059] Figure 1a Schematic diagram of the simulated artificial neural network 10 is shown. The simulated artificial neural network 10 is implemented as an analog circuit on a semiconductor chip 40, such as Figure 1c As shown. This means that the simulated artificial neural network 10 cannot be reprogrammed by modifying the software. The physical structure of the simulated artificial neural network 10 is fixed. The analog circuit is hard-wired, so that the simulated artificial neural network 10 is also hard-wired.

[0060] The simulated circuit includes an input 20 and an output 26 , wherein the simulated artificial neural network 10 electrically connects the input 20 to the output 26 .

[0061] like Figure 1a As shown, the simulated artificial neural network 10 may include an input layer 11, at least one hidden layer 12, and an output layer 13. All layers may include at least one simulated electronic node composed of simulated electronic components. The simulated electronic node includes a node input and a node output.

[0062] Figure 1a The analog electronic nodes in the hidden layer 12 are shown as examples of analog electronic components. However, this does not mean that the analog electronic nodes are limited to these analog electronic components.

[0063] In addition, this example shows two hidden layers 12. Of course, the simulated artificial neural network may also include only one or more than two hidden layers 12.

[0064] The node input of the input layer 11 can be electrically connected to the input 20. Figure 1a In the example shown, input 20 may be input layer 11. Electrical signals from input 20 may propagate to node inputs of input layer 11.

[0065] The input 20 may be a sensor array, such as a two-dimensional array of pixels that collects light emitted from or reflected from an object 31. In this example, the object 31 is an image.

[0066] The node outputs of the output layer 13 may be electrically connected to the output 26. The electrical signals from the node outputs of the output layer 13 may propagate to the output 26.

[0067] The nodes of at least one hidden layer 12 are electrically connected to the nodes of the input layer 11 and / or the nodes of the output layer 13. Wires 18, 19 may provide electrical connections between node outputs and node inputs.

[0068] Wire 18 connects the node output closer to input 20 to the node input closer to output 26. Thus, the electrical signal propagates along wire 18 from input 20 to output 26 in the forward direction.

[0069] Wire 19 connects the node output closer to output 26 to the node input closer to input 20. In this example, wire 19 connects only the nodes of hidden layer 12. Therefore, wire 19 may connect the node output and the node input of the same node or a node closer to input 20. Therefore, the electrical signal propagates backward from output 26 to input 20 along wire 19.

[0070] In the input layer 11 and the first hidden layer 12 ( Figure 1aThe simulated artificial neural network 10 may include a switching layer 33 between the nodes of the input layer 11 and the remaining nodes of the simulated artificial neural network 10. The switching layer 33 may have at least two switching states. In the first switching state, the switching layer 33 may interrupt any electrical connection between the nodes of the input layer 11 and the remaining nodes of the simulated artificial neural network 10. In the second switching state, the switching layer 33 may establish an electrical connection between the nodes of the input layer 11 and the remaining nodes of the simulated artificial neural network 10 (for example, the nodes of the first hidden layer 12). This allows the processing of input signals by the simulated artificial neural network 10 to be started and stopped. The switching layer 33 can simultaneously switch all electrical connections between the input layer 11 and the remaining layers.

[0071] The switching layer 33 may include at least one analog electronic switch 34, such as Figure 1b As shown. The analog electronic switch 34 may include, for example, a field effect transistor having a control signal input. The control signal at the gate of the field effect transistor may switch the analog electronic switch 34 on and off. For example, if the control signal has a negative voltage U B , the analog electronic switch 34 can be turned off and interrupt the electrical connection between the drain and the source. For example, if the control signal has a positive voltage U B , the analog electronic switch 34 can be turned on and establish an electrical connection between the drain and the source.

[0072] Controller 35 may provide control signals via control input 36. Controller 35 may be a component of semiconductor chip 40. Alternatively, controller 35 and semiconductor chip 40 may be separate components of a device (not shown).

[0073] In addition, the controller 35 may provide an output control signal to the output layer 13 via a control signal line 84. The controller 35 may also include an analog electronic control circuit for controlling the analog artificial neural network 10. In addition, the controller 35 may include a digital electronic control circuit for controlling the second digital artificial neural network 50. In addition, the controller 35 may include a control program and a processor, wherein the control program running on the processor may control the control circuit.

[0074] Due to the analog signal processing, the analog artificial neural network 10 is much faster than a digital artificial neural network with the same network structure and the same level of training.

[0075] Figure 2a A schematic diagram of a first trained digital artificial neural network 17 is shown, which is used to manufacture Figure 2b A master version of the simulated artificial neural network 10 is shown in FIG.

[0076] The vertical arrow 14 represents the digital input signal. The arrow 15 represents the processing order of the digital nodes of the first trained digital artificial neural network 17. This shows that the digital input signal is fed one by one in sequence. In addition, the digital nodes are processed one by one in sequence. The number of nodes determines the processing speed.

[0077] Figure 2b The vertical arrows 16 in the figure show the processing order of the simulated nodes of the simulated artificial neural network 10. All nodes of a layer operate simultaneously. Therefore, the number of layers determines the processing speed.

[0078] Since the number of nodes is usually greater than the number of layers, the simulated artificial neural network 10 processes signals much faster than the first trained digital artificial neural network 17. Therefore, the simulated artificial neural network 10 provides output data earlier than the first trained digital artificial neural network 17.

[0079] Figure 3a and 3b An example of a sensor array of input 20 is shown which can simultaneously provide input signals to each node of the input layer 11 of the simulated artificial neural network 10. In order to collect signals from input 20 simultaneously, input 20 may not operate as a charge coupled device.

[0080] Figure 3a A schematic diagram of a pixel line of a two-dimensional array of photodiodes 21 is shown. Each photodiode 21 is connected to the base of a transistor 22. Figure 3b A schematic diagram of a pixel line of a two-dimensional array of phototransistors 23 is shown. In both examples, each pixel includes transistors 22, 23 to amplify the resulting signal. These components can be active pixel sensors known in the prior art. This pixel architecture allows all pixels of the array to be read out simultaneously. In addition, the pixel architecture also allows pixel signals to be provided sequentially.

[0081] By designing the simulated artificial neural network 10, the input layer 11 directly processes the signal of the sensor array of the input 20, without normalizing the signal of the sensor array. Therefore, the simulated nodes of the input layer 11 can be sensors of the sensor array. This can further speed up the processing speed of the simulated artificial neural network 10.

[0082] Obviously, the sensor array may include any type and number of sensors, such as olfactory sensors, pressure sensors, ultrasonic sensors, temperature sensors, and / or acoustic sensors.

[0083] Figure 4An example of a controllable sensor 21 of the input 20 is shown. The sensor is a photodiode 21, which is connected to the base of a first field effect transistor 43. The first field effect transistor 43 amplifies the signal of the photodiode 21. If a reset control signal is applied, the second field effect transistor 42 can reset the signal of the photodiode 21. The third field effect transistor 44 can turn on the amplification of the first field effect transistor 43 when receiving a readout control signal.

[0084] The reset control signal and the read control signal can be sent by the controller 35 via Figure 1a A control input 36 is shown provided.

[0085] For clarity, Figure 4 Passive electronic components such as resistors and / or capacitors are omitted. However, the dimensions of these passive electronic components in such electronic circuits are known in the prior art.

[0086] The following discussion relates to the design process of analog nodes that simulate the hidden layer 12 of the artificial neural network 10. The analog electronic nodes should mimic the functions of biological neurons and implement basic mathematical operations, such as AND, NOR, OR, NAND, etc. Therefore, in the design process of analog circuits representing analog electronic nodes, it is required that all node parameters are adaptable.

[0087] Figure 5 The basic mathematical definition of a node for programming a digital artificial neural network is shown. A node links multiple input signals x1, ..., x2 from multiple previous nodes. n , where each input signal is represented by a weight w 1j , ..., w nj The weights can be positive, negative, or zero, where zero means the connection to the corresponding previous node is closed.

[0088] The transfer function Σ links the input signals, for example by adding them. However, the transfer function may also multiply the input signals, perform Boolean operations, differentiate, or integrate, or perform any other logical operation.

[0089] The activation function φ determines the output signal O of the node j The output signal can be a Gaussian bell function, a jump function, a rectangular signal, a cylindrical function, or an S-shaped function. Threshold or bias θ j May affect the activation function.

[0090] For converting digital nodes to analog circuit techniques, designs can be based on basic circuit variations of passive four-pole theory of electrical engineering and analog circuits of operational amplifiers.

[0091] according to Figures 3a to 5The examples of known circuits are shown, which have a well-defined transfer function and are therefore "reasonable" to use. Such circuits can, for example, map neurons. However, circuits that are not "reasonable" in the electronic sense can also be used. For example, a circuit with passive and active components as basic elements does not replicate a neuron. These basic elements may only have defined inputs and outputs, wherein the connections between different basic elements are non-transient, e.g. indestructible but changeable. The circuit established between these basic elements may not solve a technically defined object, e.g. these basic elements cannot simulate a neuron. However, the circuit may still provide the functionality of an artificial neural network.

[0092] Figures 6a to 6h shows examples of basic analog circuits that can provide the above Figure 5 Some or all of the examples may be combined in any manner to provide an analog electronic node.

[0093] Figure 6a and 6b Passive electronic components are shown, where Figures 6c to 6h Active electronic components, such as operational amplifiers, are shown.

[0094] Figure 6a A voltage divider is shown for weighting the input signal. Figure 6b A circuit is shown for shifting an arbitrary function around the zero line to achieve a bias or threshold. Figure 6c shows the two inputs U e1 and U e2 Summing operational amplifier circuit. Figure 6e A circuit is shown including an operational amplifier for subtracting inputs V1 and V2. Figure 6d The circuit in represents a combination of mixing different signals, adding, and amplifying. Figure 6f A circuit comprising an operational amplifier for differentiating input signals. Figure 6g An integrator is shown. Figure 6h A non-inverting comparator is shown, which allows adjacent transitions of the function curve.

[0095] Figure 7a Another example of a circuit with an operational amplifier is shown. This example allows an offset to be introduced into the signal as a bias implementation. In addition, any function can be implemented by adding resistors and / or capacitors and connecting with other operational amplifiers. Examples of these functions are Figure 7b As shown at 7h. Figure 7b A one-dimensional Gaussian clock is shown. Figure 7c The cone function is shown. Figure 7d A cylindrical function is shown. Figure 7eThe mexican hat function is shown. Figure 7f The hyperbolic tangent function is shown. Figure 7g The Fermi function with temperature parameter is shown.

[0096] The nodes of the hidden layer 12 can be implemented according to the state of the first trained digital artificial neural network 17. The state includes at least information about the digital nodes of the first trained digital artificial neural network 17 and information about the digital connection architecture between the digital nodes of the first trained digital artificial neural network 17. The state of each digital node of the first trained digital artificial neural network 17 is determined.

[0097] The information may include information about biases, transfer functions, activation functions and / or weights.The information about the digital connection architecture may include information about connections between nodes.

[0098] Information about the digital nodes of the first trained digital artificial neural network is used to design analog electronic nodes using analog circuits (such as those discussed above). Information about the digital connection architecture is used to design wires between nodes, thereby producing an analog connection architecture.

[0099] The analog electronic nodes and analog connection architecture are implemented as analog circuits on semiconductor chip 40 .

[0100] The analog electronic nodes and / or the analog connection architecture may include non-adaptive electronic components with fixed characteristics. In this case, the analog artificial neural network 10 cannot learn.

[0101] In order to provide a simulated artificial neural network 10 that can learn, the simulation circuit may include adaptive electronic components. These electronic components may have variable characteristics.

[0102] Since the analog artificial neural network 10 is based on a trained digital artificial neural network, only a few analog electronic nodes and / or parts of the analog connection architecture require such electronic components with variable characteristics.

[0103] These analog electronic nodes and / or parts of the analog connection architecture may be connected, for example, to digital potentiometers, capacitors diodes, etc., which are electronic components with variable characteristics. The controller may control these electronic components during the training of the simulated artificial neural network 10.

[0104] Figure 8 shows the use of a field effect transistor bypass resistor R L1 To R L3 This produces a variable resistor R LThe controller can control each field effect transistor individually using a control signal at the corresponding gate. Turning on the field effect transistor causes the corresponding resistor to be bypassed.

[0105] In the same way, the electrical connection 102, 103 between the nodes 101 can be established or interrupted, such as Figure 9a Circuit 104 shows a field effect transistor in wire 103. If the field effect transistor is turned off, the field effect transistor interrupts wire 103.

[0106] Figure 9b A line 103 with a circuit 104 is shown. Furthermore, the line 103 comprises a voltage divider 105. The voltage divider 105 serves as a weight for the signal propagating along the line 103. Therefore, in order to implement the weights of the digital nodes into an analog electronic circuit, it may be sufficient to implement these weights into an analog connection architecture. This simplifies the implementation of the analog artificial neural network 10.

[0107] For example, line 103 may include a plurality of different voltage dividers that may be switched by corresponding field effect transistors. The weight of line 103 may then be changed depending on which of the different voltage dividers are active and how many are active. This may be an exemplary way of training a simulated artificial neural network 10.

[0108] In order to train the simulated artificial neural network 10, the controller 35 may include a training algorithm that can be implemented as a digital artificial neural network. Then, the controller 35 may control the electronic components with variable characteristics to perform the training process. In the final training state, when the simulated artificial neural network 10 should process a signal, the controller 35 may provide a corresponding switching signal to the semiconductor chip 40.

[0109] Fig.10 A system 110 is shown, which comprises an input projection layer 111, a semiconductor chip 40 and a second digital artificial neural network 50. The second digital artificial neural network 50 may be a trained digital neural network.

[0110] In addition, the system 110 may include a controller 35 and an analog digital interface 112. The interface 112 receives the analog output signal of the semiconductor chip 40, that is, the output signal of the analog artificial neural network 10. The interface 112 converts the analog output signal into a digital signal and transmits it to the digital node of the second digital artificial neural network 50. The digital node may be arranged in the hidden layer of the second digital artificial neural network 50.

[0111] This results in the analog artificial neural network 10 being recursively coupled to the second digital artificial neural network 50 .

[0112] For example, the analog artificial neural network 10 may provide an output signal roughly classifying elements of the image 31 into dangerous elements and harmless elements. The second digital artificial neural network 50 may, for example, identify image elements of the image 31. The categories of image elements provided by the analog artificial neural network may affect the identification of image elements by the second digital artificial neural network.

[0113] The input projection layer 111 may feed input signals to both neural networks 10, 50. The input projection layer 111 may be the input layer 11 of the analog artificial neural network 10. The analog artificial neural network 10 simultaneously receives input signals from all nodes of the input layer 11. The second digital artificial neural network 50 receives input signals sequentially.

[0114] The controller 35 can synchronize the operation of the simulated artificial neural network 10 with the second digital artificial neural network 50. For example, when the second digital artificial neural network 50 starts to operate, the controller 35 can provide a start signal to the simulated artificial neural network 10. The start signal can cause the switching layer 31 to establish a connection between the input layer 11 and the first hidden layer 12 of the simulated artificial neural network. In addition, the controller 35 can reset the simulated artificial neural network 10 after the system 110 operates.

[0115] Fig.11 A flow chart of a method 120 for manufacturing a semiconductor chip is shown.

[0116] In a first step 121, a first trained digital artificial neural network is provided. The first trained digital artificial neural network performs a specific task with sufficient accuracy. The first trained digital artificial neural network is a software-based artificial neural network running on an IT platform.

[0117] The training of the first trained digital artificial neural network may be performed as known in the art using training data.

[0118] Then, in a further step 122, a state of the first trained digital artificial neural network is determined. The state comprises information about the digital nodes and digital connection architecture of the first trained digital artificial neural network.

[0119] The state characterizes the complete first trained digital artificial neural network, for example, the weights, transfer functions, activation functions and biases of the nodes. In addition, the state characterizes the connections between the digital nodes of the first trained digital artificial neural network, ie, the digital connection architecture.

[0120] In a further step 123, the semiconductor chip is manufactured. During the manufacturing process, an analog circuit is designed to form the simulated artificial neural network. The states of the first trained digital artificial neural network are implemented into the design of the simulated artificial neural network.

[0121] For example, the simulated artificial neural network may include simulated electronic nodes and simulated connection architectures between the simulated electronic nodes. The simulated electronic nodes are designed according to the digital nodes of the first trained digital artificial neural network. If the first trained digital artificial neural network includes a hidden layer with ten digital nodes, the simulated artificial neural network is implemented with a hidden layer with ten simulated nodes, which includes the same weights, transfer functions, activation functions and biases as the first trained artificial neural network.

[0122] Therefore, the analog connection architecture is designed according to the digital connection architecture. Thus, if a particular digital node is connected to a set of further digital nodes, the corresponding analog electronic node is connected to a set of corresponding analog electronic nodes.

[0123] The result of method 120 is a semiconductor chip as described above.

[0124] Fig.12 A flow chart of a method 130 for making a system having an analog artificial neural network recursively connected to a second digital artificial neural network is shown.

[0125] In step 131, the second digital artificial neural network is trained separately.

[0126] In a further step 132, a semiconductor chip with an individually trained simulated artificial neural network is provided. The semiconductor chip may include any number of individually trained simulated artificial neural networks.

[0127] Step 132 may be performed simultaneously with step 131. Alternatively, steps 131 and 132 may be performed in any order.

[0128] In order to provide a semiconductor chip with a separately trained analog artificial neural network, the analog artificial neural network may be trained. Alternatively, or in addition, a first trained digital artificial neural network may be trained before manufacturing the semiconductor chip.

[0129] In a further step 133, the semiconductor chip is recursively coupled to the separately trained second digital artificial neural network. An interface as described above can be used for the recursive coupling.

[0130] After step 133, the analog artificial neural network and the separately trained second digital artificial neural network are trained together in step 134. In this training, the separately trained second digital artificial neural network receives input from the analog artificial neural network.

[0131] The separate training of the simulated artificial neural network and / or of the first digital artificial neural network as a basis for the simulated artificial neural network can use the first training data set.

[0132] A separate training of the second digital artificial neural network may be performed using a separate second training data set.

[0133] The analog artificial neural network and the second digital artificial neural network are trained together using a third training data set.

[0134] Each training data set may be optimized for a specific training purpose, ie, a first training data set may be optimized to provide an output signal that may influence the operation of a second digital artificial neural network.

Claims

1. A system comprising an input projection layer (111), at least one second digital artificial neural network (50) and at least one semiconductor chip (40), the system being obtained by at least the following steps: - providing (121) a first trained digital artificial neural network (17); - determining (122) a state of the first trained digital artificial neural network (17), the state comprising at least information about digital nodes of the first trained digital artificial neural network (17) and information about a digital connection architecture between the digital nodes of the first trained digital artificial neural network (17); - manufacturing (123) a semiconductor chip (40) comprising an analog circuit having an analog artificial neural network (10), the analog artificial neural network (10) being designed according to the state of the first trained digital artificial neural network (17), in, The simulation circuit comprises at least one input (20) configured to receive at least one input signal and at least one output (26) configured to provide at least one simulated output signal, wherein the simulated artificial neural network (10) electrically connects the input (20) to the output (26), wherein the semiconductor chip (40), in particular the analog artificial neural network (10), is recursively coupled to a second digital artificial neural network (50), such that the output of the semiconductor chip (40) is provided to at least one hidden layer of the second digital artificial neural network (50), and wherein the input (20) of the semiconductor chip (40) and the input layer of the second digital artificial neural network (50) are electrically connected to the input projection layer (111).

2. The system according to claim 1, wherein: The analog artificial neural network (10) comprises analog electronic nodes and analog connection structures between the analog electronic nodes, wherein, in the step of manufacturing a semiconductor chip (40), the analog electronic nodes and the analog connection structures are manufactured to correspond to the digital nodes and the digital connection structures of the first trained digital artificial neural network (17).

3. The system according to claim 1 or 2, wherein: The simulated artificial neural network (10) comprises at least one simulated electronic switch (34) and / or at least one simulated electronic node.

4. The system according to claim 1, wherein: The input (20) comprises a sensor array configured to simultaneously provide a sensor data signal from each sensor (21, 23) of the sensor array to the simulated artificial neural network (10).

5. The system according to one of claims 1 to 4, wherein: The simulation circuit includes only electronic components with fixed characteristics, so that the simulated artificial neural network (10) cannot be trained.

6. The system according to one of claims 1 to 5, wherein: The simulation circuit comprises at least one electronic component having variable characteristics, making it possible to train the simulated artificial neural network (10).

7. The system according to one of claims 1 to 6, comprising at least one controller (35), the controller (35) being configured to provide at least one control signal to the semiconductor chip (40), the control signal preferably being an activation signal of a sensor array of the semiconductor chip (40), the controller (35) preferably comprising at least one of the following group: an analog electronic control circuit, a digital electronic control circuit, a control program, and a processor, wherein, The semiconductor chip (40) preferably further comprises a control input (36) configured to receive an enable signal, wherein further preferably, the sensor array is further configured to provide a sensor data signal upon receiving the enable signal.

8. The system according to one of claims 1 to 7, wherein: The system (110) further comprises at least one interface (112) for controlling and transmitting data, the interface (112) being configured to recursively couple the semiconductor chip (40) to the second digital artificial neural network (50), wherein the interface (112) is preferably configured to provide at least one analog control signal to the analog artificial neural network (10), wherein the interface (112) is further preferably configured to receive the analog output signal from the semiconductor chip (40) to generate a digital control signal from the analog output signal, and to provide at least one digital control signal to at least one digital node in at least one hidden layer of the second digital artificial neural network (50), so that the interface (112) recursively couples the semiconductor chip (40) to the second digital artificial neural network (50).

9. The system according to one of claims 1 to 8, wherein: The input projection layer (111) includes at least one of the following group: a pixel array, an olfactory sensor array, a pressure sensor array, an ultrasound sensor array, a temperature sensor array, and an acoustic sensor array.

10. Method for manufacturing a system according to one of claims 1 to 9, wherein: The method (130) comprises at least the following steps: - training (131) the second digital artificial neural network alone without providing the output of the analog artificial neural network to the second digital artificial neural network; - providing (132) a semiconductor chip having a separately trained analog artificial neural network, wherein the training of the analog artificial neural network is performed without providing an output of the analog artificial neural network to the second digital artificial neural network; - recursively connecting (133) the semiconductor chip to the separately trained second digital artificial neural network such that the output of the analog artificial neural network is provided to at least one hidden layer of the second digital artificial neural network; and - training (134) together the analog artificial neural network of the recursively connected semiconductor chips and the separately trained second digital artificial neural network.

11. The method according to claim 10, wherein: The step of providing (132) a separately trained simulated artificial neural network to a semiconductor chip comprises at least the following sub-steps: - Training said first digital artificial neural network alone (135).

12. The method according to claim 10 or 11, wherein: The first training data set is used to provide a separately trained analog artificial neural network for the semiconductor chip, wherein preferably the second digital artificial neural network is trained using the second training data set, and wherein further preferably the third training data set is used to train the analog artificial neural network and the separately trained second digital artificial neural network together.

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