Neural network-based method and apparatus

Abstract

Comprising a neural network method and device. A neural network circuit includes a synaptic memory cell including a resistive memory element arranged along an output line and may have a first resistance value and a second resistance value as resistance values, the synaptic memory cell generates a column signal based on a resistance value of the resistive memory element and an input signal received via the input line; a reference memory cell including a reference memory element arranged along a reference line and having a resistance value as a ratio of a first resistance value to a second resistance value, the reference memory cell generating a reference signal based on the input signal and the resistance value of the reference memory element; and an output circuit generating an output signal of the output line based on the column signal and a reference signal.

Description

Technical Field

[0001] This application claims the benefit of Korean Patent Application No. 10-2022-0033964, filed in the Korean Intellectual Property Office on March 18, 2022, under Section 119(a) of the U.S. Patent Act, and claims the benefit of U.S. Non-provisional Application No. 17 / 883,546, filed in the U.S. Patent and Trademark Office on August 8, 2022, under Section 119(e) of the U.S. Patent Act, and the entire disclosures of the Korean Patent Application and the U.S. Non-provisional application are incorporated herein by reference for all purposes.

[0002] The following description relates to neural network methods and apparatus. Background Art

[0003] In the current von Neumann computer architecture, the frequent movement of large amounts of data between the processor and the memory results in long delays and high power consumption, limiting chip performance. In machine learning applications, the movement of data (e.g., between layers of a neural network) can be a major aspect of the computational load. In view of the computational cost of implementing machine learning on the von Neumann architecture, artificial intelligence (AI) accelerator hardware can be used for current software-based deep neural network operations. This acceleration hardware can be, for example, a high-performance central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC).

[0004] As another example, a neuromorphic architecture may be used. The neuromorphic architecture may perform operations directly at the location of the storage data of the memory device, and may store and update the connection strength (e.g., synaptic weight) between neuron circuits in the memory device. The neuromorphic operation method may be applied to AI, big data, sensor networks, pattern recognition / object recognition, etc. The neuromorphic architecture may be implemented as hardware using analog memory. Summary of the invention

[0005] Technical Solution

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one general aspect, a neural network circuit includes: a synaptic memory cell including a resistive memory element arranged along an output line and configured to change between a first resistance value and a second resistance value having as resistance values, wherein the synaptic memory cell is configured to generate a column signal based on the resistance value of the resistive memory element and an input signal received via an input line; a reference memory cell including a reference memory element arranged along a reference line and having a resistance value that is a predetermined ratio of the first resistance value to the second resistance value, wherein the reference memory cell is configured to generate a reference signal based on the input signal and the resistance value of the reference memory element and the input signal; and an output circuit configured to generate an output signal of the output line based on the column signal and the reference signal.

[0008] The synapse memory cell may include a number of resistive memory elements corresponding to the number of bits for representing a synapse weight assigned to the synapse memory cell, wherein the number of resistive memory elements corresponding to the number of bits may be arranged along the input line.

[0009] The reference memory unit may include reference memory elements of a number corresponding to the number of bits for representing the synaptic weight, wherein the reference memory elements corresponding to the number of bits may be arranged along the input line.

[0010] The reference memory unit may include: a reference memory element for representing a sign bit.

[0011] The output circuit may also be configured to generate a current corresponding to a positive integer multiple of a net current as an output signal, wherein the net current may be a difference between a first current based on a resistive memory element having a first resistance value and a second current based on a resistive memory element having a second resistance value.

[0012] The output circuit may also be configured to generate a current corresponding to a negative integer multiple of a net current as an output signal, wherein the net current may be a difference between a first current based on a resistive memory element having a first resistance value and a second current based on a resistive memory element having a second resistance value.

[0013] The neural network circuit may include a neuron circuit, which may also include a synaptic memory unit, a reference memory unit and an output circuit, and wherein the output circuit may also include a leaky integrate-and-fire (LIF) circuit, which may be configured to perform firing at another neuron circuit based on a result of comparing the output signal with a threshold.

[0014] The LIF circuit may be further configured to increase the output voltage when the output signal corresponds to a positive integer multiple of the net current.

[0015] The LIF circuit may be further configured to reduce the output voltage when the output signal corresponds to a negative integer multiple of the net current.

[0016] The LIF circuit may be further configured to leak the output signal from a capacitor when a voltage based on the integration of the output signal does not reach a threshold voltage within a threshold time.

[0017] The LIF circuit may be further configured to: when a voltage based on the integration of the output signal reaches a threshold voltage within a threshold time corresponding to a threshold, perform firing at the other neuron circuit.

[0018] The output circuit may be further configured to set a threshold time corresponding to the threshold value according to a signal generated based on the threshold memory unit and a signal generated based on the additional reference memory unit.

[0019] The output circuit can also be configured to: initiate integration of a current corresponding to a difference between a signal generated based on a threshold memory cell and a signal generated based on an additional reference memory cell, and output a signal indicating a threshold time corresponding to a threshold, wherein the initiated processing can be based on a voltage corresponding to the integrated current exceeding a threshold voltage.

[0020] The output circuit may be further configured to apply a threshold time to the output signal of the output line and another output signal of another output line, the threshold time corresponding to a threshold determined based on the threshold memory unit and the additional reference memory unit.

[0021] The resistive memory elements of the synaptic memory cells connected to the output line may be connected in parallel to each other.

[0022] The synaptic memory cell may include a bit that may include a corresponding resistor, wherein the reference memory cell may include a bit that may also include a corresponding resistor, and wherein the output circuit may include a readout circuit, and the readout circuit may be configured to generate a column integrated signal by integrating a column signal for each bit of the synaptic memory cell, and to generate a reference integrated signal by integrating a reference signal for each bit of the reference memory cell.

[0023] The readout circuit may include a current mirror, and the current mirror may be configured to replicate the column signal of each bit of the synapse memory cell and the reference memory cell into a current multiple corresponding to the bit.

[0024] The output signal corresponds to the difference between the column integrated signal and the reference integrated signal.

[0025] The output circuit may also include a capacitor, which may be configured to allow a current corresponding to a reference integral signal to flow in a node and allow a current corresponding to a column integral signal to flow out of the node, so that a current corresponding to a difference between the column integral signal and the reference integral signal flows through the node, wherein the node may include the neural network circuit.

[0026] The neural network circuit may include a neuron circuit, and the neuron circuit may also include a synaptic memory unit, a reference memory unit and an output circuit, and wherein the output circuit may also be configured to: obtain a multiplication-accumulation (MAC) value between the synaptic weight and the input signal received along the input line based on the result obtained by parsing the output signal, and transmit a node value determined based on the obtained MAC value to another neuron circuit.

[0027] The ratio may be predetermined based on the application.

[0028] In one general aspect, a method for operating a neural network circuit includes: generating a column signal based on an input signal and a resistance value of a resistive memory element of a synaptic memory cell to which the input signal can be applied via an input line, wherein the synaptic memory cell is among one or more synaptic memory cells arranged along an output line; generating a reference signal based on the input signal and a reference memory element, the reference memory element having a reference resistance value of a reference memory cell to which the input signal is applied, wherein the reference memory cell is among one or more reference memory cells arranged along the reference line; and generating an output signal of an output line according to the column signal and the reference signal, wherein the reference resistance value is configured to be determined based on a combination of a first resistance value and a second resistance value different from the first resistance value.

[0029] The combination may be predetermined based on the application.

[0030] In one general aspect, a processor includes: a memory array including rows and columns of resistive memory cells, the resistive memory cells also including corresponding resistors, wherein each resistive memory cell of the memory array has a resistance that can be programmed to vary between a first resistance and a second resistance, wherein the columns of the memory array provide an integrated column current based on an input signal supplied to the corresponding resistive memory element of the column and based on the resistance of the individual memory elements of the column; and a reference array of resistive memory cells, the resistive memory cells also including corresponding resistors, wherein each resistive memory cell of the reference column has a resistance that can be programmed to vary between a first resistance and a second resistance, wherein the reference memory array provides an integrated reference current based on the input signal supplied to the resistive memory element of the reference array and based on the resistance of the individual memory elements of the reference array.

[0031] The memory cells of the memory array may be configured to store respective synaptic weights, and the reference array may not be configured to store synaptic weights.

[0032] The step of determining whether to output a fire signal may be based on a current difference between the integrated column current and the integrated reference current.

[0033] The processor may be configured to convert the current difference into a voltage, and determine whether to output a discharge signal by comparing the voltage with a threshold voltage.

[0034] The step of determining whether to output a fire signal may also be based on a current difference between an integrated current of the second reference column and an integrated current of the threshold column.

[0035] The step of determining whether to output a release signal may include determining a threshold voltage based on a current difference between an integrated current of a second reference column and an integrated current of a second reference column, and comparing the threshold voltage with a voltage based on a current difference between an integrated current of a column of a cross switch array and an integrated current of a reference array.

[0036] The integrated column current may correspond to a linear combination of first and second resistances stored in resistors of the column, and wherein the integrated current of the reference column may correspond to a linear combination of first and second resistances stored in resistors of the reference array.

[0037] The processor may further include a capacitor, and the processor may be configured to leak an output signal from the capacitor based on the integrated column current and the integrated reference current.

[0038] The processor may be configured to implement a spiking neural network using the memory array and the reference array.

[0039] The input signal may include a release or leakage signal provided from a second memory array of resistive memory cells.

[0040] The processor may be configured to implement a leak integration and release activation function that may be associated with the memory array.

[0041] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 An example of a neural network circuit is shown in accordance with one or more embodiments.

[0043] Figure 2 Examples of synaptic memory cells and readout circuits are shown in accordance with one or more embodiments.

[0044] Figure 3An example of a leaky integrate-fire (LIF) circuit of an output circuit is shown in accordance with one or more embodiments.

[0045] Figure 4 Examples of threshold generation circuits and additional reference circuits included in a neural network circuit are shown according to one or more embodiments.

[0046] Figure 5a An example of a net signal generated from a synaptic memory column and a reference column, a threshold generation column, and an additional reference column in accordance with one or more embodiments is shown.

[0047] Figure 5b An example of a net signal generated from a synaptic memory column and a reference column is shown in accordance with one or more embodiments.

[0048] Figure 5c An example of a firing comparison using a net signal generated from a synaptic memory column, a reference column, a threshold generation column, and an additional reference column is shown in accordance with one or more embodiments.

[0049] Figure 6a An example of a firing comparison using a net signal generated from a synaptic memory column, a reference column, a threshold generation column, and an additional reference column is shown in accordance with one or more embodiments.

[0050] Figure 6b An example of a net signal generated from a synaptic memory column and a reference column is shown in accordance with one or more embodiments.

[0051] Figure 6c An example of a leaky integral comparison using a net signal generated from a synaptic memory column, a reference column, a threshold generation column, and an additional reference column is shown in accordance with one or more embodiments.

[0052] Figure 7 An example of a threshold time generating circuit of an output circuit according to one or more embodiments is shown.

[0053] Figure 8 An example of elements included in a LIF circuit in an output circuit according to one or more embodiments and a timing diagram of each element are shown.

[0054] Fig. 9 An example of a firing operation of a neural network circuit according to one or more embodiments is shown.

[0055] Fig.10 An example of a method of operation of a neural network circuit according to one or more embodiments is shown.

[0056] Hereinafter, examples will be described in detail with reference to the accompanying drawings. When describing the examples with reference to the accompanying drawings, the same reference numerals denote the same components, and repeated descriptions thereof will be omitted. DETAILED DESCRIPTION

[0057] The following specific embodiments are provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is merely an example and is not limited to those order of operations set forth herein, but except for the operations that must occur in a specific order, the order of operations can be changed as will be clear after understanding the disclosure of the application. In addition, in order to increase clarity and simplicity, the description of features known after understanding the disclosure of the application can be omitted.

[0058] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein that will be clear after understanding the disclosure of the present application.

[0059] The terms used herein are only used to describe various examples and are not used to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more. As non-limiting examples, the terms "include", "comprise" and "have" specify the presence of the features, numbers, operations, components, elements and / or their combinations set forth, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or their combinations.

[0060] Throughout the specification, when a component or element is described as being "connected to," "coupled to," or "engaged to" another component or element, it may be directly "connected to," "coupled to," or "engaged to" another component or element, or one or more other components or elements may reasonably exist between them. When a component or element is described as being "directly connected to," "directly coupled to," or "directly engaged to" another component or element, there may not be other elements between them. Similarly, expressions such as "between" and "immediately between," as well as "adjacent to" and "immediately adjacent to" may also be interpreted as described above.

[0061] Although terms such as "first", "second" and "third", or A, B, (a), (b) may be used herein to describe various components, assemblies, regions, layers or parts, these components, assemblies, regions, layers or parts are not limited by these terms. Each of these terms is not used to define, for example, the essence, order or sequence of the corresponding component, component, region, layer or part, but is only used to distinguish the corresponding component, component, region, layer or part from other components, components, regions, layers or parts. Therefore, without departing from the teaching of the example, the first component, first component, first region, first layer or first part mentioned in the example described herein may also be referred to as the second component, second component, second region, second layer or second part.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the present disclosure belongs and generally understood after understanding the disclosure of the present application. Unless explicitly defined as such herein, terms (such as terms defined in general dictionaries) will be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of the present application, and are not interpreted in an idealized or overly formalized meaning. The use of the term "may" with respect to an example or embodiment herein (e.g., with respect to what an example or embodiment may include or may achieve) indicates that there is at least one example or embodiment that includes or achieves such a feature, but all examples are not limited thereto.

[0063] Figure 1 An example of a neural network circuit according to one or more embodiments is shown. The neural network circuit 100 may be implemented as a circuit for simulating a synapse that connects a neuron circuit of a previous layer in a neural network to a neuron circuit of a target layer. An electronic device including the neural network circuit 100 may also be referred to as a neural network device. The neuron circuit may include a circuit that implements the activation of a neuron and / or an activation function of a neural network. The neural network may include a plurality of layers, each layer having a plurality of nodes. With respect to any target layer in the neural network, the previous layer may be a layer connected before the target layer (e.g., with respect to forward propagation). The nodes of the neural network may correspond to the neuron circuits of the neural network circuit 100. The neural network circuit 100 may transmit a node value (e.g., an input value) output from a neuron circuit of a previous layer to an input of a neuron circuit of a target layer, and the node value received by the neuron circuit of the target layer may be based on the connection strength (e.g., synaptic weight) between the two neuron circuits. The target neuron circuit of the target layer may generate a result of applying the activation function to a weighted sum as a node output value, wherein the weighted sum is based on the synaptic weight value and the respective node values ​​received by the respective previous neuron circuits of the previous layer connected to the target neuron circuit.

[0064] In the present specification, the neuron circuit may be implemented as the output circuit 150, and the neuron circuit of the neural network circuit 100 may implement a spiking neural network (SNN) by including a leaky integrate-and-fire (LIF, or leaky integration and release) circuit. However, the example is not limited thereto, and the activation function of the neural network may also be implemented as a circuit designed in a different manner. Here, the activation function or the resulting activation value of the activation function is distinguished from whether the line or operator is active or inactive (e.g., whether the line has been activated or deactivated). However, for example, if a non-zero activation value output of a previous layer is applied to an input line, the input line may be considered to be active or activated, while if a zero activation value is applied to the line or no signal is applied to the line, the line may be considered to be inactive or deactivated.

[0065] The neural network circuit 100 may include a synaptic memory array 110, a reference memory array 120, and an output circuit 150. The synaptic memory array 110 and the reference memory array 120 may be collectively referred to as a memory array.

[0066] The synaptic memory array 110 may include a plurality of synaptic memory cells 111 arranged along input lines and output lines. The plurality of synaptic memory cells 111 may be arranged in the form of a crossbar switch array. The input line may be a line for receiving an input, and the output line may be a line for receiving an input. Figure 1 The word lines WL are shown as "K" in FIG. 0 To WL K-1 . "K" may be an integer greater than or equal to 1. The signals from each word line may each represent "0" or "1", and "0" or "1" may be the respective outputs of the K nodes of the previous layer. The output line may output an output signal 159, which represents the value (e.g., the result of a summation operation (e.g., a product result) between a synaptic weight (indicated by a resistive memory element (or referred to as a resistive memory element) of a synaptic memory unit 111 arranged along the output line) and an input value (indicated by each input signal) (e.g., a result value of a multiplication-accumulation (MAC) or a weighted sum). The output line is at Figure 1 , and “J” may be an integer greater than or equal to 1. Therefore, the synaptic memory array 110 may include “K×J” synaptic memory cells 111. For a given synaptic memory cell 111 in the j-th cell column (j from 1 to J) and the k-th cell row (k from 1 to K), the value stored by the given synaptic memory cell 111 may be the synaptic weight between the j-th node in the previous layer and the k-th node in the current layer / next layer. In other words, Figure 1The neural network circuit 100 may also be interpreted as a circuit in which synaptic connections connecting K previous nodes to J next nodes are implemented. When the synaptic weight is represented as "a" bits, each output line may include "a" bit lines. In this case, "a" may be an integer greater than or equal to 1. The output signal 159 output from the output line may be a difference signal between (i) a signal obtained by integrating a column signal (e.g., a bit column signal) generated by a bit line included in the output line and (ii) a signal obtained by integrating a reference signal generated by a reference line.

[0067] The input line may receive an input signal through a pre-synaptic circuit. Specifically, the pre-synaptic circuit may receive an output of a previous node of the neural network (e.g., a previous neuron circuit) and transmit the output to a synaptic memory element (e.g., a synaptic memory element) of the current node. Figure 1 The presynaptic circuit may also be referred to as the axonal circuit.

[0068] The output line may be connected to a post-synaptic circuit and may transmit a signal to the post-synaptic circuit corresponding to a MAC value calculated between the input signal and the respective synaptic weights of the synaptic memory elements connected to the output line. The post-synaptic circuit may emit or transmit an output signal 159 to the next node (e.g., the next synaptic circuit), the output signal 159 corresponding to the MAC value between the input signal and the synaptic weight (the column of the cell currently on the output line). The post-synaptic circuit may be represented as a dendrite circuit and may be implemented as a LIF circuit, examples of which are described below.

[0069] The input signal may be a signal received through an input line. In one example, if the neural network circuit 100 receives an input signal corresponding to a bit value "1" from the input line, an input voltage may be applied to the input line. In another example, when the input signal of the input line represents a bit value "0", the neural network circuit 100 may deactivate the input line. In other words, the neural network circuit 100 may not apply a voltage to the input line or may apply a voltage of 0 volts (V). However, the input voltage applied for each bit represented by the input signal is not limited to the aforementioned examples. Figure 1 In the example shown in , an activation value (e.g., a voltage corresponding to a bit value of "1") may be applied to "k" of the "K" input lines, and "k" may be an integer greater than 0 and less than or equal to K. In other words, for a given input, some of the input lines may be active ("1") while others may be inactive ("0").

[0070] Each synaptic memory cell 111 may include a resistive memory element, which is arranged along an output line and has a first resistance value or a second resistance value. The synaptic memory cells 111 may each include a number of resistive memory elements corresponding to the number of bits required to represent a synaptic weight assigned to the synaptic memory cell 111. The resistive memory elements (corresponding to the number of bits) of a given synaptic memory cell 111 may be arranged along the same input line of the given synaptic memory cell 111.

[0071] The synaptic memory cells 111 in the column may generate a column signal based on the corresponding resistive memory element and the input signal, and may do so in response to receiving the input signal through the input line. The first resistance value and / or the second resistance value may be mapped to a corresponding binary value. For example, the first resistance value and the second resistance value may indicate a bit value "0" or "1", respectively. For example, the first resistance value as a low resistance may represent a bit value "0", and the second resistance value as a high resistance may represent a bit value "1". However, the example is not limited thereto, and the bit values ​​mapped to the first resistance value and the second resistance value may vary according to the design.

[0072] When the synaptic weight is represented as a bit sequence including a plurality of bits, the synaptic memory unit 111 may include a plurality of subunits. For example, the synaptic weight may be represented as a bit sequence having "a" bits. For a synaptic weight of "a" bits, the synaptic memory unit 111 may include "a" subunits, respectively. The first subunit may have a resistance value of a bit value corresponding to a least significant bit (LSB) digit of the bit sequence, and the "a"th subunit may have a resistance value of a bit value corresponding to a most significant bit (MSB) digit of the bit sequence. Each of the "a" subunits of the unit may include a corresponding resistive memory element having a resistance value corresponding to a bit value of a bit digit among the bit digits forming the synaptic weight of the unit. The resistive memory element included in each of the "a" subunits may be set to have a resistance value having a bit value mapped to a corresponding bit digit. Each resistive memory element may be set to have a first resistance value or a second resistance value. Reference Figure 2 An example of the synaptic memory cell 111 being implemented as a 3-bit cell is described.

[0073] The column signal may be a signal obtained by integrating a signal provided by the synaptic memory cell 111 arranged along the corresponding column line in the synaptic memory array 110. For example, the column signal may be a signal corresponding to a MAC value between an input value of an input signal and a bit value stored in a resistive memory element of a sub-unit of the same bit line in the column line connected to the synaptic memory array 110. In other words, the column signal of the bit line may be a signal corresponding to a MAC value of a bit number represented by the bit line in the output line. As described below, the neural network circuit 100 may obtain a signal by multiplying each of the column signals of the bit lines included in the same output line by each of the weights (hereinafter, referred to as "bit weights") corresponding to the bit numbers of the bit lines included therein and summing the multiplication result values. For example, the bit weight corresponding to the LSB may be 1 / 4, the bit weight corresponding to the first bit number from the LSB may be 1 / 2, and the bit weight corresponding to the second bit number from the LSB may be 1. This example is designed under the assumption that the second bit number from the LSB is the MSB and its bit weight is 1. However, the bit weight is not limited to the aforementioned example and may vary according to the design. For ease of description, in this specification, the columns are mainly shown as vertical lines. However, the example is not limited thereto, and the shape of the column lines may vary according to design.

[0074] As described above, the resistive memory element may be an element that may have a first resistance value or a second resistance value. For example, the resistive memory element may be a magnetic random access memory (MRAM) element. The MRAM element may have any of two states of a magnetic tunnel junction (MTJ). The MRAM element in the parallel (P) state may have a first resistance value, and the MRAM element in the antiparallel (AP) state may have a second resistance value. The second resistance value may be greater than the first resistance value. The second resistance value and the first resistance value may be referred to as a high resistance value and a low resistance value, respectively. The AP state and the P state may also be referred to as a high resistance state and a low resistance state, respectively. For example, the resistance ratio of the second resistance value of the MRAM to the first resistance value may be 2. However, the resistance ratio of the resistive memory element is not limited to the aforementioned example, and may vary according to the type of the resistive memory element, design parameters, etc. The neural network circuit 100 may generate a net signal (netsignal) by using the reference memory array 120 described below to distinguish signals output based on the first resistance value and the second resistance value of the resistive memory element.

[0075] For ease of description, in this specification, the resistive memory element in the P state and the AP state is mainly described, but the example is not limited thereto. Unless otherwise described, the P state and the AP state can be interpreted as a state with a first resistance value and a state with a second resistance value, respectively.

[0076] The reference memory array 120 may include a plurality of reference memory cells 121 arranged along reference lines. The reference memory array 120 may include the same number of reference memory cells 121 as the number of input lines (input bit lines), ie, there may be K reference memory cells 121.

[0077] The reference memory cells 121 may be arranged along a reference line, and may each include a reference memory element (or referred to as a reference memory element) having a programmable resistance value that can be programmed based on an application. In this case, having a "programmable" resistance value may mean that the resistance value is variously variable. Each reference memory cell 121 may include a number of reference memory elements corresponding to the number of bits used to represent a synaptic weight. For a given reference cell, its reference memory element (corresponding to the number of bits of the synaptic weight) may be arranged along the same input line corresponding to the given reference cell.

[0078] In one example, similar to the above-described synaptic memory cell 111, each reference memory cell 121 may include the same number of reference sub-cells as the number of bits; in other words, the number of resistive memory elements is the same as the number of bits. In this case, the reference memory cell 121 may include a resistive memory element set to a resistance value predetermined between a first resistance value and a second resistance value.

[0079] In another example, regardless of the number of bits of the synapse memory cell 111 , each reference memory cell 121 may be a 1-bit cell for storing a single bit of information (eg, a sign bit).

[0080] A given reference memory cell 121 may contribute to a reference signal of the reference memory array 120 based on a reference memory element of a given memory cell and based on an input signal. The reference signal may be a signal obtained by integrating a signal output from each of the reference memory cells 121 arranged along a reference line in the reference memory array 120. The reference line may include the same number of reference bit lines as the number of bits in each reference cell. For example, the reference signal may be a signal corresponding to a MAC value calculated between an input value of the input signal and a bit value corresponding to a resistive memory element of a reference sub-cell in the reference memory array 120 connected to the same reference bit line (e.g., reference bit lines). Figure 2 In other words, the reference signal of the reference bit line may be a signal corresponding to the MAC value of the bit number represented by the reference bit line in the reference line.

[0081] The output circuit 150 may generate an output signal 159 of the output line according to the column signal and the reference signal. For reference, the neural network circuit 100 may further include other synaptic memory cells arranged along another output line (e.g., another column of the synaptic memory array 110). In this case, the output circuit 150 may generate the respective output signals of the output line and the other output line respectively by using the same reference memory cell. In other words, the output circuit 150 may generate different output signals for each output line respectively using the same reference column signal. The operation of the output circuit 150 is described below.

[0082] When performing a synaptic operation (e.g., generating J 0 / 1 output signals in response to K 0 / 1 input signals from K previous nodes), the neural network circuit 100 may integrate all signals (e.g., current signals) generated for each column when an input (of "1") is provided to "K" word lines to access each synaptic memory element. Each output line may include respective bit lines corresponding to a bit number, and the column integration signal I output from a given output line may be a bit line corresponding to a bit number. Cells It can be a signal obtained by integrating the component column signals obtained by applying the bit weights to the column signals of the individual bit lines. Such a column integrated signal I Cells It can be expressed as Equation 1.

[0083] Equation 1

[0084] I cells =MI P +(NM)I AP

[0085] In equation 1, I P represents the current flowing in the resistive memory element in the P state (eg, the first resistance value), and I AP The column integrated signal I represents the current flowing in the resistive memory element in the AP state (eg, the second resistance value). Cells It can be I P and I AP The synaptic readout circuit 151 of the output circuit 150 may generate a column integration signal I Cells .

[0086] As expressed in Equation 2, the reference integrated signal I of the reference array (eg, reference array 120) can be obtained in a similar manner: Ref .

[0087] Equation 2

[0088] I REF =XI P +(NX)IAP

[0089] Equation 2 represents a signal obtained by applying the bit weight of each bit number to the current signal flowing in the resistive memory element to which the "1" (activated) input signal is applied, for each resistive memory element among the resistive memory elements included in the reference memory array 120. REF It may be a signal integrated by applying a bit weight to a reference signal for each bit number. In this case, X may be determined as any integer less than or equal to N and greater than or equal to 0 based on the application. When each reference memory cell 121 is a 1-bit cell, X may have a value of 0 or N.

[0090] The reference readout circuit 152 of the output circuit 150 can generate a reference integrated signal I REF In the above-mentioned Equation 1 and Equation 2, coefficients N and M of the linear combination may be expressed as in the following Equation 3 and Equation 4.

[0091] Equation 3

[0092] N=k·(2 a -1)

[0093] Equation 4

[0094] Where M≤N,m ij =0 or 1

[0095] N represents a value determined based on the sub-cells connected to any k word lines that are activated. As described above, the variable k represents the number of activated (e.g., "1") word lines (e.g., input lines) among the K word lines / input lines. The variable "a" may be the number of sub-cells included in each memory cell (i.e., the number of bits of the synaptic weight). For example, N may be the sum of powers of 2 using the number of bits represented by each sub-cell included in the "synaptic memory cell 111 connected to the activated word line among the synaptic memory cells 111 connected to the output line" as an exponent. M is an integer less than or equal to N, and M may be a value determined based on (and reflecting) the number of sub-cells in the P state (e.g., the first resistance value) among the synaptic memory cells 111 connected to the k-adjusted activated word line. For example, when the i-th synaptic memory sub-cell of the activated j-th word line has the first resistance value, m ij may be 1, and when the i-th synaptic memory sub-unit of the j-th word line has the second resistance value, m ijIt may be 0. For example, M may be the sum of powers of 2 using the number of bits represented by the sub-cells in the P state included in the “synaptic memory cell 111 connected to the activated word line among the synaptic memory cells 111 connected to the output line” as an exponent. In summary, N may be proportional to the number of bits with respect to the activated input line, and M may be proportional to the number of bits with respect to the activated input line in the P state (e.g., “1”).

[0096] Net signal I net,column (i.e., the integral column signal I Cells and the integrated reference signal I REF The net signal), can be generated as discussed below with reference to Equation 5.

[0097] Equation 5

[0098] I net,column =I Cells -I REF =(MX)(I P -I AP )

[0099] Based on Equation 5, the output circuit 150 of the neural network circuit 100 can generate the column integration signal I Cells With the reference integral signal I REF (The net column integrated signal I Cells With the reference integral signal I REF ) corresponds to the output signal 159I net,column Note that in some embodiments, signal I net,column The signal may not be the signal finally output by the output circuit 150, but may be the signal output by the LIF circuit (eg, Figure 3 The LIF circuit 260 in the embodiment is processed to control whether a fire-and-reset event occurs.

[0100] The first current I P (resistive memory element based on the first resistance value) and the second current I AP The difference I between the resistance memory element (based on the second resistance value) and P -I AP Can be called the effective signal or the net signal. Optionally, because the difference I P -I AP It can be a current (I) signal, so the difference can be called the net current. In this case, the output signal 159I net,column It corresponds to MX times the net signal. Depending on the value of X, MX can be a positive or negative integer, so MX can be used for IPSP and EPSP as described below.

[0101] In the present specification, in some embodiments, the neural network circuit 100 may implement an SNN that simulates the function of a natural neural network by integrating a current based on a synaptic weight, but the example is not limited thereto. The neural network circuit 100 may also be applied to a system that implements a MAC operation, such as a computation in memory (CIM) circuit and a vector matrix product (VMM) circuit that use a memory having a relatively low resistance ratio (and therefore having lower power consumption). Although the resistance ratio between the low resistance and the high resistance of a resistive memory element may be used in some embodiments of the neural network circuit 100, the output values ​​may be distinguished from each other using the “above-mentioned net signal that may be based on a reference signal”. In some embodiments of the neural network circuit 100, even when a resistive memory element having a resistance ratio of a second resistance value to a first resistance value exceeding 1 is used, the output values ​​may be distinguished from each other by the net signal. Therefore, there may be fewer design restrictions for sensing and summing the current to be output from a memory array, such as a cross-switch MRAM.

[0102] Therefore, the neural network circuit 100 can have a memory array with an increased size by offsetting the high resistance state. In addition, the neural network circuit 100 can be applied to an artificial intelligence processor that processes a large amount of data.

[0103] In addition, as described in detail below, in some embodiments, the neural network circuit 100 can use the synaptic memory array 110 to implement an excitatory postsynaptic potential (EPSP) and an inhibitory postsynaptic potential (IPSP), in which the potential increases based on the input stimulus and in which the potential decreases based on the input, which is similar to the response of a natural neural network. More specifically, in some embodiments, the neural network circuit 100 can implement an output signal 159I net,column An ESPS that increases voltage in response to stimulation in proportion to a positive multiple of the net signal and can achieve output signal 159I net,column An IPSP whose voltage decreases in response to stimulation is proportional to the net signal of a negative multiple.

[0104] For reference, although the present specification describes an example of the output circuit 150 including a LIF circuit as an activation function circuit, the example is not limited thereto. For example, instead of the LIF circuit, the neural network circuit 100 may include an analog-to-digital converter for converting the above-mentioned output signal from an analog signal to a digital value (e.g., output data). An electronic device including the neural network circuit 100 may also determine a value to be propagated to the next node by applying an activation function to such output data. In other words, the electronic device may also perform an operation corresponding to a digital activation function.

[0105] Figure 2An example of a synaptic memory cell and a readout circuit according to one or more embodiments is shown. The output circuit of the neural network circuit may include a LIF circuit 260 and a synaptic readout circuit 251 connected to a synaptic memory array 210, which may be, for example, Figure 1 The output circuit may also include a reference readout circuit 152 connected to the reference memory array. In general, the synaptic readout circuit 251 refers to Figure 2 is described, and the reference readout circuit 152 may be configured similarly to how the synaptic readout circuit 251 is configured.

[0106] like Figure 2 As shown in , the resistive memory elements of the synaptic memory cell 211 connected to the same output line may be connected in parallel with each other. For example, the synaptic memory cell 211 may be implemented as Figure 1 For example, the resistive memory elements connected to the same bit line among the synaptic memory cells 211 connected to the same output line may be connected in parallel to each other. Therefore, the current signals output from the resistive memory elements connected to the same bit line may be integrated along the corresponding output line. Figure 2 In the resistive memory element, the resistance is represented by R DATA As mentioned above, through the word line WL 0 To WL K-1 Each resistive memory element of each cell (elements arranged along the bit lines BL0 to BL2) to which an input signal is applied may output respective current signals based on “the voltage applied to the corresponding resistive memory element and the resistance value of the corresponding resistive memory element”. 0 To WL K-1 is applied, the switch SW data Can be connected.

[0107] The switch SWsense (e.g., a transistor) may connect the resistive memory element to the sense line. In this case, when the signal Sel_data is applied, the switch SWsense (e.g., a transistor) may be turned on. Therefore, when the input signal is supplied, the first, second, and third bit lines BL0 to BL2 and the sense line SL may be connected to a power supply voltage and ground, respectively.

[0108] The operational amplifier OP may have a high gain and may fix the voltages of the first, second, and third bit lines BL0 to BL2 to V regardless of the resistance values ​​between the sensing line SL and the first, second, and third bit lines BL0 to BL2. amp,refIn other words, a constant voltage difference between the sensing line SL and the first, second, and third bit lines BL0 to BL2 can be maintained. Regarding the fixed voltage V (samely applied to the end of each resistive memory element) amp,ref The resistive memory element can output a signal based on the resistor R on the first bit line, the second bit line, and the third bit line BL0 to BL2. DATA Determine the individual currents (eg, column signals).

[0109] The synaptic readout circuit 251 of the output circuit may include a current mirror configured to copy the column signal of each bit of the reference memory cell and each bit of the synaptic memory cell 211 to a current that is a multiple of the corresponding current. For example, the current mirror of the readout circuit 251 may copy the column signal generated in the bit lines BL0 to BL2 to the corresponding other bit lines BL'0 to BL'2, and the signals to BL'0 to BL'2 may have an amplitude that varies according to the current mirror. The amplitude of the copied current may vary according to the width of the transistor. As described above, the current mirror may copy the column signal at a current copy ratio corresponding to the bit weight. For example, in Figure 2 In the embodiment, the first bit line BL0, the second bit line BL1 and the third bit line BL3 may have their corresponding currents copied by corresponding weights ×1 / 4, ×1 / 2 and ×1.

[0110] The readout circuit 251 of the output circuit can generate a column integration signal I by integrating the column signal of each bit of each synaptic memory cell 211. Cells , and a reference integrated signal I can be generated by integrating the reference signal of each bit of each reference memory cell. REF For example, the output circuit can generate the column integrated signal I by summing the current copied from the column signal Cells The output circuit can generate a reference integrated signal I for the reference signal by using a reference readout circuit 152 having a structure identical or similar to that of the synaptic readout circuit 251 and the corresponding operation as described above. REF For reference, when the resistive memory element is implemented as an MRAM element, read disturbance may not occur when a small current flows through the MTJ. Therefore, an amplifier capable of handling a relatively low common input may be required. The output circuit may be based on the column integration signal I Cells and the reference integral signal I REF Generates output signal (I net,column ), and may further include a LIF circuit 260, which is configured to process the generated output signal. The structure and operation of the LIF circuit 260 are described below.

[0111] According to the output circuit of the synaptic readout circuit 251 described above, by using the output signal I net,column (which is the column integration signal ICells With the reference integral signal I REF The difference between the reference integrated signal I and the reference integrated signal I can accurately distinguish signals when there is one resistive memory element in the P state and a plurality of resistive memory elements in the AP state. REF Generated using a reference memory element having a programmable resistance value, the output signal may have a value corresponding to a negative integer multiple of the net signal in addition to a positive integer multiple of the net signal. Thus, the output circuit may represent an IPSP in addition to an EPSP.

[0112] In other words, since the net signal is positive, when the output signal is a positive integer multiple of the net signal, it can be interpreted as the column integral signal I Cells Greater than the reference integral signal I REF (useful for EPSP), and when the output signal is a negative integer multiple of the net signal, it can be interpreted as the column integral signal I Cells Less than the reference integral signal I REF (Useful for IPSP).

[0113] As mentioned above Figure 2 As described above, the output signal can read the resistance value of the resistive memory element included in the synaptic memory array through the readout circuit 251 of the output circuit. Figure 3 As described, the release may be performed by using the output signal.

[0114] Figure 3 An example of a LIF circuit of an output circuit according to one or more embodiments is shown.

[0115] The output circuit 150 may include a LIF circuit 260. The LIF circuit 260 may be a circuit for simulating a neuron pulse operation, and based on the result of comparing the output signal 159 with a threshold value, the LIF circuit 260 may perform an output that is emitted, and the output that is emitted is provided as an input of another neuron circuit (e.g., as an input of a word of another neuron circuit). The output signal 159 is I described above in Equation 5. net,column The LIF circuit 260 may include a leakage sub-circuit 361 and a release sub-circuit 362 .

[0116] The postsynaptic potential may include an EPSP in which the voltage increases in response to a stimulus and an IPSP in which the voltage decreases in response to a stimulus. When a stimulus exceeding a threshold is transmitted from a front neuron to a rear neuron, or when a plurality of stimuli less than or equal to a threshold are transmitted multiple times in a short period of time and the corresponding cumulative stimulus exceeds a threshold, an action potential may occur in the neuron. After the neuron (and discharge) exceeding the threshold, the membrane potential of the neuron may be reset to a base voltage. However, when a stimulus less than or equal to a threshold is transmitted from a front neuron to a rear neuron, a postsynaptic potential (PSP) may occur instead of an action potential, and in the PSP, a gradual leakage may occur until the next stimulus is applied. The LIF circuit 260 may be a circuit for realizing the discharge or leakage of the above-mentioned artificial neuron.

[0117] The leakage subcircuit 361 can receive the above reference Figure 2 The column integrated signal and the reference integrated signal are described. Figure 3 For ease of description, the column integrated signal and the reference integrated signal are modeled and shown as current sources I Cells and I REF The column integral signal and the reference integral signal can actually be respectively Figure 2 The synaptic readout circuit 251 shown in FIG. 1 and the reference readout circuit 152 of similar configuration may supply current. The leakage subcircuit 361 may include a capacitor that provides leakage. For example, the output signal 159 may allow a current corresponding to the reference integrated signal to flow in a node of the capacitor, and may allow a current corresponding to the column integrated signal to flow out of the same node of the capacitor. The inflow of the reference integrated signal and the outflow of the column integrated signal may allow a current corresponding to the difference between the column integrated signal and the reference integrated signal to flow into the capacitor.

[0118] The output circuit 150 may generate a current corresponding to an integer multiple of a net current as an output signal 159, the net current being the difference between a first current IP (based on a resistive memory element having a first resistance value) and a second current IAP (based on a resistive memory element having a second resistance value). The leakage subcircuit 361 may be deactivated when the reset signal RESET is applied, and may be activated when the reset signal RESET is released from application. In other words, the leakage subcircuit 361 may leak an output current based on the output signal 159 within a threshold time after the reset signal RESET is released from application.

[0119] The output current of the output signal 159 can be converted into an output voltage by flowing into the capacitor. The leakage operational amplifier OP of the leakage subcircuit 361 integ The leakage operational amplifier OP may be connected to a window switch at the output terminal, and the window switch may be connected to a capacitor connected to ground. When the window signal WINDOW is applied to the window switch, the leakage operational amplifier OP integcan be connected to a capacitor connected to ground. Therefore, the output current of the output signal 159 can be in the capacitor connected to ground and in the leakage operational amplifier OP integ The capacitor connected to the ground can convert the output current into an output voltage by leaking the charge based on the output current. In this case, the voltage charged in the capacitor connected to the ground can be leaked by the leakage transistor LEAKAGE.

[0120] Based on V CM_COLOUMN_IN The bias voltage of may be applied to the leakage transistor LEAKAGE. The window switch may be turned on for a predetermined threshold time (eg, leakage time) by the window signal WINDOW. In other words, the capacitor connected to the ground may leak the output current after reset until the threshold time elapses.

[0121] The leakage sub-circuit 361 can transmit the output voltage leaked within the threshold time to the emission sub-circuit 362. fire The predetermined threshold voltage V TH With output voltage V COLUMN For example, when the output voltage V integrated within the threshold time COLUMN Exceeding the threshold voltage V TH When the comparator OP fire The output signal (eg, 1) can be output, and when the output voltage V COLUMN Less than or equal to the threshold voltage V TH When , a leakage signal (eg, 0) may be output.

[0122] For reference, as described below, the threshold time may be set by a separate circuit (e.g., a threshold time generation circuit) to be “suitable for achieving the threshold voltage V by leaking a threshold current corresponding to the threshold value”. TH " time. The output current and the threshold current are both currents, and comparing one current to another current may be challenging. Therefore, the comparator OP of the issuing sub-circuit 362 fire The voltage converted from the current leaked within the threshold time may be compared with the threshold voltage, the threshold time being a value obtained from (i) the RESET signal based on the WINDOW signal (hereinafter referred to as Figure 7 Description) becomes 0 to (ii) when the signal WINDOW becomes 0. When the amount of current is small, the amount of current converted to voltage may also be small, and the voltage may therefore be less than the threshold voltage. Conversely, when the amount of current is large, the amount of current converted to voltage may also be large, and the voltage may therefore be greater than or equal to the threshold voltage. Therefore, the comparator OP fire Can output pulses.

[0123] In response to a voltage (VCOLUMN ) does not reach the threshold voltage within the threshold time, the LIF circuit 260 may leak the output signal 159. For example, when the leaked output voltage is less than the threshold voltage, the issuing sub-circuit 362 of the LIF circuit 260 may transmit the output voltage to the leakage operational amplifier OP integ The analog multiplexer (MUX) can provide the output voltage as a leakage operational amplifier OP integ The new common-mode input V CM_COLUMN When the output signal 159 is generated based on the next neuron input, the leakage subcircuit 361 can be generated by using the common mode input V CM_COLUMN The output current continues to leak to obtain the leakage output voltage.

[0124] In response to the voltage integrated based on the output signal 159 reaching the threshold voltage within the threshold time corresponding to the threshold, the LIF circuit 260 may perform a discharge, which is output to another neuron circuit. For example, when the leaked output voltage exceeds the threshold voltage, or when the leaked voltage of a plurality of small output signals (e.g., the output signal 159) exceeds the threshold voltage, the comparator OP of the discharge sub-circuit 362 may discharge the comparator OP of the discharge sub-circuit 362. fire A release signal may be generated. The release signal may be a pulse output indicating release. Based on an analog amplifier synchronized with a clock signal, the release signal may be transmitted through a trigger circuit and a comparator OP fire A signal generated in synchronization with a clock signal.

[0125] The issuing sub-circuit 362 can control the selection signal SEL of the analog MUX circuit and set V CM_COLUMN_IN The input is sent externally to the leakage operational amplifier OP integ to initialize the common-mode voltage.

[0126] The output circuit 150 may classify the operation into integration, comparison, and leakage for each circuit and perform the corresponding operation. Therefore, the error caused by the limitation of the leakage current or the size of the capacitor may be reduced in the output circuit 150. In addition, the output circuit 150 may stimulate the discharge in milliseconds (ms), which is the time interval for stimulating the biological body.

[0127] exist Figure 3 In the embodiment, the signal RESET and the signal SW may be generated by a timing generator that receives an external clock signal Clk as a control signal. A threshold time generation circuit (described below) may generate a window signal WINDOW indicating a threshold time that may determine whether the release is performed. The window signal WINDOW may provide a threshold time (e.g., an integration time) that is robust to changes in the set threshold voltage, the resistive memory element, and the capacitor.

[0128] Figure 4Examples of threshold generation circuits and additional reference circuits included in a neural network circuit are shown according to one or more embodiments.

[0129] The neural network circuit may also include a circuit for setting a threshold. For example, the neural network circuit may also include a threshold memory array 480 and an additional reference memory array 490. Figure 1 A synaptic memory array 110 and a reference memory array 120 are depicted.

[0130] The threshold memory array 480 may include a plurality of memory elements. At least one memory element (specified based on a set threshold value among the plurality of memory elements in the threshold memory array 480) may have a first resistance value (eg, a P state). Figure 4 In the embodiment of the present invention, the memory cell included in the threshold memory array 480 can be a threshold memory cell and can be represented by Th. For example, the memory element used to represent the threshold value can be selected based on the bit number. In other words, the threshold value can be represented based on the number of memory elements having the first resistance value and the bit number represented by the memory element.

[0131] The threshold memory array 480 may include threshold memory cells arranged along column lines. The column lines may include a plurality of bit lines representing a plurality of bits. Each of the threshold memory cells may include a sub-cell for each bit line, respectively. For example, when the threshold is set to a threshold current of 6IP, a memory element corresponding to a first digit (e.g., 21=2) of the LSB from the threshold memory array 480 and a memory element corresponding to a second digit (e.g., 22=4) of the LSB may have a first resistance value, thereby representing (2+4)×IP.

[0132] The additional reference memory cell may share reference word lines Ref_WL0 to Ref_WLL-1 with the threshold generation circuit. The additional reference memory cell may have an additional reference memory element that is arranged along the reference word line and has a second resistance value. The additional reference memory element of the additional reference memory cell of the additional reference memory array 490 may have a programmable resistance value that can be programmed based on the application. The additional reference memory cell described below can be used to represent the specified threshold in the above-mentioned threshold memory array 480 as a net signal.

[0133] For example, a signal integrated along a column of the above-described threshold memory array 480 (hereinafter, referred to as a “threshold integrated signal”) may be expressed as in Equation 6 below.

[0134] Equation 6

[0135] I Th =TI P +(RT)IAP

[0136] In equation 6 above, I P represents the current flowing in the resistive memory element in the P state (eg, the first resistance value), and I AP represents the current flowing in the resistive memory element in the AP state (eg, the second resistance value). The threshold integrated signal I Th It can be I P and I AP The second readout circuit 452 of the output circuit 450 can generate a threshold integration signal I Th .

[0137] Equation 7

[0138] I REF,Th =YI P +(RY)I AP

[0139] Equation 7 represents a signal obtained by applying the bit weight of each bit number to the current signal flowing in the resistive memory element to which the reference word signal is applied among the resistive memory elements included in the additional reference memory array 490. Additional reference integrated signal I REF,Th It may be a signal integrated by applying a bit weight to a reference signal of each bit number. In this case, Y may be determined as an integer less than or equal to R and greater than or equal to 0 based on the application. When the additional reference memory array 490 is configured with a 1-bit cell, Y may have a value of 0 or R.

[0140] The second readout circuit 452 of the output circuit 450 can generate an additional reference integrated signal I REF,Th In Equation 6 and Equation 7, coefficients T and R of the linear combination may be expressed as in Equation 8 and Equation 9 below.

[0141] Equation 8

[0142] R=L·(2 a -1)

[0143] Equation 9

[0144] Where T≤R,t ij =0 or 1

[0145] R represents a value determined based on a sub-cell connected to an activated reference word line. L represents the number of activated reference word lines. Figure 4An example is shown in which all reference word lines are activated. The variable "a" may be the number of sub-units included in each memory cell or the number of bits of the synaptic weight. For example, R may be the sum of values ​​raised to the power of 2 using the bit number represented by each sub-unit included in "reference memory cells connected to the activated reference word line among the threshold memory cells connected along the column" as an exponent. T may be an integer less than or equal to R and may be a value determined based on the sub-units in the P state (e.g., a first resistance value) among the threshold memory cells connected to the activated reference word line. T may correspond to a preset threshold. When the i-th threshold memory sub-unit of the activated j-th word line has a first resistance value, the variable t ij can be 1, and when the activated i-th threshold memory sub-cell of the j-th word line has the second resistance value, the variable t ij It may be 0. For example, T may be the sum of "k" values ​​of powers of 2 using the bit number represented by the sub-cells in the P state in the threshold memory cells connected to the same column as exponents.

[0146] Equation 10

[0147] I net,Th =I Th -I REF,Th =(TY)(I P -I AP )

[0148] The output circuit 450 of the neural network circuit can generate a threshold integrated signal I according to the above equation 10. Th With the additional reference integral signal I REF,Th The difference between the corresponding threshold net signal I net,Th The output circuit 450 can convert the threshold net signal I obtained based on equation 10 into net,Th and from the first readout circuit 451 (eg, including Figure 1 The output signal I obtained by the synaptic readout circuit 151 and the reference readout circuit 152 net,column However, the current-to-current comparison is not easily implemented in the circuit described above, and the output circuit 450 may further include a threshold time generation circuit configured to indirectly convert the output signal I net,column The net signal with threshold I net,Th For comparison. Figure 7 Describe the threshold time generation circuit.

[0149] The output circuit 450 may apply a threshold time corresponding to the “threshold determined based on the threshold memory cell and the additional reference memory cell” to an output signal of the output line and another output signal of the output line. In other words, the output circuit 450 may apply a threshold time corresponding to a common threshold to an output signal obtained from an output line of the synaptic memory array.

[0150] Figure 5a to Figure 5c An example of a firing comparison using a net signal generated from a synaptic memory column, a reference column, a threshold generation column, and an additional reference column is shown.

[0151] exist Figure 5a , one column in the synaptic memory array is shown as a synaptic memory column 510. In addition, one column in the reference memory array is shown as a reference column 520. One column in the threshold memory array is shown as a threshold generation column 580. One column in the additional reference memory array is shown as an additional reference column 590. For ease of description, each column may include, for example, 3-bit bit lines, and an input signal may be applied to one input line.

[0152] For example, the third sub-unit of the synaptic memory column 510 may have a resistive memory element set to a second resistance value (e.g., AP), and the first and second sub-units of the synaptic memory column 510 may have resistive memory elements set to a first resistance value (e.g., P), respectively. The first and third sub-units of the reference column 520 may have memory elements set to a second resistance value (e.g., AP), and the second sub-unit of the reference column 520 may have a memory element set to a first resistance value (e.g., P). However, the resistance value of each of the first, second, and third sub-units of the reference column 520 is not limited to the aforementioned examples, and may be variously changed based on the application.

[0153] The first subunit, the second subunit, and the third subunit may generate a current signal to which a bit weight corresponding to the LSB (e.g., multiplied by 1), a bit weight corresponding to the first digit from the LSB (e.g., multiplied by 2), and a bit weight corresponding to the second digit from the LSB (e.g., multiplied by 4) are applied, respectively. Cells It can be (2+4)×I P +1×I AP The reference integrated signal I of the reference column 520 REF Can be 2×I P +(1+4)×I AP . Output signal I net,column It can be 4 (I P -I AP ). Since the output signal I net,column is a positive number, so the output signal Inet,column Can be interpreted as an output signal for performing EPSP operation.

[0154] Similarly, the threshold integrated signal I in the threshold generation column 580 Th Can be 2×I AP +(1+4)×I P =5I P +2I AP The additional reference integrated signal I generated in the additional reference column 590 REF,Th Can be 2×I P +(1+4)×I AP =2I P +5I AP .exist Figure 5a In the threshold net signal I net,Th Can be determined as 3(I P -I AP ). Because the output signal I net,column Greater than the threshold net signal I net,Th , so the output circuit can generate a release signal.

[0155] Reference Figure 5b , the third sub-unit of the synaptic memory column 510 may have a resistive memory element set to a first resistance value, and the first sub-unit and the second sub-unit of the synaptic memory column 510 may each have a resistive memory element set to a second resistance value. Figure 5a The first sub-unit and the third sub-unit of the reference column 520 may each have a resistive memory element set to the second resistance value, and the second sub-unit of the reference column 520 may have a resistive memory element set to the first resistance value. However, the resistance value of each of the first sub-unit, the second sub-unit, and the third sub-unit of the reference column 520 is not limited to the aforementioned example, and may be variously changed based on the application.

[0156] The first subunit, the second subunit, and the third subunit may generate current signals to which a bit weight corresponding to the LSB (e.g., multiplied by 1), a bit weight corresponding to the first digit from the LSB (e.g., multiplied by 2), and a bit weight corresponding to the second digit from the LSB (e.g., multiplied by 4) are applied, respectively. Cells Can be 1×I P +(2+4)×I AP The reference integrated signal I of the reference column 520 REF Can be 2×I P +(1+4)×I AP . Output signal I net,column Can be -1(I P -IAP ). Since the output signal I net,column is a negative number, so the output signal I net,column Can be interpreted as an output signal for performing IPSP operations.

[0157] Figure 5c An example of an input signal 530 applied via two input lines is shown.

[0158] Figure 5c The output signal I net,column It can be 4 (I P -I AP )-(I P -I AP )=3(I P -I AP ), which is accomplished by Figure 5a and Figure 5b Similarly, the threshold net signal I net,Th Can be determined as 6(I P -I AP ). Because the output signal I net,column Less than the threshold net signal I net,Th , so the output circuit can perform leakage operation.

[0159] Figures 6a to 6c Other examples of firing comparisons using net signals generated from synaptic memory columns, reference columns, threshold generation columns, and additional reference columns are shown.

[0160] exist Figure 6a , a column in the synaptic memory array is illustrated as a synaptic memory column 610. In addition, a column in the reference memory array may be illustrated as a reference column 620. A column in the threshold memory array may be illustrated as a threshold generation column 680. A column in the additional reference memory array may be illustrated as an additional reference column 690. For ease of description, each column may include 3-bit bit lines, and an input signal may be applied to one input line.

[0161] For example, the third sub-unit of the synaptic memory column 610 may have a resistive memory element set to a first resistance value, and the first sub-unit and the second sub-unit of the synaptic memory column 610 may respectively have a resistive memory element set to a second resistance value. The reference column 620 may be a 1-bit unit for storing a single bit of information (e.g., a sign bit) regardless of the number of bits of the synaptic memory column 610. Specifically, the reference column 620 may have a resistive memory element in a 1-bit unit that is set to the second resistance value or the first resistance value based on whether the operation to be simulated is EPSP or IPSP. Figure 6aIn the example, the operation to be simulated is EPSP, and the cell of 1 bit of the reference column 620 may have a resistive memory element set to the second resistance value.

[0162] The first subunit, the second subunit, and the third subunit of the synaptic memory column 610 may generate current signals to which a bit weight corresponding to the LSB (e.g., multiplied by 1), a bit weight corresponding to the first digit from the LSB (e.g., multiplied by 2), and a bit weight corresponding to the second digit from the LSB (e.g., multiplied by 4) are applied, respectively. The column integration signal I of the synaptic memory column 610 Cells It can be (4+2)×I P +1×I AP .

[0163] The 1-bit cell of the reference column 620 may generate a current signal to which a predetermined bit weight (eg, multiplied by 7) is applied. REF Can be 7×I AP . Output signal I net,column It can be 6(I P -I AP ). Since the output signal I net,column is a positive number, so the output signal I net,column Can be interpreted as EPSP.

[0164] Similarly, the threshold integrated signal I in the threshold generation column 680 is Th Can be 2×I AP +(1+4)×I P =5I P +2I AP The additional reference integrated signal I generated in the additional reference column 690 REF,Th Can be 7×I AP .exist Figure 6a In the threshold net signal I net,Th Can be determined as 5(I P -I AP ). Because the output signal I net,column Greater than the threshold net signal I net,Th , so the output circuit can generate a release signal.

[0165] Reference Figure 6b , the third sub-unit of the synaptic memory column 610 may have a resistive memory element set to the second resistance value, and the first sub-unit and the second sub-unit may have a resistive memory element set to the first resistance value. Figure 6b In the example, the operation to be simulated is IPSP, and the cell of 1 bit of the reference column 620 may have a resistive memory element set to a first resistance value.

[0166] The first subunit, the second subunit, and the third subunit of the synaptic memory column 610 may generate current signals that are respectively applied to the bit weight corresponding to the LSB (e.g., multiplied by 1), the bit weight corresponding to the first digit from the LSB (e.g., multiplied by 2), and the bit weight corresponding to the second digit from the LSB (e.g., multiplied by 4). The column integration signal I of the synaptic memory column 610 Cells It can be (2+4)×I P +1×I AP .

[0167] The 1-bit cell of the reference column 620 may generate a current signal to which a predetermined bit weight (eg, multiplied by 7) is applied. REF It can be 7×IP. Output signal I net,column Can be -1(I P -I AP ).

[0168] Figure 6c An example of an input signal 630 applied to two input lines is shown.

[0169] Figure 6c The output signal I net,column This can be done by Figure 6a and Figure 6b The output signals of P -I AP )-(I P -I AP )=5(I P -I AP ). Similarly, the threshold net signal I net,Th can be determined as 10(I P -I AP ). Because the output signal I net,column Less than the threshold net signal I net,Th , so the output circuit can perform leakage operation.

[0170] Figure 7 An example of a threshold time generating circuit of an output circuit is shown.

[0171] The output circuit may set a threshold time 791 corresponding to a threshold value based on a signal generated from the threshold memory cell and a signal generated from the additional reference memory cell. Figure 7 , the threshold time generating circuit 753 in the output circuit for setting the threshold time 791 is described. The first readout circuit 451, the second readout circuit 452, and the LIF circuit 260 are described above.

[0172] Since it may be difficult to directly compare the output current with the current set as a threshold, as described above, the threshold time generation circuit 753 may set a threshold time 791 for current comparison. The threshold time generation circuit 753 may set the time taken to reach the threshold voltage by leakage of the current corresponding to the threshold as the threshold time 791. As described above, the output circuit may determine whether the time taken to reach the same threshold voltage by leakage of the output current is less than the threshold time 791. For example, the output circuit may indirectly compare the threshold current with the output current by determining whether the output voltage converted from the leakage of the output current within the set threshold time 791 exceeds the threshold voltage.

[0173] The output circuit may initiate integration of a current corresponding to the difference between a signal generated based on the threshold memory cell and a signal generated based on the additional reference memory cell. When a voltage corresponding to the integrated current exceeds a threshold voltage, the output circuit may output a signal indicating a threshold time 791 corresponding to the threshold.

[0174] The threshold time generating circuit 753 may have the same Figure 3 For example, the threshold time generation circuit 753 may allow the threshold integration signal I Th flows in the nodes of the capacitor and allows the addition of a reference integral signal I REF,Th The threshold net signal I net,Th The capacitor and the operational amplifier can be designed to be the same in type and size.

[0175] The reset signal RESET and the hold signal HOLD shown in the timing diagram 790 may be generated by a timing generator. When the reset signal is RESET=1, the threshold net signal I net,Th The voltage across the capacitor is V CM and V TWG When the reset signal is RESET=0 and the hold signal is HOLD=1, the net signal I net,Th The integral conversion voltage V TWG can be stored in a capacitor. The voltage V TWG Based on the threshold net signal I netTh The integral of VT increases gradually. WG Exceeding the threshold voltage V TH When the window comparator OP window Therefore, the threshold time 791 can be defined as the time from when the reset signal is RESET==0 to when the window signal is WINDOW=0. CM,TWG can be set to be less than V CM_COLUMN_IN For example, when the output signal Inet,column and the threshold net signal I net,Th When the same (for example, I net,column =7I P -7I AP , I net,Th =7I P -7I AP Hours), 7I P -7I AP The example can be only (based on V CM_COLUMN_IN Voltage V TWG Greater than (based on V CM,TWG Threshold voltage V TH It is confirmed as issued when

[0176] Figure 8 An example of elements included in the LIF circuit in the output circuit and a timing chart of each element are shown.

[0177] The reset trigger 810 may generate a reset signal RESET in response to a clock signal divided by 4 and a neuron input (input signal). The hold trigger 820 may generate a hold signal HOLD in response to a clock signal divided by 8 and a neuron input (input signal). The comparison trigger 830 may generate a comparison signal COMPARE in response to a clock signal, a power supply voltage VDD, and an inverted hold signal HOLDB. The comparison signal COMPARE may be a signal that initiates a comparison operation of the comparator when the integrated output signal has been transmitted to the input of the comparator. The leakage trigger 840 may generate a leakage signal LEAKAGE in response to a clock signal, a power supply voltage VDD, and an inverted comparison signal COMPAREB. The leakage signal LEAKAGE may be a signal for performing a leakage operation of the output voltage after the comparison operation described above. When there is a leaked voltage, the SW trigger 870 may generate a SW signal to transmit the leaked voltage to the leakage subcircuit so that the leaked voltage and the output based on the next input are combined. As shown in the timing diagram 890 of the above-mentioned signals, the threshold time 891 may be a time interval after the reset until the window signal WINDOW is deactivated.

[0178] Fig. 9 An example of a firing operation of a neural network circuit according to one or more embodiments is shown.

[0179] The neural network circuit may include a memory array 910, an output circuit 950, a frequency divider and timing generator 940, a word line driver 970, and a write driver 980. The memory array 910 may include a synaptic memory array, a reference memory array, a threshold memory array, and an additional reference memory array. The output circuit 950 may include a readout circuit 951, a threshold time generation circuit 953, and a LIF circuit 960. The memory array 910 and the output circuit 950 are described above. The frequency divider and timing generator 940 may generate signals used in the circuit (e.g., clock signals and control signals for individual elements). The word line driver 970 may drive a word line (e.g., an input line) of the memory array 910. The write driver 980 may set the resistance value of the resistive memory element of the memory cell arranged along the bit line of the memory array 910, and may drive the bit line and the sense line.

[0180] Fig. 9 The timing diagram 990 in FIG. 1 shows an example of the operation of a neural network circuit with a threshold value set to T=6. The threshold net signal I net,Th It can be 6(I P -I AP ). Flow through the columns <0> The current can be changed to 7 (I P -I AP )→2(I P -I AP )→7(I P -I AP )+(-3)(I P -I AP ), and flows through the columns <1> The current can be changed to 7 (I P -I AP )→-2(I P -I AP )→3(I P -I AP )+(-3)(I P -I AP ). As described above, when a stimulus less than or equal to the threshold is transmitted, the emission signal may not be output, and the integrated voltage V_integrated may be transmitted until the interval in which the leakage pulse (LEAKAGE) is high. During the interval in which the leakage pulse is high, the level of the integrated voltage V_integrated may gradually decrease. When a stimulus greater than or equal to the threshold is transmitted, the emission signal may be output and the integrated voltage V_integrated may be initialized. In addition, when a stimulus is transmitted after the integrated voltage V_integrated is leaked when a stimulus less than or equal to the threshold has been transmitted, and the sum of the stimuli is greater than or equal to the threshold, the emission signal may be output. Fig. 9In the example shown in FIG. 1 , when the threshold is T=6, for the flow through the column <0> The current flowing through the column can be released → leaked → leaked in sequence. <1> The current can occur in the sequence of release → leakage → leakage.

[0181] Fig.10 An example of a method of operation of a neural network circuit according to one or more embodiments is shown.

[0182] In operation 1010, the neural network circuit may generate a column signal based on an input signal and a resistive memory element of a synaptic memory cell among one or more memory cells arranged along an output line (to which the input signal is applied through the input line). For example, when an input signal (e.g., a pulse signal) is received through a pre-synaptic circuit, the neural network circuit may access a word line of a memory array. A readout circuit of the neural network circuit may generate a column signal (e.g., a current) based on a synaptic weight and an input signal.

[0183] In operation 1020, the neural network circuit may generate a reference signal based on the input signal and based on a reference memory element having a reference resistance value of a reference memory cell to which the input signal is applied. The reference memory cell may be among one or more memory cells arranged along a reference line. The reference resistance value may be set by a predetermined combination of one or more of the first resistance value and / or the second resistance value, and the reference resistance value may be selected based on its suitability for a particular application. Different reference resistance values ​​(derived from different combinations of the first value and / or the second value) may be selected for different applications.

[0184] In operation 1030, the neural network circuit may generate an output signal of the output line according to the column signal and the reference signal. To cancel the current in the high resistance state, the neural network circuit may generate an output signal corresponding to the difference between the column integrated signal and the reference integrated signal.

[0185] In operation 1040, the neural network circuit may perform emission or integration based on the output signal. For example, the neural network circuit may leak the output signal (as a voltage) within a threshold time. The neural network circuit may perform emission or integration based on a result of comparing the leaked output voltage with a threshold voltage. When the output voltage exceeds the threshold voltage, the neural network circuit may perform emission. When the output voltage is less than or equal to the threshold voltage, the neural network circuit may perform integration and maintain the output voltage until the next neuron input is provided.

[0186] The processing of the output signal of the neural network is not limited to the aforementioned operation 1040. The output circuit of the neural network circuit may obtain a MAC value between the synaptic weight and the input signal received along the input line based on the result (e.g., analog-to-digital conversion value) obtained by parsing the output signal, and the output circuit may transmit a node value (e.g., activation value) determined based on the obtained MAC value to another neuron circuit.

[0187] Here about Figures 1 to 10The computing devices, electronic devices, processors, memories, storage devices, and other devices, devices, units, modules, and components described are implemented or represent hardware components by hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components in the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a limited manner to achieve the desired result). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or a computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. The hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used for the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include: a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0188] Figures 1 to 10The method for performing the operations described in the present application shown in is performed by computing hardware (e.g., by one or more processors or computers), and the computing hardware is implemented as the above-described execution for performing the instructions or software for the operations performed by the method described in the present application. For example, a single operation or two or more operations can be performed by a single processor or two or more processors, or a processor and a controller. One or more operations can be performed by one or more processors or a processor and a controller, and one or more other operations can be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can perform a single operation or two or more operations.

[0189] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform methods as described above may be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as machines or special-purpose computers to perform operations performed by hardware components and methods as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include higher-level code that is executed by one or more processors or computers using a parser. Instructions or software may be written in any programming language based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein, and the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein disclose algorithms for performing operations performed by hardware components and methods as described above.

[0190] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, and any associated data, data files, and data structures may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, card-type memory (such as, micro multimedia card or card (for example, secure digital (SD) or extreme digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files and data structures are distributed on a networked computer system so that the instructions and software and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0191] Although the present disclosure includes specific examples, it will be clear after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of features or aspects in each example is considered to be applicable to similar features or similar aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents.

[0192] Therefore, the scope of the disclosure may be defined by the claims and their equivalents in addition to the above disclosure, and all variations within the scope of the claims and their equivalents should be construed as being included in the disclosure.

Claims

1. A neural network circuit, comprising: a synaptic memory cell including a resistive memory element arranged along an output line and configured to change between having a first resistance value and a second resistance value as resistance values, wherein the synaptic memory cell is configured to generate a column signal based on the resistance value of the resistive memory element and an input signal received via an input line; a reference memory cell including a reference memory element arranged along a reference line and having a resistance value that is a predetermined ratio of a first resistance value to a second resistance value, wherein the reference memory cell is configured to generate a reference signal based on the input signal and the resistance value of the reference memory element; and The output circuit is configured to generate an output signal of the output line based on the column signal and the reference signal.

2. The neural network circuit according to claim 1, wherein: The synaptic memory cell includes: a number of resistive memory elements corresponding to the number of bits used to represent the synaptic weight assigned to the synaptic memory cell, wherein A number of resistive memory elements corresponding to the number of bits are arranged along the input line.

3. The neural network circuit according to claim 2, wherein: The reference memory cells include: a number of reference memory elements corresponding to the number of bits used to represent the synaptic weight, and Therein, reference memory elements corresponding to the number of bits are arranged along the input line.

4. The neural network circuit according to claim 2, wherein: The reference memory cells include: Reference memory element used to represent the sign bit.

5. The neural network circuit according to claim 1, wherein: The output circuit is also configured as: A current corresponding to a positive integer multiple of a net current that is a difference between a first current based on the resistive memory element having a first resistance value and a second current based on the resistive memory element having a second resistance value is generated as the output signal.

6. The neural network circuit according to claim 1, wherein: The output circuit is also configured as: A current corresponding to a negative integer multiple of a net current is generated as the output signal, the net current being a difference between a first current based on the resistive memory element having a first resistance value and a second current based on the resistive memory element having a second resistance value.

7. The neural network circuit according to claim 1, wherein: The neural network circuit comprises a neuron circuit, the neuron circuit comprises a synaptic memory unit, a reference memory unit and an output circuit, and wherein, The output circuit also includes: The leaky integration firing circuit is configured to execute firing at another neuron circuit based on a result of comparing the output signal with a threshold.

8. The neural network circuit according to claim 7, wherein: The leakage credit issuance circuit is further configured as follows: When the output signal corresponds to a positive integer multiple of the net current, the output voltage is increased.

9. The neural network circuit according to claim 7, wherein: The leakage credit issuance circuit is further configured as follows: When the output signal corresponds to a negative integer multiple of the net current, the output voltage is reduced.

10. The neural network circuit according to claim 7, wherein: The leakage credit issuance circuit is further configured as follows: When a voltage based on the integration of the output signal does not reach a threshold voltage within a threshold time, the output signal leaks from the capacitor.

11. The neural network circuit according to claim 7, wherein: The leakage credit issuance circuit is further configured as follows: When a voltage based on the integration of the output signal reaches a threshold voltage within a threshold time corresponding to a threshold value, firing is performed at the other neuron circuit.

12. The neural network circuit of claim 7, further comprising: A threshold memory array includes a plurality of memory elements, wherein at least one memory element among the plurality of memory elements specified based on a threshold value has a first resistance value.

13. The neural network circuit of claim 12, further comprising: An additional reference memory cell is configured to share a reference word line with the threshold memory array and includes an additional reference memory element, wherein the additional reference memory element is arranged along the reference word line and has a second resistance value.

14. The neural network circuit of claim 13, wherein: The output circuit is also configured as: A threshold time corresponding to the threshold is set according to a signal generated based on the threshold memory cell and a signal generated based on the additional reference memory cell.

15. The neural network circuit of claim 14, wherein: The output circuit is also configured as: Initiating integration of a current corresponding to a difference between a signal generated based on a threshold memory cell and a signal generated based on an additional reference memory cell, and outputting a signal indicating a threshold time corresponding to a threshold, wherein the initiated processing is based on a voltage corresponding to the integrated current exceeding a threshold voltage.

16. The neural network circuit of claim 14, wherein: The output circuit is also configured as: A threshold time is applied to the output signal of the output line and another output signal of another output line, the threshold time corresponding to a threshold value determined based on the threshold memory cell and the additional reference memory cell.

17. The neural network circuit of claim 1, wherein: The resistive memory elements of the synaptic memory cells connected to the output line are connected in parallel to each other.

18. The neural network circuit of claim 1, further comprising: another synaptic memory cell arranged along another output line different from the output line, The output circuit is further configured as: An output signal of each of the output line and the another output line is generated respectively by using the same reference memory cell.

19. The neural network circuit of claim 1, wherein: The synaptic memory cell comprises a bit including a corresponding resistor, wherein, The reference memory cell comprises a bit including a corresponding resistor, and wherein, The output circuit includes: The readout circuit is configured to generate a column integrated signal by integrating a column signal for each bit of the synapse memory cell and to generate a reference integrated signal by integrating a reference signal for each bit of the reference memory cell.

20. The neural network circuit of claim 19, wherein: The readout circuit includes: A current mirror is configured to replicate a column signal for each bit of the synaptic memory cell and the reference memory cell into a current multiple corresponding to the bit.

21. The neural network circuit of claim 19, wherein: The output signal corresponds to the difference between the column integrated signal and the reference integrated signal.

22. The neural network circuit of claim 21, wherein: The output circuit also includes: A capacitor is configured to allow a current corresponding to a reference integrated signal to flow into a node and allow a current corresponding to a column integrated signal to flow out of the node, so that a current corresponding to a difference between the column integrated signal and the reference integrated signal flows through the node, wherein the node includes the neural network circuit.

23. The neural network circuit of claim 1, wherein: The neural network circuit comprises a neuron circuit, the neuron circuit comprises a synaptic memory unit, a reference memory unit and an output circuit, and wherein, The output circuit is also configured as: Based on the result obtained by parsing the output signal, a product-accumulation value between the synaptic weight and the input signal received along the input line is obtained, and a node value determined based on the obtained product-accumulation value is transmitted to another neuron circuit.

24. The neural network circuit of claim 1, wherein: The ratio is predetermined based on the application.

25. A method for operating a neural network circuit, the method comprising: generating a column signal based on an input signal and a resistance value of a resistive memory element of a synaptic memory cell to which the input signal is applied through an input line, wherein the synaptic memory cell is among one or more synaptic memory cells arranged along an output line; generating a reference signal based on an input signal and a reference memory element having a reference resistance value of a reference memory cell to which the input signal is applied, wherein the reference memory cell is among one or more reference memory cells arranged along a reference line; and Generate an output signal of the output line according to the column signal and the reference signal, Among them, the reference resistance value is configured as: The resistance value is determined based on a combination of the first resistance value and a second resistance value different from the first resistance value.

26. The operating method according to claim 25, wherein: The combination is predetermined based on the application.

27. A processor comprising: a memory array comprising rows and columns of resistive memory cells, the resistive memory cells comprising respective resistors, wherein each resistive memory cell of the memory array has a resistance programmable to vary between a first resistance and a second resistance, wherein the columns of the memory array provide an integrated column current based on an input signal supplied to the respective resistive memory element of the column and based on the resistance of the respective memory element of the column; and A reference array of resistive memory cells, the resistive memory cells including respective resistors, wherein each resistive memory cell of a reference column has a resistance programmable to vary between a first resistance and a second resistance, wherein the reference memory array provides an integrated reference current based on an input signal supplied to the resistive memory elements of the reference array and based on the resistance of the respective memory elements of the reference array.

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