Dynamic spread spectrum clock control

Abstract

The circuits and methods described herein provide a technical solution for technical issues for USB links. To reduce or eliminate the effects associated with the entry of a USB link into a low power mode, an initial link acquisition may be performed while disabling spread spectrum clock (SSC) modulation. After initial link acquisition, SSC modulation may be dynamically enabled at a later stage. This delayed activation of the retimer provides improved performance compared to a solution in which SSC modulation is continually activated, including reducing the complexity of the timing training process and enabling faster USB link re-establishment. This reduced link acquisition period may enable the system to enter the power saving mode more frequently and may reduce the latency involved in exiting the power saving mode. This may maintain or improve the overall USB transmission speed, and may reduce USB-related power consumption for USB-connected devices.

Description

[0001] priority

[0002] This application claims the benefit of priority to U.S. patent application Ser. No. 17 / 858,692, filed on July 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments described herein generally relate to Universal Serial Bus (USB) devices. Background Art

[0004] A USB cable can be used to connect electronic devices via a USB link. Each USB link can include two endpoint transceivers and up to 6 bit-level retimers between the two endpoint transceivers. When sending data over a USB link, the data is sent from the endpoint transmitter using a spread spectrum clock (SSC), and the data is retransmitted in each of the retimers using a recovered clock extracted from the signal.

[0005] The USB link may include an SSC modulated clock that may be required to comply with client connection standards such as requirements for reducing electromagnetic interference (EMI). The SSC modulated clock may also be used to comply with EMI requirements for other communication systems, such as DisplayPort, Peripheral Component Interconnect Express (PCI-E), and other communication systems. Although the use of an SSC modulated clock may provide improved EMI performance, the SSC modulated clock creates timing challenges and other technical challenges.

[0006] When a USB link enters a power save mode, the USB link goes down until one of the endpoints initiates link reestablishment. However, reestablishing a USB link across retimers requires additional time for each of the retimers, which increases the latency associated with a given USB link. To enter a low power mode, an additional delay of 60 μs or more may be added to allow the USB link to switch to an incoming clock containing SSC modulation.

[0007] The total time required to reestablish a USB link may exceed the requirements for the USB link and often results in an exit delay that is higher than the time required to reestablish the link without corrupting USB data. This additional delay may cause the USB link to be prevented from entering a low power mode, especially for higher bandwidth USB links. An improved USB link low power mode is needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same reference numerals with different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example and not limitation in the accompanying drawings, in which:

[0009] Figure 1A-Figure 1D is a block diagram illustrating communication link reestablishment according to an embodiment.

[0010] Figure 2 is a circuit diagram of a dynamic SSC activated transmitter according to an embodiment.

[0011] Figure 3 is a flow chart illustrating a method for communication link synchronization according to an embodiment.

[0012] Figure 4 is a block diagram of a computing device according to an embodiment. DETAILED DESCRIPTION

[0013] The circuits and methods described herein provide technical solutions for technical problems of USB links. In order to reduce or eliminate the effects associated with the USB link entering a low power mode, initial link acquisition can be performed while disabling spread spectrum clock (SSC) modulation, which will provide a more relaxed initial condition and will achieve a faster and more robust link establishment. After the initial link acquisition, SSC modulation can be dynamically enabled at a later stage, for example, to maintain compliance with electromagnetic interference (EMI) requirements. When the USB link includes a retimer, SSC modulation can be disabled during the initial USB link training, and activation of the retimer can be delayed until the clock switching process within each retimer is completed. In order to achieve this dynamic delay in the activation of the clock switching process, once all retimers have been switched, the training protocol that manages the clock switching process can provide an indication to the endpoint transmitter to forward incoming data using the associated receiver clock. In response to receiving the indication from the retimer, the endpoint transmitter can implement SSC modulation.

[0014] This delayed enabling of the retimer provides improved performance compared to solutions in which SSC modulation is continuously enabled, including reducing the complexity of the timing training process and enabling faster USB link reestablishment. This reduced link acquisition period can enable the system to enter a power saving mode more frequently, and can reduce the latency involved in exiting a power saving mode (e.g., faster system wake-up). This can maintain or improve overall USB transfer speeds, and can reduce USB-related power consumption for USB-connected devices.

[0015] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of some example embodiments. However, it is apparent to one skilled in the art that the present disclosure may be practiced without these specific details.

[0016] Figure 1A-Figure 1D is a block diagram illustrating a communication link reestablishment 100 according to an embodiment. Figure 1A-Figure 1D A communication link reconstruction 100 is shown divided into stages 1-4, respectively. Each stage shows an example communication link including an endpoint transceiver (TX), two intermediate retimers, and an endpoint receiver (RX), for example, endpoint TX 110, first retimer 115, second retimer 120, and endpoint RX 125. Although Figure 1A-Figure 1D Two intermediate retimers are shown, but more than two retimers may be used.

[0017] After entering low power mode, the components can be activated by a predetermined sequence. In an example, all link components (e.g., endpoints and retimers) can be activated (e.g., woken up), for example, using low frequency periodic signaling (LFPS). After this activation, the endpoint can begin sending high-speed training data with SSC clock modulation. The retimer can begin sending training data from a local training engine using an unmodulated local clock (e.g., without SSC modulation). While sending this training data, the retimer may not forward incoming data or clock signals from either endpoint because the retimer receiver has not been fully trained, so the recovered data and clock are too unreliable to use. Once all endpoints are fully trained, the retimer can sequentially switch from sending local data using a local clock to forwarding incoming data using an associated recovered clock. When the incoming clock contains SSC modulation, switching from a local clock in the retimer to using an incoming clock signal may be unreliable or time consuming. In order to avoid large frequency steps that may be difficult to track between endpoints, clock switching can be applied when the instantaneous frequency of the incoming clock is close enough to the frequency of the local clock. In an example, a switching delay of two SSC cycles (eg, approximately 60 μs) may be observed before switching from the local to the incoming SSC modulation clock.

[0018] like Figure 1A As shown in , Phase 1 can be used to prepare the communication link for reduced switching delay. In Phase 1, endpoint TX 110 sends data without activating its SSC clock modulation circuitry. First retimer 115 sends training data timed with the first retimer local clock, and second retimer 120 similarly sends training data timed with the second retimer local clock to endpoint RX 125.

[0019] exist Figure 1BIn stage 2 shown, the clock within the first retimer 135 has been recovered. Endpoint TX 130 continues to send training data without SSC clock modulation to the first retimer 135. The first retimer 135 sends the incoming data to the second retimer 140 using the first recovered clock signal, and the second retimer 140 sends the training data timed with the second retimer local clock (e.g., the unrecovered clock signal) to the endpoint RX 145.

[0020] exist Figure 1C In stage 3 shown, the clock has been recovered within the second retimer 160. Endpoint TX 150 continues to send training data without SSC clock modulation to the first retimer 155. The first retimer 155 sends incoming data to the second retimer 160 using the first recovered clock signal, and the second retimer 160 sends incoming data to the endpoint RX 165 using the second recovered clock signal.

[0021] exist Figure 1D In the illustrated stage 4, the recovered clock signal is used by both the first retimer 175 and the second retimer 180. The endpoint TX 170 may send data to the first retimer 175 using SSC clock modulation, the first retimer 175 sends the incoming data timed with the first recovered clock signal to the second retimer 180, and the second retimer 180 sends the incoming data timed with the second recovered clock signal to the endpoint RX 185.

[0022] Figure 1A-Figure 1DThe four-phase sequence shown in can be extended to configurations involving more than two intermediate retimers. In the example, to extend to a configuration with three intermediate retimers, an additional phase is inserted between phases 3 and 4. In this example additional phase, the clock within the third retimer (not shown) has been recovered. Endpoint TX 150 continues to send training data without SSC clock modulation to the first retimer 155. The first retimer 155 sends incoming data to the second retimer 160 using the first recovered clock signal, and the second retimer 160 sends incoming data to the third retimer using the second recovered clock signal, and the third retimer sends incoming data to the endpoint RX 165 using the third recovered clock signal. The final stage 4 occurs after all intermediate retimers have fully recovered the clock signal, at which point endpoint TX 170 sends data to the first retimer 175 using SSC clock modulation, the first retimer 175 sends the incoming data timed with the first recovered clock signal to the second retimer 180, the second retimer 180 sends the incoming data timed with the second recovered clock signal to the third retimer, and the third retimer sends the incoming data timed with the third recovered clock signal to the endpoint RX 185.

[0023] Figure 2 is a circuit diagram of a dynamic SSC activation transmitter 200 according to an embodiment. The transmitter 200 may be used to provide an improved communication link, for example, Figure 1A-Figure 1D The terminal TX is shown in FIG. 2. The SSC modulation in the transmitter 200 may be applied in a transmitter phase locked loop (PLL) 210.

[0024] The PLL 210 may receive a reference clock signal 205, which may be used to generate a TX clock signal 215. The PLL 210 may provide the TX clock signal 215 (e.g., SSC modulated or otherwise) to the TX logic circuit 220. The TX logic circuit 220 may use the TX clock signal 215 and the TX data input signal 235 to generate a TX logic output signal 245. The TX logic output signal 245 may be amplified at the driver 230 to generate a TX output signal 255 to be provided to a connected retimer.

[0025] The PLL 210 may receive an SSC enable control signal 225 (e.g., an SSC control bit) that may be used to enable or disable SSC modulation. When the SSC enable control signal 225 indicates that SSC modulation is disabled (e.g., the SSC control bit is set to low), the reference clock signal 205 may be used to generate the TX clock signal 215, for example, by passing the reference clock signal 205 through without modification. When the SSC enable control signal 225 indicates that SSC modulation is enabled (e.g., the SSC control bit is set to high), the TX clock signal 215 may be generated using SSC modulation of the reference clock signal 205. The SSC enable control signal 225 may be dynamically set based on the USB link state. In an example, the SSC enable control signal 225 may be turned off during training, may be switched on when all retimers have switched their clocks, and may remain on during steady-state USB link operation. In an example, the SSC enable control signal 225 may be turned off during training, may be switched on when all retimers have switched their clocks, and may remain on during steady-state USB link operation. In an example, the SSC enable control signal 225 may be turned on at an endpoint RX (e.g., Figure 1A-Figure 1D The endpoint RX) shown in is modified.

[0026] Figure 3 is a flow chart illustrating a method 300 for communication link synchronization according to an embodiment. The method 300 includes: performing 305 a first clock signal recovery of a first clock signal at a first retimer after exiting a low power communication link mode. The method 300 includes: generating 310 a clock modulation enable control signal at a second transceiver in response to the first clock signal recovery. The method 300 includes: transmitting 315 communication data from the first transceiver to the second transceiver through the first retimer in response to receiving the clock modulation enable control signal. The first transceiver, the first retimer, and the second transceiver may form a universal serial bus (USB) communication link. The method 300 may include: generating 320 a phase-locked clock signal at a phase-locked loop within the first transceiver based on the clock modulation enable control signal and a reference clock signal.

[0027] The method 300 may include, at the first retimer, switching 325 the first clock signal from the first local retimer clock signal to the first recovered clock signal in response to completion of the first clock signal recovery. The method 300 may include, at the first retimer, generating 330 first retimer data based on the first clock signal. The method 300 may include, at the second transceiver, generating 335 a clock modulation enable control signal based on the first retimer data.

[0028] The method 300 may include, after receiving the first retimer data, performing 340 a second clock signal recovery of the second clock signal at the second retimer. The method 300 may include, in response to completion of the second clock signal recovery, switching 345 the second clock signal at the second retimer from the second local retimer clock signal to the second recovered clock signal. The method 300 may include, at the second retimer, generating 350 the second retimer data based on the second clock signal. The method 300 may include, at the second transceiver, generating 355 a clock modulation enable control signal based on the second retimer data.

[0029] Figure 4 is a block diagram of a computing device 400 according to an embodiment. The performance of one or more components within the computing device 400 may be improved by including one or more of the circuits or circuit system methods described herein. The computing device 400 may include a dynamic SSC activated transmitter, which may include a transmitter PLL, a TX logic circuit, and a driver.

[0030] In one embodiment, multiple such computer systems are used in a distributed network to implement multiple components in a communication-based environment. Object-oriented, service-oriented or other architectures can be used to implement such functionality and communicate between multiple systems and components. In some embodiments, Figure 4 The computing device is an example of a client device that can invoke the methods described herein over a network. In other embodiments, the computing device is an example of a computing device that can be included in or connected to a motion interactive video projection system, as described elsewhere herein. In some embodiments, Figure 4 The computing device is an example of one or more of a personal computer, a smart phone, a tablet computer, or various servers.

[0031] An example computing device in the form of a computer 410 may include a processing unit 402, a memory 404, a removable storage 412, and a non-removable storage 414. Although the example computing device is shown and described as a computer 410, in different embodiments, the computing device may be in different forms. For example, the computing device may alternatively be a smartphone, a tablet computer, or a computer system including a processor, a memory, ... Figure 4 Other computing devices with the same or similar elements as shown and described. Furthermore, although various data storage elements are shown as part of computer 410, the storage may include cloud-based storage accessible via a network such as the Internet.

[0032] Returning to the computer 410, the memory 404 may include volatile memory 406 and non-volatile memory 408. The computer 410 may include or have access to a computing environment that includes various computer-readable media, such as volatile memory 406 and non-volatile memory 408, removable storage 412, and non-removable storage 414. Computer storage includes random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium capable of storing computer-readable instructions. The computer 410 may include or have access to a computing environment that includes input 416, output 418, and communication connection 420. The input 416 may include one or more of a touch screen, a touch pad, a mouse, a keyboard, a camera, and other input devices. Input 416 may include navigation sensor input, such as a GNSS receiver, a SOP receiver, an inertial sensor (e.g., an accelerometer, a gyroscope), a local range sensor (e.g., a LIDAR), an optical sensor (e.g., a camera), or other sensors. The computer may operate in a networked environment using a communication connection 420 to connect to one or more remote computers, such as a database server, a web server, and another computing device. Example remote computers may include a personal computer (PC), a server, a router, a network PC, a peer device, or other public network nodes, etc. Communication connection 420 may be a network interface device, such as an Ethernet card and one or both of a wireless card or circuit that may be connected to a network. The network may include one or more of a local area network (LAN), a wide area network (WAN), the Internet, and other networks.

[0033] Computer-readable instructions stored on a computer-readable medium may be executed by a processing unit 402 of a computer 410. Hard drives (disk or solid state), CD-ROMs, and RAM are some examples of articles of manufacture that include non-transitory computer-readable media. For example, various computer programs 425 or apps (e.g., one or more applications and modules that implement one or more of the methods shown and described herein, or apps or applications that execute on a mobile device or are accessible via a web browser) may be stored on a non-transitory computer-readable medium.

[0034] The above-mentioned apparatus and method can include or be included in high-speed computers, communication and signal processing circuit systems, single processor modules or multi-processor modules, single embedded processors or multiple embedded processors, multi-core processors, message information switches and special modules including multi-layer or multi-chip modules. Such apparatus can be further included as a subcomponent in various other devices (e.g., electronic systems), for example, televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablet computers (e.g., tablet computers), workstations, radio equipment, video players, audio players (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical equipment (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.

[0035] In the detailed description and claims, the term "on," one "above," used with respect to two or more elements (e.g., materials) means at least some contact between the elements (e.g., between the materials). The term "above" means the elements (e.g., materials) are in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Unless so stated, neither "on" nor "over" implies any directionality as used herein.

[0036] In the detailed description and claims, a list of items connected by the term “at least one of…” may mean any combination of the listed items. For example, if items A and B are listed, the phrase “at least one of A and B” means: only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase “at least one of A, B, and C” means: only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0037] In the detailed description and claims, a list of items connected by the term "one of..." may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means: only A (excluding B), or only B (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means: only A; only B; or only C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0038] Additional Notes and Examples

[0039] Example 1 is a system for communication link synchronization, the system comprising: a first retimer, the first retimer being used to: perform a first clock signal recovery of a first clock signal after exiting a low power communication link mode; a second transceiver, the second transceiver being used to: generate a clock modulation enable control signal in response to the first clock signal recovery; and a first transceiver, the first transceiver being used to: send communication data to the second transceiver through the first retimer in response to receiving the clock modulation enable control signal.

[0040] In Example 2, the subject matter of Example 1 includes: the first transceiver includes: a phase-locked loop, the phase-locked loop is used to: generate a phase-locked clock signal based on the clock modulation enable control signal and a reference clock signal.

[0041] In Example 3, the subject matter of Examples 1-2 includes: the first retimer is also used to: switch the first clock signal from a first local retimer clock signal to a first recovered clock signal in response to completion of recovery of the first clock signal; and generate first retimer data based on the first clock signal.

[0042] In Example 4, the subject matter of Example 3 includes the second transceiver being further for generating the clock modulation enable control signal based on the first retimer data.

[0043] In Example 5, the subject matter of Example 4 includes: a second retimer, wherein the second retimer is used to: perform a second clock signal recovery of a second clock signal after receiving the first retimer data; switch the second clock signal from a second local retimer clock signal to a second recovered clock signal in response to completion of the second clock signal recovery; and generate second retimer data based on the second clock signal.

[0044] In Example 6, the subject matter of Example 5 includes the second transceiver being further for generating the clock modulation enable control signal based on the second retimer data.

[0045] In Example 7, the subject matter of Examples 1-6 includes, wherein the first transceiver, the first retimer, and the second transceiver form a universal serial bus (USB) communication link.

[0046] Example 8 is a method for communication link synchronization, the method comprising: after exiting a low-power communication link mode, performing a first clock signal recovery of a first clock signal at a first retimer; at a second transceiver, generating a clock modulation enable control signal in response to the first clock signal recovery; and sending communication data from the first transceiver to the second transceiver through the first retimer in response to receiving the clock modulation enable control signal.

[0047] In Example 9, the subject matter of Example 8 includes generating, at a phase-locked loop within the first transceiver, a phase-locked clock signal based on the clock modulation enable control signal and a reference clock signal.

[0048] In Example 10, the subject matter of Examples 8-9 includes: at the first retimer, switching the first clock signal from a first local retimer clock signal to a first recovered clock signal in response to completion of recovery of the first clock signal; and at the first retimer, generating first retimer data based on the first clock signal.

[0049] In Example 11, the subject matter of Example 10 includes generating, at the second transceiver, the clock modulation enable control signal based on the first retimer data.

[0050] In Example 12, the subject matter of Example 11 includes: after receiving the first retimer data, performing a second clock signal recovery of a second clock signal at a second retimer; at the second retimer, switching the second clock signal from a second local retimer clock signal to a second recovered clock signal in response to completion of the second clock signal recovery; and at the second retimer, generating second retimer data based on the second clock signal.

[0051] In Example 13, the subject matter of Example 12 includes generating, at the second transceiver, the clock modulation enable control signal based on the second retimer data.

[0052] In Example 14, the subject matter of Examples 8-13 includes, wherein the first transceiver, the first retimer, and the second transceiver form a universal serial bus (USB) communication link.

[0053] Example 15 is at least one non-temporary machine-readable storage medium, comprising instructions, which, in response to being executed by a processor circuit system of a device controlled by a computer, cause the processor circuit system to perform the following operations: after exiting a low-power communication link mode, perform a first clock signal recovery of a first clock signal at a first retimer; at a second transceiver, generate a clock modulation enable control signal in response to the first clock signal recovery; and in response to receiving the clock modulation enable control signal, send communication data from the first transceiver to the second transceiver through the first retimer.

[0054] In Example 16, the subject matter of Example 15 includes: the instructions further cause the processor circuit system to perform the following operations: generate a phase-locked clock signal at a phase-locked loop within the first transceiver based on the clock modulation enable control signal and a reference clock signal.

[0055] In Example 17, the subject matter of Examples 15-16 includes: the instructions also cause the processor circuit system to perform the following operations: at the first retimer, in response to completion of recovery of the first clock signal, switching the first clock signal from a first local retimer clock signal to a first recovered clock signal; and at the first retimer, generating first retimer data based on the first clock signal.

[0056] In Example 18, the subject matter of Example 17 includes the instructions further causing the processor circuitry to: generate, at the second transceiver, the clock modulation enable control signal based on the first retimer data.

[0057] In Example 19, the subject matter of Example 18 includes: the instructions also cause the processor circuit system to perform the following operations: after receiving the first retimer data, perform a second clock signal recovery of the second clock signal at the second retimer; at the second retimer, in response to completion of the second clock signal recovery, switch the second clock signal from the second local retimer clock signal to the second recovered clock signal; and at the second retimer, generate second retimer data based on the second clock signal.

[0058] In Example 20, the subject matter of Example 19 includes the instructions further causing the processor circuitry to perform, at the second transceiver, generating the clock modulation enable control signal based on the second retimer data.

[0059] In Example 21, the subject matter of Examples 15-20 includes, wherein the first transceiver, the first retimer, and the second transceiver form a universal serial bus (USB) communication link.

[0060] Example 22 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to implement operations for implementing any of Examples 1-21.

[0061] Example 23 is an apparatus comprising means for implementing any of Examples 1-21.

[0062] Example 24 is a system for implementing any one of Examples 1-21.

[0063] Example 25 is a method for implementing any one of Examples 1-21.

[0064] The subject matter of any of the examples above may be combined in any combination.

[0065] The above description and accompanying drawings illustrate some embodiments of the subject matter of the present invention so that those skilled in the art can practice the embodiments of the subject matter of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent possible variations only. The parts and features of some embodiments may be included in the parts and features of other embodiments or replace the parts and features of other embodiments. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art.

[0066] The Abstract is provided to comply with the requirement of 37 CFR Section 1.72(b), i.e., the Abstract should allow the reader to ascertain the nature and gist of the technical disclosure. It should be understood that the Abstract will not be used to limit or interpret the scope or meaning of the claims. The appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A system for synchronizing a communication link, the system comprising: a first retimer, the first retimer being configured to: perform a first clock signal recovery of a first clock signal after exiting a low power communication link mode; a second transceiver configured to: generate a clock modulation enable control signal in response to recovery of the first clock signal; as well as A first transceiver is configured to transmit communication data to the second transceiver through the first retimer in response to receiving the clock modulation enable control signal.

2. The system according to claim 1, wherein the first transceiver comprises: A phase-locked loop is configured to generate a phase-locked clock signal based on the clock modulation enable control signal and a reference clock signal.

3. The system of claim 1 , wherein the first retimer is further configured to: responsive to completion of recovery of the first clock signal, switching the first clock signal from a first local retimer clock signal to a first recovered clock signal; and First retimer data is generated based on the first clock signal. 4 . The system of claim 3 , the second transceiver further configured to generate the clock modulation enable control signal based on the first retimer data.

5. The system of claim 4, further comprising a second retimer, the second retimer being configured to: performing a second clock signal recovery of a second clock signal after receiving the first retimer data; responsive to completion of recovery of the second clock signal, switching the second clock signal from a second local retimer clock signal to a second recovered clock signal; and Second retimer data is generated based on the second clock signal. 6 . The system of claim 5 , the second transceiver further configured to generate the clock modulation enable control signal based on the second retimer data.

7. The system according to claim 1, wherein: The first transceiver, the first retimer, and the second transceiver form a Universal Serial Bus (USB) communication link.

8. A method for synchronizing a communication link, the method comprising: performing a first clock signal recovery of the first clock signal at the first retimer after exiting the low power communication link mode; generating, at a second transceiver, a clock modulation enable control signal in response to recovery of the first clock signal; as well as In response to receiving the clock modulation enable control signal, communication data is sent from the first transceiver to the second transceiver through the first retimer.

9. The method according to claim 8, further comprising: At a phase-locked loop within the first transceiver, a phase-locked clock signal is generated based on the clock modulation enable control signal and a reference clock signal.

10. The method according to claim 8, further comprising: at the first retimer, switching the first clock signal from a first local retimer clock signal to a first recovered clock signal in response to completion of recovery of the first clock signal; and At the first retimer, first retimer data is generated based on the first clock signal.

11. The method of claim 10, generating, at the second transceiver, the clock modulation enable control signal based on the first retimer data.

12. The method according to claim 11, further comprising: performing a second clock signal recovery of a second clock signal at a second retimer after receiving the first retimer data; at the second retimer, switching the second clock signal from a second local retimer clock signal to a second recovered clock signal in response to completion of recovery of the second clock signal; and At the second retimer, second retimer data is generated based on the second clock signal.

13. The method according to claim 12, further comprising: At the second transceiver, the clock modulation enable control signal is generated based on the second retimer data.

14. The method according to claim 8, wherein: The first transceiver, the first retimer, and the second transceiver form a Universal Serial Bus (USB) communication link.

15. At least one non-transitory machine-readable storage medium comprising instructions that, in response to being executed by processor circuitry of a device controlled by a computer, cause the processor circuitry to: performing a first clock signal recovery of the first clock signal at the first retimer after exiting the low power communication link mode; generating, at a second transceiver, a clock modulation enable control signal in response to the first clock signal recovery; and In response to receiving the clock modulation enable control signal, communication data is sent from the first transceiver to the second transceiver through the first retimer.

16. The at least one non-transitory machine-readable storage medium of claim 15, the instructions further causing the processor circuitry to generate, at a phase-locked loop within the first transceiver, a phase-locked clock signal based on the clock modulation enable control signal and a reference clock signal.

17. The at least one non-transitory machine-readable storage medium of claim 15, the instructions further causing the processor circuitry to: at the first retimer, switching the first clock signal from a first local retimer clock signal to a first recovered clock signal in response to completion of recovery of the first clock signal; and At the first retimer, first retimer data is generated based on the first clock signal.

18. The at least one non-transitory machine-readable storage medium of claim 17, the instructions further causing the processor circuitry to generate, at the second transceiver, the clock modulation enable control signal based on the first retimer data.

19. The at least one non-transitory machine-readable storage medium of claim 18, wherein the instructions further cause the processor circuitry to: performing a second clock signal recovery of a second clock signal at a second retimer after receiving the first retimer data; at the second retimer, switching the second clock signal from a second local retimer clock signal to a second recovered clock signal in response to completion of recovery of the second clock signal; and At the second retimer, second retimer data is generated based on the second clock signal.

20. The at least one non-transitory machine-readable storage medium of claim 19, the instructions further causing the processor circuitry to generate, at the second transceiver, the clock modulation enable control signal based on the second retimer data.

21. The at least one non-transitory machine-readable storage medium of claim 15, wherein: The first transceiver, the first retimer, and the second transceiver form a Universal Serial Bus (USB) communication link.

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